A memory and an operating method of the memory

Abstract

The application discloses a memory and an operating method of the memory. The memory comprises a storage array and a peripheral circuit. The peripheral circuit comprises a plurality of gating switch units and a plurality of discharge switch units. One end of each gating switch unit is connected with a bit line end of a storage unit structure. The gating switch unit is configured to control an operating state of the storage unit structure and to be continuously turned on or turned on for a part of time and then turned off during a discharge operation on a selected storage unit structure. Each discharge switch unit is connected with the other end of the gating switch unit. The discharge switch unit is configured to provide a reset voltage signal to the other end of the gating switch unit connected with the selected storage unit structure during the discharge operation. Through the technical features, the reliability of a reading process can be improved by setting the gating switch unit to be continuously turned on or turned on for a part of time and then turned off during the discharge operation.

Description

Technical Field

[0001] This application relates to the field of phase-change memory technology, specifically to a memory and a method for operating the memory. Background Technology

[0002] PCM (Phase Change Memory) is a type of non-volatile memory that uses the resistance difference of phase change materials to represent data state. During data reading, the storage state of the memory cell is typically determined by the charge sharing between the BL (bit line) and DL (data line).

[0003] In related technologies, the reading of a storage cell structure is easily affected by factors such as BL leakage current and parasitic capacitance corresponding to BL, which can lead to inaccurate reading of the storage cell structure's state. Summary of the Invention

[0004] In view of the above-mentioned deficiencies of the prior art, the technical problem to be solved by this application is how to improve the reliability of the memory cell structure reading process.

[0005] To address at least one of the aforementioned technical problems, this application discloses a memory and a method for operating the memory.

[0006] According to one aspect of this application, a memory is provided, the memory including a memory array and peripheral circuitry, the memory array including multiple memory cell structures, and the peripheral circuitry electrically connected to the memory cell structures, the peripheral circuitry including:

[0007] Multiple gating switch units, each gating switch unit including a first terminal and a second terminal, the first terminal being connected to the bit line terminal of any memory cell structure, the gating switch units being configured as follows:

[0008] Control the operational state of the storage unit structure;

[0009] During the discharge operation of the selected memory cell structure, it is continuously turned on or turned on for a partial time and then turned off;

[0010] Multiple discharge switch units, each discharge switch unit being connected to the second terminal of any gating switch unit, are configured to provide a reset voltage signal to the second terminal of the gating switch unit connected to the selected memory cell structure during a discharge operation on the selected memory cell structure.

[0011] Optionally, the gating switch unit includes:

[0012] The first bit line switch has a third terminal and a fourth terminal. The third terminal is connected to the bit line terminal of the memory cell structure, and the fourth terminal is connected to the local bit line of the memory array.

[0013] The second line switch has a fifth terminal and a sixth terminal. The fifth terminal is connected to the fourth terminal of the first line switch, and the sixth terminal is connected to the discharge switch unit.

[0014] Optionally, the first line switch is configured to remain on during the discharge and read operations of the selected memory cell structure;

[0015] The second bit line switch is configured to: turn on for a partial time and then turn off during a discharge operation on the selected memory cell structure, and turn off for a partial time and then turn on during a read operation.

[0016] Optionally, the first line switch is configured to: turn on for a partial time and then turn off during the discharge operation of the selected memory cell structure, and turn off for a partial time and then turn on during the read operation.

[0017] The second bit line switch is configured to remain on during discharge and read operations on the selected memory cell structure.

[0018] Optionally, the discharge switch unit includes:

[0019] A voltage switch, one end of which is connected to the second terminal of the gating switch unit and the other end of which is connected to a negative voltage signal, is configured such that during a discharge operation on the selected memory cell structure, the voltage switch is turned on to provide a reset voltage signal to the second terminal of the gating switch unit.

[0020] Optionally, the peripheral circuitry also includes an equalization switch.

[0021] The equalization switch has a seventh terminal and an eighth terminal, which are respectively connected to the second terminals of two adjacent gating switch units;

[0022] The equalization switch is configured such that its seventh terminal is connected to the selected memory cell structure, and a reference voltage is obtained at its eighth terminal during the discharge operation of the selected memory cell structure.

[0023] Optionally, the peripheral circuitry also includes:

[0024] The signal control structure is configured as follows:

[0025] An initialization operation is performed, during which the control gating switch unit is turned on.

[0026] After the initialization operation, the discharge operation is performed. During the discharge operation, the discharge switch unit is turned on and the gating switch unit is turned off after being turned on for a partial time.

[0027] The read operation is performed after the discharge operation. During the read operation phase, the selected memory cell structure remains on, and the discharge switch unit is turned off after being turned on for a partial time.

[0028] According to a second aspect of this application, a method for operating a memory as described in any of the preceding claims is provided, comprising:

[0029] Perform initialization operations to activate the gating switch unit in order to control the operating state of the memory cell structure;

[0030] After initialization, a discharge operation is performed, turning on the discharge switch unit to provide a reset voltage signal to the second terminal of the gating switch unit; wherein, the gating switch unit is turned on for a partial time and then turned off.

[0031] A read operation is performed after the discharge operation to enable the selected memory cell structure.

[0032] Optionally, the discharge operation includes a first operation stage, a second operation stage, and a third operation stage; the peripheral circuit also includes an equalization switch.

[0033] The discharge operation includes:

[0034] In the first operating phase, the equalization switch is turned on to generate a reference voltage at the eighth terminal of the equalization switch; the equalization switch remains on in the second and third operating phases.

[0035] Optionally, the discharge operation includes a first operation stage, a second operation stage, and a third operation stage; the gating switch unit includes a first bit line switch and a second bit line switch;

[0036] The discharge operation also includes:

[0037] In the first operation phase, the first line switch and the second line switch are turned on.

[0038] In the second operation phase, one of the first line switch and the second line switch is turned off, while the other remains on.

[0039] In the third operation phase, the first line switch and the second line switch remain in the same on or off state as in the second operation phase.

[0040] The memory disclosed in this application can improve the reliability of the reading process of the memory cell structure by adjusting the timing control method of each switch of the peripheral circuit.

[0041] Specifically, by setting up a selection switch unit in the peripheral circuit, and by controlling some selection switch units to be continuously turned on and others to be turned off after being turned on for a certain period of time during the discharge operation of the selected memory cell structure, the reading time of the selected memory cell structure can be optimized, thereby making the reading voltage closer to the intrinsic reading voltage and improving the reliability of the reading process.

[0042] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0043] To more clearly illustrate the technical solutions of this application, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0044] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0045] Figure 1 A schematic diagram of the structure corresponding to the memory provided for an exemplary embodiment of this disclosure;

[0046] Figure 2 A circuit diagram corresponding to the peripheral circuitry of the memory provided for an exemplary embodiment of this disclosure;

[0047] Figure 3 A first voltage change timing diagram provided for an exemplary embodiment of this disclosure;

[0048] Figure 4 A first switch control timing diagram provided for an exemplary embodiment of this disclosure;

[0049] Figure 5 A second voltage change timing diagram provided for an exemplary embodiment of this disclosure;

[0050] Figure 6 A second switch control timing diagram provided for an exemplary embodiment of this disclosure;

[0051] Figure 7 A flowchart illustrating a memory operation method provided for an exemplary embodiment of this disclosure.

[0052] Explanation of reference numerals in the attached figures:

[0053] 1-Memory array, 2-Peripheral circuit, 3-Word line unit, 4-Circuit control structure, 5-Signal control structure, 6-Memory cell structure, 7-Selected memory cell structure;

[0054] 10-Gating switch unit, 11-Local bit line, 20-Discharge switch unit, 30-Compensation capacitor, 40-Comparator;

[0055] S0 - Equalization switch, S1 - Initialization switch, S2 - Voltage switch, S3 - First position line switch, S4 - Second position line switch;

[0056] Vneg - negative voltage signal, Vref - reference voltage, Vss - initialization signal. Detailed Implementation

[0057] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of them. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this application.

[0058] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such as a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0059] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0060] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0061] In this document, the term "and / or" describes a relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0062] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0063] As described in the background section, the reading process of a storage cell is easily affected by factors such as BL leakage current and the parasitic capacitance corresponding to BL.

[0064] Figure 1 This is a schematic diagram of a memory embodiment, such as... Figure 1 The memory includes a storage array 1 and peripheral circuits 2, wherein the storage array 1 has multiple storage cell structures 6, and the peripheral circuits 2 are connected to the storage array 1.

[0065] In some embodiments, the storage array 1 corresponds to at least a portion of the phase-change memory and includes a plurality of word lines (WL), a plurality of bit lines, and a plurality of storage cell structures 6. The storage cell structures 6 are located at the intersection of the WL and BL, and binary data can be written to or read from the storage cell structures 6.

[0066] The memory cell structure 6 can include crystalline and amorphous states, each corresponding to a different voltage threshold. The transition between these states is achieved by applying different forms of heat to the memory cell structure 6. The crystalline state is defined as 1, corresponding to a lower threshold voltage, while the amorphous state is defined as 0, corresponding to a higher threshold voltage. A programming operation to write a "1" to the memory cell structure 6 is defined as a set operation, and a programming operation to write a "0" is defined as a reset operation. By applying a voltage greater than the set state but less than the reset state threshold voltage to the selected memory cell structure 7, the crystalline state memory cell structure 6 can be opened, but the amorphous state memory cell structure 6 cannot be opened, thus completing the state reading of the memory cell structure 6. The voltage threshold corresponding to each memory cell structure 6 is the intrinsic read voltage corresponding to the BL voltage when reading the selected memory cell structure.

[0067] The peripheral circuit 2 includes a word line unit 3, a circuit control structure 4, and a signal control structure 5. The word line unit 3 is configured to determine the target memory level (WL) corresponding to the target memory cell structure. The signal control structure 5 is configured to perform operations associated with the circuit control structure 4, such as controlling the on / off state of switches corresponding to various components of the circuit control structure 4 during the reading of the memory cell structure 6.

[0068] In the embodiment described above, when reading any storage cell structure 6 in the storage array 1, the BL voltage rises prematurely due to BL leakage sensitivity, resulting in inaccurate reading voltage when reading the storage cell structure cell. Alternatively, the BL capacitance sensitivity affects the charge sharing effect between BL and DL, leading to inaccurate reading status of the storage cell structure cell.

[0069] To address the technical problems existing in the above embodiments, this application proposes a peripheral circuit for a memory. By controlling a portion of the selection switch units to remain continuously on and a portion of the selection switch units to be turned off after being on for a certain period of time during the discharge operation of the selected memory cell structure, the reading time of the selected memory cell structure can be optimized, thereby making the reading voltage closer to the intrinsic reading voltage and improving the reliability of the reading process.

[0070] Figure 2 The circuit diagram corresponding to the peripheral circuitry of the memory provided for an exemplary embodiment of this disclosure is as follows: Figure 1 and Figure 2 As shown, the peripheral circuit 2 of the memory includes a circuit control structure 4.

[0071] Circuit control structure 4 includes:

[0072] Multiple gating switch units 10, each gating switch unit 10 including a first terminal and a second terminal, the first terminal being connected to the bit line terminal of any memory cell structure 6, and the gating switch unit 10 being configured as follows:

[0073] Control the operational state of storage unit structure 6;

[0074] During the discharge operation of the selected memory cell structure 7, it is continuously turned on or turned on for a partial time and then turned off.

[0075] Multiple discharge switch units 20, each discharge switch unit 20 is connected to the second terminal of any gating switch unit 10, and the discharge switch unit 20 is configured to provide a reset voltage signal to the second terminal of the gating switch unit 10 connected to the selected memory cell structure 7 during the discharge operation of the selected memory cell structure 7.

[0076] In some embodiments, the peripheral circuit 2 includes a circuit control structure 4, a word line unit 3, and a signal control structure 5. The circuit control structure 4 is configured to select and read a target memory cell structure from a plurality of memory cell structures 6 of the memory array 1 to determine the storage state of the target memory cell structure. The components of the circuit control structure 4 can be equivalent to, for example, Figure 2 The circuit diagram shown is shown. The circuit control structure 4 includes multiple gating switch units 10 and multiple discharge switch units 20. The first end of each gating switch unit 10 is connected to a storage cell structure 6, and the second end is connected to a discharge switch unit 20. That is, each storage cell structure 6 corresponds to one gating switch unit 10 and one discharge switch unit 20.

[0077] When the turn-on switch unit 10 is turned on, the corresponding storage cell structure 6 can be considered as the selected storage cell structure 7, i.e., the aforementioned target storage cell structure. When binary data needs to be read from the selected storage cell structure 7, the corresponding operation state is "read," and when binary data needs to be written to the selected storage cell structure 7, the corresponding operation state is "write." This application uses the "read" operation state of the selected storage cell structure 7 as an example for explanation.

[0078] In some embodiments, such as Figure 2 As shown, the gating switch unit 10 includes:

[0079] The first bit line switch S3 has a third terminal and a fourth terminal. The third terminal is connected to the bit line terminal of the memory cell structure 6, and the fourth terminal is connected to the local bit line 11 of the memory array 1.

[0080] The second line switch S4 has a fifth terminal and a sixth terminal. The fifth terminal is connected to the fourth terminal of the first line switch S3, and the sixth terminal is connected to the discharge switch unit 20.

[0081] In some embodiments, the gating switch unit 10 includes a first bit line switch S3 connected to the bit line terminal of any memory cell structure 6, and a second bit line switch S4 connected to the first bit line switch S3 and the discharge switch unit 20, respectively. The third terminal of the first bit line switch S3 is the first terminal of the gating switch unit 10, and the sixth terminal of the second bit line switch S4 is the second terminal of the gating switch unit 10.

[0082] Figure 3 A first voltage change timing diagram provided for an exemplary embodiment of this disclosure, Figure 4 A first switch control timing diagram provided for an exemplary embodiment of this disclosure. Figure 3 According to the voltage of each part Figure 4 The changes occur due to the on or off states of the various switches within the system. For example... Figure 3 and Figure 4As shown, in some embodiments, the first line switch S3 is configured to remain on during the discharge and read operations of the selected memory cell structure 7.

[0083] The second bit line switch S4 is configured to: turn on for a partial time and then turn off during the discharge operation of the selected memory cell structure 7, and turn off for a partial time and then turn on during the read operation.

[0084] In some embodiments, such as Figure 3 and Figure 4 As shown, the first bit switch S3 and the second bit switch S4 are simultaneously turned on during the initialization operation. Specifically, the first bit switch S3 remains continuously turned on throughout the entire reading process of the selected memory cell structure 7; that is, the first bit switch S3 is turned on during the initialization operation and remains on until the reading of the selected memory cell structure 7 is completed, at which point it is turned off. The second bit switch S4 is turned on during the initialization operation, turns off after a partial time during the discharge operation phase, and turns on after a partial time during the read operation phase.

[0085] In some embodiments, the first bit line switch S3 and the second bit line switch S4 are simultaneously turned on during the initialization operation phase. The second bit line switch S4 is configured to be turned on for a partial time and then off for a partial time during the entire reading process of the selected memory cell structure 7. The continuous on-state of the first bit line switch S3 helps maintain accurate control and level recovery of the BL voltage. The timely off-state of the second bit line switch S4 after it is turned on during the discharge phase avoids over-discharge and path interference, reducing voltage noise. Simultaneously, the initial off-state followed by the on-state during the reading process avoids interference with the charge sharing process in the early stages of reading, effectively improving the voltage stability, discrimination accuracy, and anti-interference capability of the memory during the reading process, and to a certain extent reducing overall power consumption.

[0086] In some embodiments, the discharge switch unit 20 is connected to the gating switch unit 10, and the discharge switch unit 20 is turned on after the gating switch unit 10 is turned on, so as to provide a DC signal to the gating switch unit 10.

[0087] Specifically, such as Figure 2 As shown, the discharge switch unit 20 includes:

[0088] The voltage switch S2 is connected at one end to the second terminal of the gating switch unit 10 and at the other end to the negative voltage signal Vneg. The voltage switch S2 is configured to turn on during the discharge operation of the selected memory cell structure 7 to provide a reset voltage signal to the second terminal of the gating switch unit 10.

[0089] In some embodiments, the discharge switch unit 20 includes a voltage switch S2, one end of which is connected to the sixth terminal of the second bit line switch S4, and the other end is connected to the negative voltage signal Vneg. (See also...) Figure 3 as well as Figure 4 Voltage switch S2 is turned on in stage p3 and remains on until stage p6, then turns off in stage p7. Voltage switch S2 provides a reset voltage signal to the first line switch S3 and the second line switch S4, causing the BL voltage and LBL voltage to change from 0V to the value corresponding to the reset voltage signal. The reset voltage signal is equal to the negative voltage signal Vneg.

[0090] Voltage switch S2 is turned on during the discharge phase, which can quickly adjust the BL voltage and LBL voltage to the reset voltage signal, effectively realizing deep discharge and voltage reset of the node, thereby improving the voltage consistency and initialization stability of the node, and improving the reliability and accuracy of memory read operations. It can also shorten preprocessing time and improve overall read efficiency.

[0091] Please continue reading. Figure 2 The circuit control structure 4 also includes an initialization switch S1. One end of the initialization switch S1 is connected to the second terminal of the selection switch unit 10, and the other end is grounded. The initialization switch S1 is configured as follows:

[0092] When initializing the selected memory cell structure 7, the initialization switch S1 is turned off to provide an initialization signal Vss to the second terminal of the gating switch unit 10.

[0093] In some embodiments, please continue reading Figure 3 and Figure 4 Before initializing the selected memory cell structure 7, i.e., before performing any operations on the selected memory cell structure 7, the corresponding... Figure 3 and Figure 4 In the p1 stage, which is the inactive stage, the initialization switch S1 is turned on and the other switches in the circuit control structure 4 are turned off, so that the BL voltage and LBL voltage are maintained at the voltage value of the initialization signal Vss, that is, the BL voltage and LBL voltage are maintained at 0V.

[0094] When the selected memory cell structure 7 is initialized, corresponding to stage p2, the initialization switch S1 is turned off, and the first bit line switch S3 and the second bit line switch S4 are turned on.

[0095] Please continue reading. Figure 2 The circuit control structure 4 also includes an equalization switch S0, which has a seventh terminal and an eighth terminal, and the seventh terminal and the eighth terminal are respectively connected to the second terminal of two adjacent gating switch units 10.

[0096] The equalization switch S0 is configured such that its seventh terminal is connected to the selected memory cell structure 7, and during the discharge operation of the selected memory cell structure 7, a reference voltage Vref is obtained at its eighth terminal.

[0097] In some embodiments, the equalization switch S0 is connected to the second end of two adjacent gating switch units 10, that is, to the sixth end of the second bit line switch S4 of the two adjacent gating switch units 10. One end of the equalization switch S0 is connected to the selected memory cell structure 7 through the gating switch unit 10, and the other end is connected to the unselected memory cell structure 7 through the gating switch unit 10.

[0098] In some embodiments, the equalization switch S0 includes a seventh terminal and an eighth terminal. The seventh terminal is connected to the selected memory cell structure 7, and the eighth terminal is connected to the unselected memory cell structure 7. The seventh terminal corresponds to the DL voltage, and the eighth terminal corresponds to the Unsel DL voltage. During the p8-p9 phase of the read operation, the Unsel DL voltage value is the reference voltage Vref.

[0099] Please continue reading. Figure 2 The circuit control structure 4 also includes a compensation capacitor 30, one end of which is connected to the eighth terminal of the equalization switch S0, and the other end is connected to the discharge switch unit 20.

[0100] The compensation capacitor 30 is configured to adjust the voltage value of the reference voltage Vref by adjusting the capacitance value of the compensation capacitor 30.

[0101] In some embodiments, one end of the compensation capacitor 30 is connected to the eighth terminal of the equalization switch S0 corresponding to the selected memory cell structure 7, and the other end is connected to the discharge switch unit 20 corresponding to the unselected memory cell structure 7.

[0102] In some embodiments, the first line switch S3 corresponds to a first parasitic capacitance, the second line switch S4 corresponds to a second parasitic capacitance, and the third terminal of the equalization switch S0 corresponds to a third parasitic capacitance. The capacitance value during the discharge process may include the sum of the first parasitic capacitance, the second parasitic capacitance, the third parasitic capacitance, and the capacitance value of the compensation capacitor 30.

[0103] In some embodiments, the reference voltage Vref is negatively correlated with the on-time of the equalization switch S0 and positively correlated with the capacitance value during the discharge process. Therefore, a compensation capacitor 30 is introduced at the fourth terminal of the equalization switch S0, and the reference voltage Vref is adjusted by adjusting the capacitance value of the compensation capacitor 30. Alternatively, the reference voltage Vref can also be adjusted by adjusting the on-time of the equalization switch S0.

[0104] In some embodiments, the word line unit 3 further includes a word line switch, the specific location of which is... Figure 2 It is not shown in the diagram, but it is clear that one end of it is connected to the word line corresponding to the selected memory cell structure 7, and in conjunction with... Figure 3 as well as Figure 4 It can be seen that the WL switch is turned on in stage p5 and continues to be turned on until stage p7, and is turned off in stage p8, so that the WL voltage increases in stage p5 and decreases in stage p8.

[0105] like Figure 3 and Figure 4 As shown, during the p8 stage, the WL voltage drops, and the second bit line switch S4 turns on again. The equalization switch S0 is already off, and the second bit line switch S4 turns on, enabling charge sharing between BL, LBL, and DL, achieving a new voltage balance. This process satisfies the following:

[0106]

[0107] In a specific embodiment, assume C bl :C lbl :C dl = 1:1:2, and for the selected memory cell structure 7, when performing a "1" state operation, V bl =V lbl = -500mV, V when performing a "0" state operation bl =V lbl = -2.2V,V dl = -2.5V.

[0108] According to the above formula, when performing a "1" state operation... When performing a "0" state operation Assume V ref = -1.925V, then the reading window voltage is 425mV.

[0109] In another specific embodiment, when the second bit line switch S4 is turned off, it is still assumed that C bl :C lbl :C dl = 1:1:2, and for the selected memory cell structure 7, when performing a "1" state operation, V bl = -500mV, V when performing a "0" state operation bl =-2V,V lbl =V dl = -2.5V.

[0110] According to the above formula, when performing a "1" state operation... When performing a "0" state operation Assume V ref= -2.1875V, then the reading window voltage is 187mV.

[0111] Therefore, during the read operation, an electrical connection is established between BL, LBL, and DL during the WL voltage drop phase, forming a complete charge-sharing path. This allows for a significant voltage difference between BL and DL corresponding to the data state of memory cell structure 6, thereby expanding the read window voltage. When the second bit line switch S4 is turned on, a larger read voltage difference can be obtained between memory cell structures 6 with storage states of "1" and "0", which can improve the discrimination margin, thereby improving the accuracy and reliability of the read operation and reducing the false positive rate.

[0112] Please continue reading. Figure 2 The circuit control structure 4 also includes a comparator 40, whose input terminals are connected to the seventh and eighth terminals of the equalization switch S0, respectively, and whose output terminal outputs a read signal.

[0113] In some embodiments, the circuit control structure 4 further includes a comparator 40 connected to both ends of the equalization switch S0. The comparator 40 acquires and compares the DL voltage and the UnselDL voltage, and outputs the comparison result as the read signal corresponding to the selected memory cell structure 7. The read signal represents the storage state corresponding to the selected memory cell structure 7.

[0114] In some embodiments, the seventh terminal of the equalization switch S0 is connected to the sixth terminal of the second bit line switch S4, and when the selected memory cell structure 7 is turned on, the voltage values ​​of DL, BL, and LBL are equal and change synchronously. The eighth terminal of the equalization switch S0 corresponds to the Unsel DL voltage, and the voltage value of the Unsel DL voltage is equal to the reference voltage Vref during the read operation. Therefore, the comparator 40 connected to both ends of the equalization switch S0 can acquire the DL voltage and the Unsel DL voltage respectively. By comparing the DL voltage and the Unsel DL voltage, the relationship between the BL voltage and the reference voltage Vref can be determined, and a read signal can be output to determine the storage state corresponding to the selected memory cell structure 7. The storage state includes a "0" state and a "1" state.

[0115] Please continue reading. Figure 3 It can be seen that when the selected memory cell structure 7 is in the "0" state, the voltage value of BL remains unchanged from the reset voltage signal and is less than the voltage value of the reference voltage Vref. When the selected memory cell structure 7 is in the "1" state, the voltage value of BL increases from the reset voltage signal and is greater than the voltage value of the reference voltage Vref.

[0116] Figure 3In the voltage change timing diagram shown, due to the voltage difference between WL and BL, the selected memory cell structure 7 has a subthreshold conduction current in a non-ideal state. Therefore, when the selected memory cell structure 7 is in the "0" state, the BL voltage will still partially charge, and the smaller the BL capacitance, the greater the charge amplitude of the BL voltage. If we consider it as an ideal state, the BL voltage will not charge and will remain stable at the reset voltage signal.

[0117] Please see Figure 1 The peripheral circuit 2 of the memory also includes: a signal control structure 5, configured as follows:

[0118] An initialization operation is performed, during which the control gating switch unit 10 is turned on;

[0119] After the initialization operation, the discharge operation is performed. During the discharge operation, the discharge switch unit 20 is turned on and the gating switch unit 10 is turned on for a period of time and then turned off.

[0120] After the discharge operation, the read operation is performed. During the read operation phase, the selected memory cell structure 7 remains on, and the discharge switch unit 20 is turned off after being turned on for a certain period of time.

[0121] In some embodiments, the signal control structure 5 is configured to control the on and off states of each switch. Please refer to... Figure 3 as well as Figure 4 , Figure 3 as well as Figure 4 In the diagram, stage p1 corresponds to the inactive stage, stage p2 corresponds to the initialization stage, stages p3, p4, and p5 correspond to the discharge stage, and stages p6-p9 correspond to the read stage.

[0122] according to Figure 4 As can be seen, based on the control of signal control structure 5, initialization switch S1 is turned on in stage p1, turned off in stage p2, and remains turned off until the end of the reading process. First bit line switch S3 and second bit line switch S4 are turned on in stage p2, with first bit line switch S3 remaining on until the end of the reading process; second bit line switch S4 remains on until stage p3 of the discharge operation phase, turns off in stage p4, remains off until stage p7 of the reading operation phase, and turns off in stage p8. Voltage switch S2 and equalization switch S0 are turned on in stage p3, remain on until stage p6, and turn off in stage p7. The WL switch is turned on in stage p5, remains on until stage p7, and turns off in stage p8, so that the WL voltage increases in stage p5 and decreases in stage p8.

[0123] Another circuit timing control method according to an embodiment of this application is as follows: Figure 5 as well as Figure 6As shown, the first line switch S3 is configured to: turn on for a partial time and then turn off during the discharge operation of the selected memory cell structure 7, and turn off for a partial time and then turn on during the read operation.

[0124] The second bit line switch S4 is configured to remain on during the discharge and read operations of the selected memory cell structure 7.

[0125] In this embodiment, the coupling relationships of the initialization switch S1, voltage switch S2, equalization switch S0, first bit line switch S3, and second bit line switch S4 in the circuit control structure 4 are all related to... Figure 3 and Figure 4 The configuration functions of the initialization switch S1, voltage switch S2, and equalization switch S0 are the same as in the previous embodiments. In this embodiment, the configuration functions of the first line switch S3 and the second line switch S4 have changed, and these changes will be explained below. Other structures will not be described in detail here.

[0126] In some embodiments, such as Figure 3 and Figure 4 As shown, the first bit line switch S3 and the second bit line switch S4 are simultaneously turned on during the initialization operation. Specifically, the second bit line switch S4 remains continuously turned on throughout the entire reading process of the selected memory cell structure 7; that is, the second bit line switch S4 is turned on during the initialization operation and remains on until the reading of the selected memory cell structure 7 is completed, at which point it is turned off. The first bit line switch S3 is turned on during the initialization operation, turned on for a partial time during the discharge operation phase, and turned on again after being turned off for a partial time during the read operation phase.

[0127] In this embodiment, the configuration function settings of the first line switch S3 and the second line switch S4 can also achieve the same technical effect as in the previous embodiment.

[0128] Accordingly, this application also provides a memory, including:

[0129] Storage array 1, comprising multiple storage cell structures 6;

[0130] like Figure 2 The peripheral circuit 2 shown is connected to the storage array 1. During the reading process of the storage cell structure 6, the signal control structure 5 controls the circuit control structure 4 to obtain the following... Figure 3 and Figure 4 The temporal changes are shown.

[0131] Accordingly, this application also discloses a method for operating a memory, such as... Figure 7 As shown, it includes:

[0132] S10: In the non-operation stage p1, the initialization switch S1 is turned on to provide the initialization signal Vss to the seventh terminal of the first line switch S3, the second line switch S4 and the equalization switch S0.

[0133] In some embodiments, the inactive phase may correspond to a phase where the selected memory cell structure 7 is not read, or it may correspond to a state where the memory cell structure 6 is not selected. Please refer to [link to documentation]. Figure 3 as well as Figure 4 At this time, the initialization switch S1 is turned on, the other switches are turned off, and the voltages BL, DL, LBL and Unsel DL are all 0V.

[0134] S20: Initialization phase p2, turns on the first bit line switch S3 and the second bit line switch S4 to control the operation state of the memory cell structure 6;

[0135] In some embodiments, please refer to Figure 3 as well as Figure 4 During the initialization phase, the first bit line switch S3 and the second bit line switch S4 are turned on, making memory cell structure 6 the selected memory cell structure 7. At this time, since the other switches are still in the off state, the BL voltage, DL voltage, LBL voltage, and Unsel DL voltage remain at 0V.

[0136] S30: During the discharge operation phase p3, the voltage switch S2 is turned on to provide a reset voltage signal to the second terminal of the gating switch unit 10; and the equalization switch S0 is turned on to generate a reference voltage Vref at the eighth terminal of the equalization switch S0.

[0137] S40: Discharge operation stage p4, turn off the second position line switch S4;

[0138] S50: During the discharge operation phase p5, the WL switch is turned on, causing the WL voltage to rise;

[0139] In some embodiments, please refer to Figure 3 as well as Figure 4 The discharge operation is performed after the initialization operation.

[0140] In the p3 stage, which is the first operation stage of the discharge operation, the voltage switch S2 is turned on and provides a reset voltage signal, so that the BL voltage, DL voltage and LBL voltage change from 0V to the voltage value Vneg corresponding to the reset voltage signal.

[0141] In phase p3, the equalization switch S0 is turned on, and the seventh and eighth terminals of the equalization switch S0 are connected, making the equalization switch S0 equivalent to a finite resistor and generating a reference voltage Vref, so that the voltage value of the Unsel DL voltage at the eighth terminal is equal to the voltage value of the reference voltage Vref.

[0142] In stage p4, the second operation phase of the discharge process, the second bit line switch S4 is turned off, reducing the parasitic capacitance connected to BL, improving voltage accuracy during the reading phase, and reducing noise interference and leakage errors. At this time, the first bit line switch S3 remains on.

[0143] In stage p5, the third stage of the discharge operation, after the BL, DL, and LBL voltages change in stage p3 and remain stable through stage p4, the WL switch is turned on, the WL voltage increases, and the BL voltage is charged. When the WL voltage rises to the point where the voltage difference between the WL and BL voltages equals the threshold voltage corresponding to the selected memory cell structure 7 in the "1" state, the selected memory cell structure 7 is turned on. At this time, the first bit line switch S3 remains on, and the second bit line switch S4 remains off.

[0144] S60: During the read operation phases p6-p7, the selected memory cell structure 7 is turned on, and the WL switch and the first line switch S3 remain on; in addition, the voltage switch S2 and the equalization switch S0 are turned on during phase p6 and turned off during phase p7.

[0145] In some embodiments, the voltage difference between the WL voltage and the BL voltage remains stable after the p5 stage and reaches the threshold voltage corresponding to the selected memory cell structure 7 in the "1" state. Therefore, the selected memory cell structure 7 is turned on in the p6 stage and remains turned on.

[0146] In some embodiments, the voltage switch S2 and the equalization switch S0 are turned off in stage p6 and in stage p7, which can improve voltage stability and reduce the perception error or drift caused by premature path disconnection, thereby improving the discrimination accuracy and reliability of memory read operations.

[0147] S70: During the read operation phase p8-p9, the selected memory cell structure 7 remains on, the WL switch is off, and the first bit line switch S3 and the second bit line switch S4 are on.

[0148] In some embodiments, during the p8 stage, after the reading is completed, the WL switch is turned off and the WL voltage gradually decreases; during the p9 stage, the BL voltage, DL voltage, LBL voltage, and Unsel DL voltage return to 0V.

[0149] The aforementioned memory operation method can improve read accuracy and expand the voltage window while reducing power consumption. By turning off the second bit line switch S4, unnecessary charge-sharing paths can be effectively isolated, thereby reducing voltage crosstalk. Delaying the turn-off of voltage switch S2 and equalization switch S0 during the p6-p7 stage ensures the integrity of the charge-sharing path and the stability of the reference level during the read operation of the memory cell structure 6, thus forming a larger read window and enhancing the accuracy of determining the state of the memory cell structure 6.

[0150] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0151] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0152] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0153] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent variations, or alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application. The terminology used herein is chosen to best explain the principles, practical applications, or technical improvements to the market of the various embodiments, or to enable other persons skilled in the art to understand the various embodiments disclosed herein.

Claims

1. A memory, the memory comprising a memory array and peripheral circuitry, the memory array comprising a plurality of memory cell structures, the peripheral circuitry being electrically connected to the memory cell structures, characterized in that, The peripheral circuit includes: Multiple gating switch units, each gating switch unit including a first terminal and a second terminal, wherein the first terminal is connected to a bit line terminal of any of the memory cell structures, and the gating switch unit is configured to: Controlling the operational state of the storage unit structure; During the discharge operation of the selected memory cell structure, it is continuously turned on or turned on for a partial time and then turned off; Multiple discharge switch units, each of the discharge switch units being connected to the second terminal of any of the gating switch units, wherein the discharge switch unit is configured to provide a reset voltage signal to the second terminal of the gating switch unit connected to the selected memory cell structure during a discharge operation on the selected memory cell structure; The selection switch unit includes a first bit line switch and a second bit line switch connected in series. During the discharge operation of the selected memory cell structure, the first bit line switch is continuously turned on, and the second bit line switch is turned off after being turned on for a partial time.

2. The memory according to claim 1, characterized in that, The first bit line switch has a third terminal and a fourth terminal, the third terminal being connected to the bit line terminal of the memory cell structure, and the fourth terminal being connected to the local bit line of the memory array; The second bit line switch has a fifth terminal and a sixth terminal, the fifth terminal being connected to the fourth terminal of the first bit line switch, and the sixth terminal being connected to the discharge switch unit.

3. The memory according to claim 2, characterized in that, The first bit line switch is configured to remain on during a read operation on the selected memory cell structure; The second bit line switch is configured to be turned on after being turned off for a period of time during a read operation on the selected memory cell structure.

4. The memory according to claim 1, characterized in that, The discharge switch unit includes: A voltage switch, one end of which is connected to the second terminal of the gating switch unit and the other end of which is connected to a negative voltage signal, is configured to turn on during a discharge operation of the selected memory cell structure to provide the reset voltage signal to the second terminal of the gating switch unit.

5. The memory according to claim 1, characterized in that, The peripheral circuit also includes an equalization switch. The equalization switch has a seventh terminal and an eighth terminal, and the seventh terminal and the eighth terminal are respectively connected to the second terminal of two adjacent gating switch units; The equalization switch is configured such that the seventh terminal is connected to the selected memory cell structure, and a reference voltage is obtained at the eighth terminal during the discharge operation of the selected memory cell structure.

6. The memory according to claim 1, characterized in that, The peripheral circuit also includes: The signal control structure is configured as follows: An initialization operation is performed, during which the gating switch unit is turned on. After the initialization operation, a discharge operation is performed. During the discharge operation, the discharge switch unit is controlled to be turned on, and the gating switch unit is controlled to be turned off after being turned on for a partial time. A read operation is performed after the discharge operation. During the read operation phase, the selected storage cell structure remains open, and the discharge switch unit is turned off after being turned on for a certain period of time.

7. A method of operating a memory as described in any one of claims 1-6, characterized in that, include: An initialization operation is performed to activate the gating switch unit, thereby controlling the operating state of the memory cell structure; After the initialization operation, a discharge operation is performed, the discharge switch unit is turned on to provide a reset voltage signal to the second terminal of the gating switch unit, the first bit switch of the gating switch unit is continuously turned on, and the second bit switch of the gating switch unit is turned off after being turned on for a partial time. A read operation is performed after the discharge operation to enable the selected memory cell structure.

8. The method of operating the memory according to claim 7, characterized in that, The discharge operation includes a first operation stage, a second operation stage, and a third operation stage; the peripheral circuit also includes an equalization switch. The discharge operation includes: In the first operation phase, the equalization switch is turned on to generate a reference voltage at the eighth terminal of the equalization switch; the equalization switch remains on in the second operation phase and the third operation phase.

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