Operation method of memory, memory and memory system

Abstract

The invention relates to the technical field of memories, and discloses a memory operation method, a memory and a memory system.The method comprises the steps that in the verification stage of a first programming loop, a first bit line voltage is provided for a bit line coupled with a first memory unit; the first storage unit is a storage unit which is coupled with a selection word line and is to be programmed to a first programming state, and the first programming cycle is a programming cycle which needs to verify the first storage unit; providing a second bit line voltage for a bit line coupled to the first memory cell in a verification phase of a second programming loop; the second programming loop is a programming loop which needs to verify the first storage unit after the first programming loop, and the second bit line voltage is smaller than the first bit line voltage. According to the invention, the problem of threshold voltage distribution broadening caused by common source noise can be improved, and the threshold voltage distribution width of the storage unit can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a memory operation method, a memory, and a memory system. Background Art

[0002] NAND memory is a nonvolatile memory device widely used in embedded products such as digital cameras and portable memory cards. With the development of NAND memory, its storage cells can correspond to multiple programming states. To meet higher reliability requirements, the width of the threshold voltage (Vth) distribution of each programming state must be limited.

[0003] However, during the programming operation of the NAND memory, the threshold voltage distribution of the programmed state is easily widened. How to reduce the width of the threshold voltage distribution of the programmed state is a key issue. Summary of the Invention

[0004] In view of this, the present invention provides a memory operating method, a memory, and a memory system to solve the problem of excessively wide distribution of threshold voltages of programmed states during programming operations.

[0005] In a first aspect, the present invention provides a method for operating a memory, comprising:

[0006] In a verification phase of a first programming loop, a first bit line voltage is provided to a bit line coupled to a first memory cell; the first memory cell is a memory cell coupled to a selected word line and to be programmed to a first programming state, and the first programming loop is a programming loop in which verification of the first memory cell is required;

[0007] During the verification phase of a second programming loop, a second bit line voltage is provided for the bit line coupled to the first memory cell; the second programming loop is a programming loop that is performed after the first programming loop and requires verification of the first memory cell, and the second bit line voltage is less than the first bit line voltage.

[0008] In some optional embodiments, the method further includes: providing a third bit line voltage for a bit line coupled to the first memory cell during a verification phase of a third programming loop, wherein the third programming loop is a programming loop after the second programming loop and requires verification of the first memory cell, and the third bit line voltage is less than the second bit line voltage.

[0009] In some optional implementations, a voltage difference between the first bit line voltage and the second bit line voltage is equal to a voltage difference between the second bit line voltage and the third bit line voltage.

[0010] In some optional embodiments, the method further includes: providing the first bit line voltage to the bit line coupled to the first memory cell during a verification phase of a fourth programming loop between the first programming loop and the second programming loop; the fourth programming loop is a programming loop that requires verification of the first memory cell.

[0011] In some optional embodiments, the method further includes: providing the second bit line voltage to the bit line coupled to the first memory cell during a verification phase of a fifth programming loop between the second programming loop and the third programming loop; the fifth programming loop is a programming loop that requires verification of the first memory cell.

[0012] In some optional embodiments, the method further includes: when a count value of a programming loop for verifying the first storage cell exceeds a preset value, providing a fixed bit line voltage for a bit line coupled to the first storage cell in a subsequent programming loop for verifying the first storage cell.

[0013] In some optional embodiments, the method further includes: in the verification phase of the first programming loop or the second programming loop, verifying a second storage cell coupled to the selection word line and to be programmed to a second programming state, the bit line voltage coupled to the second storage cell being the same as the first bit line voltage or the second bit line voltage.

[0014] In some optional embodiments, the method further includes: in the verification phase of the first programming loop or the second programming loop, providing the same bit line voltage to a plurality of memory cells coupled to the selection word line that are to be programmed to the first programming state and have not reached the first programming state.

[0015] In some optional implementations, the method further includes: after the first storage cell reaches the first programming state, prohibiting programming of the first storage cell.

[0016] In a first aspect, the present invention provides a method for operating a memory, wherein the memory includes a plurality of memory cells coupled to a same selected word line, and performing a programming operation on the plurality of memory cells includes performing a plurality of programming loops, the method comprising:

[0017] providing a first bit line voltage to a bit line coupled to a memory cell to be programmed to a certain program state among the plurality of memory cells during a verification phase of a first program loop among the plurality of program loops; and

[0018] providing a second bit line voltage to a bit line coupled to a memory cell to be programmed to the programmed state among the plurality of memory cells during a verification phase of a second programming loop among the plurality of programming loops;

[0019] The second programming loop is after the first programming loop, and the second bit line voltage is lower than the first bit line voltage.

[0020] In some optional embodiments, the plurality of programming loops include a first programming loop group and a second programming loop group, the first programming loop group includes a plurality of the first programming loops, and the second programming loop group includes a plurality of the second programming loops, and the method further includes:

[0021] During the verification phase of the multiple first programming loops, the first bit line voltage is provided to the bit lines coupled to the memory cells to be programmed to the programmed state among the multiple memory cells, and during the verification phase of the multiple second programming loops, the second bit line voltage is provided to the bit lines coupled to the memory cells to be programmed to the programmed state among the multiple memory cells.

[0022] In a third aspect, the present invention provides a memory comprising: a memory array, a peripheral circuit, and a plurality of bit lines;

[0023] The memory array includes a plurality of memory strings, and the memory strings include a plurality of memory cells;

[0024] The plurality of bit lines are respectively coupled to the plurality of memory strings;

[0025] The peripheral circuit is coupled to the memory array and is configured to:

[0026] In a verification phase of a first programming loop, a first bit line voltage is provided to a bit line coupled to a first memory cell; the first memory cell is a memory cell coupled to a selected word line and to be programmed to a first programming state, and the first programming loop is a programming loop in which verification of the first memory cell is required;

[0027] During the verification phase of a second programming loop, a second bit line voltage is provided for the bit line coupled to the first memory cell; the second programming loop is a programming loop that is performed after the first programming loop and requires verification of the first memory cell, and the second bit line voltage is less than the first bit line voltage.

[0028] In some optional embodiments, the peripheral circuit is further configured to: provide a third bit line voltage for the bit line coupled to the first memory cell during a verification phase of a third programming loop, wherein the third programming loop is a programming loop after the second programming loop and requires verification of the first memory cell, and the third bit line voltage is less than the second bit line voltage.

[0029] In some optional implementations, a voltage difference between the first bit line voltage and the second bit line voltage is equal to a voltage difference between the second bit line voltage and the third bit line voltage.

[0030] In some optional embodiments, the peripheral circuit is further configured to: provide the first bit line voltage to the bit line coupled to the first storage cell during a verification phase of a fourth programming loop between the first programming loop and the second programming loop; the fourth programming loop is a programming loop that requires verification of the first storage cell.

[0031] In some optional embodiments, the peripheral circuit is further configured to: provide the second bit line voltage to the bit line coupled to the first storage cell during a verification phase of a fifth programming loop between the second programming loop and the third programming loop; the fifth programming loop is a programming loop that requires verification of the first storage cell.

[0032] In some optional embodiments, the peripheral circuit is further configured to: when the count value of the programming loop for verifying the first storage cell exceeds a preset value, provide a fixed bit line voltage for the bit line coupled to the first storage cell in a subsequent programming loop for verifying the first storage cell.

[0033] In some optional embodiments, the peripheral circuit is further configured to: in the verification phase of the first programming loop or the second programming loop, verify the second storage cell coupled to the selection word line and to be programmed to the second programming state, and the bit line voltage coupled to the second storage cell is the same as the first bit line voltage or the second bit line voltage.

[0034] In some optional embodiments, the peripheral circuit is further configured to: provide the same bit line voltage to a plurality of memory cells coupled to the selection word line that are to be programmed to the first programming state and have not reached the first programming state during the verification phase of the first programming loop or the second programming loop.

[0035] In some optional implementations, the peripheral circuit is further configured to: prohibit programming of the first storage cell after the first storage cell reaches the first programming state.

[0036] In a fourth aspect, the present invention provides a memory system, comprising: one or more memories according to the third aspect;

[0037] A memory controller coupled to the memory and configured to control the memory.

[0038] By adjusting the bitline voltage provided during the verification phase of different programming cycles, the present invention can improve the threshold voltage distribution widening caused by common source noise, effectively reducing the threshold voltage distribution width of the memory cell and increasing the read window. This method does not require additional circuitry, which can reduce costs, and does not require multiple reads, which does not sacrifice read time, while also ensuring subsequent read efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0040] Figure 1 is a structural diagram of a memory according to an embodiment of the present invention;

[0041] Figure 2 is a schematic diagram of a threshold voltage distribution of a TLC memory cell according to an embodiment of the present invention;

[0042] Figure 3 is a flow chart of a method for operating a memory according to an embodiment of the present invention;

[0043] Figure 4 is a schematic diagram illustrating the effect of common source noise on threshold voltage distribution according to an embodiment of the present invention;

[0044] Figure 5 is a waveform diagram of a programming verification process according to an embodiment of the present invention;

[0045] Figure 6 is a schematic diagram of a threshold voltage distribution according to an embodiment of the present invention;

[0046] Figure 7 is another waveform diagram of a programming verification process according to an embodiment of the present invention;

[0047] Figure 8 1 is another waveform diagram of a program verification process according to an embodiment of the present invention;

[0048] Figure 9 is another flowchart of a method for operating a memory according to an embodiment of the present invention;

[0049] Figure 10 is a structural diagram of a memory according to an embodiment of the present invention;

[0050] Figure 11is a structural diagram of a peripheral circuit according to an embodiment of the present invention;

[0051] Figure 12 is a structural diagram of a memory system according to an embodiment of the present invention;

[0052] Figure 13 is a structural diagram of a memory card according to an embodiment of the present invention;

[0053] Figure 14 FIG. 4 is a schematic structural diagram of a solid-state drive according to an embodiment of the present invention. DETAILED DESCRIPTION

[0054] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0055] Figure 1 A schematic diagram of a memory structure according to an embodiment of the present invention is shown. The memory may be a NAND memory, such as a 3D NAND memory. The memory includes one or more memory blocks 100. Each memory block 100 includes a plurality of memory cells 101 arranged in an array; a plurality of memory cells 101 are connected in series to form a memory string 111. Figure 1 As shown, multiple memory cells 101 in each column can form a memory string 111, and the memory string 111 is coupled to a bit line (BitLine, BL). In addition, the memory cells 101 sharing the same word line (WordLine, WL) can form a memory page (Page) 112, which is a physical page; Figure 1 As shown, multiple memory cells 101 in each row share the same word line and can form a memory page 112; Figure 1 Take the example where the memory block 100 corresponds to 4 memory strings 111 and m memory pages 112 .

[0056] At least one control device may be provided at both ends of each storage string 111 to achieve selection control of the storage string 111. Figure 1As shown, a drain select gate (DSG) transistor 102 (also known as a top select gate (TSG) transistor) is provided at the drain end of a memory string 111, and a source select gate (SSG) transistor 103 (also known as a bottom select gate (BSG) transistor) is provided at the source end. The drain terminal of the drain select gate transistor 102 is connected to a corresponding bit line, and the source terminal of the source select gate transistor 103 is connected to a common source (ACS) 113 of the memory cell array. All memory strings 111 in the memory block 100 can be connected to the common source 113. The corresponding memory string 111 is selected by controlling the gate of the drain select gate transistor 102 and the gate of the source select gate transistor 103.

[0057] In some embodiments, each storage string 111 is configured to be selected or deselected by applying a selection voltage (e.g., a positive voltage higher than the threshold voltage of the drain select gate transistor 102) or a deselection voltage (e.g., a ground voltage) to the gate of the corresponding drain select gate transistor 102 via one or more DSG lines 114, and / or applying a selection voltage (e.g., a positive voltage higher than the threshold voltage of the source select gate transistor 103) or a deselection voltage (e.g., a ground voltage) to the gate of the corresponding source select gate transistor 103 via one or more SSG lines 115.

[0058] The memory cell 101 may be a single-level cell (SLC), i.e., one memory cell 101 stores one bit of data, in which case each memory cell 101 has two states, specifically 0 and 1. Alternatively, the memory cell 101 may be a multi-level cell (MLC), i.e., one memory cell 101 stores two bits of data, in which case each memory cell 101 has four states, specifically 00, 01, 10, and 11. Alternatively, the memory cell 101 may be a triple-level cell (TLC), i.e., one memory cell stores three bits of data, in which case each memory cell 101 has eight states, specifically 000, 001, 010, 011, 100, 101, 110, and 111. The memory cell 101 may also be a cell with more levels, which is not limited in this embodiment. When the memory cell 101 is an MLC or TLC, a physical page of storage page 112 includes multiple logical pages.

[0059] Taking a TLC memory cell as an example, the eight states of a TLC memory cell can be specifically 1 erased state and 7 programmed states. The erased state is recorded as L0, and the programmed states are recorded as L1, L2, L3, L4, L5, L6 and L7 from the 1st state to the 7th state. The threshold voltage distribution corresponding to each state can be seen in Figure 2 shown.

[0060] The operation of NAND memory consists of three parts: erase operation, programming operation (i.e., write operation) and read operation. The erase operation can be performed in units of blocks, and the programming operation and read operation can be performed in units of pages. For the programming operation of NAND memory, the process can include the pressure programming (i.e., applying programming pulses) stage and the program verification (PV) stage. For the convenience of description, the pressure programming stage will be referred to as the programming stage, and the program verification stage will be referred to as the verification stage.

[0061] The programming operation can be implemented using an incremental step pulse program (ISPP) method, which requires multiple programming loops, each of which includes a corresponding programming phase and a verification phase. During the programming phase of each programming loop, a certain pulse is provided to the word line to inject electrons into the storage layer of the memory cell 101 (for example, for a charge trap type memory cell, the storage layer is a charge trap layer; for a floating gate type memory cell, the storage layer is a floating gate). Each time a programming pulse is applied, the threshold voltage of the memory cell 101 can be read and verified in the verification phase to detect whether its threshold voltage has reached the desired target programming state. If the threshold voltage has reached the desired target programming state, electron injection is stopped. Otherwise, the above process of injecting electrons and verifying the threshold voltage is continued in the next programming loop until the threshold voltage of the memory cell 101 reaches the target programming state. For example, through the above programming operation, a TLC memory cell can be programmed to the L1 state, L2 state, L3 state, etc.

[0062] During a NAND memory programming operation, the channel current in memory cell 101 affects the threshold voltage of memory cell 101, causing the threshold voltage distribution of the programmed state to widen. For example, the common source (ACS) voltage divider reduces the string sense current, forming common source noise (ACS noise), which causes the threshold voltage distribution to widen. Common source noise can be improved by adding common source circuits or performing multiple reads (e.g., coarse reads). However, common source circuits increase the circuit area of ​​the NAND memory, and multiple reads sacrifice read time.

[0063] An embodiment of the present invention provides a memory operation method, which compensates for the effect of reduced channel current by providing different bit line voltages in verification phases of different programming cycles, thereby reducing the width of threshold voltage distribution.

[0064] According to an embodiment of the present invention, an embodiment of a method for operating a memory is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0065] In this embodiment, a memory operation method is provided, which can be used for NAND memory, etc. Figure 3 is a flow chart of an operating method according to an embodiment of the present invention, such as Figure 3 As shown, the process includes the following steps S301 to S302.

[0066] In step S101 , during a verification phase of a first programming loop, a first bit line voltage is provided to a bit line coupled to a first memory cell.

[0067] Step S102 , in a verification phase of a second programming loop, providing a second bit line voltage to a bit line coupled to the first memory cell; the second bit line voltage is lower than the first bit line voltage.

[0068] Among them, the first storage cell is a storage cell coupled to the selection word line and to be programmed to the first programming state, the first programming loop is a programming loop that requires verification of the first storage cell; the second programming loop is a programming loop that requires verification of the first storage cell after the first programming loop.

[0069] When programming a memory cell in a memory, a programming voltage may be applied to a selected word line to program the memory cell coupled to the selected word line to a desired target, that is, to a target programming state. Figure 1 Taking the memory shown as an example, if the word line WL2 is the selected word line, the memory cells in the same row coupled to the selected word line WL2 can be programmed. After one or more programming cycles, these memory cells can be programmed to their respective desired target programming states.

[0070] The select word line can be coupled to multiple memory cells, some of which typically have different target programming states. For example, in the case of TLC memory cells, some of the memory cells coupled to the select word line may have a target programming state of L1, some of the memory cells may have a target programming state of L2, and so on, and some of the memory cells may have a target programming state of L7, depending on the actual situation.

[0071] In this embodiment, a target programming state is referred to as a first programming state, and a memory cell to be programmed to the first programming state is referred to as a first memory cell. For example, if the first programming state is the L2 state, the first memory cell is the memory cell to be programmed to the L2 state. Furthermore, generally, the select word line is coupled to a plurality of first memory cells, i.e., among the memory cells coupled to the select word line, there are a plurality of first memory cells to be programmed to the first programming state.

[0072] Programming multiple memory cells coupled to a selected word line requires multiple programming cycles, and programming a memory cell to a desired target programming state may also require multiple programming cycles; therefore, a first memory cell coupled to a selected word line may need to go through multiple programming cycles, and the first memory cell needs to be verified in multiple programming cycles.

[0073] In this embodiment, if the first memory cell needs to undergo multiple programming cycles, the programming cycle in which the first memory cell needs to be verified is referred to as the first programming cycle, and the other programming cycle in which the first memory cell needs to be verified is referred to as the second programming cycle; wherein the second programming cycle is performed after the first programming cycle. The second programming cycle and the first programming cycle may be adjacent to each other or separated by other programming cycles.

[0074] Table 1 shows the verification results for a certain programming scheme. As shown in Table 1, after 16 programming loops, the memory cells to be programmed to the L1 to L7 states are programmed and verified. During the first through fifth programming loops, the memory cells to be programmed to the L1 state are verified; during the third through seventh programming loops, the memory cells to be programmed to the L2 state are verified, and so on. If the first programming state is the L1 state, then the first memory cell may need to be programmed and verified five times.

[0075] Table 1

[0076] Loop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 L1 V V V V V L2 V V V V V L3 V V V V L4 V V V V V L5 V V V V V L6 V V V V V L7 V V V V

[0077] For example, if the first programming state is the L1 state, and the first storage unit needs to be verified in the first programming loop to the fifth programming loop, the first programming loop may be the first programming loop and the second programming loop may be the second programming loop, or the first programming loop may be the second programming loop and the second programming loop may be the third programming loop, or the first programming loop may be the second programming loop and the second programming loop may be the fourth programming loop; or the programming loops may be grouped, and the first programming loop and the second programming loop belong to different groups, for example, the first programming loop and the second programming loop are one group, and the third programming loop and the fourth programming loop are another group, the first programming loop may be the first programming loop or the second programming loop, and the second programming loop may be the third programming loop or the fourth programming loop, which is not limited in this embodiment.

[0078] It should be noted that the first storage cell in this embodiment is a storage cell that still needs to be verified whether its programming state reaches the first programming state in the first programming loop and the second programming loop, that is, the first storage cell still needs to be verified in the first programming loop and the second programming loop. In other words, the first storage cell failed to pass the verification in the previous programming loop of the first programming loop and the previous programming loop of the second programming loop. If the first storage cell passes the verification (pass) in a certain programming loop, it means that the first storage cell has been programmed to the first programming state and is no longer a storage cell to be programmed, and the first storage cell does not need to be verified in subsequent programming loops. Therefore, after the first storage cell reaches the first programming state, programming of the first storage cell is prohibited, and verification of the first storage cell is not required. The subsequent programming loops are not programming loops that require verification of the first storage cell.

[0079] Still using Table 1 as an example, if a first memory cell passes verification in the third programming loop, then in the subsequent fourth and fifth programming loops, verification is still performed on other first memory cells that have not yet been programmed to the first programming state. However, programming is prohibited for the first memory cell that passed verification, for example, by applying a program inhibit pulse to the first memory cell that passed verification. In this case, the first and second programming loops corresponding to the first memory cell that passed verification are two of the first, second, and third programming loops.

[0080] When programming a memory cell of a memory, the presence of common source noise, etc., may cause the channel current in the memory cell to decrease, thereby causing the threshold voltage distribution of the corresponding programming state to become wider.

[0081] Figure 4The diagram shows the effect of common source noise on threshold voltage distribution, with the threshold voltage Vth as the horizontal axis. The target programming state of the multiple memory cells coupled to the selected word line is the jth programming state, and the verification voltage for verifying whether these memory cells have reached the jth programming state is VPV. j , and in the i-th programming loop, the i+1-th programming loop, and the i+2-th programming loop, the memory cells that fail the verification among these memory cells need to be verified.

[0082] In early programming loops, such as the i-th programming loop, only a small number of memory cells have reached the target programming state due to the small number of memory cells that have passed verification. This means that only a small number of memory cells are in the off state, while the majority of memory cells are in the on state. This results in a large current flowing through the common source (ACS). Because the common source has a certain resistance, the voltage divided by the common source is large. Generally, the bit line voltage (BL voltage) provided to the memory cells coupled to the selected word line is fixed. This results in a larger common source voltage divided by the common source, a smaller channel current, and a greater impact of common source noise, which leads to a wider threshold voltage (Vth) distribution.

[0083] Figure 4 The solid line in represents the ideal threshold voltage distribution, that is, if there is no common source noise, the threshold voltage distribution is as follows Figure 4 As shown by the solid line in ; however, due to the influence of common source noise, the actual threshold voltage distribution is relatively wide, see Figure 4 As shown by the dotted line in .

[0084] As the programming cycle proceeds, more and more memory cells reach the target programming state, that is, in the verification phase, more and more memory cells are in the off state, and accordingly, the number of memory cells in the on state decreases. Figure 4 Medium verification voltage VPV j The shaded area on the left corresponds to the memory cell in the on state.

[0085] In some embodiments, when verifying the same programming state, the bit line voltage provided in different programming loops is the same, that is, the bit line voltage is fixed. Figure 5 FIG. 1 shows a waveform diagram of a programming verification process. Figure 5 As shown in the figure, the WL voltage represents the voltage of the selected word line, and the BL voltage represents the corresponding bit line voltage. In the programming phase of each programming loop, a programming pulse Vpgm is provided to the selected word line, and a high level Vdd or a low level Vss is provided to the bit line based on the requirements; in the verification phase of the programming loop, a verification pulse for verifying the target programming state is provided to the selected word line. If the target programming state to be verified is the jth programming state, the verification pulse provided is VPV jAt this time, the corresponding bit line voltage is provided to the bit line. Figure 5 As shown, in the verification phase of different programming loops, the bit line voltage provided is fixed and is VBL. It is understandable that the bit line voltage can represent the bit line voltage provided to the same memory cell to be programmed to a certain programming state in different programming loops. In some embodiments, the bit line voltage can also represent the bit line voltage provided to multiple memory cells coupled to the same selection word line and to be programmed to a certain programming state in different programming loops (voltages on multiple bit lines coupled to multiple memory cells, respectively). The number of multiple memory cells to be programmed to the programming state in different programming loops may be different. In some embodiments, if a certain programming loop requires verification of multiple programming states, Figure 8 As shown, the BL voltage refers to the voltage applied to the bit line coupled to the memory cell to be verified. For example, the BL voltage can be used to represent the voltage applied to the bit line coupled to the first memory cell when verifying the first programming state, and the voltage applied to the bit line coupled to the second memory cell when verifying the second programming state.

[0086] When the bit line voltage is fixed, as the number of memory cells in the on state decreases, the current flowing through the common source decreases, so the common source voltage divider decreases, and the influence of the common source noise also decreases, making the actual threshold voltage distribution closer to the ideal threshold voltage distribution. For details on the changes in the influence of common source noise, please refer to Figure 4 Schematic diagram of the i+1th programming loop, i+2th programming loop, etc.

[0087] In this embodiment, a first bitline voltage is provided to the bitline coupled to the first memory cell during a first programming loop. A second, smaller bitline voltage is provided to the bitline coupled to the first memory cell during a subsequent second programming loop. This second bitline voltage is therefore lower than the first bitline voltage. By providing the bitline coupled to the first memory cell with gradually smaller bitline voltages as the programming loops proceed, the impact of common source noise can be reduced, effectively preventing a broadening of the threshold voltage distribution.

[0088] Specifically, during the initial programming cycle, a higher bitline voltage is provided to the bitline coupled to the first memory cell. For example, during the first programming cycle, a higher first bitline voltage is provided to the bitline coupled to the first memory cell. As described above, during the initial programming cycle, due to the large number of memory cells in the on state, a larger current flows through the common source, a larger voltage is divided across the common source, and a larger string current is reduced. At this time, providing a higher bitline voltage to the bitline coupled to the first memory cell can compensate for the effects of common source noise.

[0089] In later programming cycles, a smaller bitline voltage is provided to the bitline coupled to the first memory cell. For example, in the second programming cycle, a smaller second bitline voltage is provided to the bitline coupled to the first memory cell. At this time, since fewer memory cells are in the on state, the current flowing through the common source is smaller, and the common source voltage is also smaller, resulting in a smaller drop in string current. Therefore, a larger bitline voltage is not required, and a smaller bitline voltage can be provided to the bitline coupled to the first memory cell.

[0090] and Figure 4 For comparison, Figure 6 FIG. 1 shows a schematic diagram of the threshold voltage distribution obtained by gradually reducing the bit line voltage in different programming cycles in this embodiment, where the horizontal axis represents the threshold voltage Vth. Figure 6 As shown in FIG, in the first i-th programming loop, although there are more memory cells in the on state, a larger bit line voltage is provided to the bit line of the first memory cell, which ensures that the string current will not be reduced too much due to the common source, and the string current can be kept within a reasonable range, thereby reducing the impact of the common source noise on the string current and ensuring that the actual threshold voltage distribution is basically consistent with the ideal threshold voltage distribution. Figure 4 similar, Figure 6 The solid line in represents an ideal threshold voltage distribution, and the dotted line represents an actual threshold voltage distribution determined based on this embodiment.

[0091] As the programming cycle progresses, the number of memory cells in the on state becomes smaller and smaller. In order to avoid the influence of the larger bit line voltage on the distribution of the threshold voltage, the provided bit line voltage can be gradually reduced. While reducing the influence of the common source noise, new noise will not be introduced, ensuring that the actual threshold voltage distribution is basically consistent with the ideal threshold voltage distribution.

[0092] like Figure 6 As shown, as the programming loop proceeds, in the i-th programming loop, the i+1-th programming loop, and the i+2-th programming loop, a gradually decreasing bit line voltage is provided to the bit line coupled to the first memory cell, which can effectively compensate for the influence of the common source noise, so that the actual threshold voltage distribution is basically consistent with the ideal threshold voltage distribution.

[0093] Figure 7 FIG. 1 shows a waveform diagram of the bit line voltage provided in the verification phase of different programming cycles in this embodiment. Figure 7 As shown, in the verification phase of the i-th programming loop, a larger bit line voltage VBL is provided to the bit line i , in the verification phase of the i+1th programming loop, a medium bit line voltage VBL is provided to the bit line i+1, in the verification phase of the i+2th programming loop, a smaller bit line voltage VBL is provided to the bit line i+2 , that is, VBL i >VBL i+1 >VBL i+2 .

[0094] In this embodiment, the bitline voltage provided for the bitline coupled to the first memory cell is positively correlated with the number of memory cells currently in the on state. That is, the greater the number of memory cells currently in the on state, the greater the bitline voltage provided for the bitline coupled to the first memory cell. In other words, the bitline voltage provided for the bitline coupled to the first memory cell is positively correlated with the current flowing through the common source when the bitline voltage is constant. That is, when the bitline voltage is constant, the greater the current flowing through the common source, the greater the bitline voltage provided for the bitline coupled to the first memory cell.

[0095] For example, the bit line voltage provided for the bit line coupled to the first memory cell has a value range of 0.3V to 1V, and the appropriate bit line voltage can be determined in combination with the value range. Figure 7 As an example, the bit line voltage VBL provided to the bit line during the verification phase of the i-th programming loop is i The bit line voltage VBL provided to the bit line during the verification phase of the i+1th programming loop is 0.9V. i+1 The bit line voltage VBL provided to the bit line during the verification phase of the i+2th programming loop is 0.6V. i+2 is 0.3V.

[0096] It is understandable that the above Figures 4 to 7 Taking the example of a memory cell whose target programming state is the jth programming state and whose number of programming cycles to be verified is 3, the method provided in this embodiment is also applicable to memory cells that need to be programmed to other target programming states, or memory cells whose number of programming cycles involved is 2, 4 or other values.

[0097] In this embodiment, since there are multiple memory cells coupled to the same selection word line that are to be programmed to the first programming state, during the verification phase, it is necessary to provide corresponding bit line voltages to all of these memory cells to be programmed to the first programming state. Specifically, the method further includes: during the verification phase of the first programming loop or the second programming loop, providing the same bit line voltage to multiple memory cells coupled to the selection word line that are to be programmed to the first programming state and have not yet reached the first programming state. For example, during the verification phase of the first programming loop, the same first bit line voltage is provided to multiple memory cells coupled to the selection word line that are to be programmed to the first programming state and have not yet reached the first programming state; similarly, during the verification phase of the second programming loop, the same second bit line voltage is provided to multiple memory cells coupled to the selection word line that are to be programmed to the first programming state and have not yet reached the first programming state.

[0098] The memory operation method provided in this embodiment improves the threshold voltage distribution widening caused by common source noise by adjusting the bit line voltage provided during the verification phase of different programming cycles. This effectively reduces the threshold voltage distribution width of the memory cells and improves the read window. This method does not require additional circuitry, reducing costs, and eliminates the need for multiple reads, which does not sacrifice read time and ensures subsequent read efficiency.

[0099] In some optional embodiments, the number of programming loops required to verify the first memory cell is at least 3; the operating method also includes: in a verification phase of a third programming loop, providing a third bit line voltage for a bit line coupled to the first memory cell, the third programming loop being a programming loop after the second programming loop and requiring verification of the first memory cell, the third bit line voltage being less than the second bit line voltage.

[0100] In this embodiment, the first storage cell needs to be verified in the first programming loop, the second programming loop, and the third programming loop. Similar to the first programming loop and the second programming loop mentioned above, in the subsequent third programming loop, a smaller third bit line voltage is provided for the bit line coupled to the first storage cell, that is, the third bit line voltage is smaller than the second bit line voltage.

[0101] For example, participate Figure 7 As shown, if the first programming state is the jth programming state, for the first memory cell whose target programming state is the first programming state, a verification pulse can be applied to it during the verification phase of multiple programming cycles, and a gradually decreasing bit line voltage can be provided to the bit line coupled thereto until the first memory cell passes the verification. Figure 7 As shown, the i-th programming loop may be the first programming loop, and in its verification phase, the first bit line voltage VBL is provided to the bit line of the first memory cell. iThe i+1th programming loop may be the second programming loop, and in its verification phase, a second bit line voltage VBL is provided to the bit line of the first memory cell. i+1 The i+2th programming loop may be the third programming loop, and in its verification phase, a third bit line voltage VBL is provided to the bit line of the first memory cell. i+2 ; and, the first line voltage VBL i Greater than the second bit line voltage VBL i+1 , and the second bit line voltage VBL i+1 Greater than the third bit line voltage VBL i+2 .

[0102] Optionally, as the programming loop progresses, the bit line voltage is gradually reduced, and the reduction amplitudes of the bit line voltages may be different or the same. Specifically, the voltage difference between the first bit line voltage and the second bit line voltage is equal to the voltage difference between the second bit line voltage and the third bit line voltage, so that the reduction amplitudes of the bit line voltages are the same.

[0103] For example, the first programming loop, the second programming loop, and the third programming loop are three consecutive programming loops. During the verification phase of each programming loop, a first bit line voltage, a second bit line voltage, and a third bit line voltage that decrease in sequence can be provided to the bit line coupled to the first memory cell. The difference between the bit line voltages provided in two consecutive programming loops is the same, which can simplify the control of the bit line voltages. Alternatively, the first programming loop, the second programming loop, and the third programming loop can be three programming loops separated by the same number of programming loops. For example, the first programming loop, the second programming loop, and the third programming loop are the first programming loop, the third programming loop, and the fifth programming loop, respectively. This embodiment is not limited to this.

[0104] Alternatively, memory cells to be programmed to a target programming state generally require a relatively large number of programming cycles. As shown in Table 1 above, memory cells programmed to the L1 state require a maximum of five programming cycles. That is, only during the verification phase of the fifth programming cycle can it be determined that all memory cells to be programmed to the L1 state have passed verification. Therefore, the programming cycles can be grouped. For the programming cycles in the same group, the same bit line voltage can be applied during the verification phase, while for the programming cycles in different groups, different bit line voltages can be applied during the verification phase.

[0105] Specifically, if there is a fourth programming loop between the first programming loop and the second programming loop, the operating method may further include: in a verification phase of the fourth programming loop between the first programming loop and the second programming loop, providing a first bit line voltage to the bit line coupled to the first storage cell; the fourth programming loop is a programming loop that requires verification of the first storage cell.

[0106] Similarly, if there is a fifth programming loop between the second programming loop and the third programming loop, the operating method may further include: in a verification phase of the fifth programming loop between the second programming loop and the third programming loop, providing a second bit line voltage to the bit line coupled to the first memory cell; the fifth programming loop is a programming loop that requires verification of the first memory cell.

[0107] In this embodiment, in addition to the first and second programming loops, a fourth programming loop also requires verification of the first memory cell, and the fourth programming loop is located between the first and second programming loops. That is, the first memory cell is program-verified in the order of the first, fourth, and second programming loops. In this case, the first and fourth programming loops can be grouped together, and the same first bit line voltage is provided to the bit line coupled to the first memory cell during the verification phases of the first and fourth programming loops, and a smaller second bit line voltage is provided to the bit line coupled to the first memory cell during the subsequent second programming loop. For example, the first and fourth programming loops are two adjacent programming loops.

[0108] Similarly, if verification of the first memory cell is also required during the fifth programming loop between the second and third programming loops, program verification of the first memory cell can be performed in the order of the first programming loop, the second programming loop, the fifth programming loop, and the third programming loop. In this case, the second programming loop and the fifth programming loop can be grouped together, and the same second bit line voltage can be provided to the bit line coupled to the first memory cell during the verification phase of the second and fifth programming loops. A smaller third bit line voltage can be provided to the bit line coupled to the first memory cell during the subsequent third programming loop. For example, the second and fifth programming loops are adjacent programming loops.

[0109] In this embodiment, the number of programming loops contained in each group can be pre-set. As the programming loop progresses, the group to which the current programming loop belongs can be determined in real time, and then it can be determined how much bit line voltage needs to be provided in the verification phase of the current programming loop until all storage cells programmed to a certain programming state are verified.

[0110] For example, taking the programming scheme shown in Table 1 as an example, during the verification phase of the first programming loop, a higher first bitline voltage is provided to the bitlines of memory cells to be programmed to the L1 state but currently not verified. During the second programming loop, this loop is grouped with the first loop, i.e., during the verification phase of the second programming loop, the first bitline voltage is still provided to the bitlines of memory cells to be programmed to the L1 state but currently not verified. During the verification phase of the third programming loop, a medium second bitline voltage is provided to the bitlines of memory cells to be programmed to the L1 state but currently not verified. Furthermore, the fourth programming loop is grouped with the third programming loop, and during the verification phase of the fourth programming loop, the second bitline voltage is still provided to the bitlines of memory cells to be programmed to the L1 state but currently not verified. During the verification phase of the fifth programming loop, a third, smaller bit line voltage is provided to the bit lines of the memory cells that are to be programmed to the L1 state but have not yet passed the verification. If all the memory cells to be programmed to the L1 state pass the verification at this time, that is, there are no memory cells to be programmed to the L1 state at this time, then these memory cells no longer need to be verified in subsequent programming loops (e.g., the sixth programming loop).

[0111] It can be understood that the first programming loop to the fifth programming loop can be the first programming loop, the fourth programming loop, the second programming loop, the fifth programming loop, and the third programming loop mentioned above, respectively.

[0112] Optionally, in later programming loops, since fewer memory cells are in the on state, the current flowing through the common source is also smaller, and the noise impact caused by the common source voltage divider is also smaller, a fixed bit line voltage can be applied in the later programming loops. Specifically, the operating method further includes: if the count value of the programming loop for verifying the first memory cell exceeds a preset value, in a subsequent programming loop requiring verification of the first memory cell, providing a fixed bit line voltage to the bit line coupled to the first memory cell.

[0113] In this embodiment, the number of programming cycles performed on the first memory cell during verification can be counted to determine a current count value, which represents the number of programming cycles performed on the first memory cell during verification. If the count value exceeds a preset value, it indicates that the current programming cycle is a relatively recent programming cycle, and a constant bit line voltage can be provided to the bit line coupled to the first memory cell.

[0114] For example, if the preset value is 3, and still referring to Table 1, during the verification phase of the first programming loop, a higher first bitline voltage is applied to the bitlines of memory cells to be programmed to the L1 state but currently failing verification; during the second programming loop, a medium second bitline voltage is applied to the bitlines of memory cells to be programmed to the L1 state but currently failing verification; and during the verification phase of the third programming loop, a lower third bitline voltage is applied to the bitlines of memory cells to be programmed to the L1 state but currently failing verification. In the fourth programming loop, since the current count value is 4, which is greater than the preset value 3, starting from the fourth programming loop, a fixed bitline voltage is applied during the verification phases of the fourth programming loop and the fifth programming loop thereafter. For example, during the verification phases of the fourth programming loop and the fifth programming loop thereafter, the bitlines of memory cells to be programmed to the L1 state but currently failing verification continue to be applied with the third bitline voltage, or a fourth bitline voltage that is lower than the third bitline voltage is applied.

[0115] In some optional embodiments, the operating method further includes: in the verification phase of the first programming loop or the second programming loop, verifying the second storage cell coupled to the selected word line and to be programmed to the second programming state, and the bit line voltage coupled to the second storage cell is the same as the first bit line voltage or the second bit line voltage.

[0116] In this embodiment, during the verification phase of a certain programming loop, it may be necessary to verify memory cells to be programmed to different programming states separately. As shown in Table 1 above, during the verification phase of the third programming loop, in addition to verifying the memory cells to be programmed to the L1 state, it is also necessary to verify the memory cells to be programmed to the L2 state. For example, if the first memory cell is a memory cell to be programmed to the L1 state, then the second memory cell is a memory cell to be programmed to the L2 state. In this case, the bit line voltage provided to the bit line coupled to the second memory cell is the same as the bit line voltage provided to the bit line coupled to the first memory cell. Specifically, during the verification phase of the first programming loop, the first bit line voltage is provided to the bit line coupled to the second memory cell, or during the verification phase of the second programming loop, the second bit line voltage is provided to the bit line coupled to the second memory cell.

[0117] Figure 8 FIG. 1 shows another waveform diagram of the bit line voltage provided during the verification phase of different programming cycles. Figure 8 As shown, in the verification phase of the i-th programming loop and the i+1-th programming loop, only the memory cells whose target state is the j-th programming state need to be verified; and in the verification phase of the i+2-th programming loop, the memory cells whose target state is the j+1-th programming state also need to be verified. Figure 8 As shown, in the verification phase of the i+2th programming loop, the verification voltage VPV is applied to the selected bit line. j, to verify the memory cell whose target state is the jth programming state, and then, by applying the verification voltage VPV to the selected bit line j+1 , to verify that the target state is the memory cell of the j+1th programming state.

[0118] The jth programming state may be the first programming state, and the j+1th programming state may be the second programming state; accordingly, the memory cell whose target state is the jth programming state is the first memory cell, and the memory cell whose target state is the j+1th programming state is the second memory cell. Figure 8 As shown, in the verification phase of the (i+2)th programming loop, the voltage applied to the bit line coupled to the first memory cell when verifying the first programming state is VBL. i+2 , and the voltage applied to the bit line coupled to the second memory cell when verifying the second programming state is also VBL i+2 , these two voltages are equal.

[0119] In this embodiment, a memory operation method is provided, which can be used for a memory such as a NAND memory. The memory includes a plurality of memory cells coupled to the same selected word line, and performing a programming operation on the plurality of memory cells includes performing a plurality of programming cycles. Specifically, Figure 9 As shown, the operation method includes the following steps S901 to S902.

[0120] In step S901 , in a verification phase of a first programming loop among a plurality of programming loops, a first bit line voltage is provided to a bit line coupled to a memory cell to be programmed to a certain programming state among a plurality of memory cells.

[0121] Step S902 , in a verification phase of a second programming loop among the plurality of programming loops, providing a second bit line voltage to a bit line coupled to a memory cell to be programmed to a programmed state among the plurality of memory cells.

[0122] The second programming loop is subsequent to the first programming loop, and the second bit line voltage is lower than the first bit line voltage.

[0123] In this embodiment, there are multiple memory cells coupled to the same selected word line. Since there are multiple programming states, the target programming state of each memory cell corresponds to one of them. In some embodiments, the number of memory cells corresponding to the multiple programming states coupled to the same selected word line is substantially the same. For example, taking a TLC memory cell as an example, there is one erase state L0 and seven programming states, and the number of memory cells corresponding to each state accounts for approximately 1 / 8 of the total number of memory cells.

[0124] A programming loop among the multiple programming loops is referred to as a first programming loop. During a verification phase of the first programming loop, memory cells to be programmed to a certain programming state need to be verified to verify whether these memory cells have reached the corresponding programming state. For example, memory cells to be programmed to the L1 state may be verified to verify whether these memory cells have reached the L1 state.

[0125] In this embodiment, during the verification phase of a first programming loop, a corresponding bitline voltage, i.e., a first bitline voltage, is applied to the bitlines coupled to memory cells to be programmed to a certain programming state among the plurality of memory cells. In a subsequent second programming loop, if there are still memory cells to be programmed to the same programming state, a second, smaller bitline voltage is applied to the bitlines coupled to these memory cells to be programmed to the same programming state. The second bitline voltage is lower than the first bitline voltage.

[0126] In the first programming cycle, since there are more memory cells in the on state, the current flowing through the common source is larger, the common source voltage is larger, and the string current is reduced more. At this time, a larger first bit line voltage is provided to the bit line coupled to the memory cell to be programmed to a certain programming state, which can effectively compensate for the influence of the common source noise.

[0127] In the second programming cycle, since the number of memory cells in the on state is smaller, the current flowing through the common source is smaller, and the common source voltage is also smaller. Therefore, the drop in string current due to common source noise is not obvious. Therefore, a larger bit line voltage is not required at this time. At this time, a smaller second bit line voltage is provided to the bit line coupled to the memory cell to be programmed to the programming state.

[0128] The memory operation method provided in this embodiment improves the threshold voltage distribution widening caused by common source noise by adjusting the bit line voltage provided during the verification phase of different programming cycles. This effectively reduces the threshold voltage distribution width of the memory cells and improves the read window. This method does not require additional circuitry, reducing costs, and eliminates the need for multiple reads, which does not sacrifice read time and ensures subsequent read efficiency.

[0129] In some optional embodiments, the programming loops may be grouped. Specifically, the plurality of programming loops may include a first programming loop group and a second programming loop group, wherein the first programming loop group includes a plurality of first programming loops and the second programming loop group includes a plurality of second programming loops. Furthermore, the operating method may further include: providing a first bit line voltage to bit lines coupled to memory cells to be programmed to a programmed state among the plurality of memory cells during a verification phase of the plurality of first programming loops, and providing a second bit line voltage to bit lines coupled to memory cells to be programmed to a programmed state among the plurality of memory cells during a verification phase of the plurality of second programming loops.

[0130] In this embodiment, the plurality of first pass loops may be sequentially adjacent programming loops, and the plurality of second pass loops may also be sequentially adjacent programming loops. Specifically, for a portion of the plurality of programming loops that requires verification of memory cells to be programmed to a certain programming state, the plurality of adjacent programming loops may be used as first programming loops, and the remaining plurality of adjacent programming loops may be used as second programming loops, so that during the verification phase of the corresponding programming loops, the bit lines coupled to the memory cells to be programmed to the programming state are provided with a corresponding first bit line voltage or a second bit line voltage.

[0131] For example, using the programming scheme shown in Table 1, for memory cells to be programmed to the L1 state, five programming loops are involved, namely, the first to fifth programming loops. For example, the first and second programming loops can both be considered first programming loops. That is, during the verification phases of the first and second programming loops, the first bit line voltage is applied to the bit lines of the memory cells to be programmed to the L1 state. Similarly, the third and fourth programming loops can both be considered second programming loops. That is, during the verification phases of the third and fourth programming loops, the second bit line voltage is applied to the bit lines of the memory cells to be programmed to the L1 state. The fifth programming loop can be treated as a separate group, and during its verification phase, a smaller third bit line voltage is applied to the bit lines of the memory cells to be programmed to the L1 state. Alternatively, the fifth programming loop can also be considered a second programming loop, although this embodiment is not limited thereto.

[0132] In this embodiment, a memory is provided. Figure 10 A structural diagram of the memory is shown in FIG. Figure 10 As shown, the memory includes a memory array 1010 , a peripheral circuit 1020 and a plurality of bit lines 1030 .

[0133] The memory array 1010 includes a plurality of memory cells arranged in an array. Figure 1 FIG. 1 shows a schematic diagram of a structure of a storage array 1010. Figure 1 As shown, the memory array 1010 includes a plurality of memory strings 111 , and the memory strings 111 include a plurality of memory cells 101 ;

[0134] The plurality of bit lines 1030 are respectively coupled to the plurality of memory strings. For example, the plurality of bit lines 1030 are respectively coupled to Figure 1 Storage string 111 is shown.

[0135] The peripheral circuit 1020 is coupled to the memory array 1010 and configured to operate according to any of the above embodiments. The peripheral circuit 1020 can compensate for the impact of common source noise by providing an appropriate bit line voltage to the bit line coupled to the first memory cell, thereby reducing the width of the threshold voltage distribution.

[0136] Specifically, the peripheral circuit 1020 is configured to: provide a first bit line voltage for the bit line coupled to the first memory cell during the verification phase of the first programming loop; the first memory cell is a memory cell coupled to the selected word line and to be programmed to the first programming state, and the first programming loop is a programming loop in which the first memory cell needs to be verified; provide a second bit line voltage for the bit line coupled to the first memory cell during the verification phase of the second programming loop; the second programming loop is a programming loop after the first programming loop in which the first memory cell needs to be verified, and the second bit line voltage is less than the first bit line voltage.

[0137] It is understood that the memory further includes a plurality of word lines coupled to the memory array 1010, and the peripheral circuit 1020 may also be coupled to the memory array 1010 through the plurality of word lines. The peripheral circuit 1020 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory array 1010 by applying voltage signals and / or current signals to memory cells via bit lines, word lines, etc., and sensing voltage signals and / or current signals from each memory cell.

[0138] The peripheral circuit 1020 may include various types of peripheral circuits formed using metal oxide semiconductor (MOS) technology. For example, Figure 11 Some exemplary peripheral circuits are shown, and the peripheral circuit 1020 includes: a page buffer / sense amplifier 1021, a column decoder / bit line driver 1022, a row decoder / word line driver 1023, a voltage generator 1024, a control logic unit 1025, a register 1026, an interface 1027, and a data bus 1028. It should be understood that in some examples, the peripheral circuit 1020 may also include Figure 11 Additional peripheral circuits not shown.

[0139] The page buffer / sense amplifier 1021 can be configured to read data from the memory array 1010 and program (write) data to the memory array 1010 based on control signals from the control logic unit 1025. In one example, the page buffer / sense amplifier 1021 can store a page of program data (write data) to be programmed into one memory page 112 of the memory array 1010. In another example, the page buffer / sense amplifier 1021 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 101 coupled to the selected word line. In yet another example, the page buffer / sense amplifier 1021 can also sense a low-power signal from the bit line 1030 representing a data bit stored in the memory cell 101 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 1022 can be configured to be controlled by the control logic unit 1025 and select one or more memory strings 111 by applying a bit line voltage generated by the voltage generator 1024.

[0140] The row decoder / word line driver 1023 can be configured to be controlled by the control logic unit 1025 and select / deselect word lines coupled to the memory array 1010. The row decoder / word line driver 1023 can also be configured to drive the word lines using word line voltages generated from the voltage generator 1024. In some embodiments, the row decoder / word line driver 1023 can also select / deselect and drive source select gate lines and drain select gate lines. The row decoder / word line driver 1023 is configured to perform an erase operation on the memory cells 101 coupled to the selected word line(s). The voltage generator 1024 can be configured to be controlled by the control logic unit 1025 and generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 1010.

[0141] The control logic unit 1025 can be coupled to each circuit described above and is configured to control the operation of each peripheral circuit. The register 1026 can be coupled to the control logic unit 1025 and includes a status register, a command register, and an address register for storing and controlling status information, command operation codes (OP codes), and command addresses for the operation of each peripheral circuit. The interface 1027 can be coupled to the control logic unit 1025 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 1025, as well as buffer status information received from the control logic unit 1025 and relay it to the host. The interface 1027 can also be coupled to the column decoder / bit line driver 1022 via the data bus 1028 and act as a data I / O interface and data buffer to buffer data and relay it to the memory array 1010 or relay or buffer data from the memory array 1010.

[0142] In this embodiment, a memory system is provided. Figure 12 As shown, the memory system 1200 includes the memory 1201 provided by the above embodiment; and a memory controller 1202 coupled to the memory 1201 and configured to control the memory 1201 .

[0143] Among them, such as Figure 12 As shown, the memory system 1200 can be applied to an electronic device including a host 200, which can be, for example, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. The host 200 can be a processor (e.g., a central processing unit) or a system on a chip (SoC) of the electronic device. The host 200 can be configured to send data to the memory system 1200; alternatively, the host 200 can be configured to receive data from the memory system 1200.

[0144] The memory 1201 may be any memory device disclosed in the present disclosure. The memory 1201 (e.g., a NAND flash memory device) may have reduced leakage current from a driver transistor (e.g., a string driver) coupled to an unselected word line during an erase operation, which allows for further size reduction of the driver transistor.

[0145] According to some embodiments, the memory controller 1202 is also coupled to the host 200. The memory controller 1202 may manage data stored in the memory 1201 and communicate with the host 200.

[0146] In some embodiments, the memory controller 1202 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0147] In some embodiments, the memory controller 1202 is designed to operate in a high duty cycle environment solid state drive (SSD) or embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0148] The memory controller 1202 may be configured to control operations of the memory 1201, such as read, erase, and program operations. The memory controller 1202 may also be configured to manage various functions related to data stored or to be stored in the memory 1201, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 1202 is further configured to process error correction code (ECC) on data read from or written to the memory 1201.

[0149] The memory controller 1202 may also perform any other suitable functions, such as formatting the memory 1201. The memory controller 1202 may communicate with an external device (e.g., the host 200) according to a specific communication protocol. For example, the memory controller 1202 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini-interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, and the like.

[0150] The memory controller 1202 and the one or more memories 1201 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 1200 can be implemented and packaged into different types of terminal electronic products.

[0151] In such Figure 13In one example shown in FIG, a memory controller 1202 and a single memory 1201 may be integrated into a memory card 1300. The memory card 1300 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RSMMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 1300 may also include a computer that connects the memory card 1300 to a host (e.g., Figure 12 A memory card connector 1301 coupled to the host 200 in the memory card connector.

[0152] In such Figure 14 In another example shown in FIG, a memory controller 1202 and a plurality of memories 1201 may be integrated into a solid state drive (SSD) 1400. The solid state drive 1400 may also include a computer that interfaces the solid state drive 1400 with a host (e.g., Figure 12 In some embodiments, the solid-state drive 1400 has a storage capacity and / or an operating speed greater than that of the memory card 1300.

[0153] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for operating a memory, characterized in that: The method comprises: In a verification phase of a first programming loop, a first bit line voltage is provided to a bit line coupled to a first memory cell; the first memory cell is a memory cell coupled to a selected word line and to be programmed to a first programming state, and the first programming loop is a programming loop in which verification of the first memory cell is required; During the verification phase of a second programming loop, a second bit line voltage is provided for the bit line coupled to the first memory cell; the second programming loop is a programming loop that is performed after the first programming loop and requires verification of the first memory cell, and the second bit line voltage is less than the first bit line voltage.

2. The method according to claim 1, characterized in that Also includes: During a verification phase of a third programming loop, a third bit line voltage is provided for a bit line coupled to the first memory cell. The third programming loop is a programming loop that is performed after the second programming loop and in which verification of the first memory cell is required. The third bit line voltage is lower than the second bit line voltage.

3. The method according to claim 2, characterized in that A voltage difference between the first bit line voltage and the second bit line voltage is equal to a voltage difference between the second bit line voltage and the third bit line voltage.

4. The method according to claim 1 or 2, characterized in that Also includes: providing the first bit line voltage to a bit line coupled to the first memory cell during a verification phase of a fourth programming loop between the first programming loop and the second programming loop; The fourth program loop is a program loop that requires verification of the first memory cells.

5. The method according to claim 2, characterized in that Also includes: providing the second bit line voltage to a bit line coupled to the first memory cell during a verification phase of a fifth programming loop between the second programming loop and the third programming loop; The fifth program loop is a program loop requiring verification of the first memory cells.

6. The method according to claim 1, characterized in that Also includes: When the count value of the program loop for verifying the first memory cell exceeds a preset value, a fixed bit line voltage is provided for a bit line coupled to the first memory cell in a subsequent program loop for verifying the first memory cell.

7. The method according to claim 1, characterized in that Also includes: During the verification phase of the first programming loop or the second programming loop, a second memory cell coupled to the selected word line and to be programmed to a second programming state is verified, and a bit line voltage coupled to the second memory cell is the same as the first bit line voltage or the second bit line voltage.

8. The method according to claim 1, characterized in that Also includes: During a verification phase of the first program loop or the second program loop, a same bit line voltage is provided to a plurality of memory cells coupled to the selected word line that are to be programmed to the first program state and have not yet reached the first program state.

9. The method according to claim 1, characterized in that Also includes: After the first memory cell reaches the first programming state, programming of the first memory cell is prohibited.

10. A method for operating a memory, characterized in that: The memory includes a plurality of memory cells coupled to a same selected word line, performing a programming operation on the plurality of memory cells includes performing a plurality of programming loops, and the method includes: providing a first bit line voltage to a bit line coupled to a memory cell to be programmed to a certain program state among the plurality of memory cells during a verification phase of a first program loop among the plurality of program loops; and providing a second bit line voltage to a bit line coupled to a memory cell to be programmed to the programmed state among the plurality of memory cells during a verification phase of a second programming loop among the plurality of programming loops; The second programming loop is after the first programming loop, and the second bit line voltage is lower than the first bit line voltage.

11. The method according to claim 10, characterized in that The plurality of program loops include a first program loop group and a second program loop group, the first program loop group includes a plurality of the first program loops, and the second program loop group includes a plurality of the second program loops, the method further comprising: During the verification phase of the multiple first programming loops, the first bit line voltage is provided to the bit lines coupled to the memory cells to be programmed to the programmed state among the multiple memory cells, and during the verification phase of the multiple second programming loops, the second bit line voltage is provided to the bit lines coupled to the memory cells to be programmed to the programmed state among the multiple memory cells.

12. A memory, characterized in that: include: a memory array, peripheral circuits, and a plurality of bit lines; The memory array includes a plurality of memory strings, and the memory strings include a plurality of memory cells; The plurality of bit lines are respectively coupled to the plurality of memory strings; The peripheral circuit is coupled to the memory array and is configured to: In a verification phase of a first programming loop, a first bit line voltage is provided to a bit line coupled to a first memory cell; the first memory cell is a memory cell coupled to a selected word line and to be programmed to a first programming state, and the first programming loop is a programming loop in which verification of the first memory cell is required; providing a second bit line voltage to a bit line coupled to the first memory cell during a verification phase of a second programming loop; The second programming loop is a programming loop that is performed after the first programming loop and requires verifying the first memory cell, and the second bit line voltage is lower than the first bit line voltage.

13. The memory according to claim 12, wherein: The peripheral circuit is further configured to: During a verification phase of a third programming loop, a third bit line voltage is provided for a bit line coupled to the first memory cell. The third programming loop is a programming loop that is performed after the second programming loop and in which verification of the first memory cell is required. The third bit line voltage is lower than the second bit line voltage.

14. The memory according to claim 13, wherein: A voltage difference between the first bit line voltage and the second bit line voltage is equal to a voltage difference between the second bit line voltage and the third bit line voltage.

15. The memory according to claim 12 or 13, characterized in that: The peripheral circuit is further configured to: providing the first bit line voltage to a bit line coupled to the first memory cell during a verification phase of a fourth programming loop between the first programming loop and the second programming loop; The fourth program loop is a program loop that requires verification of the first memory cells.

16. The memory according to claim 13, wherein: The peripheral circuit is further configured to: providing the second bit line voltage to a bit line coupled to the first memory cell during a verification phase of a fifth programming loop between the second programming loop and the third programming loop; The fifth program loop is a program loop requiring verification of the first memory cells.

17. The memory according to claim 12, wherein: The peripheral circuit is further configured to: When the count value of the program loop for verifying the first memory cell exceeds a preset value, a fixed bit line voltage is provided for a bit line coupled to the first memory cell in a subsequent program loop for verifying the first memory cell.

18. The memory according to claim 12, wherein: The peripheral circuit is further configured to: During the verification phase of the first programming loop or the second programming loop, a second memory cell coupled to the selected word line and to be programmed to a second programming state is verified, and a bit line voltage coupled to the second memory cell is the same as the first bit line voltage or the second bit line voltage.

19. The memory according to claim 12, wherein: The peripheral circuit is further configured to: During a verification phase of the first program loop or the second program loop, a same bit line voltage is provided to a plurality of memory cells coupled to the selected word line that are to be programmed to the first program state and have not yet reached the first program state.

20. The memory according to claim 12, wherein: The peripheral circuit is further configured to: After the first memory cell reaches the first programming state, programming of the first memory cell is prohibited.

21. A memory system, characterized in that: include: One or more memories according to any one of claims 12 to 20; A memory controller coupled to the memory and configured to control the memory.

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