A capacitor and an operation control circuit thereof

Abstract

The application discloses a capacitor and an operation control circuit thereof, which are used for a charge-discharge circuit and relate to the technical field of capacitors. A plurality of controlled switches are connected with a plurality of capacitor cores to form a capacitor structure combined in series and parallel. The application is characterized in that a charge-discharge monitoring module is used to monitor the charge-discharge state of the capacitor, and outputs a discharge end signal when it is determined that the capacitor is discharged. A state monitoring module is used to monitor the working time length of each capacitor core and generate a working state signal. A control module controls the opening and closing of some of the controlled switches in the plurality of controlled switches based on the working state signal of each capacitor core and the discharge end signal, so as to adjust the capacitor structure, replace the capacitor core in the alarm state with the capacitor core in the idle state, keep the capacitance of the capacitor unchanged, effectively avoid the long-time high-load work of the capacitor core, reduce the heat generation, and keep the capacitance of the capacitor stable.

Description

Technical Field

[0001] This invention relates to the field of capacitor technology, and more specifically to a capacitor and its operation control circuit. Background Technology

[0002] In modern electronic devices, capacitors are used as an important energy storage component and are widely used in various industries.

[0003] During operation, capacitors generate heat in their cores due to factors such as current flow and ambient temperature. If the capacitor core operates under high load for an extended period, its temperature will continuously rise. Excessively high temperatures can degrade the electrochemical performance of the capacitor core, thereby affecting the capacitor's lifespan and causing changes in its capacitance.

[0004] Currently, heat dissipation is often achieved by adding heat dissipation fins or providing heat dissipation channels to the outside of the capacitor, but the effectiveness is still unclear, especially in applications where the capacitor needs to operate for a long time. Summary of the Invention

[0005] This invention provides a capacitor and its operation control circuit, which can effectively prevent the capacitor core from working under high load for a long time, thereby reducing heat generation and maintaining the capacitor's capacitance stability.

[0006] To address the aforementioned problems, in a first aspect, embodiments of the present invention disclose a capacitor operation control circuit for a charging and discharging circuit, comprising:

[0007] Multiple capacitor cores;

[0008] Multiple controlled switches are connected to multiple capacitor cores to form a capacitor structure that combines series and parallel connections;

[0009] The charge and discharge monitoring module is used to monitor the charge and discharge status of the capacitor and output a discharge end signal when it is determined that the capacitor has finished discharging.

[0010] The status monitoring module includes monitoring units corresponding to multiple capacitor cores. Each monitoring unit is used to monitor the working time of its corresponding capacitor core and generate working status signals. The working status signals include: idle state, alarm state, and running state. Among them, the alarm state indicates that the capacitor core is in the running state and the working time has exceeded its timing threshold.

[0011] The control module generates a first control signal for controlling the opening and closing of some of the multiple controlled switches based on the working status signal and discharge end signal of each capacitor core.

[0012] The drive module adjusts the capacitor structure according to the first control signal so that the idle capacitor core replaces the capacitor core in the alarm state, and keeps the capacitor at its current capacitance.

[0013] In one embodiment of the present invention, the plurality of capacitor cores include: m first capacitor cores Cx[0,m-1] and n second capacitor cores Cy[0,n-1], where m is a positive integer ≥2 and n is a positive integer ≥2; the plurality of controlled switches include: m+1 first switches K[0,m] and n second switches S[0,n-1]; wherein, the positive terminal of each first capacitor core is connected to the positive power supply terminal of the capacitor through its corresponding first switch, and the negative terminals of each first capacitor core are connected to form a common terminal; each second capacitor core is connected in series with its corresponding second switch to form a series branch, and the series branches are connected in parallel to form a parallel circuit, which is connected between the common terminal and the negative power supply terminal of the capacitor and connected to the positive power supply terminal of the capacitor through its corresponding first switch.

[0014] In one embodiment of the present invention, the capacitance of the first capacitor core is greater than the capacitance of the second capacitor core; m is 2, and the value of n ranges from 2 to 6.

[0015] In one embodiment of the present invention, the capacitor structure remains a series-connected and parallel-connected capacitor structure before and after the capacitor structure is adjusted.

[0016] In one embodiment of the present invention, a first storage module connected to the control module is further included; the first storage module is used to store the mapping relationship between the adjustment mode of the capacitor structure and the capacitance, wherein, except for the maximum capacity, the same capacitance corresponds to at least two adjustment modes, and the adjustment mode is characterized as the opening and closing control logic of multiple controlled switches; the control module generates a first control signal based on the discharge end signal, working status signal and mapping relationship of each capacitor core.

[0017] In one embodiment of the present invention, the monitoring unit includes:

[0018] A current sensor is used to monitor whether current is flowing through the capacitor core and to send a timing start signal when current is detected.

[0019] A timer is used to start timing when a timing start signal is received and to output a timing signal.

[0020] The signal processor outputs a working status signal based on the timing signal and the timing threshold set for the capacitor core.

[0021] In one embodiment of the present invention, the monitoring unit includes:

[0022] The first comparator has a first input terminal connected to the control terminal level signal of the controlled switch connected in series with the capacitor core corresponding to the monitoring unit, a second input terminal based on a default level signal, and an output terminal outputting the first comparison signal.

[0023] A timer is used to time the first comparison signal and output a timing signal;

[0024] The second comparator outputs an operating status signal based on the timing signal and the timing threshold set for the capacitor core.

[0025] In one embodiment of the present invention, when the control module receives a working status signal that is in an alarm state, it sends a timing reset signal to the monitoring unit that issued the working status signal.

[0026] In one embodiment of the present invention, the load in the charging and discharging circuit is variable;

[0027] The capacitor operation control circuit also includes:

[0028] The load detection module is connected to the load in the charging and discharging circuit, and is used to detect the resistance of the load.

[0029] The second storage module is used to store the correspondence between the resistance value of different loads and the target capacitance.

[0030] The control module is also used to determine the target capacitance based on the resistance value of the load detected by the load detection module and the corresponding relationship, and to generate a second control signal for controlling the opening and closing of some of the multiple controlled switches.

[0031] The drive module adjusts the capacitor structure according to the second control signal so that the capacitor capacitance is adjusted to the target capacitance.

[0032] This invention also discloses a capacitor, including the capacitor operation control circuit as described in the first aspect of this invention.

[0033] The embodiments of the present invention have the following advantages:

[0034] In this embodiment of the invention, multiple controlled switches are connected to multiple capacitor cores to form a switchable series and parallel capacitor structure. The control module switches the controlled switches through the drive module when the capacitor core's working time reaches a certain timing threshold and the capacitor discharge is complete, based on the working time of the capacitor core monitored by the monitoring unit. This allows the idle capacitor core to replace the capacitor core in the alarm state, avoiding prolonged high-load operation of a single capacitor core, reducing heat generation, lowering the degree to which capacitance is affected by temperature, ensuring the stability of capacitance, and extending the service life of the capacitor core. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the structure of a capacitor operation control circuit according to an embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram of a capacitor structure according to an embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram of the structure of a monitoring unit according to an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram of the structure of another monitoring unit according to an embodiment of the present invention;

[0040] Figure 5 This is a schematic diagram of another capacitor operation control circuit according to an embodiment of the present invention. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0042] This invention provides a capacitor operation control circuit for use in charging and discharging circuits, such as... Figure 1 As shown, the control circuit includes:

[0043] Multiple capacitor cores;

[0044] Multiple controlled switches are connected to multiple capacitor cores to form a capacitor structure that combines series and parallel connections;

[0045] The charge / discharge monitoring module is used to monitor the charge / discharge status of the capacitor and output a discharge end signal when it is determined that the capacitor has finished discharging.

[0046] The status monitoring module includes monitoring units corresponding to multiple capacitor cores. Each monitoring unit is used to monitor the working time of its corresponding capacitor core and generate working status signals. The working status signals include: idle state, alarm state, and running state. Among them, the alarm state indicates that the capacitor core is in the running state and the working time has exceeded its timing threshold.

[0047] The control module generates a first control signal for controlling the opening and closing of some of the multiple controlled switches based on the working status signal and the discharge end signal of each capacitor core.

[0048] The drive module adjusts the capacitor structure according to the first control signal so that the idle capacitor core replaces the capacitor core in the alarm state, and keeps the capacitor at its current capacitance.

[0049] In this embodiment of the invention, multiple controlled switches are connected to multiple capacitor cores, forming a capacitor structure combining series and parallel connections, which improves voltage quality and enhances the voltage withstand capability of the capacitors. In a series circuit, voltage can be distributed across multiple capacitor cores, reducing the voltage withstand capability of a single capacitor core; in a parallel circuit, capacitance can be increased, improving circuit stability and voltage quality.

[0050] The capacitor of this invention comprises multiple capacitor cores in three states: idle, alarm, and operating. Idle capacitor cores are those not connected in series or parallel in the capacitor structure; they are not connected to the positive and negative power supply terminals and cannot participate in the capacitor's operation (e.g., charge / discharge control). Operating capacitor cores are those connected in series or parallel in the capacitor structure; they are connected to the positive and negative power supply terminals and can participate in the capacitor's operation; the capacitor's capacitance is affected by the capacitor core in the operating state. Alarm capacitor cores are those that have been in the operating state for an extended period, exceeding their timing threshold. Different capacitor cores have different timing thresholds, allowing for staggered rest based on the adjustment scheme of this invention.

[0051] If a capacitor core in an alarm state continues to operate for an extended period, its actual capacitance will deviate from the rated capacitance due to factors such as excessive temperature, affecting the overall effective capacitance of the capacitor. This impacts practical applications, such as charging and discharging speed, affecting not only application accuracy but also posing safety hazards. Therefore, in this embodiment of the invention, multiple controlled switches are connected to multiple capacitor cores to form a switchable capacitor structure. The control module monitors the charging and discharging state of the capacitor based on the operating time of the capacitor cores monitored by the monitoring unit. When the capacitor is determined to be fully discharged, the control module adjusts the opening and closing of the controlled switches, allowing different capacitor cores to work alternately. This avoids prolonged high-load operation of any single capacitor core, reduces heat generation, and extends the lifespan of the capacitor cores. This invention, through the cooperation of a control module, a charge / discharge monitoring module, and a status monitoring module, enables a switchover via a drive module when the capacitor core's operating time reaches a certain timing threshold and the capacitor is fully discharged. This allows an idle capacitor core to replace the one in an alarm state, ensuring the capacitor core operates at a relatively low temperature, reducing the degree to which capacitance is affected by temperature, and guaranteeing capacitance stability. This invention achieves backup operation of the capacitor core by adjusting the capacitor structure, improving the reliability and stability of the capacitor. In particular, this embodiment of the invention performs the switching action only when the capacitor is fully discharged, without affecting the normal operation of the capacitor and preventing the replacement of a fully charged capacitor.

[0052] It is worth noting that when the control module receives an alarm status signal from a monitoring unit, it sends a timing reset signal to that monitoring unit to save power and facilitate the subsequent reintroduction of the capacitor structure. In various embodiments of the present invention, the timing threshold is a preset time value used to determine whether the capacitor core needs to be replaced. The timing threshold needs to be determined based on the performance parameters of the capacitor core and the actual application scenario. The timing threshold can be set and adjusted by software or hardware.

[0053] This invention allows for changes in the capacitor structure and different adjustment methods by controlling the opening and closing of different controlled switches. This application does not limit the specific adjustment methods, as long as the capacitor structure changes while the capacitance remains constant.

[0054] Regarding capacitor structures combining series and parallel connections, embodiments of the present invention provide the following optional capacitor structures, see reference. Figure 2The system comprises multiple capacitor cores, including m first capacitor cores Cx[0,m-1] and n second capacitor cores Cy[0,n-1], where m is a positive integer ≥ 2 and n is a positive integer ≥ 2; and multiple controlled switches, including m+1 first switches K[0,m] and n second switches S[0,n-1]. The positive terminal of each first capacitor core is connected to the positive power supply terminal of the capacitor via its corresponding first switch, and the negative terminals of each first capacitor core are connected to form a common terminal. Each second capacitor core is connected in series with its corresponding second switch to form a series branch, and these series branches are connected in parallel to form a parallel circuit. The parallel circuit is connected between the common terminal and the negative power supply terminal of the capacitor and is connected to the positive power supply terminal of the capacitor via its corresponding first switch. This embodiment adjusts... Figure 2 The capacitor structure shown not only enables backup operation of the capacitor core, extending its lifespan, but also improves voltage quality and enhances withstand voltage through the combination of series and parallel capacitors. The first switch described above is a controlled switch, and the second switch is also a controlled switch. Specifically, the controlled switches can be implemented using MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices.

[0055] It is worth noting that, such as Figure 2 As shown, the parallel circuit is connected between the common terminal and the negative power supply terminal of the capacitor and is connected to the positive power supply terminal of the capacitor through the corresponding first switch K[2]. When the first capacitor switch K[2] is closed, the entire capacitor structure becomes a parallel circuit. When all the second switches S[1]-S[4] in the parallel circuit are closed, the capacitance of the entire capacitor structure is at its maximum. When only K[0] is closed, and any one of the second switches S[0]-S[3] is closed, and the other switches are open, the entire capacitor structure becomes a series circuit, and the capacitance is at its minimum.

[0056] Furthermore, since the first capacitor core is mainly used to increase the withstand voltage, and the total capacitance in series is the smallest, in order to maintain the withstand voltage to adapt to high-voltage charging and discharging applications, the capacitor structure of this embodiment can be improved as follows: the capacitance of the first capacitor core can be greater than the capacitance of the second capacitor core, so as to increase the withstand voltage while ensuring a large capacitance. Optionally, the capacitance of the first capacitor core is twice the capacitance of the second capacitor core, so as to reduce the amount of computation and the circuit area.

[0057] Furthermore, m is 2, and n ranges from 2 to 6. Limiting this range allows for adjustment of the capacitor structure while maintaining capacitance, without making the overall capacitor too large, thus meeting practical requirements.

[0058] In such Figure 2During the adjustment process of the capacitor structure shown, the series-parallel capacitor structure is maintained before and after the adjustment.

[0059] Example (not shown in the figure): Assume m=2, n=2, that is, there are 2 first capacitor cores Cx[0] and Cx[1], and 2 second capacitor cores Cy[0] and Cy[1]. The capacitance of the first capacitor cores is 2C, and the capacitance of the second capacitor cores is C. The positive terminals of the first capacitor cores Cx[0] and Cx[1] are connected to the positive power supply terminal of the capacitor through the first switches K[0] and K[1], respectively, and their negative terminals are connected to form a common terminal; the second capacitor cores Cy[0] and Cy[1] are connected in series with the second switches S[0] and S[1] to form two series branches. These two series branches are connected in parallel between the common terminal and the negative power supply terminal of the capacitor, and are connected to the positive power supply terminal of the capacitor through the first switch K[2]. In the initial state, it is assumed that the first capacitor core Cx[0] and the second capacitor core Cy[0] are in the running state, and the second capacitor core Cy[1] is in the idle state. The status monitoring module detects that the working time of Cx[0] and Cy[0] gradually increases. The timing thresholds corresponding to Cx[0] and Cy[0] are different. When the working time of Cy[0] exceeds its timing threshold, the status monitoring module generates an alarm status signal. After receiving the alarm status signal, the control module generates a first control signal if it receives a discharge end signal. The drive module controls the second switch S[0] to open according to the first control signal, and at the same time controls the second switch S[1] to close, so that the second capacitor core Cy[1] replaces Cy[0] and enters the running state. At this time, the capacitor structure changes, but the total capacitance of the capacitor remains unchanged. Furthermore, after the control module generates the first control signal, it will also send a timing reset signal to the monitoring unit monitoring the second capacitor core Cy[0] to save power consumption and facilitate the subsequent reintroduction of the capacitor structure.

[0060] When the operating time of Cx[0] exceeds its timing threshold, the status monitoring module generates an alarm status signal. After receiving the alarm status signal, the control module generates a first control signal if it receives a discharge end signal. The drive module controls the first switch K[0] to open according to the first control signal, and simultaneously controls the first switch K[1] to close, so that the first capacitor core Cx[1] replaces Cx[0] and enters the running state. At this time, the capacitor structure changes, but the total capacitance of the capacitor remains unchanged. Furthermore, after generating the first control signal, the control module also sends a timing reset signal to the monitoring unit monitoring the first capacitor core Cx[0] to save power consumption and facilitate the subsequent reintroduction of the capacitor structure.

[0061] For example: Figure 2As shown, assuming m=2 and n=4, there are 2 first capacitor cores Cx[0] and Cx[1] and 4 second capacitor cores Cy[0], Cy[1], Cy[2], and Cy[3]. The capacitance of the first capacitor cores is 2C and the capacitance of the second capacitor cores is C. The positive terminals of the first capacitor cores Cx[0] and Cx[1] are connected to the positive power supply terminal of the capacitor through the first switches K[0] and K[1], respectively, and their negative terminals are connected to form a common terminal. The second capacitor cores Cy[0], Cy[1], Cy[2], and Cy[3] are connected in series with the second switches S[0], S[1], S[2], and S[3] to form four series branches. These four series branches are connected in parallel between the common terminal and the negative power supply terminal of the capacitor, and are connected to the positive power supply terminal of the capacitor through the first switch K[2]. Initially, it is assumed that the first capacitor core Cx[0] and the second capacitor cores Cy[0] and Cy[1] are in the running state, while the second capacitor cores Cy[2] and Cy[3] are in the idle state. The status monitoring module detects that the working time of Cx[0], Cy[0], and Cy[1] gradually increases. When the working time of Cy[0] and Cy[1] exceeds their respective timing thresholds at the same time, the status monitoring module generates an alarm status signal for these two capacitor cores. After receiving the alarm status signal, the control module generates a first control signal if it receives a discharge end signal. The drive module controls the second switches S[0] and S[1] to open according to the first control signal, and at the same time controls the second switches S[2] and S[3] to close, so that the second capacitor cores Cy[2] and Cy[3] replace Cy[0] and Cy[1] and enter the running state. At this time, the capacitor structure changes, but the current capacitance of the capacitor remains unchanged. During this process, since the switching time is extremely short, it will not affect the stability of the capacitor operation. As can be seen from the above examples, the first control signal includes control instructions for K[0], K[1] and S[0]~S[n] respectively, to control the corresponding controlled switches to close or open.

[0062] The above embodiments further optimize the performance of the capacitor. Because the capacitance of the first capacitor core is greater than that of the second capacitor core, and they satisfy specific capacitance and quantity relationships, the capacitor can achieve a wider range of capacitance selection when adjusting its structure. Simultaneously, this capacitance and quantity relationship also makes the capacitor perform better in improving voltage quality and increasing withstand voltage. In a series circuit, the first capacitor core can handle a larger voltage distribution, while the second capacitor core provides more capacitance options; in a parallel circuit, the parallel combination of the second capacitor cores can increase the capacitance and improve circuit stability.

[0063] A charge / discharge monitoring module is used to monitor the charge / discharge state of the capacitor and output a discharge end signal when it is determined that the capacitor has completed discharging. This charge / discharge monitoring module can be implemented using an existing voltage detection unit, comparator, and a reference voltage source that provides the discharge threshold. When the comparator determines that the voltage of the capacitor detected by the voltage detection unit continues to decrease and falls below the discharge threshold (which is generally set to a voltage close to 0), it outputs a discharge end signal.

[0064] The status monitoring module plays a crucial role in capacitor operation control circuits, especially in high-voltage circuits. It effectively monitors the operating status of the capacitor cores, promptly identifies cores experiencing performance degradation, and allows for appropriate adjustments through the control and drive modules. This extends the capacitor's lifespan and improves its reliability and stability. Some feasible implementation methods are provided below:

[0065] In one feasible embodiment, reference Figure 3Each monitoring unit includes a current sensor, a timer, and a signal processing module. The current sensor monitors whether current flows through the capacitor core and sends a timing start signal when current is detected. The timer starts timing upon receiving the timing start signal and outputs a timing signal. The signal processor outputs a working status signal based on the timing signal and a timing threshold set for the capacitor core. In this embodiment, when the capacitor core is not running (not working), the current sensor detects no current, indicating that the capacitor core is in an idle state. When the capacitor core is running (working), the current sensor detects current, indicating that the capacitor core is in a running state. For a capacitor core in a running state, if the signal processor determines that the capacitor core is in a running state and the working time has exceeded its preset timing threshold, it indicates that the capacitor core is in an alarm state. When the capacitor operation control circuit is started, the status monitoring module initializes all monitoring units. The timer of each monitoring unit is reset to zero, and the current sensor begins monitoring the corresponding capacitor core. A current sensor monitors in real time whether current flows through the capacitor core. If the current sensor detects current, it indicates that the capacitor core is in operation, and the timer starts counting. If no current is detected, it indicates that the capacitor core is in idle state, and the timer stops counting. When the capacitor core is in operation, the timer records the operating time. The signal processor of each monitoring unit determines the operating status of the capacitor core based on the output signals of the current sensor and the timer. If the capacitor core is in idle state, the signal processor outputs an "idle state" operating status signal; if the capacitor core is in operation and the operating time has not exceeded the timing threshold, the signal processor outputs an "operating state" operating status signal; if the capacitor core is in operation and the operating time exceeds the timing threshold, the signal processor outputs an "alarm state" operating status signal. The status monitoring module collects the operating status signals of all monitoring units and sends them to the control module. Based on these operating status signals, the control module decides whether the capacitor structure needs adjustment when the capacitor discharge is complete.

[0066] In one feasible embodiment, reference Figure 4Each monitoring unit includes: a first comparator, a timer, and a second comparator. The first input of the first comparator is connected to the control level signal of the controlled switch connected in series with the capacitor core corresponding to the monitoring unit. The second input is based on a default level signal, and the output output is a first comparison signal. The timer is used to time the first comparison signal and outputs a timing signal. The second comparator outputs a working status signal based on the timing signal and a timing threshold set for the capacitor core. In this embodiment, since the opening and closing of the controlled switch can control the corresponding capacitor core to join or leave the capacitor structure, the control level signal of the controlled switch connected in series with the corresponding capacitor core can characterize the working state of the capacitor core. For example, the controlled switch is implemented using an N-MOSFET. If the control level signal is high, the controlled switch is closed, the capacitor core joins the capacitor structure, and it is in the operating state; if the control level signal is low, the controlled switch is open, the capacitor core leaves the capacitor structure, and it is in the idle state. For a capacitor core in operation, the comparison result between the control terminal level signal of the controlled switch connected in series with its default level signal (i.e., the first comparison signal) determines whether the capacitor core is in operation. A timer starts counting when the capacitor core is in operation (i.e., when the first comparison signal is active). A second comparator compares this timing signal with a timing threshold set for the capacitor core. When the timing duration exceeds the threshold, a working status signal indicating that the capacitor core is in an alarm state is output. This implementation is relatively simple, requires no separate current sensor, occupies less circuit space, and has lower cost.

[0067] In this embodiment of the invention, reference continues to be made. Figure 1 It also includes a first storage module connected to the control module; the first storage module is used to store the mapping relationship between the adjustment mode of the capacitor structure and the capacitance, wherein, except for the maximum capacity, the same capacitance corresponds to at least two adjustment modes, and the adjustment mode is characterized by the opening and closing control logic of multiple controlled switches; the control module generates a first control signal based on the discharge end signal, working status signal and the mapping relationship of each capacitor core, and adjusts the opening and closing of some of the multiple controlled switches, so that the capacitor core in the idle state replaces the capacitor core in the alarm state to work, and keeps the capacitor at its current capacitance.

[0068] The above provides a detailed explanation of how to maintain a constant capacitance for a given load in a charging / discharging circuit. However, in existing capacitor applications, the charging and discharging process is typically quite simple, lacking precise management of the capacitor core's operating state. Especially in scenarios with changing loads, the charging and discharging times of existing capacitors are difficult to adjust quickly to match load demands, leading to low circuit efficiency or malfunction.

[0069] Therefore, in another embodiment of the invention, the load in the charging and discharging circuit is variable; see reference. Figure 5 The capacitor operation control circuit further includes a load detection module and a second storage module. The load detection module is connected to the load in the charging and discharging circuit and is used to detect the resistance value of the load. The second storage module is used to store the correspondence between the resistance values ​​of different loads and the target capacitance. The control module is also used to determine the target capacitance based on the load resistance value detected by the load detection module and the correspondence, and to generate a second control signal for controlling the opening and closing of some of the controlled switches among multiple controlled switches. The drive module adjusts the capacitor structure according to the second control signal to adjust the capacitance of the capacitor to the target capacitance. According to the charging and discharging formula T=RC, where T is the charging time, R is the load resistance, and C is the capacitance, based on the above structure, the embodiment of the present invention can dynamically adjust the capacitance of the capacitor according to the load change, so that the charging and discharging time of the capacitor meets the current load application in the charging and discharging circuit, improving the overall adaptability and stability of the circuit.

[0070] The load detection module can detect the load resistance through a resistance measurement circuit. For example, a known current is injected into the load through a constant current source, the voltage across the load is measured, the load resistance is calculated according to Ohm's law, and the measured resistance signal is converted into a digital signal and transmitted to the processing module.

[0071] The first and second storage modules can be implemented using non-volatile memory chips such as EEPROM and Flash. Alternatively, they can be the same module; the distinction is based solely on their internal storage content. The second storage module stores data showing the correspondence between different pre-measured and calculated load resistance values ​​and their target charging times. This data can be programmed into the storage chip via a host computer and accessed by the control module during circuit operation.

[0072] The control module can be implemented using programmable logic devices such as microcontrollers or FPGAs. The drive module typically consists of a power drive circuit, used to convert the control signals output by the control module into drive signals capable of driving the controlled switch. For example, when using a MOSFET as the controlled switch, the drive module can consist of a MOSFET driver chip, which converts the control signal into a suitable voltage signal to drive the gate of the MOSFET, realizing the MOSFET's conduction (i.e., switch closing) and cutoff (i.e., switch opening), thereby changing the connection method between the capacitor cores to achieve the purpose of adjusting the capacitor structure and capacitance.

[0073] Based on the above embodiments, the working process of the capacitor operation control circuit of the present invention is as follows:

[0074] After load switching and initialization, the capacitors are de-energized. The control module determines the target capacitance based on the load resistance detected by the load detection module and the corresponding relationship. Then, based on this target capacitance and the mapping relationship between the capacitor structure adjustment method and capacitance, it generates a second control signal to control the opening and closing of some of the controlled switches. This signal is adjusted by the drive module to initialize the state of all controlled switches, ensuring the capacitor cores are connected according to a preset capacitor structure. For example, some capacitor cores are connected in series, and some are connected in parallel to form the initial capacitor structure.

[0075] After the initial capacitor structure is formed, the charge and discharge monitoring module monitors the charging and discharging state of the capacitor and outputs a discharge end signal when it determines that the capacitor has finished discharging.

[0076] Each monitoring unit of the status monitoring module begins monitoring the operating time of its corresponding capacitor core. For example, the monitoring unit determines whether the capacitor core is in operation by detecting the control terminal level signal of the controlled switch connected in series with the capacitor core, and counts the operating time. When the monitoring unit detects that the operating time of the capacitor core has reached a preset timing threshold, it outputs an alarm status signal; if the operating time has not reached the threshold, it outputs a running status signal; if the capacitor core is not operating, it outputs an idle status signal.

[0077] After receiving the operating status signal and the discharge end signal, the control module, upon determining that the capacitor is in the discharge end state and a capacitor core is in the alarm state, generates a first control signal based on the mapping relationship between the capacitor structure adjustment method and capacitance, to adjust the opening and closing of the corresponding controlled switches. If a capacitor core is in the alarm state, the control module will close the controlled switch corresponding to that capacitor core and open the controlled switches corresponding to other idle capacitor cores, allowing the idle capacitor cores to replace the alarm-state capacitor cores and maintain the target capacitance corresponding to the load unchanged. When the control module receives an alarm state operating status signal from a monitoring unit, it sends a timing reset signal to that monitoring unit, causing the monitoring unit to restart timing to monitor the operating time of the replaced capacitor cores.

[0078] This invention also discloses a capacitor, including the capacitor operation control circuit as described in this invention embodiment.

[0079] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0080] Relational terms such as “first” and “second” are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations, nor should they be construed as indicating or implying relative importance. Furthermore, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase “comprising one…” does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes the element.

[0081] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand this application, and the content of this specification should not be construed as a limitation of this application. Furthermore, for those skilled in the art, there will be different forms of changes in the specific implementation methods and application scope based on this application. It is neither necessary nor possible to exhaustively list all implementation methods here, and obvious changes or modifications derived therefrom are still within the protection scope of this application.

Claims

1. A capacitor operation control circuit, characterized in that, Used in charging and discharging circuits, including: Multiple capacitor cores; Multiple controlled switches are connected to the multiple capacitor cores to form a capacitor structure that combines series and parallel connections; The charge / discharge monitoring module is used to monitor the charge / discharge status of the capacitor and output a discharge end signal when it is determined that the capacitor has finished discharging. The status monitoring module includes monitoring units corresponding to each of the plurality of capacitor cores. Each monitoring unit is used to monitor the working time of its corresponding capacitor core and generate a working status signal. The working status signal includes: idle state, alarm state, and running state. The alarm state indicates that the capacitor core is in the running state and the working time has exceeded its timing threshold. The control module generates a first control signal for controlling the opening and closing of some of the multiple controlled switches based on the working status signal and the discharge end signal of each capacitor core. The drive module adjusts the capacitor structure according to the first control signal so that the idle capacitor core replaces the capacitor core in the alarm state, and the capacitor maintains its current capacitance.

2. The capacitor operation control circuit according to claim 1, characterized in that, The plurality of capacitor cores includes: m first capacitor cores Cx[0,m-1] and n second capacitor cores Cy[0,n-1], where m is a positive integer ≥2 and n is a positive integer ≥2; The plurality of controlled switches include: m+1 first switches K[0,m] and n second switches S[0,n-1]; The positive terminal of each of the first capacitor cores is connected to the positive power supply terminal of the capacitor through its corresponding first switch, and the negative terminals of each of the first capacitor cores are connected to form a common terminal. Each of the second capacitor cores is connected in series with its corresponding second switch to form a series branch. Each of the series branches is connected in parallel to form a parallel circuit. The parallel circuit is connected between the common terminal and the negative power supply terminal of the capacitor and is connected to the positive power supply terminal of the capacitor through its corresponding first switch.

3. The capacitor operation control circuit according to claim 2, characterized in that, The capacitance of the first capacitor core is greater than the capacitance of the second capacitor core; The value of m is 2, and the value of n ranges from 2 to 6.

4. The capacitor operation control circuit according to claim 2 or 3, characterized in that, in, The capacitor structure remains a series-parallel combination before and after adjustment.

5. The capacitor operation control circuit according to any one of claims 1-3, characterized in that, It also includes a first storage module connected to the control module; The first storage module is used to store the mapping relationship between the adjustment mode of the capacitor structure and the capacitance. Except for the maximum capacity, the same capacitance corresponds to at least two adjustment modes. The adjustment mode is characterized as the opening and closing control logic of multiple controlled switches. The control module generates the first control signal based on the discharge end signal, the working status signal, and the mapping relationship of each capacitor core.

6. The capacitor operation control circuit according to claim 1, characterized in that, The monitoring unit includes: A current sensor is used to monitor whether current is flowing through the capacitor core and to send a timing start signal when current is detected. A timer is used to start timing upon receiving the timing start signal and output a timing signal; The signal processor outputs the operating status signal based on the timing signal and the timing threshold set for the capacitor core.

7. The capacitor operation control circuit according to claim 1, characterized in that, The monitoring unit includes: The first comparator has a first input terminal connected to the control terminal level signal of the controlled switch connected in series with the capacitor core corresponding to the monitoring unit, a second input terminal based on a default level signal, and an output terminal outputting a first comparison signal. A timer is used to time the first comparison signal and output a timing signal; The second comparator outputs the operating status signal based on the timing signal and the timing threshold set for the capacitor core.

8. The capacitor operation control circuit according to claim 1 or 7, characterized in that, When the control module receives a working status signal that is in alarm state, it sends a timing reset signal to the monitoring unit that issued the working status signal.

9. The capacitor operation control circuit according to claim 1, Its features are, The load in the charging and discharging circuit is variable; The capacitor operation control circuit also includes: A load detection module is connected to the load in the charging and discharging circuit, and the load detection module is used to detect the resistance value of the load. The second storage module is used to store the correspondence between the resistance value of different loads and the target capacitance. The control module is also used to determine the target capacitance based on the resistance value of the load detected by the load detection module and the corresponding relationship, and to generate a second control signal for controlling the opening and closing of some of the multiple controlled switches. The driving module adjusts the capacitor structure according to the second control signal so that the capacitance of the capacitor is adjusted to the target capacitance.

10. A capacitor, characterized in that, Includes the capacitor operation control circuit as described in any one of claims 1-9.

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