Semiconductor structure and its preparation method

Abstract

This invention provides a semiconductor structure and its fabrication method. A bottom dielectric layer, a patterned etching delay layer, and an interconnect layer comprising an interconnect dielectric layer and an interconnect metal layer are sequentially formed on the upper surface of a substrate. A deep-hole etching process is then used to sequentially etch the substrate, the bottom dielectric layer, and the etching delay layer from the lower surface of the substrate, exposing the lower surface of the bottom interconnect metal layer to form a first via. Simultaneously, the substrate, the bottom dielectric layer, and the interconnect dielectric layer located between the bottom dielectric layer and the top interconnect metal layer are etched, exposing the lower surface of the top interconnect metal layer to form a second via. By introducing an etching delay layer with an etching rate lower than that of the interconnect dielectric layer, active control of the etching rate of the bottom interconnect metal layer is achieved, ensuring that the etching depth of the multi-layer vias is simultaneously achieved. This significantly reduces the risk of thinning, increased resistance, and deterioration of the electrical performance of the bottom interconnect metal layer due to over-etching.

Description

Technical Field

[0001] This invention relates to the field of semiconductor fabrication technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Against the backdrop of the rapid development of semiconductor technology, 3D stacking technology has emerged. By integrating multi-layer chip structures in the vertical direction, it greatly improves the integration density and performance of integrated circuits, thereby meeting the growing demand for high-performance chips.

[0003] Through-Silicon Vias (TSV) technology plays a crucial role as a key process for achieving 3D stacking. Especially in the TSV-Last manufacturing process, precise etching of TSVs from the lower surface of the wafer is required to achieve reliable connections with interconnect metal layers, thereby constructing conductive pathways between layers in the three-dimensional structure. However, in actual etching processes, if interconnect metal layers at different levels need to be etched simultaneously, the higher-level interconnect metal layers (closer to the lower wafer surface) often experience over-etching due to prolonged exposure to the etching environment. This over-etching problem leads to a reduction in the thickness of the higher-level interconnect metal layers, resulting in increased resistance and significant degradation of electrical performance, severely hindering the further development and application of high-precision 3D stacking technology. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor structure and its fabrication method to solve the problem of over-etching of higher-level interconnect metal layers in existing post-through-silicon via (TW) processes due to prolonged exposure to the etching environment.

[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor structure, the method comprising:

[0006] A substrate is provided having opposing upper and lower surfaces, wherein an underlying dielectric layer is formed on the upper surface of the substrate;

[0007] A patterned etching delay layer is formed on the underlying dielectric layer;

[0008] An interconnect layer is formed on the obtained structure. The interconnect layer includes an interconnect dielectric layer and an interconnect metal layer. The interconnect metal layer is embedded in the interconnect dielectric layer. The interconnect metal layer includes a bottom interconnect metal layer close to the substrate and a top interconnect metal layer away from the substrate. The upper surface of the etching delay layer is in contact with the lower surface of the bottom interconnect metal layer at a predetermined position, and the etching rate of the etching delay layer is less than the etching rate of the interconnect dielectric layer.

[0009] A deep-hole etching process is used to sequentially etch the substrate, the bottom dielectric layer, and the etching delay layer from the lower surface of the substrate, exposing the lower surface of the bottom interconnect metal layer to form a first via. Simultaneously, the substrate, the bottom dielectric layer, and the interconnect dielectric layer located between the bottom dielectric layer and the top interconnect metal layer are sequentially etched from the lower surface of the substrate, exposing the lower surface of the top interconnect metal layer to form a second via.

[0010] Optionally, the interconnect dielectric layer is made of SiO2, and the etching delay layer is made of SiN.

[0011] Optionally, the ratio η of the etching rate of the etching delay layer to the etching rate of the interconnect dielectric layer is ≤1 / 5.

[0012] Optionally, the thickness of the etching delay layer is T, defined as T = ΔL * η, where η is the ratio of the etching rate of the etching delay layer to the etching rate of the interconnect dielectric layer, and ΔL is the distance between the lower surface of the top interconnect metal layer and the lower surface of the bottom interconnect metal layer.

[0013] Optionally, the thickness of the etching delay layer is T, defined as T = ΔL * η / (1 - η), where η is the ratio of the etching rate of the etching delay layer to the etching rate of the interconnect dielectric layer, and ΔL is the distance between the lower surface of the top interconnect metal layer and the lower surface of the bottom interconnect metal layer.

[0014] Optionally, the thickness of the etching delay layer is 0.1 μm to 0.5 μm.

[0015] Optionally, the horizontal projection of the etching delay layer is located within the underlying interconnect metal layer.

[0016] Optionally, the horizontal projection of the etching delay layer covers the underlying interconnect metal layer.

[0017] Optionally, before forming the first through-hole and the second through-hole using a deep hole etching process, the method further includes the steps of flipping the substrate so that the lower surface of the substrate faces upward and thinning the lower surface of the substrate.

[0018] The present invention also provides a semiconductor structure, which is prepared by any of the semiconductor structure preparation methods described above.

[0019] As described above, the semiconductor structure and its fabrication method of the present invention have the following beneficial effects: By sequentially forming a bottom dielectric layer, a patterned etching delay layer, and an interconnect layer including an interconnect dielectric layer and an interconnect metal layer on the upper surface of a substrate, and using a deep-hole etching process to sequentially etch the substrate, the bottom dielectric layer, and the etching delay layer from the lower surface of the substrate, the lower surface of the bottom interconnect metal layer is exposed to form a first via. Simultaneously, the substrate, the bottom dielectric layer, and the interconnect dielectric layer located between the bottom dielectric layer and the top interconnect metal layer are etched, and the lower surface of the top interconnect metal layer is exposed to form a second via. By introducing an etching delay layer with an etching rate lower than that of the interconnect dielectric layer, active control of the etching rate of the bottom interconnect metal layer is achieved, ensuring that the etching depth of the multi-layer vias is simultaneously met. This significantly reduces the risk of thinning, increased resistance, and deterioration of electrical performance of the bottom interconnect metal layer due to over-etching. In addition, this method is highly compatible with existing processes, requires no additional complex steps, and the size design of the etching delay layer is flexible and can be adapted to various design scenarios, thus providing a more efficient and reliable solution for the fabrication of semiconductor structures. Attached Figure Description

[0020] Figure 1 The diagram shows a flow chart of the method for fabricating the semiconductor structure of the present invention.

[0021] Figures 2 to 7 The diagram shows a cross-sectional structure of each step in the preparation method of the semiconductor structure of the present invention.

[0022] Component designation explanation

[0023] 10 Substrates

[0024] 101 Top surface

[0025] 102 Lower surface

[0026] 11. Bottom Dielectric Layer

[0027] 12 Etching Resistant Layer

[0028] 13 Photoresist layer

[0029] 14 Interconnection Medium Layer

[0030] 15. Bottom interconnect metal layer

[0031] 16 Top Interconnect Metal Layer

[0032] 17 First through hole

[0033] 18 Second through hole

[0034] 20 interconnect metal layers

[0035] 21 Interconnection Layer Detailed Implementation

[0036] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] Please see Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0038] like Figure 1 As shown, this embodiment provides a method for fabricating a semiconductor structure, the method comprising:

[0039] S1, providing a substrate having opposing upper and lower surfaces, wherein an underlying dielectric layer is formed on the upper surface of the substrate;

[0040] S2, a patterned etching delay layer is formed on the underlying dielectric layer;

[0041] S3, an interconnect layer is formed on the obtained structure. The interconnect layer includes an interconnect dielectric layer and an interconnect metal layer. The interconnect metal layer is embedded in the interconnect dielectric layer. The interconnect metal layer includes a bottom interconnect metal layer close to the substrate and a top interconnect metal layer away from the substrate. The upper surface of the etching delay layer is in contact with the lower surface of the bottom interconnect metal layer at a predetermined position, and the etching rate of the etching delay layer is less than the etching rate of the interconnect dielectric layer.

[0042] S4, using a deep hole etching process, the substrate, the bottom dielectric layer, and the etching delay layer are sequentially etched from the lower surface of the substrate, and the lower surface of the bottom interconnect metal layer is exposed to form a first via. At the same time, the substrate, the bottom dielectric layer, and the interconnect dielectric layer located between the bottom dielectric layer and the top interconnect metal layer are sequentially etched from the lower surface of the substrate, and the lower surface of the top interconnect metal layer is exposed to form a second via.

[0043] The semiconductor structure fabrication method of this embodiment involves sequentially forming a bottom dielectric layer, a patterned etching delay layer, and an interconnect layer containing an interconnect dielectric layer and an interconnect metal layer on the upper surface of a substrate. A deep-hole etching process is then used to sequentially etch the substrate, the bottom dielectric layer, and the etching delay layer from the lower surface of the substrate, exposing the lower surface of the bottom interconnect metal layer to form a first via. Simultaneously, the substrate, the bottom dielectric layer, and the interconnect dielectric layer located between the bottom dielectric layer and the top interconnect metal layer are etched, exposing the lower surface of the top interconnect metal layer to form a second via. By introducing an etching delay layer with an etching rate lower than that of the interconnect dielectric layer, active control of the etching rate of the bottom interconnect metal layer is achieved, ensuring that the etching depth of the multi-layer vias is simultaneously achieved. This significantly reduces the risk of thinning, increased resistance, and deterioration of electrical performance of the bottom interconnect metal layer due to over-etching. Furthermore, this method is highly compatible with existing processes, requiring no additional complex steps, and the size design of the etching delay layer is flexible, adaptable to various design scenarios, thus providing a more efficient and reliable solution for semiconductor structure fabrication.

[0044] The following is combined Figures 2 to 7 The method for fabricating the semiconductor structure in this embodiment will be described in detail.

[0045] like Figure 2 As shown, step S1 is performed first, providing a substrate 10, which has an upper surface 101 and a lower surface 102 opposite to each other, and an underlayer dielectric layer 11 is formed on the upper surface 101 of the substrate 10.

[0046] As an example, the material of the substrate 10 includes, but is not limited to, silicon, germanium, gallium arsenide, indium phosphide and silicon carbide. The size of the substrate 10 is not limited here, but is preferably wafer-level.

[0047] like Figure 5 As shown, step S2 is then performed to form a patterned etching delay layer 12 on the underlying dielectric layer 11.

[0048] As a specific example, such as Figures 3 to 5 As shown, the method for forming a patterned etching delay layer 12 on the underlying dielectric layer 11 includes:

[0049] S21, as Figure 3 As shown, an etching delay layer 12 is deposited on the underlying dielectric layer 11.

[0050] S22, as Figure 4 As shown, a photoresist layer 13 is formed on the etching delay layer 12 and patterned thereon.

[0051] S23, as Figure 5As shown, a patterned etching delay layer 12 is formed based on the patterned photoresist layer 13, and the patterned photoresist layer 13 is removed.

[0052] like Figure 6 As shown, proceed to step S3, as follows: Figure 5 An interconnect layer 21 is formed on the structure shown. The interconnect layer 21 includes an interconnect dielectric layer 14 and an interconnect metal layer 20. The interconnect metal layer 20 is embedded in the interconnect dielectric layer 14. The interconnect metal layer 20 includes a bottom interconnect metal layer 15 close to the substrate 10 and a top interconnect metal layer 16 away from the substrate 10. The upper surface of the etching delay layer 12 is in contact with the lower surface of the bottom interconnect metal layer 15 at a predetermined position, and the etching rate of the etching delay layer 12 is less than the etching rate of the interconnect dielectric layer 14.

[0053] It should be noted that those skilled in the art should understand that the formed interconnect metal layer 20 may also include other interconnect metal layers besides the bottom interconnect metal layer 15 and the top interconnect metal layer 16 to meet different electrical connection requirements, and the projections of the bottom interconnect metal layer 15 and the top interconnect metal layer 16 in the horizontal direction will not completely overlap in order to meet different electrical connection requirements.

[0054] As an example, the material of the interconnect dielectric layer 14 includes silicon dioxide (SiO2), and the material of the etching delay layer 12 includes silicon nitride (SiN). By utilizing the high etching selectivity between silicon nitride and silicon dioxide, as well as the dual effects of the chemical inertness and physical barrier of silicon nitride, the etching process is delayed, and the etching rate of the bottom interconnect metal layer 15 and the top interconnect metal layer 16 is precisely controlled to ensure that the etching depth of subsequent multi-layer vias is simultaneously achieved, while avoiding over-etching damage to the bottom interconnect metal layer 15. In addition, the material of the etching delay layer 12 may also include other materials with higher density and significantly higher etching selectivity than the material of the interconnect dielectric layer 14, as long as they can play a role in delaying the etching process, without excessive restrictions.

[0055] As an example, the ratio η of the etching rate of the etching delay layer 12 to the etching rate of the interconnect dielectric layer 14 is ≤1 / 5, which further precisely controls the etching rate of the bottom interconnect metal layer 15 and the top interconnect metal layer 16, ensuring that the etching depth of subsequent multi-layer vias is simultaneously achieved.

[0056] As an example, the thickness of the etching delay layer 12 is T, defined as T = ΔL * η, where η is the ratio of the etching rate of the etching delay layer 12 to the etching rate of the interconnect dielectric layer 14, and ΔL is the spacing between the lower surface of the top interconnect metal layer 16 and the lower surface of the bottom interconnect metal layer 15 (e.g., ...). Figure 6 As shown, when it is necessary to roughly estimate the thickness of the etching delay layer 12, or when the distance (ΔL) between the lower surface of the top interconnect metal layer 16 and the lower surface of the bottom interconnect metal layer 15 reaches more than 10 times the thickness of the etching delay layer 12 and can be ignored, the formula T=ΔL*η can be used to estimate the thickness of the etching delay layer 12.

[0057] As another example, the thickness of the etching delay layer 12 is T, defined as T = ΔL * η / (1 - η), where η is the ratio of the etching rate of the etching delay layer 12 to the etching rate of the interconnect dielectric layer 14, and ΔL is the spacing between the lower surface of the top interconnect metal layer 16 and the lower surface of the bottom interconnect metal layer 15 (e.g., ...). Figure 6 As shown, when the distance (ΔL) between the lower surface of the top interconnect metal layer 16 and the lower surface of the bottom interconnect metal layer 15 is less than 10 times the thickness of the etching delay layer 12, it cannot be ignored. The thickness of the etching delay layer 12 is determined by the formula T=ΔL*η / (1-η) to ensure the accuracy of the etching effect.

[0058] As a further example, the thickness of the etching delay layer 12 is 0.1μm to 0.5μm, which further precisely controls the etching rate of the bottom interconnect metal layer 15 and the top interconnect metal layer 16, ensuring that the etching depth of subsequent multi-layer vias is simultaneously achieved.

[0059] like Figure 7 As shown, step S4 is then performed, in which a deep hole etching process is used to sequentially etch the substrate 10, the bottom dielectric layer 11, and the etching delay layer 12 from the lower surface of the substrate 10, and expose the lower surface of the bottom interconnect metal layer 15 to form a first via 17. At the same time, the substrate 10, the bottom dielectric layer 11, and the interconnect dielectric layer 14 located between the bottom dielectric layer 11 and the top interconnect metal layer 16 are sequentially etched from the lower surface of the substrate 10, and the lower surface of the top interconnect metal layer 16 is exposed to form a second via 18.

[0060] As an example, such as Figure 7 As shown, before step S4, that is, before forming the first through hole 17 and the second through hole 18 using the deep hole etching process, the process also includes flipping the substrate 10 so that the lower surface of the substrate 10 faces upward and thinning the lower surface of the substrate 10, so that the deep hole etching process can be carried out smoothly.

[0061] To adapt to different design scenarios, as an example, the horizontal projection of the etching delay layer 12 is located within the bottom interconnect metal layer 15. That is, in step S2, the etching delay layer 12 is formed only in the area where the first via 17 is formed in the subsequent step S4, or in step S2, the etching delay layer 12 is formed in an area with a larger planar size than the area of ​​the first via 17, rather than forming the etching delay layer 12 in the entire area of ​​the bottom interconnect metal layer 15. By limiting the formation area of ​​the etching delay layer 12 to a range slightly larger than the area where the first via 17 is subsequently formed, it is easier to achieve precise alignment between the etching delay layer 12 and the area of ​​the subsequently formed first via 17, reducing process complexity and error probability. At the same time, it ensures that critical metal areas are adequately protected during subsequent etching, avoiding metal layer thinning and performance degradation caused by over-etching.

[0062] As another example, the horizontal projection of the etching delay layer 12 covers the bottom interconnect metal layer 15. The formation area of ​​the etching delay layer 12 covers the entire area of ​​the subsequent formation of the bottom interconnect metal layer 15, ensuring that all areas that may be affected by etching during the etching process can be effectively protected, and further avoiding the over-etching problem of the bottom interconnect metal layer 15.

[0063] This embodiment also provides a semiconductor structure, which is prepared using the semiconductor structure preparation method described in the above embodiment. The beneficial effects it can achieve can be found in the specific description of the preparation method, and will not be repeated here.

[0064] In summary, the semiconductor structure and its fabrication method of the present invention, by sequentially forming a bottom dielectric layer, a patterned etching delay layer, and an interconnect layer including an interconnect dielectric layer and an interconnect metal layer on the upper surface of a substrate, and employing a deep-hole etching process to sequentially etch the substrate, the bottom dielectric layer, and the etching delay layer from the lower surface of the substrate, exposing the lower surface of the bottom interconnect metal layer to form a first via, simultaneously etching the substrate, the bottom dielectric layer, and the interconnect dielectric layer located between the bottom dielectric layer and the top interconnect metal layer, exposing the lower surface of the top interconnect metal layer to form a second via, by introducing an etching delay layer with an etching rate lower than that of the interconnect dielectric layer, achieves active control of the etching rate of the bottom interconnect metal layer, ensuring that the etching depth of the multi-layer vias is simultaneously achieved, significantly reducing the risk of thinning, increased resistance, and deterioration of electrical performance of the bottom interconnect metal layer due to over-etching. In addition, this method is highly compatible with existing processes, requiring no additional complex steps, and the size design of the etching delay layer is flexible and can be adapted to various design scenarios, thus providing a more efficient and reliable solution for the fabrication of semiconductor structures. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0065] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: A substrate is provided having opposing upper and lower surfaces, wherein an underlying dielectric layer is formed on the upper surface of the substrate; A patterned etching delay layer is formed on the underlying dielectric layer; An interconnect layer is formed on the obtained structure. The interconnect layer includes an interconnect dielectric layer and an interconnect metal layer. The interconnect metal layer is embedded in the interconnect dielectric layer. The interconnect metal layer includes a bottom interconnect metal layer close to the substrate and a top interconnect metal layer away from the substrate. The upper surface of the etching delay layer is in contact with the lower surface of the bottom interconnect metal layer at a predetermined position, and the ratio of the etching rate of the etching delay layer to the etching rate of the interconnect dielectric layer, η, is ≤ 1 / 5. The thickness of the etching delay layer is T, defined as T = ΔL * η / (1 - η), where η is the ratio of the etching rate of the etching delay layer to the etching rate of the interconnect dielectric layer, and ΔL is the distance between the lower surface of the top interconnect metal layer and the lower surface of the bottom interconnect metal layer. The horizontal projection of the etching delay layer is located within the bottom interconnect metal layer or the horizontal projection of the etching delay layer covers the bottom interconnect metal layer. A deep-hole etching process is used to sequentially etch the substrate, the bottom dielectric layer, and the etching delay layer from the lower surface of the substrate, exposing the lower surface of the bottom interconnect metal layer to form a first via. Simultaneously, the substrate, the bottom dielectric layer, and the interconnect dielectric layer located between the bottom dielectric layer and the top interconnect metal layer are sequentially etched from the lower surface of the substrate, exposing the lower surface of the top interconnect metal layer to form a second via.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The interconnect dielectric layer is made of SiO2, and the etching delay layer is made of SiN.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The thickness of the etching delay layer is 0.1 μm to 0.5 μm.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: Before forming the first through-hole and the second through-hole using deep hole etching, the method further includes the steps of flipping the substrate so that the lower surface of the substrate faces upward and thinning the lower surface of the substrate.

5. A semiconductor structure, characterized in that: It is prepared by the method for preparing the semiconductor structure as described in any one of claims 1 to 4.

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