Chip packaging structure for improving binding failure and electronic equipment

Abstract

The invention provides a chip packaging structure for improving binding failure and electronic equipment, and belongs to the field of power electronics. The chip packaging structure comprises a packaging chip and a packaging frame, electrodes are arranged on the first surface of the packaging chip, and welding spots in one-to-one correspondence with the electrodes are arranged on the surface, opposite to the first surface, of the packaging frame; the electrode comprises a first metal layer and a second metal layer, the first metal layer is located on the first surface, and the second metal layer is located on the surface, close to the packaging frame, of the first metal layer; the orthographic projection of the second metal layer on the first surface is located in the orthographic projection of the first metal layer on the first surface; the welding spots are bound with the corresponding electrodes, and the surface of the second metal layer and the surface of the first metal layer are both connected with the welding spots. According to the embodiment of the invention, the connection reliability between the welding spot of the packaging frame and the electrode of the transistor can be improved, and the service life is prolonged.

Description

Technical Field

[0001] The present disclosure relates to the field of power electronics, and in particular to a chip packaging structure and electronic equipment for improving binding failure. Background Art

[0002] High Electron Mobility Transistor (HEMT) is a heterojunction field-effect transistor widely used in various electronic appliances.

[0003] In related technologies, transistors are typically packaged on a packaging frame, with the source, drain, and gate of the transistor bonded to solder joints on the packaging frame. An encapsulation layer is then formed on the surface of the packaging frame, wrapping around the transistor to form the transistor package structure.

[0004] Typically, the solder joints between transistor electrodes and package frames are relatively small. During reliability verification or actual application of chip packaging structures, cracks are likely to form between the solder joints of the package frame and the transistor electrodes due to mechanical or thermal stress, leading to reliability failure of the chip packaging structure and shortening its service life. Summary of the Invention

[0005] The present disclosure provides a chip packaging structure and electronic device that improves bonding failure, thereby enhancing the connection reliability between the solder joints of the packaging frame and the electrodes of the transistors and extending the service life. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a chip packaging structure, which includes: a packaged chip and a package frame, wherein the first surface of the packaged chip has an electrode, and the surface of the package frame opposite to the first surface has solder joints corresponding one-to-one to the electrodes; the electrodes include a first metal layer and a second metal layer, the first metal layer is located on the first surface, the second metal layer is located on the surface of the first metal layer close to the package frame, and the orthographic projection of the second metal layer on the first surface is located within the orthographic projection of the first metal layer on the first surface; the solder joints are bound to the corresponding electrodes, and the surfaces of the second metal layer and the first metal layer are both connected to the solder joints.

[0007] In one embodiment of the present disclosure, the second metal layer includes a plurality of bumps, and the plurality of bumps are arranged at intervals on the surface of the first metal layer; or, the second metal layer includes a plurality of strip blocks, and the plurality of strip blocks are arranged in parallel and at intervals on the surface of the first metal layer; or, the surface of the second metal layer away from the first metal layer has a plurality of through holes arranged at intervals, and the through holes expose the first metal layer.

[0008] In one implementation of the present disclosure, the first metal layer is cylindrical, the diameter of the first metal layer is D, and the thickness of the second metal layer is h; when 40μm<D≤60μm, 5μm≤h<10μm; when 60μm<D≤80μm, 10μm≤h<15μm; when D>80μm, h≥15μm.

[0009] In another implementation of the present disclosure, the first metal layer is cylindrical, the diameter of the first metal layer is D, the orthographic projection area of ​​the first metal layer on the first surface is S0, and the orthographic projection area of ​​the second metal layer on the first surface is S1; when 40μm<D≤60μm, 30%≤(S0-S1) / S0<50%; when 60μm<D≤80μm, 20%≤(S0-S1) / S0<30%; when D>80μm, 10%≤(S0-S1) / S0<20%.

[0010] In another implementation of the present disclosure, the first metal layer includes at least one of a Cu layer, a Ni layer, and an Au layer, and the second metal layer includes at least one of a Cu layer, a Ni layer, and an Au layer.

[0011] In another implementation of the present disclosure, the packaging frame includes at least two conductive layers connected in sequence; the surface of each conductive layer has a groove that penetrates the conductive layer, the grooves of two adjacent conductive layers are connected, and the widths of the grooves of two adjacent conductive layers are different; the chip packaging structure also includes a packaging layer, which is located on the surface of the packaging frame, in the groove and covers the packaged chip.

[0012] In another implementation of the present disclosure, the thickness of the conductive layer is 50 μm to 80 μm, and the width of the groove is 150 μm to 600 μm.

[0013] In another implementation of the present disclosure, the conductive layer includes at least one of a Cu layer, an Ag layer, a Ni layer, a Pd layer, and an Au layer.

[0014] In another implementation of the present disclosure, the welding points and the grooves are arranged at intervals.

[0015] On the other hand, an embodiment of the present disclosure provides an electronic device, comprising: a circuit board and the chip packaging structure as described above, wherein the packaging frame is located on a surface of the circuit board.

[0016] The beneficial effects of the technical solutions provided by the embodiments of the present disclosure include at least:

[0017] The chip packaging structure provided by the embodiment of the present disclosure sets the electrodes of the packaged chip as a first metal layer and a second metal layer stacked in sequence, wherein the second metal layer is located on the surface of the first metal layer close to the packaging frame, and the orthographic projection of the second metal layer on the first surface is located within the orthographic projection of the first metal layer on the first surface, that is, the size of the second metal layer is smaller than the size of the first metal layer, and the second metal layer does not completely cover the first metal layer, so that a part of the first metal layer is exposed. In this way, when the solder joint is bound to the electrode, the solder joint can not only connect to the surface of the second metal layer, but also to the surface of the first metal layer, thereby enhancing the connection reliability between the electrode and the solder joint by increasing the contact area between the solder joint and the electrode.

[0018] At the same time, the second metal layer is stacked on the first metal layer, so that the contact interface between the electrode and the solder joint is uneven. The uneven contact interface can better buffer the mechanical stress and thermal stress between the electrode and the solder joint, thereby avoiding cracks between the electrode and the solder joint, preventing the reliability failure of the chip packaging structure, and extending the service life of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 This is a schematic diagram of a chip packaging structure provided by the related art;

[0021] Figure 2 is a schematic diagram of a chip packaging structure provided by an embodiment of the present disclosure;

[0022] Figure 3 yes Figure 2 A partial enlarged schematic diagram in the middle;

[0023] Figure 4 is a schematic structural diagram of an electrode provided by an embodiment of the present disclosure;

[0024] Figure 5 is a schematic structural diagram of an electrode provided by an embodiment of the present disclosure;

[0025] Figure 6 It is a structural schematic diagram of an electrode provided in an embodiment of the present disclosure.

[0026] The descriptions of the marks in the figure are as follows:

[0027] 10. Package chip; 11. Electrode; 111. First metal layer; 112. Second metal layer;

[0028] 20. Package frame; 21. Solder joint; 22. Conductive layer; 23. Groove;

[0029] 30. Encapsulation layer. DETAILED DESCRIPTION

[0030] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0031] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," "third," and similar words used in the patent specification and claims of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, terms such as "a" or "an" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Terms such as "include" or "comprise" mean that the elements or objects preceding "include" or "comprises" encompass the elements or objects listed after "include" or "comprises," and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," "right," "top," and "bottom" are used only to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0032] Figure 1 This is a schematic diagram of a chip packaging structure provided by the related technology. Figure 1 As shown, the chip packaging structure includes: a packaging chip 10, a packaging frame 20 and a packaging layer 30. The electrodes 11 of the packaging chip 10 are bound to the solder joints 21 of the packaging frame 20. The packaging layer 30 is located on the packaging frame 20 and wraps the packaging chip 10.

[0033] Optionally, the packaged chip 10 may be a light emitting diode and / or a transistor.

[0034] Exemplarily, when the packaged chip 10 is a light emitting diode, the electrode 11 of the packaged chip 10 may be a p-electrode 11 or an n-electrode 11 .

[0035] Exemplarily, when the packaged chip 10 is a transistor, the electrode 11 of the packaged chip 10 may be a source, a drain, or a gate.

[0036] Usually, the size of the solder joints 21 of the transistor electrodes 11 and the package frame 20 is small. When verifying the reliability of the chip package structure or in actual application, due to the effects of mechanical stress or thermal stress, such as Figure 1 As shown, cracks are easily generated between the solder joints 21 of the package frame 20 and the electrodes 11 of the transistor (see Figure 1 This causes the chip packaging structure to lose reliability and shorten its service life.

[0037] To this end, an embodiment of the present disclosure provides a chip packaging structure. Figure 2 Schematic diagram of a chip packaging structure provided by an embodiment of the present disclosure. Figure 2 As shown, the chip packaging structure includes: a chip and a packaging frame 20 . The first surface of the packaged chip 10 has electrodes 11 , and the surface of the packaging frame 20 opposite to the first surface has solder joints 21 corresponding to the electrodes 11 .

[0038] Figure 3 yes Figure 2 A local enlarged schematic diagram. Figure 3 As shown, the electrode 11 includes a first metal layer 111 and a second metal layer 112. The first metal layer 111 is located on the first surface, and the second metal layer 112 is located on the surface of the first metal layer 111 close to the packaging frame 20. The orthographic projection of the second metal layer 112 on the first surface is located within the orthographic projection of the first metal layer 111 on the first surface.

[0039] like Figure 3 As shown, the solder joint 21 is bonded to the corresponding electrode 11 , and the surface of the second metal layer 112 and the surface of the first metal layer 111 are both connected to the solder joint 21 .

[0040] The chip packaging structure provided by the embodiment of the present disclosure sets the electrode 11 of the packaged chip 10 as a first metal layer 111 and a second metal layer 112 stacked in sequence, wherein the second metal layer 112 is located on the surface of the first metal layer 111 close to the packaging frame 20, and the orthographic projection of the second metal layer 112 on the first surface is located within the orthographic projection of the first metal layer 111 on the first surface, that is, the size of the second metal layer 112 is smaller than the size of the first metal layer 111, and the second metal layer 112 does not completely cover the first metal layer 111, so that a part of the first metal layer 111 is exposed. In this way, when the solder joint 21 is bound to the electrode 11, in addition to being connected to the surface of the second metal layer 112, the solder joint 21 can also be connected to the surface of the first metal layer 111, thereby enhancing the connection reliability between the electrode 11 and the solder joint 21 by increasing the contact area between the solder joint 21 and the electrode 11.

[0041] At the same time, the second metal layer 112 is stacked on the first metal layer 111, so that the contact interface between the electrode 11 and the solder joint 21 is uneven, and the uneven contact interface can better buffer the mechanical stress and thermal stress between the electrode 11 and the solder joint 21, thereby avoiding cracks between the electrode 11 and the solder joint 21, preventing the reliability failure of the chip packaging structure, and extending the service life of the chip packaging structure.

[0042] Figure 4 Schematic diagram of the structure of an electrode 11 provided in an embodiment of the present disclosure. Figure 4 As shown, the second metal layer 112 includes a plurality of bumps, and the plurality of bumps are arranged on the surface of the first metal layer 111 at intervals.

[0043] For example, Figure 4 As shown, the bumps have a rectangular cross-section, and a plurality of bumps are arranged in an array on the surface of the first metal layer 111. This results in a grid-like pattern of the exposed first metal layer 111, exposing a larger area of ​​the first metal layer 111 for contact with the solder joint 21. Furthermore, the array of bumps makes the contact interface between the electrode 11 and the solder joint 21 more uneven. This uneven structure on the contact interface changes the thermal stress distribution, shifting the local tensile stress concentration area while releasing the compressive stress, thereby delaying failure of the connection between the electrode 11 and the solder joint 21.

[0044] The cross-sectional shape of the bump refers to the shape of a cross section of the bump parallel to the first surface.

[0045] It should be noted that the cross-sectional shape of the bump may also be circular, triangular, elliptical or arcuate, which is not limited in the embodiment of the present disclosure.

[0046] Figure 5 Schematic diagram of the structure of an electrode 11 provided in an embodiment of the present disclosure. Figure 5 As shown, the second metal layer 112 includes a plurality of strip-shaped blocks, and the plurality of strip-shaped blocks are arranged in parallel and at intervals on the surface of the first metal layer 111 .

[0047] For example, Figure 5 As shown, multiple strip blocks are arranged in parallel to form directionally arranged reinforcement ribs on the surface of the first metal layer 111. When subjected to mechanical stress and thermal stress in a specific direction, the strip-shaped second metal layer 112 can disperse the pressure through its own long axial span to delay the failure of the connection between the electrode 11 and the solder joint 21.

[0048] Figure 6 Schematic diagram of the structure of an electrode 11 provided in an embodiment of the present disclosure. Figure 6 As shown, a surface of the second metal layer 112 away from the first metal layer 111 has a plurality of spaced-apart through holes, and the through holes expose the first metal layer 111 .

[0049] For example, the cross-sectional shape of the through-holes is rectangular, and multiple through-holes are arranged in an array on the surface of the second metal layer 112. This results in a grid-like pattern of the exposed second metal layer 112. This mesh-like second metal layer 112 not only alters the thermal stress distribution, shifting areas of local tensile stress concentration while simultaneously relieving compressive stress, but also prevents the lateral expansion of cracks. Therefore, even if a crack forms between the electrode 11 and the solder joint 21, further expansion of the crack is prevented by this second metal layer 112 structure.

[0050] The cross-sectional shape of the through hole refers to the shape of the cross section of the through hole parallel to the first surface.

[0051] It should be noted that the cross-sectional shape of the through hole may also be circular, triangular, elliptical or arcuate, which is not limited in the embodiment of the present disclosure.

[0052] Alternatively, as Figure 3 As shown, the first metal layer 111 is cylindrical, the diameter of the first metal layer 111 is D, and the thickness of the second metal layer 112 is h.

[0053] When 40μm<D≤60μm, 5μm≤h<10μm.

[0054] This ensures a ratio of 8% to 25% of the diameter of the first metal layer 111, effectively increasing the discontinuity of the contact area and creating a similar anti-slip effect. When the solder joint 21 contacts the electrode 11, the array of protrusions increases the friction between the electrode 11 and the solder joint 21 through localized deformation or embedding, preventing the solder joint 21 from easily loosening from the electrode 11.

[0055] When 60μm<D≤80μm, 10μm≤h<15μm.

[0056] Within the above-mentioned size range, the ratio of the protrusion height to the diameter of the first metal layer 111 is 13% to 25%, which can form effective micro-roughness and significantly improve the friction between the electrode 11 and the solder joint 21 by increasing the discontinuity of the contact area.

[0057] When D>80μm, h≥15μm.

[0058] Within the above-mentioned size range, when the size of the first metal layer 111 is larger, the height of the second metal layer 112 is also larger, so that the ratio of the protrusion height to the diameter of the first metal layer 111 is more reasonable, and effective micro-roughness can be formed. By increasing the discontinuity of the contact area, the friction between the electrode 11 and the welding point 21 can be significantly improved.

[0059] Optionally, the first metal layer 111 is cylindrical, the diameter of the first metal layer 111 is D, the orthographic projection area of ​​the first metal layer 111 on the first surface is S0, and the orthographic projection area of ​​the second metal layer 112 on the first surface is S1.

[0060] When 40 μm<D≤60 μm, 30%≤(S0-S1) / S0<50%.

[0061] By controlling the area ratio of the second metal layer 112 not covering the first metal layer 111 within the above range, the second metal layer 112 can share at least half of the load on the electrode 11 , thereby reducing the wear rate of the electrode 11 .

[0062] When 60 μm < D ≤ 80 μm, 20% ≤ (S0-S1) / S0 < 30%, allowing the coverage of the second metal layer 112 to exceed 70%. Furthermore, when the second metal layer 112 comprises a plurality of spaced-apart protrusions, densely distributed microscopic contact peaks can be formed, thereby fully dissipating stress to each protrusion.

[0063] When D > 80 μm, 10% ≤ (S0 - S1) / S0 < 20%. This allows the coverage of the second metal layer 112 to reach 80% to 90%. When the size of the first metal layer 111 is large enough, the second metal layer 112 provides more complete coverage, effectively improving the connection reliability between the solder joint 21 and the electrode 11.

[0064] Optionally, the first metal layer 111 includes at least one of a Cu layer, a Ni layer, and an Au layer, and the second metal layer 112 includes at least one of a Cu layer, a Ni layer, and an Au layer.

[0065] Among them, Ni has good thermal stability and can maintain structural stability during high-temperature annealing.

[0066] For example, when the packaged chip 10 is a transistor, when the Ni layer contacts the barrier layer, the work function difference can form a higher Schottky barrier, effectively suppressing reverse leakage current.

[0067] Among them, the resistivity of Cu is only 1.7 μΩ·cm, which is much better than Ni and Au, and can improve the current carrying capacity of the electrode 11.

[0068] The chemical inertness of Au can protect the underlying metal from environmental oxidation or wet etching, thereby improving the long-term stability of the electrode 11 .

[0069] Exemplarily, the first metal layer 111 and the second metal layer 112 may be made of the same material. For example, the first metal layer 111 and the second metal layer 112 are both Cu layers.

[0070] Exemplarily, the first metal layer 111 and the second metal layer 112 may be made of different materials. For example, the first metal layer 111 is a Cu layer, and the second metal layer 112 is an Au layer.

[0071] Alternatively, as Figure 2 As shown, the packaging frame 20 includes at least two conductive layers 22 connected in sequence; the surface of each conductive layer 22 has a groove 23 that penetrates the conductive layer 22, the grooves 23 of the two adjacent conductive layers 22 are connected, and the widths of the grooves 23 of the two adjacent conductive layers 22 are different.

[0072] like Figure 2 As shown, the chip packaging structure further includes a packaging layer 30 . The packaging layer 30 is located on the surface of the packaging frame 20 , in the groove 23 , and covers the packaged chip 10 .

[0073] In the chip packaging structure provided by the embodiment of the present disclosure, the packaged chip 10 is bound to the packaging frame 20. The packaging frame 20 includes two stacked conductive layers 22, each of which has a groove 23, and the two grooves 23 are connected to form a through hole penetrating the packaging frame 20.

[0074] Furthermore, the grooves 23 of two adjacent conductive layers 22 have different widths. This means that the walls of the through-holes formed by the combination that penetrate the package frame 20 are not smooth, and a step exists at the junction of the two grooves 23. Therefore, when the package layer 30 extends into the two grooves 23, it not only contacts the groove walls but also the step, thereby increasing the contact area between the package layer 30 and the grooves 23. This effectively increases the contact area between the package layer 30 and the package frame 20, thereby improving the connection reliability between the packaged chip 10 and the package frame 20.

[0075] Optionally, the ratio of the widths of two adjacent grooves 23 is 0.5 to 1. By setting the ratio of the widths of two adjacent grooves 23 within the above range, it is possible to avoid a large difference in the widths of adjacent grooves 23, which would increase the difficulty of etching the grooves 23. It is also possible to avoid overlapping of adjacent grooves 23, which would prevent the formation of steps between adjacent grooves 23 and affect the connection reliability between the encapsulation layer 30 and the grooves 23.

[0076] Exemplarily, the ratio of the widths of two adjacent grooves 23 is 0.7.

[0077] Optionally, the width of the groove 23 is 150 μm to 300 μm.

[0078] Controlling the width of the groove 23 within the above range can prevent the groove 23 from being too narrow, which would increase the difficulty of etching the groove 23 and improve the efficiency of packaging frame preparation. It can also ensure that the width of the groove 23 is sufficiently large, so that when etching the groove 23, a wide range of groove 23 widths can be selected, thereby simplifying the etching difficulty of the groove 23. It can also prevent the groove 23 from being too wide, which would result in a larger groove 23 width and cause more areas of the packaging frame to be etched, affecting the stability of the packaging frame.

[0079] For example, the width of one of the two adjacent grooves 23 is 200 μm, and the width of the other of the two adjacent grooves 23 is 100 μm.

[0080] Optionally, the thickness of the conductive layer 22 is 50 μm to 80 μm.

[0081] The thicknesses of the conductive layers 22 may be the same or different.

[0082] Exemplarily, the thickness of the conductive layer 22 close to the packaged chip 10 is smaller than the thickness of the conductive layer 22 far from the packaged chip 10 .

[0083] For example, the package wireframe includes two conductive layers 22 . The thickness of the conductive layer 22 close to the package chip 10 is 60 μm, and the thickness of the conductive layer 22 far from the package chip 10 is 70 μm.

[0084] The width of the groove 23 near the packaged chip 10 can be set to be smaller, so that the thickness of the conductive layer 22 near the packaged chip 10 can also be smaller, so as to facilitate etching of the groove 23 with a smaller width.

[0085] Optionally, the conductive layer 22 includes at least one of a Cu layer, an Ag layer, a Ni layer, a Pd layer, and an Au layer.

[0086] Exemplarily, the conductive layer 22 may be a Cu layer.

[0087] Using metal Cu as the preparation material of the packaging frame can meet the electrical connection between the packaging frame and the electrode 11 of the chip, so that current can be input to the chip through the packaging frame; and metal Cu has good strength, which can improve the stability of the packaging frame.

[0088] Optionally, the welding spots 21 and the grooves 23 are arranged at intervals.

[0089] For example, Figure 2 As shown, the packaged chip 10 may be a transistor. Figure 2 In the direction from left to right in the figure, the first electrode 11 of the transistor is a drain, the second electrode 11 of the transistor is a source, and the third electrode 11 of the transistor is a gate.

[0090] For example, Figure 2 As shown, the surface of the package frame has three solder joints 21 , and each solder joint 21 is bonded to an electrode 11 of a transistor.

[0091] like Figure 2 As shown, the packaging layer 30 also extends to the gap between the electrode 11 and the solder joint 21 . By wrapping the electrode 11 and the solder joint 21 with the packaging layer 30 , the connection reliability between the electrode 11 and the solder joint 21 can be improved.

[0092] Optionally, the encapsulation layer 30 includes a resin layer. The resin layer can protect the chip, making it less susceptible to moisture or moisture absorption, and less susceptible to stress damage, thereby improving reliability.

[0093] Optionally, the packaged chip 10 may be a light emitting diode and / or a transistor.

[0094] Exemplarily, the transistor includes: an epitaxial wafer, a source, a drain and a gate; the epitaxial wafer includes a channel layer and a barrier layer stacked in sequence, the source, the drain and the gate are all located on the barrier layer, the source and the drain pass through the barrier layer and are connected to the channel layer, the gate is located between the source and the drain, and the gate is connected to the barrier layer.

[0095] For example, the channel layer is a GaN layer, and the barrier layer is an AlGaN layer. A high-concentration two-dimensional electron gas channel forms at the AlGaN / GaN heterojunction interface. This high-concentration and high-electron-mobility two-dimensional electron gas channel is the greatest advantage of GaN high-electron-mobility transistors over traditional field-effect transistors.

[0096] Exemplarily, the drain electrode, the drain electrode, and the gate electrode may each include at least one of a Ti layer, an Al layer, a Pt layer, a Ni layer, and an Au layer.

[0097] The above metal materials have good heat dissipation performance. Therefore, the drain, drain electrode and gate electrode prepared by the above materials also have good heat dissipation performance, which can improve the heat dissipation effect of the transistor.

[0098] Exemplarily, the light emitting diode includes an epitaxial layer and two electrodes 11. The epitaxial layer includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence, and a surface of the second semiconductor layer has a groove 23 exposing the first semiconductor layer.

[0099] Optionally, one electrode 11 is located in the groove 23 and connected to the first semiconductor layer, and the other electrode 11 is located on the surface of the second semiconductor layer.

[0100] In the embodiment of the present disclosure, one of the first semiconductor layer and the second semiconductor layer is an n-type layer, and the other of the first semiconductor layer and the second semiconductor layer is a p-type layer.

[0101] Exemplarily, the first semiconductor layer is an n-type layer, and the second semiconductor layer is a p-type layer.

[0102] The following describes the structure of each layer by taking a blue epitaxial structure as an example. In the blue epitaxial structure, the p-type layer includes a p-type GaN layer.

[0103] The multi-quantum well layer may include alternately grown InGaN quantum well layers and GaN quantum barrier layers. The third light-emitting layer may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0104] The n-type layer includes an n-type GaN layer.

[0105] Optionally, the epitaxial layer has a thickness of 2 μm to 10 μm.

[0106] Exemplarily, the thickness of the epitaxial layer is 6 μm.

[0107] An embodiment of the present disclosure provides an electronic device, which includes a circuit board and the chip packaging structure as described above, wherein the packaging frame 20 is located on a surface of the circuit board.

[0108] Exemplarily, the electronic device may be any electronic device including a package carrier board, such as a server, a mobile phone, a computer, a television, a game console, or an electronic watch.

[0109] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A chip packaging structure, characterized in that: The chip packaging structure comprises: a packaging chip (10) and a packaging frame (20); a first surface of the packaging chip (10) has an electrode (11); a surface of the packaging frame (20) opposite to the first surface has solder joints (21) corresponding one-to-one to the electrode (11); The electrode (11) comprises a first metal layer (111) and a second metal layer (112), the first metal layer (111) being located on the first surface, the second metal layer (112) being located on a surface of the first metal layer (111) close to the packaging frame (20), and an orthographic projection of the second metal layer (112) on the first surface being located within an orthographic projection of the first metal layer (111) on the first surface; The welding point (21) is bound to the corresponding electrode (11), and the surface of the second metal layer (112) and the surface of the first metal layer (111) are both connected to the welding point (21).

2. The chip packaging structure according to claim 1, wherein: The second metal layer (112) comprises a plurality of bumps, and the plurality of bumps are arranged at intervals on the surface of the first metal layer (111); or, The second metal layer (112) comprises a plurality of strip-shaped blocks, and the plurality of strip-shaped blocks are arranged in parallel and at intervals on the surface of the first metal layer (111); or, A surface of the second metal layer (112) away from the first metal layer (111) has a plurality of through holes arranged at intervals, and the through holes expose the first metal layer (111).

3. The chip packaging structure according to claim 1, wherein: The first metal layer (111) is cylindrical, the diameter of the first metal layer (111) is D, and the thickness of the second metal layer (112) is h; When 40μm<D≤60μm, 5μm≤h<10μm; when 60μm<D≤80μm, 10μm≤h<15μm; when D>80μm, h≥15μm.

4. The chip packaging structure according to claim 1, wherein: The first metal layer (111) is cylindrical, the diameter of the first metal layer (111) is D, the orthographic projection area of ​​the first metal layer (111) on the first surface is S0, and the orthographic projection area of ​​the second metal layer (112) on the first surface is S1; When 40μm<D≤60μm, 30%≤(S0-S1) / S0<50%; when 60μm<D≤80μm, 20%≤(S0-S1) / S0<30%; when D>80μm, 10%≤(S0-S1) / S0<20%.

5. The chip packaging structure according to claim 1, wherein: The first metal layer (111) includes at least one of a Cu layer, a Ni layer, and an Au layer, and the second metal layer (112) includes at least one of a Cu layer, a Ni layer, and an Au layer.

6. The chip packaging structure according to any one of claims 1 to 5, characterized in that: The packaging frame (20) comprises at least two conductive layers (22) connected in sequence; the surface of each conductive layer (22) has a groove (23) penetrating the conductive layer (22); the grooves (23) of two adjacent conductive layers (22) are connected; and the widths of the grooves (23) of the two adjacent conductive layers (22) are different; The chip packaging structure further comprises a packaging layer (30), wherein the packaging layer (30) is located on the surface of the packaging frame (20), in the groove (23), and covers the packaged chip (10).

7. The chip packaging structure according to claim 6, wherein: The thickness of the conductive layer (22) is 50 μm to 80 μm, and the width of the groove (23) is 150 μm to 600 μm.

8. The chip packaging structure according to claim 6, wherein: The conductive layer (22) includes at least one of a Cu layer, an Ag layer, a Ni layer, a Pd layer and an Au layer.

9. The chip packaging structure according to claim 6, wherein: The welding points (21) and the grooves (23) are arranged at intervals.

10. An electronic device, characterized in that: The electronic device comprises: a circuit board and a chip packaging structure according to any one of claims 1 to 9, wherein the packaging frame (20) is located on a surface of the circuit board.

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