Programmable second harmonic suppression circuit based on conduction angle calibration principle

Abstract

The invention belongs to the technical field of wireless communication, and relates to a harmonic suppression circuit, in particular to a programmable second harmonic suppression circuit based on a conduction angle calibration principle, which comprises a power amplifier and a conduction angle calibration loop, and is characterized in that the conduction angle calibration loop is used for detecting a direct-current component of a radio frequency signal (RF) output by the power amplifier; and the direct-current component is enabled to be equal to the reference voltage in the conduction angle calibration loop through feedback regulation, and at the moment, the conduction angle calibration loop is stable, so that harmonic suppression is realized. A traditional harmonic suppression scheme adopting an LC filter network is abandoned, an operational amplifier is used for forming a feedback loop, the feedback loop is used for dynamically adjusting the conduction angle of a power amplifier, the duty ratio of an RF signal is kept to be 50%, and suppression of a second harmonic component is achieved; compared with a traditional LC filter circuit, the filter circuit is compact in structure, smaller in area, lower in cost and easier in circuit integration.

Description

Technical Field

[0001] The present invention belongs to the technical field of wireless communications, relates to a harmonic suppression circuit, and specifically provides a programmable second harmonic suppression circuit based on a conduction angle calibration principle. Background Art

[0002] As the cornerstone of modern information technology, wireless communication technology has not only greatly promoted the rapid transmission and exchange of information, but also promoted progress in many fields such as mobile Internet, Internet of Things, telemedicine, and intelligent transportation. With the popularization of 5G technology and the advancement of 6G research, wireless communication is achieving higher-speed and lower-latency data transmission, providing support for emerging applications such as virtual reality and autonomous driving, thereby profoundly changing people's lifestyles and social structures.

[0003] As a key module in wireless communication technology, the RF transceiver is responsible for sending and receiving signals and is the basis for the effective transmission of information. Its performance directly affects the overall performance of the communication system. In the working principle of the RF transceiver, the processing of RF signals is a complex and delicate process. In particular, the signal spectrum quality determines the reliability and efficiency of communication. When RF signals pass through amplifiers or other nonlinear components, they are prone to generating unnecessary harmonics. If these harmonics are not controlled, they will cause serious interference to the communication system and even cause mutual interference with other devices, thereby reducing the overall performance of the system. Therefore, harmonic suppression has become an important part of improving the performance of RF transceivers. Efficient harmonic suppression not only improves the quality of individual communication links, but also promotes the efficient use of spectrum resources and avoids service degradation caused by frequency band congestion. It is particularly critical to meet the growing demand for wireless communications.

[0004] In actual circuit design, since the second harmonic is closest to the fundamental frequency, it is most likely to interfere with the target signal; therefore, the suppression of the second harmonic is the most critical. Usually, in order to eliminate the second harmonic, a differential circuit structure can be applied to cancel out the second harmonic components. However, it is difficult to achieve strict differentiation in actual circuits, and it is difficult to achieve the effect of eliminating the second harmonic. In addition, harmonic suppression can also play a role in suppressing harmonics by adjusting the waveform of the PA output voltage and controlling the amplitude of the waveform at different phases. The principle is as follows: Figure 1 As shown, the specific circuit is as follows Figure 2As shown, two sets of signals with different biases are combined to adjust the PA (Power Amplifier) ​​output waveform. However, this circuit is complex to implement and lacks a feedback loop to stabilize performance to adapt to PVT (Power Voltage Temperature) changes, making it unfeasible in practical applications. At the same time, this circuit requires additional off-chip filters, which increases the chip area. Summary of the Invention

[0005] The purpose of the present invention is to provide a programmable second harmonic suppression circuit based on the conduction angle calibration principle. The innovative programmable loop control is proposed, which can not only effectively improve the second harmonic suppression capability of the system, but also make the circuit structure more compact, greatly saving design costs, and can adapt to second harmonic suppression in different PVT environments.

[0006] To achieve the above object, the technical solution adopted by the present invention is:

[0007] A programmable second harmonic suppression circuit, characterized by comprising: a power amplifier and a conduction angle calibration loop, wherein the conduction angle calibration loop detects a DC component of a radio frequency (RF) signal output by the power amplifier and, through feedback regulation, makes the DC component equal to a reference voltage in the conduction angle calibration loop. At this time, the conduction angle calibration loop reaches stability, thereby achieving harmonic suppression.

[0008] Furthermore, the reference voltage is equal to VDD / 2, where VDD is the supply voltage, to achieve second harmonic suppression.

[0009] Furthermore, the power amplifier includes a two-stage amplifier, wherein the first-stage amplifier is composed of a PMOS transistor MP1 and an NMOS transistor MN2, and the second-stage amplifier is composed of a PMOS transistor MP4 and an NMOS transistor MN5. The input signal is input through a capacitor C2, passes through the first-stage amplifier and the second-stage amplifier in sequence, and then outputs the amplified signal through a buffer.

[0010] Furthermore, the conduction angle calibration loop includes: a PMOS transistor MP2, a PMOS transistor MP3, an NMOS transistor MN1, an NMOS transistor MN3, an NMOS transistor MN4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a capacitor C1 and an operational amplifier (OPA);

[0011] The source of the PMOS transistor MP1 is connected to the power supply voltage VDD; the drain of the PMOS transistor MP1 is connected to the source of the PMOS transistor MP2 and the source of the PMOS transistor MP3; the drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN1, the drain of the PMOS transistor MP3, the drain of the NMOS transistor MN4, the gate of the PMOS transistor MP4, and the gate of the NMOS transistor MN5; the source of the NMOS transistor MN1 is connected to the source of the NMOS transistor MN4 and the drain of the NMOS transistor MN2; the source of the NMOS transistor MN2 is connected to the drain of the NMOS transistor MN3; and the source of the NMOS transistor MN3 is grounded; the gate of the PMOS transistor MP1 is connected to the gate of the NMOS transistor MN2 and leads to the input of the power amplifier; the resistor R1 is connected between the source and drain of the PMOS transistor MP3; and the resistor R2 is connected between the source and drain of the NMOS transistor MN4.

[0012] The source of the PMOS transistor MP4 is connected to the power supply voltage VDD, the source of the NMOS transistor MN5 is grounded, and the drain of the PMOS transistor MP4 is connected to the drain of the NMOS transistor MN5 and leads to the output of the power amplifier;

[0013] Resistor R3 and capacitor C1 are connected to form a low-pass filter. The output of the power amplifier passes through the low-pass filter to extract the DC component of the work and input it to the negative input of the operational amplifier (OPA). The positive input of the operational amplifier (OPA) is connected to the reference voltage VHD2. The output of the operational amplifier (OPA) feeds back a regulation signal to the gate of the PMOS transistor MP2 and the gate of the NMOS transistor MN1. Resistor R4 is connected between the input of the power amplifier and the positive input of the operational amplifier (OPA).

[0014] Based on the above technical solution, the beneficial effects of the present invention are:

[0015] The present invention provides a programmable second harmonic suppression circuit based on the conduction angle calibration principle. This circuit abandons the traditional harmonic suppression solution using an LC filter network, uses an operational amplifier to form a feedback loop, and uses the feedback loop to dynamically adjust the conduction angle of the power amplifier to maintain a 50% duty cycle of the RF signal, thereby suppressing the second harmonic component. Compared with traditional LC filter circuits, the present invention has a compact structure, a smaller area, a lower cost, and is easier to integrate into the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The figure is a schematic diagram of the principle of the harmonic suppression method based on PA output voltage shaping in the prior art.

[0017] Figure 2 The figure is a schematic diagram of the structure of a harmonic suppression circuit based on PA output voltage shaping in the prior art.

[0018] Figure 3Schematic diagram of the principle of the programmable second harmonic suppression circuit based on the conduction angle calibration principle in the present invention.

[0019] Figure 4 This is a model diagram of the power amplifier in the present invention.

[0020] Figure 5 This is an equivalent model diagram of the output voltage waveform of the power amplifier in the present invention.

[0021] Figure 6 This is a diagram showing the relationship between the harmonic components in the output signal of the power amplifier and the conduction angle in the present invention.

[0022] Figure 7 Schematic diagram of the structure of the programmable second harmonic suppression circuit based on the conduction angle calibration principle in the present invention. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and beneficial effects of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0024] The present invention proposes a programmable second harmonic suppression circuit based on the conduction angle calibration principle, which can achieve second harmonic suppression without reducing system efficiency. Figure 3 The circuit, shown in Figure 1, includes a Class D amplifier with a conduction angle calibration loop for second-harmonic suppression. This circuit is AC-coupled. The first input buffer converts the sine wave output from the on-chip LC oscillator into a square wave. The second buffer then provides sufficient drive capability to drive the PA (power amplifier). The PA consists of several subunits, the number of which determines the output power. An off-chip π-matching network is designed at the PA output to convert the 50-ohm antenna resistance to 100-ohm resistance for maximum output power. The conduction angle calibration loop includes a first-order RC low-pass filter (LPF) and the necessary logic circuitry, a comparator. The input buffer is controlled by the calibration loop to adjust the duty cycle of its output square wave, thereby adjusting the PA's conduction angle.

[0025] Theoretical analysis of the second harmonic suppression of the present invention is as follows:

[0026] like Figure 4The figure shows a simplified model of a Class D amplifier. The LC at the output port is used to filter square wave signals. If the on-resistance of the transistor is zero, the Class D amplifier can theoretically achieve 100% efficiency. This is the main advantage of switch-mode power amplifiers (Class D and Class E) compared to linear power amplifiers. However, in current CMOS technology, the on-resistance of transistors is generally non-zero, which becomes one of the main losses in Class D power amplifiers. In addition, if the on-resistance is reduced by increasing the transistor size, the high dynamic power consumption of the buffer will reduce the overall efficiency.

[0027] Since a simple LC bandpass filter cannot completely filter out all harmonic components, the harmonic components generated in the circuit will leak to the load. In this case, the harmonic leakage is related to the harmonic components on the drive node, which depends largely on the conduction angle of the drive buffer; Figure 5 As shown, the conduction angle of PA (2α) is defined as the conduction angle of PMOS switch normalized to 2π. The square wave waveform is Fourier transformed. Assuming VDD = 1, the equivalent drive voltage V SW It can be expressed as:

[0028]

[0029] Wherein, ω0 represents the operating frequency, k is an integer representing the kth harmonic in the harmonic component;

[0030] The above formula shows Figure 4 The relationship between the harmonic amplitude of the drain voltage and the conduction angle of the PA is shown in Figure 2. It can be seen that the relationship between the harmonic component and the conduction angle after the normalized amplitude (the maximum value is normalized to 1) is as follows: Figure 6 As shown in the figure, it can be seen that the even harmonics become zero when the conduction angle is 2α = π (α = π / 2), and at the same time, the amplitude of the fundamental wave reaches its maximum. Assuming that half of the conduction angle (α) changes slightly from π / 2 to π / 2 + β (β represents the change in the conduction angle, and β is much less than 1), substituting it into the above expression, it can be further expressed as:

[0031]

[0032] From the above formula, we can see that the even harmonic component (βcos 2ω0t), DC voltage offset are all proportional to β; therefore, if the size of β can be obtained and adjusted to zero, the even harmonic components of the driving node will all be zero, and at this time, the DC voltage will be exactly equal to half of the power supply voltage;

[0033] Therefore, the present invention uses the DC component of the driving voltage As an error signal to suppress harmonics, if the DC voltage is higher than VDD / 2, the PA conduction angle is adjusted to decrease so that β is zero. As a result, the amplitudes of the even harmonics at the drive node are all zero. Therefore, even if the LC filter has poor harmonic suppression performance, there will be no even harmonic leakage.

[0034] Based on the above working principle, this embodiment provides a programmable second harmonic suppression circuit based on the conduction angle calibration principle, such as Figure 7 As shown, it includes: a power amplifier and a conduction angle calibration loop. The conduction angle calibration loop detects the DC component of the radio frequency (RF) signal output by the power amplifier and makes the DC component equal to the reference voltage in the conduction angle calibration loop through feedback adjustment. At this time, the conduction angle calibration loop reaches stability and achieves harmonic suppression; when the reference voltage is VDD / 2, second harmonic suppression is achieved.

[0035] Furthermore, the power amplifier includes a two-stage amplifier, wherein the first-stage amplifier is composed of a PMOS transistor MP1 and an NMOS transistor MN2, and the second-stage amplifier is composed of a PMOS transistor MP4 and an NMOS transistor MN5. The capacitor C2 is used for AC coupling of the input RF signal. The input signal is input through the capacitor C2, passes through the first-stage amplifier and the second-stage amplifier in sequence, and then outputs the amplified signal through the buffer.

[0036] Furthermore, the conduction angle calibration loop includes: a PMOS transistor MP2, a PMOS transistor MP3, an NMOS transistor MN1, an NMOS transistor MN3, an NMOS transistor MN4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a capacitor C1 and an operational amplifier (OPA);

[0037] The source of the PMOS transistor MP1 is connected to the power supply voltage VDD; the drain of the PMOS transistor MP1 is connected to the source of the PMOS transistor MP2 and the source of the PMOS transistor MP3; the drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN1, the drain of the PMOS transistor MP3, the drain of the NMOS transistor MN4, the gate of the PMOS transistor MP4, and the gate of the NMOS transistor MN5; the source of the NMOS transistor MN1 is connected to the source of the NMOS transistor MN4 and the drain of the NMOS transistor MN2; the source of the NMOS transistor MN2 is connected to the drain of the NMOS transistor MN3; and the source of the NMOS transistor MN3 is grounded; the gate of the PMOS transistor MP1 is connected to the gate of the NMOS transistor MN2 and leads to the input of the power amplifier; the resistor R1 is connected between the source and drain of the PMOS transistor MP3; and the resistor R2 is connected between the source and drain of the NMOS transistor MN4.

[0038] The source of the PMOS transistor MP4 is connected to the power supply voltage VDD, the source of the NMOS transistor MN5 is grounded, and the drain of the PMOS transistor MP4 is connected to the drain of the NMOS transistor MN5 and leads to the output of the power amplifier;

[0039] Resistor R3 and capacitor C1 are connected to form a low-pass filter. The output of the power amplifier passes through the low-pass filter to extract the DC component of the work and input it to the negative input of the operational amplifier (OPA). The positive input of the operational amplifier (OPA) is connected to the reference voltage VHD2. The output of the operational amplifier (OPA) feeds back a regulation signal to the gate of the PMOS transistor MP2 and the gate of the NMOS transistor MN1. Resistor R4 is connected between the input of the power amplifier and the positive input of the operational amplifier (OPA).

[0040] In this embodiment, second harmonic suppression is controlled by adjusting a reference voltage, VHD2. A low-pass filter, formed by R3 and C1, filters the output signal, generating a DC component representing the output duty cycle. By comparing this DC voltage with the reference voltage, VHD2, it is determined whether the conduction angle is greater than or less than the optimal value. The output of the operational amplifier serves as the control voltage for MP2 and MN1, thereby adjusting the on-resistance of MP2 and MN1 and further adjusting the VTC characteristics of the circuit. Ultimately, when the loop reaches stability, the DC component of the filter equals VHD2. At this point, the duty cycle of the output signal varies with VHD2, thereby achieving the purpose of adjusting second harmonic suppression through the VHD2 voltage. For example, to suppress even harmonics, if the conduction angle is greater than π, β becomes positive, and the filter output voltage exceeds VHD2. The comparator in the operational amplifier returns a logic "high," adjusting the VTC of the first-stage amplifier and reducing the duty cycle of the power amplifier's input signal.

[0041] The above description is only a specific embodiment of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other equivalent or alternative features with similar purposes; all disclosed features, or all steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A programmable second harmonic suppression circuit based on the conduction angle calibration principle, characterized in that: include: The power amplifier and the conduction angle calibration loop detect the DC component of the radio frequency (RF) signal output by the power amplifier and adjust the DC component to be equal to the reference voltage in the conduction angle calibration loop through feedback. At this time, the conduction angle calibration loop reaches stability and achieves harmonic suppression.

2. The programmable second harmonic suppression circuit based on the conduction angle calibration principle according to claim 1, characterized in that: The reference voltage is equal to VDD / 2, where VDD is the supply voltage, to achieve second harmonic suppression.

3. The programmable second harmonic suppression circuit based on the conduction angle calibration principle according to claim 1, characterized in that: The power amplifier includes a two-stage amplifier, wherein the first-stage amplifier is composed of a PMOS transistor MP1 and an NMOS transistor MN2, and the second-stage amplifier is composed of a PMOS transistor MP4 and an NMOS transistor MN5. The input signal is input through capacitor C2, passes through the first-stage amplifier and the second-stage amplifier in sequence, and then outputs the amplified signal through a buffer.

4. The programmable second harmonic suppression circuit based on the conduction angle calibration principle according to claim 3, characterized in that: The conduction angle calibration loop includes: a PMOS transistor MP2, a PMOS transistor MP3, an NMOS transistor MN1, an NMOS transistor MN3, an NMOS transistor MN4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a capacitor C1 and an operational amplifier (OPA); The source of the PMOS transistor MP1 is connected to the power supply voltage VDD; the drain of the PMOS transistor MP1 is connected to the source of the PMOS transistor MP2 and the source of the PMOS transistor MP3; the drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN1, the drain of the PMOS transistor MP3, the drain of the NMOS transistor MN4, the gate of the PMOS transistor MP4, and the gate of the NMOS transistor MN5; the source of the NMOS transistor MN1 is connected to the source of the NMOS transistor MN4 and the drain of the NMOS transistor MN2; the source of the NMOS transistor MN2 is connected to the drain of the NMOS transistor MN3; and the source of the NMOS transistor MN3 is grounded; the gate of the PMOS transistor MP1 is connected to the gate of the NMOS transistor MN2 and leads to the input of the power amplifier; the resistor R1 is connected between the source and drain of the PMOS transistor MP3; and the resistor R2 is connected between the source and drain of the NMOS transistor MN4. The source of the PMOS transistor MP4 is connected to the power supply voltage VDD, the source of the NMOS transistor MN5 is grounded, and the drain of the PMOS transistor MP4 is connected to the drain of the NMOS transistor MN5 and leads to the output of the power amplifier; Resistor R3 and capacitor C1 are connected to form a low-pass filter. The output of the power amplifier passes through the low-pass filter to extract the DC component of the work and input it to the negative input terminal of the operational amplifier; the positive input terminal of the operational amplifier is connected to the reference voltage VHD2; the output of the operational amplifier feeds back the adjustment signal to the gate of the PMOS transistor MP2 and the gate of the NMOS transistor MN1; resistor R4 is connected between the input of the power amplifier and the positive input terminal of the operational amplifier.

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