Analog front-end circuit

Abstract

The embodiment of the invention provides an analog front-end circuit, and relates to the field of communication. Specifically, the analog front-end circuit comprises a plurality of differential amplification branches which are respectively provided with a switch; the control module is used for controlling on-off of the switch based on a communication protocol; wherein communication protocols of different differential amplification branches are different, the communication protocols are obtained based on a digital processing system, and the plurality of differential amplification branches are connected with the digital processing system. The problem that an analog front-end circuit in the related technology is poor in adaptability to a protocol is solved, and the effect of improving the adaptability of the analog front-end circuit to the protocol is achieved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of communications, and in particular, to an analog front-end circuit. Background Art

[0002] The analog front end (AFE) is a key circuit module connecting the analog signal source and the digital processing system.

[0003] The analog front-end circuit is primarily responsible for preprocessing the input analog signal, including amplification, filtering, sample-and-hold, and analog-to-digital conversion, to convert the raw analog signal into a form suitable for digital system processing. Analog front-end circuits are widely used in a wide range of fields, including communications, audio processing, sensor interfaces, medical equipment, and industrial control. Their performance directly impacts the accuracy, noise level, dynamic range, and reliability of the entire system.

[0004] However, the analog front-end circuits in related technologies usually only support one protocol. When the data to be processed uses another protocol, a new targeted design is required, which results in high complexity and poor adaptability. Summary of the Invention

[0005] An embodiment of the present invention provides an analog front-end circuit, which at least solves the problem of poor adaptability of the analog front-end circuit to the protocol in the related art.

[0006] According to one embodiment of the present invention, an analog front-end circuit is provided, comprising: a plurality of differential amplification branches, each provided with a switch; and a control module for controlling the on and off of the switches based on a communication protocol; wherein different differential amplification branches have different communication protocols, the communication protocol being obtained based on a digital processing system, and the plurality of differential amplification branches being connected to the digital processing system.

[0007] Through one of the above-mentioned embodiments of the present invention, due to the use of multiple differential amplifier branches in conjunction with a control module, wherein the multiple differential amplifier branches each support a different communication protocol, and the control module controls the switching of these differential amplifier branches based on the communication protocol provided by the digital processing system, thereby solving the problem of poor adaptability of the analog front-end circuit to the protocol in the related art, thereby achieving the effect of improving the adaptability of the analog front-end circuit to the protocol. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 Schematic diagram of the structure of the analog front-end circuit according to an embodiment of the present invention Figure 1 ;

[0009] Figure 2 Schematic diagram of the structure of the analog front-end circuit according to an embodiment of the present invention Figure 2;

[0010] Figure 3 is a schematic structural diagram of a preprocessing module of an analog front-end circuit according to an embodiment of the present invention;

[0011] Figure 4 is a schematic structural diagram of an analog front-end circuit according to an embodiment of the present invention;

[0012] Figure 5 is a structural diagram of another analog front-end circuit according to an embodiment of the present invention;

[0013] Figure 6 is a structural diagram of another analog front-end circuit according to an embodiment of the present invention;

[0014] Figure 7 Schematic diagram of the structure of an analog front-end circuit including a bias circuit and an output offset adjustment circuit according to an embodiment of the present invention Figure 1 ;

[0015] Figure 8 Schematic diagram of the structure of an analog front-end circuit including a bias circuit and an output offset adjustment circuit according to an embodiment of the present invention Figure 2 .

[0016] Explanation of the accompanying symbols: 1. Cascode differential pair; 2. Tail current unit; 3. Load unit. DETAILED DESCRIPTION

[0017] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in combination with embodiments.

[0018] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0019] In this embodiment, an analog front-end circuit is provided, which includes:

[0020] Multiple differential amplification branches are each provided with a switch;

[0021] A control module, used to control the on and off of the switch based on the communication protocol;

[0022] Different differential amplification branches have different communication protocols, the communication protocols are obtained based on a digital processing system, and multiple differential amplification branches are connected to the digital processing system.

[0023] In an exemplary embodiment, Figure 1 Schematic diagram of the structure of the analog front-end circuit according to an embodiment of the present invention Figure 1 ,like Figure 1As shown, the plurality of differential amplification branches may include a differential amplification branch obtained by a PMOS full differential pair, and the branch is provided with a switch. Figure 1 In the differential amplifier branch 1, the switch may be S1. It may also include a differential amplifier branch obtained by an NMOS full differential pair, which is provided with a switch. For example Figure 1 The second differential amplifier branch in the digital processing system can be switched on by switch S2. The control module analyzes the protocol adopted by the received data based on the digital processing system and closes the switch of the differential amplifier branch that supports the protocol, so that the received data passes through the differential amplifier branch, so that the corresponding differential amplifier circuit processes the received data. Figure 1 It is not shown in the figure, but it can be a control circuit or a control terminal such as a single-chip microcomputer or a PLC. The communication protocol can be SERDES, LVDS, Sub-LVDS, PCIE, HDMI, DP, USB, DDR, etc.

[0024] By adopting the above technical solution, in related technologies, the analog front-end circuit usually only supports one protocol, which means that different analog front-end circuits need to be designed for different communication protocols, resulting in high design complexity. Therefore, it is not possible to flexibly adapt to multiple protocols.

[0025] First, the present invention proposes an analog front-end circuit design that includes multiple differential amplifier branches, each supporting a different communication protocol. This design allows a single analog front-end circuit to be compatible with multiple protocols simultaneously, thereby improving the flexibility and adaptability of the analog front-end circuit.

[0026] Secondly, the control module in the present invention is responsible for controlling the switching state of each differential amplifier branch according to the communication protocol of the digital processing system. This means that the analog front-end circuit can dynamically select and activate the corresponding differential amplifier branch according to real-time communication requirements.

[0027] Moreover, through the intelligent control of the control module, the analog front-end circuit can dynamically adjust its working mode according to the protocol requirements of the input signal to adapt to different communication protocols.

[0028] Therefore, the above solution can achieve the following technical effects:

[0029] Improved Flexibility: The AFE circuit design integrates multiple differential amplifier branches, each optimized for different protocols, significantly enhancing its overall flexibility. This design allows the AFE circuit to quickly switch between different application scenarios without redesigning or replacing hardware.

[0030] Reduced design complexity: Compared to designing a dedicated analog front-end circuit for each protocol, the present invention implements protocol adaptation through software control logic, greatly reducing the complexity and cost of hardware design.

[0031] Improved system reliability: Because the analog front-end circuit can dynamically adjust its operating state according to the specific communication protocol, this helps ensure optimal performance under various protocols, thereby improving the accuracy, noise level, dynamic range, and reliability of the entire system.

[0032] In summary, the present invention adopts a means of cooperating with a control module of multiple differential amplifier branches, wherein the multiple differential amplifier branches each support a different communication protocol, and the control module controls the switching of these differential amplifier branches based on the communication protocol provided by the digital processing system. Therefore, the problem of poor adaptability of the analog front-end circuit to the protocol in the related art is solved, thereby achieving the effect of improving the adaptability of the analog front-end circuit to the protocol.

[0033] In one embodiment, Figure 1 As shown, the differential amplifier branch includes:

[0034] A first fully differential amplifying branch includes a cascode differential pair, a tail current unit, and a load unit;

[0035] The tail current unit includes a MOS tube, and the load unit includes a first adjustable resistor.

[0036] In an exemplary embodiment, a cascode differential pair of a differential amplifier branch includes: a first Cascode structure, a second Cascode structure, and a second adjustable resistor.

[0037] A first Cascode structure includes a first PMOS transistor and a third PMOS transistor, wherein the source of the first PMOS transistor is connected to the drain of the third PMOS transistor, the gate of the first PMOS transistor is used to input a first input signal, and the drain of the first PMOS transistor is used to output a first output signal;

[0038] In an exemplary embodiment, Figure 1 As shown, the first PMOS transistor may be MP1, and the third PMOS transistor may be MP3.

[0039] A second Cascode structure includes a second PMOS transistor and a fourth PMOS transistor, wherein the source of the second PMOS transistor is connected to the drain of the fourth PMOS transistor, the gate of the second PMOS transistor is used to input a second input signal, the drain of the second PMOS transistor is used to output a second output signal, the source of the fourth PMOS transistor and the source of the third PMOS transistor are connected to a power supply, and the gate of the fourth PMOS transistor and the gate of the third PMOS transistor are connected to a switch;

[0040] In an exemplary embodiment, Figure 1 As shown, the second PMOS transistor may be MP2, and the fourth PMOS transistor may be MP4.

[0041] One end of the second adjustable resistor is connected to the drain of the third PMOS tube, and the other end is connected to the drain of the fourth PMOS tube.

[0042] In an exemplary embodiment, Figure 1 As shown, the second adjustable resistor may be R2. The second adjustable resistor acts as a variable gain amplifier (VGA) between the first Casocde structure and the second Casocde structure, and the gain of the amplifier is adjusted by changing the resistance of the second adjustable resistor.

[0043] The tail current unit includes: a fifth PMOS tube and a sixth PMOS tube, wherein the gate of the fifth PMOS tube is connected to the gate of the sixth PMOS tube, and the source of the fifth PMOS tube is connected to the source of the sixth PMOS tube, the source of the third PMOS tube, and the source of the fourth PMOS tube.

[0044] In an exemplary embodiment, Figure 1 As shown, the fifth PMOS transistor may be MP5, and the sixth PMOS transistor may be MP6.

[0045] In an exemplary embodiment, the load unit may include a MOS transistor, wherein the MOS transistor includes: a seventh PMOS transistor and an eighth PMOS transistor, wherein the gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor, the source of the seventh PMOS transistor is connected to the drain of the fifth PMOS transistor, and the source of the eighth PMOS transistor is connected to the drain of the sixth PMOS transistor. The drain of the seventh PMOS transistor is connected to the drain of the first PMOS transistor for outputting a first output signal. The drain of the eighth PMOS transistor is connected to the drain of the second PMOS transistor for outputting a second output signal. Figure 1 As shown, the seventh PMOS transistor may be MP7, and the eighth PMOS transistor may be MP8.

[0046] In another exemplary embodiment, the load unit may also include a first adjustable resistor, wherein the first adjustable resistor may include: a first adjustable resistor 1 and a first adjustable resistor 2. Figure 1 As shown in the figure, but you can refer to Figure 1 Rload1 and Rload2 replace MP7 and MP8. For example, one end of the first adjustable resistor 1 is connected to the drain of the fifth PMOS transistor MP5, and the other end of the first adjustable resistor 1 is connected to the drain of the first PMOS transistor MP1, for outputting the first output signal. One end of the first adjustable resistor 2 is connected to the drain of the sixth PMOS transistor MP6, and the other end of the first adjustable resistor 2 is connected to the drain of the second PMOS transistor MP2, for outputting the second output signal.

[0047] Specifically, the first adjustable resistor 1 and the first adjustable resistor 2 act as load resistors. Their primary function is to provide the required load for the op amp circuit, thereby affecting the circuit's output voltage and current. These resistors can be multi-position adjustable or single-position adjustable to accommodate varying speed or output level requirements. Furthermore, the values ​​of the first adjustable resistor 1 and the first adjustable resistor 2 directly affect the output voltage swing. Smaller resistance values ​​provide a larger swing, while larger resistance values ​​limit the swing. Furthermore, in high-speed circuit design, the first adjustable resistor 1 and the first adjustable resistor 2 are used to match the output impedance to ensure efficient signal transmission to subsequent digital processing systems. Furthermore, since the first adjustable resistor 1 and the first adjustable resistor 2 are adjustable, they can be used to adjust the gain of the op amp circuit. Gain is the ratio of the output voltage to the input voltage. By changing the value of the load resistor, the circuit's gain can be varied. In high-speed circuits, the values ​​of the first adjustable resistor 1 and the first adjustable resistor 2 can affect the circuit's speed. Larger resistor values ​​can slow down a circuit because they increase the circuit's output resistance, affecting the circuit's response time.

[0048] In summary, the first adjustable resistor 1 and the first adjustable resistor 2 are Figure 1 The resistors play a key role in improving high-speed op amp circuits. They not only affect the circuit's gain and output swing, but also involve impedance matching and speed adjustment. By adjusting the values ​​of these resistors, the circuit's performance can be optimized to suit different application scenarios and signal processing requirements.

[0049] In one embodiment, the cascode differential pair further includes:

[0050] One end of the first adjustable capacitor is connected to the drain of the third PMOS tube, and the other end is connected to the drain of the fourth PMOS tube.

[0051] In an exemplary embodiment, Figure 1As shown, the first adjustable capacitor can be C2, and the second adjustable resistor can be R2. The first adjustable capacitor and the second adjustable resistor are connected in parallel between the first and second Cascade structures, functioning as a continuous time linear equalizer (CTLE) to compensate for high-frequency signal loss during high-speed transmission. The combination of the first adjustable capacitor and the second adjustable resistor forms a high-pass filter that enhances the high-frequency components of the signal, thereby offsetting high-frequency attenuation caused by the line or other transmission medium. The combination of the first adjustable capacitor and the second adjustable resistor helps restore distorted signals, particularly in high-speed data eye diagrams, where they help improve data eye opening, thereby enhancing signal integrity and reliability. The resistance value of the second adjustable resistor determines the gain and frequency response of the CTLE. By adjusting these resistor values, the gain of the CTLE can be adjusted to accommodate varying signal conditions and insertion loss. The first adjustable capacitor determines the cutoff frequency of the CTLE, in other words, the frequency at which the circuit begins to significantly amplify high-frequency signals. By adjusting the capacitance value, the frequency response of the CTLE can be adjusted to suit different signal transmission requirements.

[0052] In an exemplary embodiment, a cascode differential pair of a differential amplifier branch includes: a first Cascode structure, a second Cascode structure, and a second adjustable resistor.

[0053] A first Cascode structure includes a first NMOS transistor and a third NMOS transistor, wherein the source of the first NMOS transistor is connected to the drain of the third NMOS transistor, the gate of the first NMOS transistor is used to input a first input signal, and the drain of the first NMOS transistor is used to output a first output signal;

[0054] In an exemplary embodiment, Figure 1 As shown, the first NMOS transistor may be MN1, and the third NMOS transistor may be MN3.

[0055] A second Cascode structure includes a second NMOS transistor and a fourth NMOS transistor, wherein the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the second NMOS transistor is used to input a second input signal, the drain of the second NMOS transistor is used to output a second output signal, the source of the fourth NMOS transistor and the source of the third NMOS transistor are connected to a power supply, and the gate of the fourth NMOS transistor and the gate of the third NMOS transistor are connected to a switch;

[0056] In an exemplary embodiment, Figure 1 As shown, the second NMOS transistor may be MN2, and the fourth NMOS transistor may be MN4.

[0057] The third adjustable resistor has one end connected to the drain of the third NMOS tube, and the other end connected to the drain of the fourth NMOS tube.

[0058] In an exemplary embodiment, Figure 1 As shown, the third adjustable resistor may be R1. The third adjustable resistor acts as a variable gain amplifier (VGA) between the first Casocde structure and the second Casocde structure, and the gain of the amplifier is adjusted by changing the resistance of the third adjustable resistor.

[0059] The tail current unit includes: a seventh PMOS tube and an eighth PMOS tube, wherein the gate of the seventh PMOS tube is connected to the gate of the eighth PMOS tube, the source of the seventh PMOS tube is connected to the drain of the first NMOS tube, and the source of the eighth PMOS tube is connected to the drain of the second NMOS tube.

[0060] In an exemplary embodiment, Figure 1 As shown, the seventh PMOS transistor may be MP7, and the eighth PMOS transistor may be MP8.

[0061] In an exemplary embodiment, the load unit may include a first adjustable resistor, wherein the first adjustable resistor may include: a first adjustable resistor 1 and a first adjustable resistor 2. One end of the first adjustable resistor 1 is connected to the source of the third NMOS tube, and the other end of the first adjustable resistor 1 is connected to the drain of the seventh PMOS tube, for outputting a first output signal. One end of the first adjustable resistor 2 is connected to the source of the fourth NMOS tube, and the other end of the first adjustable resistor 2 is connected to the drain of the eighth PMOS tube, for outputting a second output signal. Figure 1 As shown, the first adjustable resistor 1 may be Rload1, and the first adjustable resistor 2 may be Rload2.

[0062] Specifically, the first adjustable resistor 1 and the first adjustable resistor 2 act as load resistors. Their primary function is to provide the required load for the op amp circuit, thereby affecting the circuit's output voltage and current. These resistors can be multi-position adjustable or single-position adjustable to accommodate varying speed or output level requirements. Furthermore, the values ​​of the first adjustable resistor 1 and the first adjustable resistor 2 directly affect the output voltage swing. Smaller resistance values ​​provide a larger swing, while larger resistance values ​​limit the swing. Furthermore, in high-speed circuit design, the first adjustable resistor 1 and the first adjustable resistor 2 are used to match the output impedance to ensure efficient signal transmission to subsequent analog / digital sampling circuits. Furthermore, since the first adjustable resistor 1 and the first adjustable resistor 2 are adjustable, they can be used to adjust the gain of the op amp circuit. Gain is the ratio of output voltage to input voltage. By changing the value of the load resistor, the circuit's gain can be varied. In high-speed circuits, the values ​​of the first adjustable resistor 1 and the first adjustable resistor 2 can affect the circuit's speed. Larger resistor values ​​may reduce the speed of the circuit because they increase the output resistance of the circuit, thereby affecting the response time of the circuit. Finally, since the first adjustable resistor 1 and the first adjustable resistor 2 are related to the common mode level. For example, in Figure 1 In the case of a CMOS circuit, the common-mode level is close to ground, which means that the load resistor needs to have an appropriate voltage drop to ground to ensure proper amplification and processing of the signal.

[0063] In summary, the first adjustable resistor 1 and the first adjustable resistor 2 are Figure 1 The resistors play a key role in improving high-speed op amp circuits. They not only affect the circuit's gain and output swing, but also involve impedance matching and speed adjustment. By adjusting the values ​​of these resistors, the circuit's performance can be optimized to suit different application scenarios and signal processing requirements.

[0064] In another exemplary embodiment, the load unit may also include a MOS transistor. The MOS transistor includes a ninth PMOS transistor and a tenth PMOS transistor, wherein the gate of the ninth PMOS transistor is connected to the gate of the tenth PMOS transistor, and the source of the ninth PMOS transistor is connected to the drain of the seventh PMOS transistor, for outputting a first output signal. The source of the tenth PMOS transistor is connected to the drain of the eighth PMOS transistor, for outputting a second output signal. The drain of the ninth PMOS transistor is connected to the source of the third NMOS transistor, and the drain of the tenth PMOS transistor is connected to the drain of the fourth NMOS transistor.

[0065] In one embodiment, the cascode differential pair further includes:

[0066] The second adjustable capacitor has one end connected to the drain of the third NMOS transistor and the other end connected to the drain of the fourth NMOS transistor.

[0067] In an exemplary embodiment, Figure 1 As shown, the second adjustable capacitor can be C1, and the third adjustable resistor can be R2. The second adjustable capacitor and the third adjustable resistor are connected in parallel between the first and second Cascade structures, functioning as a continuous time linear equalizer (CTLE) to compensate for high-frequency signal loss during high-speed transmission. The second adjustable capacitor and the third adjustable resistor form a high-pass filter that enhances the high-frequency components of the signal, thereby offsetting high-frequency attenuation caused by cables or other transmission media. The combination of the second adjustable capacitor and the third adjustable resistor helps restore distorted signals, particularly in high-speed data eye diagrams, where they help improve data eye opening, thereby enhancing signal integrity and reliability. The value of the third adjustable resistor determines the gain and frequency response of the CTLE. By adjusting these resistor values, the gain of the CTLE can be adjusted to accommodate varying signal conditions and insertion loss. The second adjustable capacitor determines the cutoff frequency of the CTLE, in other words, the frequency at which the circuit begins to significantly amplify high-frequency signals. By adjusting the capacitance value, the frequency response of the CTLE can be adjusted to suit different signal transmission requirements.

[0068] In an exemplary embodiment, Figure 1 As shown, the source of the third PMOS transistor MP3, the source of the fourth PMOS transistor MP4, the source of the fifth PMOS transistor MP5, and the source of the sixth PMOS transistor MP6 are all connected to the power supply, and the source of the third NMOS transistor MN3, the source of the fourth NMOS transistor MN4, one end of the first adjustable resistor Rload1, and one end of the first adjustable resistor Rload2 are all grounded. This can form an analog front-end circuit with a high-speed ground and a load as the output to ground. At this time, the common-mode level of the output is close to the ground.

[0069] Or, as Figure 2 As shown, Figure 2 Schematic diagram of the structure of the analog front-end circuit according to an embodiment of the present invention Figure 2 The source of the third PMOS transistor MP3, the source of the fourth PMOS transistor MP4, one end of the first adjustable resistor Rload1, and one end of the first adjustable resistor Rload2 are all connected to the power supply, and the source of the third NMOS transistor MN3, the source of the fourth NMOS transistor MN4, the source of the seventh PMOS transistor MP7, and the source of the eighth PMOS transistor MP8 are all grounded. This can form a high-speed analog front-end circuit with the ground and the load as the power supply output. At this time, the output common-mode level is close to the power supply.

[0070] In one embodiment, the analog front-end circuit further includes: a pre-processing circuit module, including a DC coupling branch and an AC coupling branch, wherein the DC coupling branch is provided with a first switch and the AC coupling branch is provided with a second switch, wherein one end of the pre-processing circuit module is used to input a third input signal;

[0071] The control module is also used to: control the on and off of the first switch and the second switch based on the third input signal, so that the third input signal passes through the DC coupling branch and / or the AC coupling branch to obtain a third output signal, so that the third output signal serves as the input of the differential amplifier branch.

[0072] In an exemplary embodiment, Figure 3 FIG. 1 is a schematic diagram of the structure of a pre-processing module of an analog front-end circuit according to an embodiment of the present invention. Figure 3 As shown, the first switch may be S1, and the second switch may be S2. The first and second switches are key switches for controlling the circuit coupling mode of the preprocessing circuit module. When the first switch is on and the second switch is off, the signal is AC-coupled via the AC coupling branch, allowing the AC signal to pass while blocking the DC component. This helps isolate the DC bias voltage to produce a third output signal. When the first switch is off and the second switch is on, the signal is DC-coupled via the DC coupling branch, allowing both the DC component and the AC signal to pass simultaneously to produce a third output signal.

[0073] In one embodiment, the DC coupling branch is provided with a fourth adjustable resistor, one end of which is connected to the first switch, and the other end of which is used to obtain the third output signal.

[0074] In an exemplary embodiment, Figure 3 As shown, the fourth adjustable resistor may be R1. When the second switch S2 is turned on, the signal is DC coupled through R1 of the DC coupling branch, allowing the DC component and the AC signal to pass through simultaneously to obtain a third output signal.

[0075] In one embodiment, the AC coupling branch is provided with a third adjustable capacitor, one end of which is connected to the second switch, and the other end is used to obtain a third output signal.

[0076] In an exemplary embodiment, Figure 3 As shown, the third adjustable capacitor may be C1. When the first switch S1 is turned on, the signal is AC-coupled through C1 of the AC coupling branch, allowing the AC signal to pass through while blocking the DC component, which helps to isolate the DC bias voltage to obtain the third output signal.

[0077] In an exemplary embodiment, Figure 3As shown, the first switch S1 and the second switch S2 are key switches for controlling the circuit coupling mode of the preprocessing circuit module. When the first switch S1 is open and the second switch S2 is closed, the signal undergoes AC coupling through C1 of the AC coupling branch, allowing the AC signal to pass while blocking the DC component. This helps isolate the DC bias voltage to produce the third output signal. When the first switch S1 is closed and the second switch S2 is open, the signal undergoes DC coupling through R1 of the DC coupling branch, allowing both the DC component and the AC signal to pass simultaneously to produce the third output signal.

[0078] The third adjustable capacitor C1 is a capacitive element used to achieve AC coupling. When the first switch S1 is turned on, the third adjustable capacitor C1 allows the AC signal to pass through while blocking the DC component, thereby achieving AC coupling of the signal.

[0079] The value (capacitance) of the third adjustable capacitor C1 affects the cutoff frequency of the signal, that is, it determines which high-frequency components can pass through. Different configurations of the third adjustable capacitor C1 can support different signal transmission rates and bandwidth requirements.

[0080] The fourth adjustable resistor R1 is a resistance element used to achieve DC coupling. When the second switch S2 is turned on, the fourth adjustable resistor allows the DC component and the AC signal to pass through, thereby achieving DC coupling of the signal.

[0081] The value (resistance) of the fourth adjustable resistor R1 affects the attenuation degree of the signal and the power loss. Different configurations of the fourth adjustable resistor R1 can adapt to different signal strengths and impedance matching requirements.

[0082] In summary, the first switch S1, the second switch S2, the third adjustable capacitor C1, and the fourth adjustable resistor R1, within the preprocessing module's dedicated capacitor-resistor network, collectively implement flexible signal processing, including the choice of DC and AC coupling, and adaptability to varying signal rates and bandwidths. This design enables the preprocessing module to dynamically adjust its coupling method and circuit parameters based on different communication protocols and signal characteristics, thereby enhancing its adaptability and flexibility.

[0083] In one embodiment, the preprocessing circuit module also includes multiple branches, each branch including a third switch, a fifth adjustable resistor or a fourth adjustable capacitor or a series structure of a fifth adjustable resistor and a fourth adjustable capacitor, wherein one end of the branch is connected to the output end of the DC coupling branch and the AC coupling branch, and the other end is grounded or connected to a power supply.

[0084] In an exemplary embodiment, Figure 3As shown, the branch may include a first branch, which includes: a third switch S3 and a fourth adjustable capacitor C2. One end of the third switch S3 is connected to the output ends of the DC coupling branch and the AC coupling branch, and the other end is connected to one end of the fourth adjustable capacitor C2. The other end of the fourth adjustable capacitor C2 is grounded or connected to a power supply.

[0085] The third switch S3 is another key switch used to implement more complex signal processing functions in the pre-processing module circuit, such as zero-point compensation or high-frequency boost compensation. The configuration of the third switch S3 can be adjusted according to the characteristics of the signal and the required frequency response.

[0086] When the third switch S3 is turned on, it can introduce the fourth adjustable capacitor C2 into the circuit, thereby changing the frequency response of the circuit to achieve compensation or suppression of a specific frequency point.

[0087] The fourth adjustable capacitor C2 is another capacitive element used in conjunction with the third switch S3 to adjust the frequency response of the preprocessing module circuit. The introduction of the fourth adjustable capacitor C2 can change the cutoff frequency of the circuit, thereby enhancing or suppressing specific frequency bands in the signal.

[0088] Different configurations of the fourth adjustable capacitor C2 can support different signal transmission rates and bandwidth requirements, and achieve compensation or suppression of different frequency points.

[0089] Specifically, the first switch S1 and the second switch S2 control whether the analog front-end circuit performs AC coupling or DC coupling. The first switch S1 controls the third adjustable capacitor C1 for AC coupling, while the second switch S2 controls the fourth adjustable resistor R1 for DC coupling. This configuration allows the analog front-end circuit to flexibly switch coupling modes in different application scenarios.

[0090] S3 can further expand this flexibility by introducing a fourth adjustable capacitor C2 to adjust the frequency response of the AC coupling, or cooperate with the fourth adjustable resistor R1 to implement more complex signal processing functions.

[0091] The combination of the third adjustable capacitor C1 and the fourth adjustable capacitor C2 allows the analog front-end circuit to precisely control signals in different frequency bands. The third adjustable capacitor C1 may be used for basic AC coupling, while the fourth adjustable capacitor C2 can be used for more precise frequency adjustment, such as zero compensation or high-frequency boost.

[0092] The combination of the fourth adjustable resistor R1 and the fourth adjustable capacitor C2 can be used to achieve frequency compensation under DC coupling. For example, the low-frequency signal can be enhanced or suppressed by adjusting the values ​​of the fourth adjustable resistor R1 and the fourth adjustable capacitor C2.

[0093] In summary, S3 and the fourth adjustable capacitor C2 provide additional flexibility and control within the dedicated capacitor-resistor network of the analog front-end circuit, enabling the analog front-end circuit to adapt to a wider range of signal processing requirements and communication protocols. Combined with the first switch S1, the second switch S2, the third adjustable capacitor C1, and the fourth adjustable resistor R1, the analog front-end circuit can implement complex signal preprocessing, including but not limited to DC and AC coupling, frequency compensation, and impedance matching, thereby improving the performance and adaptability of the analog front-end circuit.

[0094] In an exemplary embodiment, Figure 3 As shown, the branch may further include a second branch, which includes: a third switch S5 and a fifth adjustable resistor R3. One end of the third switch S5 is connected to the output ends of the DC coupling branch and the AC coupling branch, and the other end is connected to one end of the fifth adjustable resistor R3. The other end of the fifth adjustable resistor R3 is grounded or connected to a power supply.

[0095] The third switch S5 is used to further adjust the frequency response of the analog front-end circuit. It typically works together with the other switches (the first switch S1, the second switch S2, and the third switch S3) to select and configure different capacitor and resistor paths in the analog front-end circuit.

[0096] When the third switch S5 is turned on, it can introduce another capacitance or resistance path into the circuit, thereby changing the frequency response characteristics of the circuit and achieving compensation or suppression of a specific frequency point.

[0097] The third switch S5 can also be used to implement comprehensive frequency point calculation in the case of mixed AC coupling and DC coupling, which involves frequency response calculation of the capacitor-resistor network.

[0098] The fifth adjustable resistor R3 is a resistance element used for impedance matching and frequency response adjustment. It can be adjusted according to the characteristics of the signal and the required frequency response.

[0099] Different configurations of the fifth adjustable resistor R3 can support different signal transmission rates and bandwidth requirements, and achieve compensation or suppression of different frequency points.

[0100] The fifth adjustable resistor R3 also has an impedance matching function and can be designed to have multiple gears or a single gear to achieve reception of transmission levels of multiple transmitters.

[0101] The introduction of the fifth adjustable resistor R3, through control of the third switch S5, provides the pre-processing module with an additional impedance matching option, which is crucial for ensuring effective signal transmission between different devices. Different configurations of the fifth adjustable resistor R3 can adapt to different transmitter transmission levels, ensuring signal compatibility across different systems.

[0102] In summary, the role of the third switch S5 and the fifth adjustable resistor R3 in the dedicated capacitor-resistor network of the analog front-end circuit is to provide additional flexibility and controllability, enabling the analog front-end circuit to adapt to a wider range of signal processing requirements and communication protocols. Combined with the first switch S1, the second switch S2, the third adjustable capacitor C1, the fourth adjustable resistor R1, the third switch S3, and the fourth adjustable capacitor C2, the analog front-end circuit can implement complex signal preprocessing, including but not limited to DC and AC coupling, frequency compensation, and impedance matching, thereby improving the performance and adaptability of the analog front-end circuit. This design enables the analog front-end circuit to flexibly adapt to different communication environments and signal processing requirements.

[0103] In an exemplary embodiment, the branch may further include a third branch, comprising: a third switch S4, a fourth adjustable capacitor C3, and a fifth adjustable resistor R2. One end of the third switch S4 is connected to the output ends of the DC coupling branch and the AC coupling branch, and the other end is connected to one end of the fifth adjustable resistor R2. The other end of the fifth adjustable resistor R2 is connected to one end of the fourth adjustable capacitor C3. The other end of the fourth adjustable capacitor C3 is grounded or connected to a power supply.

[0104] Among them, the third switch S4, the fifth adjustable resistor R2, and the fourth adjustable capacitor C3 are components of the capacitor-resistor network dedicated to the analog front-end circuit. They work together with the first switch S1, the second switch S2, the third adjustable capacitor C1, the fourth adjustable resistor R1, the third switch S3, the fourth adjustable capacitor C2, the third switch S5, the fifth adjustable resistor R3 and other components to achieve precise control and processing of the signal.

[0105] Specifically, the third switch S4 is used to further adjust the frequency response of the analog front-end circuit. Together with the other switches (the first switch S1, the second switch S2, the third switch S3, and the third switch S5), it can select and configure different capacitor and resistor paths in the analog front-end circuit.

[0106] When the third switch S4 is turned on, it can introduce the fourth adjustable capacitor C3 (capacitance) into the circuit, thereby changing the frequency response characteristics of the circuit and achieving compensation or suppression of a specific frequency point.

[0107] The third switch S4 can also be used to implement comprehensive frequency point calculation in the case of mixed AC coupling and DC coupling, which involves frequency response calculation of the capacitor-resistor network.

[0108] The fifth adjustable resistor R2 is a resistance element used for impedance matching and frequency response adjustment. It can be adjusted according to the characteristics of the signal and the required frequency response.

[0109] Different configurations of the fifth adjustable resistor R2 can support different signal transmission rates and bandwidth requirements, and achieve compensation or suppression of different frequency points.

[0110] The fifth adjustable resistor R2 also has an impedance matching function and can be designed to have multiple gears or a single gear to achieve reception of transmission levels of multiple transmitters.

[0111] The fourth adjustable capacitor C3 is a capacitive element used in conjunction with the third switch S4 to adjust the frequency response of the analog front-end circuit. The introduction of the fourth adjustable capacitor C3 can change the cutoff frequency of the circuit, thereby enhancing or suppressing specific frequency bands in the signal.

[0112] Different configurations of the fourth adjustable capacitor C3 can support different signal transmission rates and bandwidth requirements, and achieve compensation or suppression of different frequency points.

[0113] The first switch S1 and the second switch S2 control whether the analog front-end circuit uses AC coupling or DC coupling. The first switch S1 controls the third adjustable capacitor C1 for AC coupling, while the second switch S2 controls the fourth adjustable resistor R1 for DC coupling. This configuration allows the analog front-end circuit to flexibly switch coupling modes in different application scenarios.

[0114] The third switches S3, S4, and S5 can further expand this flexibility by introducing the fourth adjustable capacitors C2 and C3 to adjust the frequency response of the AC coupling, or cooperate with the fourth adjustable resistors R1, R2, and R3 to implement more complex signal processing functions.

[0115] The combined use of the third, fourth, and fourth adjustable capacitors C1, C2, and C3 allows the analog front-end circuit to precisely control signals of different frequency bands. The third adjustable capacitor C1 may be used for basic AC coupling, while the fourth and fourth adjustable capacitors C2 and C3 can be used for more precise frequency adjustment, such as zero compensation or high-frequency boost.

[0116] The combination of the fourth adjustable resistor R1, the fifth adjustable resistor R2 and the fifth adjustable resistor R3 can be used to achieve frequency compensation under DC coupling. For example, the low-frequency signal can be enhanced or suppressed by adjusting the values ​​of the fourth adjustable resistor R1, the fifth adjustable resistor R2 and the fifth adjustable resistor R3.

[0117] The introduction of the fifth adjustable resistor R2 and the fifth adjustable resistor R3 provides additional impedance matching options, which is essential for ensuring effective signal transmission between different devices.

[0118] Different configurations of the fifth adjustable resistor R2 and the fifth adjustable resistor R3 can adapt to different transmitter transmission levels, ensuring signal compatibility between different systems.

[0119] In summary, the role of the third switch S4, the fifth adjustable resistor R2, and the fourth adjustable capacitor C3 in the dedicated capacitor-resistor network of the analog front-end circuit is to provide additional flexibility and controllability, enabling the analog front-end circuit to adapt to a wider range of signal processing requirements and communication protocols. By combining the first switch S1, the second switch S2, the third adjustable capacitor C1, the fourth adjustable resistor R1, the third switch S3, the fourth adjustable capacitor C2, the third switch S5, and the fifth adjustable resistor R3, the analog front-end circuit can implement complex signal preprocessing, including but not limited to DC and AC coupling, frequency compensation, and impedance matching, thereby improving the performance and adaptability of the analog front-end circuit. This design enables the analog front-end circuit to flexibly adapt to different communication environments and signal processing requirements.

[0120] In an exemplary embodiment, Figure 4 FIG. 1 is a schematic structural diagram of an analog front-end circuit according to an embodiment of the present invention. Figure 4 As shown, the differential amplifier branch has a positive input terminal and a negative input terminal. The differential amplifier branch receives data based on the positive input terminal and the negative input terminal. The control circuit selects the corresponding differential amplifier branch to process the data based on the protocol of the digital processing system. The control circuit can be configured based on actual conditions.

[0121] In one embodiment, both input terminals of the differential amplifier branch are connected to the output terminals of the DC coupling branch and the AC coupling branch.

[0122] In an exemplary embodiment, Figure 5 FIG. 1 is a schematic structural diagram of another analog front-end circuit according to an embodiment of the present invention. Figure 5 As shown, the positive input end of the differential amplifier branch is connected to the output end of the pre-processing module, and the negative input end of the differential amplifier branch is connected to the output end of the pre-processing module. Figure 1 、 Figure 3 、 Figure 5The first differential amplifier branch of the differential amplifier branch is a dual-input, dual-output circuit. One of its inputs is connected to the output of the DC coupling branch and the AC coupling branch of a pre-processing module. One of its inputs is connected to the output of the DC coupling branch and the AC coupling branch of a pre-processing module. The second differential amplifier branch of the differential amplifier branch is a dual-input, dual-output circuit. One of its inputs is connected to the output of the DC coupling branch and the AC coupling branch of a pre-processing module. One of its inputs is connected to the output of the DC coupling branch and the AC coupling branch of a pre-processing module.

[0123] In one embodiment, one input end of the differential amplifier branch is connected to the output ends of the DC coupling branch and the AC coupling branch, and the other input end is connected to the level generator.

[0124] In an exemplary embodiment, Figure 6 FIG. 1 is a schematic structural diagram of another analog front-end circuit according to an embodiment of the present invention. Figure 6 As shown, the positive input of the differential amplifier branch is connected to the output of the pre-processing module, and the negative input of the differential amplifier branch is connected to the level generator. For example, the level generator can be a common-mode level generator for providing a common-mode level for the differential amplifier branch.

[0125] In one embodiment, the analog front-end circuit also includes: a bias circuit for providing a stable operating point for the common-source common-gate differential pair, the tail current unit, and the load unit, for example, providing an appropriate DC bias voltage for the common-source common-gate differential pair, the tail current unit, and the load unit to ensure that the amplifier composed of the common-source common-gate differential pair, the tail current unit, and the load unit operates within the expected area, for example, in the saturation region or the linear region.

[0126] In one embodiment, the analog front-end circuit further includes an output offset adjustment circuit. Output offset voltage is caused by minor variations in the manufacturing process and can affect the DC accuracy of the op amp. Therefore, an output offset adjustment circuit is provided to calibrate and adjust the output offset voltage of the amplifier comprised of the cascode differential pair, the tail current cell, and the load cell.

[0127] In an exemplary embodiment, Figure 7 Schematic diagram of the structure of an analog front-end circuit including a bias circuit and an output offset adjustment circuit according to an embodiment of the present invention Figure 1 ,like Figure 7As shown, in a high-speed analog front-end circuit with a load as a ground output, the bias circuit includes a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a seventh NMOS transistor MN7. The source of the tenth PMOS transistor MP10, the source of the eleventh PMOS transistor MP11, the source of the fifth PMOS transistor, and the source of the sixth PMOS transistor are connected and connected to a power supply. The gates of the tenth PMOS transistor MP10, the gates of the fifth NMOS transistor MN5, and the gates of the sixth PMOS transistor are all connected to the drain of the twelfth PMOS transistor MP12. The gates of the twelfth PMOS transistor MP12, the gates of the thirteenth PMOS transistor MP13, the gates of the seventh PMOS transistor MP7, and the gates of the eighth PMOS transistor MP8 are all connected. The source of the twelfth PMOS transistor MP12 is connected to the drain of the tenth PMOS transistor MP10, and the source of the twelfth PMOS transistor MP12 is connected to the drain of the eleventh PMOS transistor MP11. The gates of the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, and the seventh NMOS transistor MN7 are connected to the second switch. The sources of the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, and the seventh NMOS transistor MN7 are all grounded. The gate and drain of the seventh NMOS transistor MN7 are connected and serve as the IBIAS port.

[0128] The output offset adjustment circuit includes a current mirror and a control transistor to precisely control the current flowing to the op amp output stage. The current mirror includes a first current mirror and a second current mirror. The first current mirror comprises multiple cascaded PMOS transistors MP14 with a common source and common gate configuration. The sources of the multiple PMOS transistors MP14 are connected to the sources of the tenth PMOS transistor MP10 and the eleventh PMOS transistor MP11, as well as to a power supply. The gates of the multiple PMOS transistors MP14 are connected and serve as the OFF_BIAS port. The second current mirror comprises multiple cascaded PMOS transistors MP15 with a common source and common gate configuration. The PMOS transistors MP14 of the first current mirror and the PMOS transistors MP15 of the second current mirror are arranged in pairs. The drain of the PMOS transistor MP14 of the first current mirror is connected to the source of the PMOS transistor MP15 of the second current mirror. The drains of the multiple PMOS transistors MP15 of the second current mirror are connected, and the gates of the multiple PMOS transistors MP15 of the second current mirror are connected and serve as the OFF_SEL port.

[0129] The control transistors include a sixteenth PMOS transistor MP16 and a seventeenth PMOS transistor MP17. The source of the sixteenth PMOS transistor MP16, the source of the seventeenth PMOS transistor MP17, and the drains of the PMOS transistors MP15 of the plurality of second current mirrors are connected. The gate of the sixteenth PMOS transistor MP16 is an OFFSET A port, and the gate of the seventeenth PMOS transistor MP17 is an OFFSET B port. The drain of the sixteenth PMOS transistor MP16 is connected to the drain of the eighth PMOS transistor MP8, and the drain of the seventeenth PMOS transistor MP17 is connected to the drain of the seventh PMOS transistor MP7.

[0130] In an exemplary embodiment, Figure 8 Schematic diagram of the structure of an analog front-end circuit including a bias circuit and an output offset adjustment circuit according to an embodiment of the present invention Figure 2 ,like Figure 8 As shown, in a high-speed analog front-end circuit with a load as a power output, the bias circuit includes: a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, and a twelfth NMOS transistor MN12.

[0131] The gates of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 are connected to the first switch S1. The sources of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, the third PMOS transistor MP3, the fourth PMOS transistor MP4, one end of Rload1, and one end of Rload2 are connected and connected to the power supply. The drain of the seventh PMOS transistor MP7 is the IBIAS port. The drain of the fifth PMOS transistor MP5 is connected to the drain of the ninth NMOS transistor MN9, and the drain of the sixth NMOS transistor is connected to the drain of the tenth NMOS transistor MN10.

[0132] The gates of the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6 are connected. The drain of the ninth NMOS transistor MN9 is connected to the gate of the eleventh NMOS transistor MN11. The gate of the eleventh NMOS transistor MN11 is connected to the gates of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8. The drain of the tenth NMOS transistor MN10 is connected to the gate of the tenth NMOS transistor MN10. The source of the tenth NMOS transistor MN10 is connected to the drain of the twelfth NMOS transistor MN12.

[0133] The source of the eleventh NMOS transistor MN11 , the source of the twelfth NMOS transistor MN12 , the source of the seventh NMOS transistor MN7 , and the source of the eighth NMOS transistor MN8 are connected and grounded.

[0134] The output offset adjustment circuit includes a current mirror and a control transistor to precisely control the current flowing to the op amp output stage. The current mirror includes a first current mirror and a second current mirror. The first current mirror comprises multiple cascaded cascode NMOS transistors MP16. The sources of the multiple NMOS transistors MP16 are connected to the sources of the eleventh and twelfth NMOS transistors and to ground. The gates of the multiple NMOS transistors MN16 are connected and serve as the OFF_BIAS port. The second current mirror comprises multiple cascaded cascode NMOS transistors MP15. The NMOS transistors MN16 of the first current mirror are paired with the NMOS transistors MP15 of the second current mirror. The drain of the NMOS transistors MN16 of the first current mirror is connected to the source of the NMOS transistor MP15 of the second current mirror. The drains of the multiple NMOS transistors MP15 of the second current mirror are connected, and the gates of the multiple NMOS transistors MP15 of the second current mirror are connected and serve as the OFF_SEL port.

[0135] The control transistors include a thirteenth NMOS transistor MN13 and a fourteenth NMOS transistor MN14. The source of the thirteenth NMOS transistor MN13, the source of the fourteenth NMOS transistor MN14, and the drains of the multiple second current mirror PMOS transistors MP15 are connected. The gate of the thirteenth NMOS transistor MN13 is the OFFSET A port, and the gate of the fourteenth NMOS transistor MN14 is the OFFSET B port. The drain of the thirteenth NMOS transistor MN13 is connected to the drain of the fifth NMOS transistor MN5, and the drain of the fourteenth NMOS transistor MN14 is connected to the drain of the sixth NMOS transistor MN6.

[0136] Specifically, through the above settings, the output offset adjustment circuit can fine-tune the output offset voltage of the op amp by changing the offset current and offset injection direction. This is usually achieved by injecting a small current into the output of the op amp. This current can be positive or negative, depending on the polarity of the offset voltage.

[0137] The output offset adjustment circuit can select the appropriate NMOS or PMOS transistor to conduct to inject positive or negative offset current. For example, if the common-mode level of output port OUT is lower than the common-mode level of output port OUTX, the NMOS / PMOS transistor controlled by OFFSET A can be selected to conduct to raise the common-mode level of output port OUTX.

[0138] According to the tube size of the current mirror connected to the OFF_BIAS port, the size of the injected current can be adjusted in increasing quantities (such as 1, 2, 4, or 8 times the quantity).

[0139] The OFF_SEL port can select different offset current injections according to the offset size to achieve finer offset adjustment.

[0140] In summary, the output offset adjustment circuit calibrates and adjusts the output offset voltage by precisely controlling the current flowing to the op amp's output stage. This adjustment can be static or dynamic, depending on the specific application requirements and circuit design. By reducing the offset voltage, the output offset adjustment circuit significantly improves the op amp's DC accuracy and signal processing quality.

[0141] It should be noted that the above modules can be implemented through software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0142] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0143] Obviously, those skilled in the art will appreciate that the various modules or steps of the present invention described above can be implemented using a general-purpose computing device, can be centralized on a single computing device, or can be distributed across a network of multiple computing devices. They can be implemented using program code executable by the computing device, and thus, can be stored in a storage device and executed by the computing device. In some cases, the steps shown or described herein can be performed in a different order than that shown, or can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0144] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. An analog front-end circuit, characterized in that: include: Multiple differential amplification branches are each provided with a switch; A control module, configured to control the on and off of the switch based on a communication protocol; Among them, different differential amplification branches have different communication protocols, and the communication protocols are obtained based on a digital processing system. The multiple differential amplification branches are connected to the digital processing system.

2. The analog front-end circuit according to claim 1, wherein: The differential amplification branch comprises: A first fully differential amplifying branch includes a cascode differential pair, a tail current unit, and a load unit; Wherein, the tail current unit includes a MOS tube, and the load unit includes a first adjustable resistor.

3. The analog front-end circuit according to claim 2, wherein: The cascode differential pair comprises: A first Cascade structure includes a first PMOS transistor and a third PMOS transistor, wherein the source of the first PMOS transistor is connected to the drain of the third PMOS transistor, the gate of the first PMOS transistor is used to input a first input signal, and the drain of the first PMOS transistor is used to output a first output signal; A second Cascode structure includes a second PMOS transistor and a fourth PMOS transistor, wherein the source of the second PMOS transistor is connected to the drain of the fourth PMOS transistor, the gate of the second PMOS transistor is used to input a second input signal, the drain of the second PMOS transistor is used to output a second output signal, the source of the fourth PMOS transistor and the source of the third PMOS transistor are connected to a power supply, and the gate of the fourth PMOS transistor and the gate of the third PMOS transistor are connected to the switch; A second adjustable resistor has one end connected to the drain of the third PMOS tube, and the other end connected to the drain of the fourth PMOS tube.

4. The analog front-end circuit according to claim 3, wherein: The cascode differential pair further includes: A first adjustable capacitor has one end connected to the drain of the third PMOS transistor and the other end connected to the drain of the fourth PMOS transistor.

5. The analog front-end circuit according to claim 2, wherein: The cascode differential pair comprises: A first Cascade structure includes a first NMOS transistor and a third NMOS transistor, wherein the source of the first NMOS transistor is connected to the drain of the third NMOS transistor, the gate of the first NMOS transistor is used to input a first input signal, and the drain of the first NMOS transistor is used to output a first output signal; A second Cascode structure includes a second NMOS transistor and a fourth NMOS transistor, wherein the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the second NMOS transistor is used to input a second input signal, the drain of the second NMOS transistor is used to output a second output signal, the source of the fourth NMOS transistor and the source of the third NMOS transistor are grounded, and the gate of the fourth NMOS transistor and the gate of the third NMOS transistor are connected to the switch; A third adjustable resistor has one end connected to the drain of the third NMOS transistor and the other end connected to the drain of the fourth NMOS transistor.

6. The analog front-end circuit according to claim 5, characterized in that: The cascode differential pair further includes: A second adjustable capacitor has one end connected to the drain of the third NMOS transistor and the other end connected to the drain of the fourth NMOS transistor.

7. The analog front-end circuit according to claim 1, wherein: Also includes: a preprocessing circuit module, comprising a DC coupling branch and an AC coupling branch, wherein the DC coupling branch is provided with a first switch, and the AC coupling branch is provided with a second switch, wherein one end of the preprocessing circuit module is used to input a third input signal; The control module is further configured to control the on and off of the first switch and the second switch based on the third input signal, so that the third input signal passes through the DC coupling branch and / or the AC coupling branch to obtain a third output signal, so that the third output signal serves as the input of the differential amplification branch.

8. The analog front-end circuit according to claim 7, wherein: The DC coupling branch is provided with a fourth adjustable resistor, one end of which is connected to the first switch, and the other end of which is used to obtain the third output signal.

9. The analog front-end circuit according to claim 7, wherein: The AC coupling branch is provided with a third adjustable capacitor, one end of which is connected to the second switch, and the other end is used to obtain the third output signal.

10. The analog front-end circuit according to claim 7, wherein: The preprocessing circuit module also includes multiple branches, each of which includes a third switch, a fifth adjustable resistor or a fourth adjustable capacitor, or a series structure of the fifth adjustable resistor and the fourth adjustable capacitor, wherein one end of each branch is connected to the output end of the DC coupling branch and the AC coupling branch, and the other end is grounded or connected to a power supply.

11. The analog front-end circuit according to claim 7, wherein: Both input ends of the differential amplification branch are connected to the output ends of the DC coupling branch and the AC coupling branch.

12. The analog front-end circuit according to claim 7, wherein: One input end of the differential amplifier branch is connected to the output ends of the DC coupling branch and the AC coupling branch, and the other input end is connected to the level generator.

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