Ethernet processing core, chip, electronic equipment and Ethernet processing core data processing method

Abstract

The invention provides an Ethernet processing core. The Ethernet processing core comprises a read-write control module, a read time sequence adjusting unit, a write time sequence adjusting unit, a first processing unit and a second processing unit, wherein the first processing unit and the second processing unit are micro-processing units; the read-write control module is used for arbitrating the internal data processing request and the external data processing request and determining a current data processing request to be processed; the second processing unit is used for acquiring second target data from the writing time sequence adjusting unit according to the data processing request under the condition that the data processing request is an internal data writing processing request, and writing the second target data into the target memory; the first processing unit is used for reading and caching first target data from the target memory under the condition that the data processing request is an internal data reading processing request; the chip area and power consumption can be saved, individual requirements are met, and the flexibility of the IP core is improved. The invention further provides a chip, electronic equipment and an Ethernet processing core data processing method.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to an Ethernet processing core, a chip, an electronic device, and an Ethernet processing core data processing method. Background Art

[0002] Ethernet is one of the most commonly used communication protocol standards in local area networks today, and GMAC (Gigabit Media Access Control) is one of the media access control protocols used for Ethernet communications. GMAC defines the Ethernet frame format, transmission rate, maximum frame length, and other specifications. It also specifies the data transmission method and collision detection mechanism between Ethernet nodes.

[0003] In Ethernet, the GMAC protocol is typically implemented in network interface card chips to control the transmission and reception of data. The GMAC protocol supports a variety of transmission rates, including 10Mbps, 100Mbps, and 1Gbps, as well as full-duplex and half-duplex communication modes. In the network component, the GMAC system framework typically consists of a MAC controller and a PHY (physical layer module). The CPU (Central Processing Unit), MAC controller, and PHY are not integrated into the same chip. Because the PHY contains a large number of analog components, while the MAC is a typical digital circuit, the MAC controller is integrated into the SoC (System on Chip) and the PHY module is kept off-chip for reasons of chip area and analog / digital hybrid architecture. The MAC controller primarily packages IP datagrams at the data link layer into network frames and sends the data to the PHY module. The PHY module primarily handles speed negotiation, converts digital signals to analog signals, and finally outputs the signals to the network cable.

[0004] When the Ethernet network PHY module and the CPU transmit data packets, this is achieved by calling the GMACIP core provided by the IP (Intellectual Property) company. One side of the GMACIP core is connected to the chip's external interface and the other side is connected to the SoC bus. After processing the physical layer data packets, the extracted data is placed in the chip's internal storage; or the data packets are read from the SoC's internal storage, processed, and sent to the external PHY through the chip interface.

[0005] The GMACIP core is not flexible enough. Some functions may not be used, but they still occupy logic area and are not customized according to application scenarios. For example, the GMACIP core supports MII (Media Independent Interface, Ethernet interface protocol) interface, RGMII (Reduced Gigabit Media Independent Interface, simplified Gigabit Ethernet interface protocol) interface, GMII (Gigabit Media Independent Interface, Gigabit Ethernet interface protocol) interface, RMII (Reduced Media Independent Interface, simplified Ethernet interface protocol) interface, etc., but the actual project application only uses the RMII interface, so other logic is wasted. For example, functions such as rate negotiation and collision detection are not needed in the project, resulting in redundant GMACIP core area. Summary of the Invention

[0006] The present disclosure provides an Ethernet processing core, a chip, an electronic device, and an Ethernet processing core data processing method.

[0007] In a first aspect, an embodiment of the present disclosure provides an Ethernet processing core, comprising a read / write control module, a read timing adjustment unit, a write timing adjustment unit, a first processing unit, and a second processing unit, wherein the first processing unit and the second processing unit are micro-processing units;

[0008] The read-write control module is used to arbitrate internal data processing requests and external data processing requests, and determine the data processing request currently to be processed;

[0009] The write timing adjustment unit is used to receive second target data sent by the network device, adjust the internal processing bit width of the second target data to the external input and output bit width, and then cache it;

[0010] The second processing unit is configured to, when the data processing request is an internal data processing request and the data processing request is a data write request, obtain the second target data from the write timing adjustment unit according to the data processing request, and write the second target data into the target memory;

[0011] The first processing unit is configured to read first target data from the target memory and cache the first target data when the data processing request is an internal data processing request and the internal data processing request is a data read request;

[0012] The read timing adjustment unit is used to obtain the first target data from the first processing unit, adjust the external input and output bit width of the first target data to the internal processing bit width and then cache it, and send the first target data to the network device.

[0013] In a second aspect, an embodiment of the present disclosure provides a chip, comprising a target memory and the aforementioned Ethernet processing core, wherein the Ethernet processing core is connected to the target memory via a bus.

[0014] In a third aspect, an embodiment of the present disclosure further provides an electronic device comprising the chip as described above.

[0015] In a fourth aspect, an embodiment of the present disclosure further provides an Ethernet processing core data processing method, the method being applied to the aforementioned Ethernet processing core, the method comprising:

[0016] Arbitrate internal and external data processing requests and determine the currently pending data processing requests;

[0017] In a case where the data processing request is an internal data processing request and the internal data processing request is a data read request, according to the data processing request, first target data is read from the target memory and cached; an external input and output bit width of the first target data is adjusted to an internal processing bit width and then cached, and the first target data is sent to the network device; or

[0018] In a case where the data processing request is an internal data processing request and the data processing request is a data write request, the second target data sent by the network device is received, the internal processing bit width of the second target data is adjusted to the external input and output bit width and then cached; according to the data processing request, the second target data is obtained, and the second target data is written into the target memory.

[0019] The Ethernet processing core provided by the embodiment of the present disclosure includes a read-write control module, a read timing adjustment unit, a write timing adjustment unit, a first processing unit and a second processing unit, wherein the first processing unit and the second processing unit are microprocessing units; the read-write control module is used to arbitrate internal data processing requests and external data processing requests to determine the data processing request currently to be processed; the second processing unit is used to obtain second target data from the write timing adjustment unit according to the data processing request when the data processing request is an internal data write processing request, and write the second target data into the target memory; the first processing unit is used to read first target data from the target memory and cache the first target data when the data processing request is an internal data read processing request; the embodiment of the present disclosure uses the read-write control module to arbitrate read and write requests from the internal and external hardware accelerators of the processing unit, realizes data processing through a softening method, and uses the microprocessing unit to customize the IP core according to needs, thereby saving chip area and power consumption to the greatest extent, meeting user personalized needs, and improving the flexibility of the IP core. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In the accompanying drawings of the embodiments of the present disclosure:

[0021] Figure 1 Schematic diagram of an application scenario of an embodiment of the present disclosure;

[0022] Figure 2 A schematic diagram of the structure of an Ethernet processing core provided in an embodiment of the present disclosure;

[0023] Figure 3 A schematic diagram of the working process of the Ethernet processing core provided in an embodiment of the present disclosure;

[0024] Figure 4 A schematic structural diagram of a first processing unit provided in an embodiment of the present disclosure;

[0025] Figure 5 A schematic diagram of the external interface of the Ethernet processing core provided in an embodiment of the present disclosure;

[0026] Figure 6 A schematic diagram of the structure of a chip provided in an embodiment of the present disclosure;

[0027] Figure 7 A flowchart of an Ethernet processing core data processing method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0029] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully understand the scope of the present disclosure to those skilled in the art.

[0030] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the detailed embodiments, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed embodiments with reference to the accompanying drawings.

[0031] The present disclosure may be described with reference to plan views and / or cross-sectional views by way of ideal schematic views of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0032] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0033] The terms used in this disclosure are only used to describe specific embodiments and are not intended to limit the disclosure. As used in this disclosure, the term "and / or" includes any and all combinations of one or more related enumerated items. As used in this disclosure, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. As used in this disclosure, the terms "comprising" and "made of" specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meanings as those commonly understood by those skilled in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined in this disclosure.

[0035] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0036] An embodiment of the present disclosure provides an Ethernet processing core, which is an IP core in a chip of an electronic device. Figure 1 This is a schematic diagram of an application scenario of an embodiment of the present disclosure, such as Figure 1As shown, the electronic device 100 is capable of receiving and storing data sent by the network device 200, as well as sending its own stored data to the network device 200. The electronic device 100 includes a chip (SoC), a CPU, an RMII interface module, a PHY module, and an RJ45 module. The chip includes a target memory (DDR, double data rate synchronous dynamic random access memory) and an Ethernet processing core. In the embodiment of the present disclosure, the Ethernet processing core can be a GMAC. The network device 200 can include a MAC controller. The network device 200 and the electronic device 100 realize data transmission through the PHY module and the RJ45 module. The MAC controller and the GMAC module are used to package the IP datagrams of the data link layer into network frames and send the data to the PHY module. The PHY module is used to perform speed negotiation, convert the digital signal into an analog signal, and transmit it through the network cable. The RMII interface is the logical interface of the chip, and the RJ45 module is the physical interface crystal head.

[0037] Figure 2 A schematic diagram of the structure of the Ethernet processing core provided in the embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the Ethernet processing core 10 includes a read-write control module 1, a first processing unit 21, a second processing unit 22, a read timing adjustment unit 31 and a write timing adjustment unit 32, wherein the first processing unit 21 and the second processing unit 22 are microprocessing units; the read-write control module 1 is used to arbitrate internal data processing requests and external data processing requests, and determine the data processing request to be processed currently; the write timing adjustment unit 32 is used to receive the second target data sent by the network device 200, adjust the internal processing bit width of the second target data to the external input and output bit width, and then cache it; the second processing unit 22 is used to receive the second target data sent by the network device 200, adjust the internal processing bit width of the second target data to the external input and output bit width, and then cache it; When the data processing request is an internal data processing request and the internal data processing request is a data read request, the second target data is obtained from the write timing adjustment unit 32 according to the data processing request, and the second target data is written into the target memory; the first processing unit 21 is used to read the first target data from the target memory and cache the first target data when the data processing request is an internal data processing request and the internal data processing request is a data read request; the read timing adjustment unit 31 is used to obtain the first target data from the first processing unit 21, cache the first target data after adjusting the external input and output bit width of the first target data to the internal processing bit width, and send the first target data to the network device 200.

[0038] Internal data processing requests refer to data processing requests within the processing module, while external data processing requests refer to hardware accelerator logic outside the processing module. The target memory 20 may include, but is not limited to, DDR, and the network device 200 may include, but is not limited to, a BMC (Baseboard Management Controller). The first processing unit 21 and the second processing unit 22 are programmable microprocessor units. The disclosed embodiment employs a flexible approach to configuring the processing units. Since the microcode can be reconfigured after tape-out, any defects can be resolved normally, and protocol upgrades can be seamlessly supported on existing devices.

[0039] The disclosed embodiment utilizes the read-write control module 1 to arbitrate read and write requests of the internal and external hardware accelerators of the processing units (i.e., the first processing unit 21 and the second processing unit 22), and realizes data processing in a softening manner; utilizing the microprocessing unit, the IP core can be customized according to demand, thereby saving chip area and power consumption to the greatest extent, meeting the personalized needs of users, and improving the flexibility of the IP core.

[0040] In some embodiments, the read timing adjustment unit 31 and the write timing adjustment unit 32 may include a cache unit. Exemplarily, the cache unit may be a FIFO (First Input First Output) queue. Accordingly, the second processing unit 22 is configured to obtain the second target data from the write timing adjustment unit 32. That is, the second processing unit 22 may read the second target data from the cache unit of the write timing adjustment unit 32.

[0041] In some embodiments, the read timing adjustment unit 31 is further configured to perform CDC (Clock Domain Crossing) processing on the cached first target data, converting the external low-speed clock domain to the internal high-speed clock domain. The write timing adjustment unit 32 is further configured to perform CDC processing on the cached second target data, converting the internal high-speed clock domain to the external low-speed clock domain. The second processing unit 22 can obtain the second target data after CDC processing from the write timing adjustment unit 32.

[0042] Figure 3 The working process diagram of the Ethernet processing core provided in the embodiment of the present disclosure is as follows: Figure 3 , which describes in detail the structure and working process of the Ethernet processing core.

[0043] In some embodiments, as Figure 3As shown, the read-write control module 1 includes a first read-write control unit 11 and a second read-write control unit 12. The first read-write control unit 11 is connected to the read timing adjustment unit 31 and the first processing unit 21 respectively, and the second read-write control unit 12 is connected to the write timing adjustment unit 32 and the second processing unit 22 respectively.

[0044] When the first read-write control unit 11 arbitrates that the data processing request to be processed is an internal processing request and the data processing request is a data read request issued by the CPU, the first processing unit (MPCORE1) 21 can obtain the first target data in the target memory (DDR) 20 for caching through DMA (Direct Memory Access) according to the data processing request, that is, read the first target data from the target memory 20 through the internal AXI (Advanced eXtens ib le Interface) bus; move the first data to the read timing adjustment unit 31, add physical layer group header information, such as the preamble and SFD (Start Frame Delimiter), and complete the CRC (Cyclic Redundancy Check) calculation and the PAD (Packet Assembler And Disassembler, terminal to host link service) addition. The read timing adjustment unit 31 reads the first target data processed by the first processing unit 21 and caches it in a cache unit with a packet length of 1.5 times. After CDC processing, the processed first target data is sent to the network device 200 according to the RMII interface timing.

[0045] When the second read / write control unit 12 arbitrates that the currently pending data processing request is an internal processing request and that the data processing request is a data write request issued by the CPU, the write timing adjustment unit 32 receives the second target data sent by the network device 200 according to the RMII interface timing, caches the second target data in a cache unit with a packet length 2.5 times that of the packet, and performs CDC processing. The second processing unit (MPCORE2) 22 can obtain the second target data from the write timing adjustment unit 32 according to the data processing request, cache it, strip the packet header information (preamble and SFD) of the second target data, and simultaneously complete the reporting of the CRC check result. The second target data is then sent to the target memory (DDR) 20 via the internal AXI bus using DMA.

[0046] Figure 4 This is a structural diagram of the first processing unit provided in the embodiment of the present disclosure, and the following is combined with Figure 4 The function and working process of the first processing unit are described.

[0047] like Figure 4 As shown, the first processing unit includes a first execution unit (EXU) 211, a first cache unit (Regfile) 212, and a second cache unit (DTCM) 213. The first execution unit 211 is configured to, when the data processing request is an internal data processing request and the internal data processing request is a data read request, read first target data from the target memory 20, cache the first target data in the second cache unit 213, process the first target data to obtain processed first target data, cache the processed first target data in the first cache unit 212, move the processed first target data from the first cache unit 212 to the second cache unit 213, and instruct the read timing adjustment unit 31 to change the data state of the second cache unit 213 to a readable state.

[0048] The read timing adjustment unit 31 is used to read and cache the processed first target data from the second cache unit 213 when the data state of the second cache unit 213 is readable, and to modify the data state of the second cache unit 213 to be writable.

[0049] The first processing unit 21 may further include an instruction fetch module (I FU) 214, an instruction tightly coupled memory (ITCM) 215, and a decode module (Decode) 216. The instruction fetch module 214 is connected to the TCM 215 and the decode module 216, respectively. The decode module 216 is connected to the first execution unit 211. The TCM 215 is a cache space for instructions, supporting offline reading and writing. The instruction fetch module 214 reads instructions from the TCM 215. The decode module 216 decodes the instructions and sends them to the first execution unit 211, which executes the instructions.

[0050] In some embodiments, the first cache unit 212 may include two first ping-pong register groups, each of which includes a first preset number of registers. After each register in a first ping-pong register group is fully populated with processed first target data, the processed first target data is moved from the fully populated first ping-pong register group to the second cache unit 213. Accordingly, the first execution unit 211 is configured to read the first preset number of first target data from the target memory 20. The first processing unit 21 utilizes the ping-pong register groups to cache the preset number of data as a group of data. Accordingly, data transmission is performed in units of this group of data, which can reduce data transmission frequency and alleviate the burden on the AXI bus.

[0051] In some embodiments, the read timing adjustment unit 31 is configured to send a complete data packet of the first target data to the network device 200. When the FIFO of the read timing adjustment unit 31 is full, the first processing unit 21 is back-pressured to write. Only after a complete data packet is stored in the FIFO of the read timing adjustment unit 31 can data be sent to the network device 200 outside the chip in units of data packets, thereby ensuring uninterrupted data transmission.

[0052] In some embodiments, the read timing adjustment unit 31 is further configured to send each data packet of the first target data to the network device 200 according to a preset packet sending interval. The packet sending interval can be set and adjusted based on demand to improve the flexibility of data reading.

[0053] In some embodiments, the read timing adjustment unit 31 may also be configured to send a first interrupt notification to the CPU after sending the first target data to the network device 200 , so that the CPU configures a next data reading task.

[0054] It should be noted that the internal structure of the second processing unit 22 is the same as the internal structure of the first processing unit 21. In some embodiments, the second processing unit 22 includes a second execution unit, a third cache unit, and a fourth cache unit. The second execution unit is configured to, when the data processing request is an internal data processing request and the data processing request is a data write request, and the data state of the fourth cache unit is writable, obtain the second target data from the write timing adjustment unit, cache the second target data in the fourth cache unit, and instruct the write timing adjustment unit to modify the data state of the fourth cache unit to a readable state; and, when it is determined that the data state of the fourth cache unit is readable, import the second target data from the fourth cache unit into the third cache unit, process the second target data to obtain processed second target data, cache the processed second target data in the third cache unit, and move the processed second target data from the third cache unit to the fourth cache unit; and write the processed second target data from the fourth cache unit to the target memory 20.

[0055] The second processing unit 22 may also include an instruction fetch module (IFU), a tightly coupled instruction memory (ITCM), and a decoder module (Decoder). The IFU is connected to the TCM and decoder modules, respectively, which are then connected to the second execution unit. The TCM is a cache for instructions, supporting offline reading and writing. The IFU reads instructions from the TCM, and the decoder module decodes the instructions and sends them to the second execution unit, which then executes them.

[0056] In some embodiments, the third cache unit may include two second ping-pong register groups, each second ping-pong register group includes a second preset number of registers; the second execution unit is used to write the second preset number of processed second target data from the fourth cache unit to the target memory 20; wherein, after all registers in a second ping-pong register group are full, the processed second target data is moved from the full second ping-pong register group to the fourth cache unit.

[0057] In some embodiments, the second execution unit is further configured to send a second interrupt notification to the CPU after writing the processed second target data into the target memory 20 .

[0058] In some embodiments, the first read / write control unit 11 and the second read / write control unit 12 are configured to arbitrate internal data processing requests and external data processing requests in a polling manner.

[0059] The first read / write control unit 11 and the second read / write control unit 12 complete read / write arbitration between the internal control information of the processing unit 2 and the hardware accelerator logic by reading and writing the register values ​​of the DTCM of the first processing unit 21 and the second processing unit 22. The arbitration method adopts a polling method. For example, a period T1 for internal data processing of the processing unit and a period T2 for external data processing of the processing unit are pre-set. T1 and T2 alternate. The register value of the DTCM is used to identify the current data processing period. If both internal data processing requests and external data processing requests are currently pending, the register value of the DTCM is used for arbitration. If the current period is determined to be period T1 for internal data processing of the processing unit, the internal data processing request is currently being processed.

[0060] In some embodiments, as Figure 3 As shown, the write timing adjustment unit 32 can also be configured to send a first indication to the read timing adjustment unit 31 when the cache occupancy rate of the write timing adjustment unit 32 is greater than a first threshold; and to send a second indication to the read timing adjustment unit 31 when the cache occupancy rate of the write timing adjustment unit 32 is less than a second threshold, where the first threshold is greater than the second threshold. Accordingly, the read timing adjustment unit 31 is configured to send a first preset frame according to a first preset frame value corresponding to the first indication; and to send a second preset frame according to a second preset frame value corresponding to the second indication.

[0061] The first threshold is the upper limit threshold of the storage capacity of the FIFO, and the second threshold is the lower limit threshold of the storage capacity of the FIFO. When the FIFO reaches the upper limit of the storage, the write timing adjustment unit 32 instructs the read timing adjustment unit 31 to send a pauseoff frame. When the FIFO reaches the lower limit of the storage, the write timing adjustment unit 32 instructs the read timing adjustment unit 31 to send a pauseon frame. By sending flow control frames, that is, inserting and sending pauseoff frames and pauseon frames, the flow control function can be achieved.

[0062] Since the RMII interface does not have a back pressure interface and cannot implement the back pressure function, the embodiment of the present disclosure implements the flow control function by inserting a flow control frame. Accordingly, in some embodiments, the read timing adjustment unit 31 is used to, when receiving a first indication and a data packet of the first target data is being sent to the network device, after the data packet is sent, send a first preset frame according to the first preset frame value corresponding to the first indication; and, when receiving a second indication and a data packet of the first target data is being sent to the network device, after the data packet is sent, send a second preset frame according to the second preset frame value corresponding to the second indication. In other words, the sending of the flow control frame cannot interrupt the original data transmission, and the flow control frame is sent after the original data transmission is completed to ensure that the data flow is continuous.

[0063] To clearly illustrate the solution of the embodiment of the present disclosure, the following Figure 3 , the packet sending process of the Ethernet processing core is described in detail. The packet sending process includes the following steps:

[0064] S101, MPCORE1 determines to read DDR data according to the data reading task configured by the CPU;

[0065] S102, MPCORE1 reads 8 32-bit data at a time and caches them into DTCM;

[0066] S103, performing PAD filling, CRC check, FCS filling, SDF and preamble filling on the read data;

[0067] S104, caching the processed data into two ping-pong register groups in Regfile, each ping-pong register group including 8 registers;

[0068] S105, moving data from the ping-pong register group to the DTCM, and rewriting the "DTCM data readable state" to a readable state;

[0069] S106, the first read / write control unit 11 completes the arbitration judgment of the MPCORE1 internal and CPU external logic read / write DTCM, determines the current pending request, and ensures that there is no read / write error;

[0070] S107, after the read timing adjustment unit 31 caches the read data into the FIFO, it changes the "DTCM data readable state" in MPCORE1 to a writable state to facilitate the transmission of the next data;

[0071] S108, the read timing adjustment unit 31 completes the CDC conversion between the internal high-speed clock and the low-speed peripheral clock;

[0072] S109, when the FIFO in the read timing adjustment unit 31 is full, the MPCORE1 is back-pressured to write. Only after a complete data packet is stored can the data be sent to the outside of the chip;

[0073] S110, the read timing adjustment unit 31 sends a data packet according to the packet sending interval configured by the CPU;

[0074] S111, until a data packet is processed, the read timing adjustment unit 31 sends an interrupt notification to the CPU;

[0075] S112: The CPU receives the interrupt notification and continues to configure the next data reading task.

[0076] To clearly illustrate the solution of the embodiment of the present disclosure, the following Figure 3 , the packet receiving process of the Ethernet processing core is described in detail. The packet receiving process includes the following steps:

[0077] S201, MPCORE2 obtains 2-bit wide data from DDR and buffers it in DTCM. Write timing adjustment unit 32 converts the 2-bit data into 32 bits and writes 48 bits, including overlength packet warning (1 bit) + received packet length (12 bits) + valid byte (3 bits) + data (32 bits), into FIFO.

[0078] S202, the write timing adjustment unit 32 performs CDC processing on the data written into the FIFO, converting the data from the peripheral low-speed clock domain to the internal high-speed clock domain;

[0079] S203, after the FIFO stores a complete data packet, MPCORE2 determines that the data is in a writable state based on the "data readable status" of the DTCM, reads the data from the FIFO and writes it into the DTCM of MPCORE2. After writing the data, MPCORE2 changes the "data readable status" of the DTCM to a readable state.

[0080] S204, the second read / write control unit 12 performs arbitration judgment on the internal and external logic read / write requests of the MPCORE to ensure that there are no read / write errors;

[0081] S205, MPCORE2 reads the data in DTCM according to the "data readable status" of DTCM, performs SFD and preamble stripping, and writes the data into two ping-pong register groups of Regfile, each ping-pong register group includes 8 registers;

[0082] S206, MPCORE2 performs MAC filtering, VLAN (Virtual Local Area Network) filtering and CRC check on the data in the ping-pong register group;

[0083] S207, once the eight registers in a set of ping-pong registers are fully stored, the data is moved from the set of ping-pong registers to the DTCM for caching via the SW8 instruction;

[0084] S208, write data from DTCM to DDR;

[0085] S209, MPCORE2 sends an interrupt notification to the CPU every time it completes processing a data packet, and the CPU can then configure a new data writing task.

[0086] To clearly illustrate the solution of the embodiment of the present disclosure, the following Figure 3 , the flow control process of the Ethernet processing core is described in detail. The flow control process is as follows:

[0087] The FIFO of the write timing adjustment unit 32 can generate a near-full (pauseoff) indication and a near-empty (pauseon) indication when the storage capacity reaches the upper and lower limits, respectively. The upper and lower thresholds are adjustable. The write timing adjustment unit 32 sends the near-full indication and the near-empty indication to the read timing adjustment unit 31. When the read timing adjustment unit 31 receives the near-full indication, it can insert and send a pauseoff frame based on the pauseoff frame value configured by the CPU. However, this does not interrupt the transmission of the original service data packet. If the original service data packet is in transmission, it will not send the pauseoff frame until it is completed. When the read timing adjustment unit 31 receives the near-empty indication, it can insert and send a pauseon frame based on the pauseon frame value configured by the CPU. Similarly, this does not interrupt the transmission of the original service data packet.

[0088] Figure 5 This is a schematic diagram of the external interface of the Ethernet processing core provided in the embodiment of the present disclosure, such as Figure 5As shown, the Ethernet processing core's external interfaces include: the AXI bus interface (AXI MASTER), the APB interface (APB SLAVE), the interrupt request interface (adb_intr_o), and the transceiver interfaces (GMII / MII, RGMII). The AXI MASTER interface is interconnected with the external bus and is used to read and write data to memory, namely, loading task descriptors, reading sent data, writing back task descriptor status, and writing received data. The APB SLAVE interface is interconnected with the bus and is used to configure registers, implement bus writes, and read back register status. The GMII / MII / RGMII interfaces are time-division multiplexed, with only one interface active at a time. The interrupt request interface is interconnected with the CPU and is used to send and receive data packets.

[0089] The embodiment of the present disclosure is described by taking the RMII as an example of the PHY module side interface. Other physical interfaces are also within the scope of protection of the embodiment of the present disclosure, such as: RevMII interface, SMII interface, SGMII interface, TBI (Ten Bit Interface) interface, RTBI (Reduced TBI) interface, SMA (Small A Type) interface, etc. The processing module of the embodiment of the present disclosure is programmable and expandable, so by adding microcode, token control, message frame structure changes, self-negotiation function, fragmentation and reorganization, hash calculation function, 1588 timestamp, conflict detection and other network functions can also be implemented. The chip of the embodiment of the present disclosure may include one or more soft cores (i.e., Ethernet processing cores), and the Ethernet processing core may also be a non-MP (MicroProcessor) structure.

[0090] The disclosed embodiment provides a self-developed IP core with the characteristics of high flexibility. It can be customized according to needs, and one or several interfaces required by the project can be selected for use, thereby saving area and power consumption to the greatest extent. By using a softening concept, since the microcode can be reconfigured after tape-out, any BUG leakage can be resolved normally, and any protocol upgrade can be seamlessly supported on existing devices.

[0091] The present disclosure also provides a chip, such as Figure 6 As shown, the chip includes a target memory 20 and the Ethernet processing core 10 as described above, and the Ethernet processing core 10 is connected to the target memory 20 via a bus.

[0092] The embodiment of the present disclosure also provides an Ethernet processing core data processing method, which is applied to the Ethernet processing core 10 as described above. Figure 7 As shown, the method includes the following steps:

[0093] Step S11 : arbitrate the internal data processing request and the external data processing request to determine the data processing request to be processed currently.

[0094] Read / write control module 1 arbitrates received data processing requests and determines whether the currently pending data processing request is an internal data processing request or an external data processing request. If it is an internal data processing request, step S12 or step S13 is executed. Internal data processing requests refer to data processing requests within the processing module, while external data processing requests refer to data processing requests sent to hardware accelerator logic outside the processing module.

[0095] Step S12, when the data processing request is an internal data processing request and the internal data processing request is a data read request, read the first target data from the target memory according to the data processing request and cache the first target data; adjust the external input and output bit width of the first target data to the internal processing bit width and cache it, and send the first target data to the network device.

[0096] If it is an internal data read request, the first processing unit 21 and the read timing adjustment unit 31 are used to read the first target data from the target memory 20 for caching, and the first target data is processed and sent to the network device 200 to realize data reading.

[0097] Step S13, when the data processing request is an internal data processing request and the data processing request is a data write request, receive the second target data sent by the network device, adjust the internal processing bit width of the second target data to the external input and output bit width, and then cache it; according to the data processing request, obtain the cached second target data, and write the second target data into the target memory.

[0098] If it is an internal data write request, the write timing adjustment unit 32 and the second processing unit 22 are used to process and cache the second target data sent by the network device 200, and send the cached second target data to the target memory 20 to implement data writing.

[0099] In some embodiments, the first processing unit includes a first execution unit, a first cache unit, and a second cache unit; when the data processing request is an internal data processing request and the internal data processing request is a data read request, the first target data is read from the target memory according to the data processing request, and the first target data is cached (i.e., step S12), including the following steps: the first execution unit reads the first target data from the target memory according to the data processing request, caches the first target data in the second cache unit, processes the first target data to obtain processed first target data, and caches the processed first target data in the first cache unit; moves the processed first target data from the first cache unit to the second cache unit, and modifies the data state of the second cache unit to a readable state; when the data state of the second cache unit is a readable state, reads the processed first target data from the second cache unit and caches it, and modifies the data state of the second cache unit to a writable state.

[0100] In some embodiments, the second processing unit includes a second execution unit, a third cache unit and a fourth cache unit; the obtaining of the cached second target data according to the data processing request and writing the second target data to the target memory (i.e., step S13) includes the following steps: when the data processing request is an internal data processing request and the data processing request is a data write request, and the data status of the fourth cache unit is a writable state, the second execution unit obtains the cached second target data, caches the second target data in the fourth cache unit, and modifies the data status of the fourth cache unit to a readable state; or, when the data processing request is an internal data processing request and the data processing request is a data write request, and the data status of the fourth cache unit is a readable state, imports the second target data from the fourth cache unit into the third cache unit, processes the second target data to obtain processed second target data, caches the processed second target data in the third cache unit, moves the processed second target data from the third cache unit to the fourth cache unit, and writes the processed second target data from the fourth cache unit to the target memory.

[0101] In some embodiments, the arbitrating the internal data processing request and the external data processing request (ie, step S11 ) includes: arbitrating the internal data processing request and the external data processing request by polling.

[0102] The first read / write control unit 11 and the second read / write control unit 12 complete read / write arbitration between the internal control information of the processing unit 2 and the hardware accelerator logic by reading and writing the register values ​​of the DTCM of the first processing unit 21 and the second processing unit 22. The arbitration method adopts a polling method. For example, a period T1 for internal data processing of the processing unit and a period T2 for external data processing of the processing unit are pre-set. T1 and T2 alternate. The register value of the DTCM is used to identify the current data processing period. If both internal data processing requests and external data processing requests are currently pending, the register value of the DTCM is used for arbitration. If the current period is determined to be period T1 for internal data processing of the processing unit, the internal data processing request is currently being processed.

[0103] In some embodiments, the Ethernet processing core data processing method may further include the following steps:

[0104] Step S21 : When the buffer occupancy rate of the write timing adjustment unit of the Ethernet processing core is greater than a first threshold, sending a first preset frame according to a first preset frame value.

[0105] Step S22 : When the cache occupancy rate of the write timing adjustment unit of the Ethernet processing core is less than the second threshold, send the second preset frame according to the second preset frame value; the first threshold is greater than the second threshold.

[0106] The first threshold is the upper limit threshold of the storage capacity of the FIFO of the write timing adjustment unit 31, and the second threshold is the lower limit threshold of the storage capacity of the FIFO of the write timing adjustment unit 31. When the FIFO reaches the upper limit of the storage, the write timing adjustment unit 32 instructs the read timing adjustment unit 31 to send a pauseoff frame. When the FIFO reaches the lower limit of the storage, the write timing adjustment unit 32 instructs the read timing adjustment unit 31 to send a pauseon frame. By sending flow control frames, that is, inserting and sending pauseoff frames and pauseon frames, the flow control function can be achieved.

[0107] Those skilled in the art will appreciate that all or some of the steps, systems, and functional modules / units in the apparatus disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0108] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation.

[0109] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; compact disc (CD-ROM), digital versatile disc (DVD) or other optical disc storage; magnetic cassettes, tapes, disk storage or other magnetic storage; any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, as is well known to those skilled in the art, communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0110] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. An Ethernet processing core, comprising a read / write control module, a read timing adjustment unit, a write timing adjustment unit, a first processing unit, and a second processing unit, wherein the first processing unit and the second processing unit are microprocessing units; The read-write control module is used to arbitrate internal data processing requests and external data processing requests, and determine the data processing request currently to be processed; The write timing adjustment unit is used to receive second target data sent by the network device, adjust the internal processing bit width of the second target data to the external input and output bit width, and then cache it; The second processing unit is configured to, when the data processing request is an internal data processing request and the data processing request is a data write request, obtain the second target data from the write timing adjustment unit according to the data processing request, and write the second target data into the target memory; The first processing unit is configured to read first target data from the target memory and cache the first target data when the data processing request is an internal data processing request and the internal data processing request is a data read request; The read timing adjustment unit is used to obtain the first target data from the first processing unit, adjust the external input and output bit width of the first target data to the internal processing bit width and then cache it, and send the first target data to the network device.

2. The Ethernet processing core according to claim 1, wherein: The first processing unit includes a first execution unit, a first cache unit and a second cache unit; The first execution unit is configured to, when the data processing request is an internal data processing request and the internal data processing request is a data read request, read first target data from the target memory, cache the first target data in the second cache unit, process the first target data to obtain processed first target data, cache the processed first target data in the first cache unit, move the processed first target data from the first cache unit to the second cache unit, and instruct the read timing adjustment unit to modify the data state of the second cache unit to a readable state; The read timing adjustment unit is configured to, when the data state of the second cache unit is a readable state, read the processed first target data from the second cache unit and cache it, and modify the data state of the second cache unit to a writable state.

3. The Ethernet processing core according to claim 2, wherein: The first cache unit includes two first ping-pong register groups, each of which includes a first preset number of registers; after each register in one of the first ping-pong register groups is full, the processed first target data is moved from the full first ping-pong register group to the second cache unit; The first execution unit is configured to read the first preset amount of first target data from the target memory.

4. The Ethernet processing core according to claim 1, wherein: The read timing adjustment unit is used to send a complete data packet of the first target data to the network device.

5. The Ethernet processing core according to claim 1, wherein: The read timing adjustment unit is further configured to send each data packet of the first target data to the network device according to a preset packet sending interval.

6. The Ethernet processing core according to claim 1, wherein: The second processing unit includes a second execution unit, a third cache unit and a fourth cache unit; The second execution unit is used to, when the data processing request is an internal data processing request and the data processing request is a data write request, and the data status of the fourth cache unit is a writable state, obtain the second target data from the write timing adjustment unit, cache the second target data in the fourth cache unit, and instruct the write timing adjustment unit to modify the data status of the fourth cache unit to a readable state; and, when it is determined that the data status of the fourth cache unit is a readable state, import the second target data from the fourth cache unit into the third cache unit, process the second target data to obtain processed second target data, cache the processed second target data to the third cache unit, move the processed second target data from the third cache unit to the fourth cache unit; and write the processed second target data from the fourth cache unit to the target memory.

7. The Ethernet processing core according to claim 6, wherein: The third cache unit includes two second ping-pong register groups, each of the second ping-pong register groups includes a second preset number of registers; The second execution unit is used to write the second preset amount of processed second target data from the fourth cache unit to the target memory; wherein, after each of the registers in a second ping-pong register group is full, the processed second target data is moved from the full second ping-pong register group to the fourth cache unit.

8. The Ethernet processing core according to claim 1, wherein: The read-write control module includes a first read-write control unit and a second read-write control unit, the first read-write control unit is connected to the read timing adjustment unit and the first processing unit respectively, and the second read-write control unit is connected to the write timing adjustment unit and the second processing unit respectively; The first read-write control unit and the second read-write control unit are configured to arbitrate the internal data processing request and the external data processing request in a polling manner.

9. The Ethernet processing core according to claim 1, wherein: The write timing adjustment unit is further configured to, when a cache occupancy rate of the write timing adjustment unit is greater than a first threshold, send a first instruction to the read timing adjustment unit; and, when a cache occupancy rate of the write timing adjustment unit is less than a second threshold, send a second instruction to the read timing adjustment unit, where the first threshold is greater than the second threshold. The read timing adjustment unit is configured to send a first preset frame according to a first preset frame value corresponding to the first indication; And, sending a second preset frame according to a second preset frame value corresponding to the second indication.

10. A chip comprising a target memory and the Ethernet processing core according to any one of claims 1 to 9, wherein the Ethernet processing core is connected to the target memory via a bus.

11. An electronic device comprising the chip according to claim 10.

12. A method for processing data in an Ethernet processing core, the method being applied to the Ethernet processing core according to any one of claims 1 to 9, the method comprising: Arbitrate internal and external data processing requests and determine the currently pending data processing requests; When the data processing request is an internal data processing request and the internal data processing request is a data read request, reading first target data from a target memory according to the data processing request and caching the first target data; Adjusting the external input and output bit width of the first target data to the internal processing bit width and then caching it, and sending the first target data to the network device; or When the data processing request is an internal data processing request and the data processing request is a data write request, receiving second target data sent by the network device, adjusting the internal processing bit width of the second target data to the external input / output bit width, and then caching the data; According to the data processing request, the cached second target data is acquired, and the second target data is written into the target memory.

13. The method according to claim 12, wherein: The first processing unit includes a first execution unit, a first cache unit, and a second cache unit; when the data processing request is an internal data processing request and the internal data processing request is a data read request, reading first target data from a target memory according to the data processing request and caching the first target data, including: The first execution unit reads first target data from the target memory according to the data processing request, caches the first target data in a second cache unit, processes the first target data to obtain processed first target data, and caches the processed first target data in the first cache unit; Moving the processed first target data from the first cache unit to the second cache unit, and changing the data state of the second cache unit to a readable state; When the data state of the second cache unit is in a readable state, the processed first target data is read from the second cache unit and cached, and the data state of the second cache unit is modified to a writable state.

14. The method according to claim 12, wherein: The second processing unit includes a second execution unit, a third cache unit, and a fourth cache unit; obtaining the cached second target data according to the data processing request and writing the second target data into the target memory includes: When the data processing request is an internal data processing request and a data write request, and the data state of the fourth cache unit is in a writable state, the second execution unit obtains the cached second target data, caches the second target data in the fourth cache unit, and modifies the data state of the fourth cache unit to a readable state; or When the data processing request is an internal data processing request and the data processing request is a data write request, and the data status of the fourth cache unit is a readable state, the second target data is imported from the fourth cache unit into the third cache unit, the second target data is processed to obtain processed second target data, the processed second target data is cached in the third cache unit, the processed second target data is moved from the third cache unit to the fourth cache unit, and the processed second target data is written from the fourth cache unit to the target memory.

15. The method according to claim 12, wherein: The arbitrating of the internal data processing request and the external data processing request includes: The internal data processing request and the external data processing request are arbitrated in a polling manner.

16. The method according to claim 12, wherein: The method further comprises: When the cache occupancy rate of the write timing adjustment unit of the Ethernet processing core is greater than a first threshold, sending a first preset frame according to a first preset frame value; When the cache occupancy of the write timing adjustment unit of the Ethernet processing core is less than a second threshold, a second preset frame is sent according to a second preset frame value; and the first threshold is greater than the second threshold.

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