Semiconductor device

Abstract

A semiconductor device includes: a substrate; a bit line extending in a first direction on the substrate; a vertical channel pattern on the bit line; a gate electrode adjacent to the vertical channel pattern in the first direction; a first work function adjustment pattern on the gate electrode; and a first contact on the vertical channel pattern. The first work function adjustment pattern is adjacent to one end of the vertical channel pattern in the first direction. The first work function adjustment pattern includes a metal material different from a metal material of the gate electrode.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This patent application claims the benefit of Korean Patent Application No. 10-2024-0031458 filed on March 5, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The inventive concept relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a vertical channel transistor. Background Art

[0003] As semiconductor device sizes shrink, it is necessary to develop a manufacturing technology that can increase the integration density of semiconductor devices and improve operating speed and yield. Therefore, a transistor with an oxide semiconductor channel has been proposed to improve the integration density, resistance characteristics, and current driving capability of the transistor. Summary of the Invention

[0004] Embodiments of the inventive concept provide a semiconductor device having improved electrical characteristics and a method of manufacturing the semiconductor device.

[0005] Problems to be solved by the present inventive concept are not limited to the above-mentioned problems, and embodiments of the present inventive concept may be applied to other problems not mentioned, and those skilled in the art will clearly understand the embodiments of the present inventive concept from the following description.

[0006] Semiconductor devices according to some embodiments of the present invention may include: a substrate; a bit line extending along a first direction on the substrate; a vertical channel pattern on the bit line; a gate electrode adjacent to the vertical channel pattern in the first direction; a first work function adjustment pattern on the gate electrode; and a first contact on the vertical channel pattern, wherein the first work function adjustment pattern is adjacent to one end of the vertical channel pattern in the first direction and includes a metal material different from a metal material of the gate electrode.

[0007] Semiconductor devices according to some embodiments of the present invention may include: a substrate; a bit line on the substrate; a bit line contact on the bit line; a vertical channel pattern and a gate structure on the bit line, the gate structure being arranged between the vertical channel patterns; a first work function adjustment pattern on the gate structure; and a storage node contact on the vertical channel pattern, wherein the gate structure includes a gate electrode, the first work function adjustment pattern has a first work function, the bit line contact and the storage node contact have a second work function, the gate electrode has a third work function, and the value of the first work function is between the values ​​of the second work function and the third work function.

[0008] Semiconductor devices according to some embodiments of the present invention may include: a substrate; a bit line on the substrate; a bit line contact on the bit line; a gate structure, a work function adjustment pattern and a vertical channel pattern on the bit line contact, the work function adjustment pattern including a first work function adjustment pattern on a lower portion of the gate structure and a second work function adjustment pattern on an upper portion of the gate structure opposite to the lower portion; a back gate structure extending into the bit line contact on the bit line; a storage node contact on one of the vertical channel patterns; a landing pad on the storage node contact; and a capacitor on the landing pad, wherein the gate structure includes a gate electrode, the first work function adjustment pattern and the second work function adjustment pattern are adjacent to the bit line contact and the storage node contact, respectively, the work function adjustment pattern has a work function of approximately 4.15 eV to approximately 4.3 eV, the bit line contact and the storage node contact have a work function of approximately 3.9 eV to approximately 4.1 eV, and the gate electrode has a work function of approximately 4.4 eV to approximately 4.6 eV. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings, which illustrate non-limiting example embodiments described herein.

[0010] Figure 1 is a block diagram illustrating a semiconductor device according to some embodiments of the inventive concept.

[0011] Figure 2 and Figure 3 is a perspective view briefly illustrating a semiconductor device according to some embodiments of the inventive concept.

[0012] Figure 4 is a plan view of a semiconductor device according to some embodiments of the inventive concept.

[0013] Figure 5 It is along Figure 4 A cross-sectional view taken along line AA' in FIG.

[0014] Figure 6 It is along Figure 4 A cross-sectional view taken along line BB' in FIG.

[0015] Figure 7 It is along Figure 4 FIG. 1 is a cross-sectional view taken along line AA′ to illustrate a semiconductor device according to another embodiment of the inventive concept.

[0016] Figure 8 It is along Figure 4 1 is a cross-sectional view taken along line AA′ to illustrate semiconductor devices according to other embodiments of the inventive concept.

[0017] Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 9D 、 Figure 9E 、 Figure 9F 、 Figure 9G and Figure 9H are cross-sectional views illustrating a manufacturing process of a semiconductor device according to some embodiments of the inventive concept.

[0018] Figure 10A and Figure 10B is a cross-sectional view illustrating a portion of a manufacturing process of a semiconductor device according to some embodiments of the inventive concept.

[0019] Figure 11A and Figure 11B is a cross-sectional view illustrating a portion of a manufacturing process of a semiconductor device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0020] Hereinafter, the present invention will be described in detail by illustrating embodiments of the present invention with reference to the accompanying drawings. The terms "first", "second", etc. may be used herein only to distinguish one component, layer, direction, etc. from another component, layer, direction, etc. When used in this article, the terms "include", "comprise", "contain", "have" and / or "contain" specify the presence of the elements, but do not exclude the presence of additional elements. The term "and / or" includes any and all combinations of one or more items listed in association. The term "connected" may be used in this article to refer to physical and / or electrical connections. When a component or layer is referred to as being "directly" on it, or "in direct contact" or "directly connected" in this article, there are no intermediate components or layers. Similarly, when components are "directly" adjacent to each other, there may be no intermediate components.

[0021] Figure 1 is a block diagram illustrating a semiconductor device according to some embodiments of the inventive concept.

[0022] refer to Figure 1 , a semiconductor memory device may include a memory cell array 1 , a row decoder 2 , a sense amplifier 3 , a column decoder 4 and a control logic 5 .

[0023] The memory cell array 1 may include a plurality of memory cells MC arranged in a three-dimensional manner. Each memory cell MC may be disposed between and connected to a word line WL and a bit line BL, which are disposed so as to intersect each other. Each memory cell MC may include a selection element TR and a data storage element DS. The selection element TR and the data storage element DS may be electrically connected to each other. The selection element TR may be connected to both the word line WL and the bit line BL. In other words, the selection element TR may be disposed at a point where the word line WL and the bit line BL intersect each other.

[0024] The selection element TR may include a transistor. The selection element TR may include a field effect transistor. The data storage element DS may include a capacitor, a magnetic tunnel junction pattern, or a variable resistor. For example, the gate terminal of the transistor serving as the selection element TR may be connected to the word line WL, and the source / drain terminals of the transistor may be connected to the bit line BL and the data storage element DS, respectively.

[0025] The row decoder 2 may decode an externally input address and select one of the word lines WL of the memory cell array 1. The address decoded in the row decoder 2 may be provided to a row driver (not shown), and the row driver may provide specific voltages to the selected word line WL and the unselected word lines WL, respectively, in response to control of the control circuit.

[0026] The sense amplifier 3 may detect and amplify a voltage difference between a selected bit line BL and a reference bit line in response to an address decoded from the column decoder 4 and output the amplified voltage difference.

[0027] Column decoder 4 provides a data transmission path between sense amplifier 3 and an external device (e.g., a memory controller). Column decoder 4 decodes an externally input address and selects one of bit lines BL. Control logic 5 generates control signals that control the operation of writing or reading data into memory cell array 1.

[0028] Figure 2 and Figure 3 is a perspective view briefly illustrating a semiconductor device according to some embodiments.

[0029] refer to Figure 2 and Figure 3 , the semiconductor device may include a peripheral circuit structure PS and a cell array structure CS connected to the peripheral circuit structure PS.

[0030] The peripheral circuit structure PS may include core and peripheral circuits formed on the substrate SUB. The core and peripheral circuits may include reference Figure 1 Depicted are row decoder 2 and column decoder 4 , sense amplifier 3 , and control logic 5 .

[0031] The cell array structure CS may include a memory cell array 1 (in Figure 1 ), the memory cell array 1 includes memory cells MC arranged two-dimensionally or three-dimensionally (in Figure 1 As mentioned above, the memory cell MC (in Figure 1 Each of the elements (in) may include a selection element TR and a data storage element DS.

[0032] In some embodiments, each memory cell MC (in Figure 1The selection element TR of the memory cell MC may include a vertical channel transistor VCT. The vertical channel transistor VCT may include a channel having a longitudinal direction perpendicular to the upper surface of the substrate SUB. Figure 1 The data storage element DS in the embodiment may include a capacitor.

[0033] In accordance with Figure 2 In an embodiment of the present invention, the peripheral circuit structure PS may be disposed on the substrate SUB. Alternatively, the cell array structure CS may be disposed on the peripheral circuit structure PS.

[0034] In accordance with Figure 3 In an embodiment, the peripheral circuit structure PS may be provided on the first substrate SUB1, and the cell array structure CS may be provided on the second substrate SUB2. The first substrate SUB1 and the second substrate SUB2 may face each other.

[0035] The first metal pad LMP may be provided at the uppermost surface of the peripheral circuit structure PS. The first metal pad LMP may be electrically connected to the core and peripheral circuits 2, 3, 4, and 5 (in the embodiment of FIG. Figure 1 middle).

[0036] The second metal pad UMP may be provided at the lowermost surface of the cell array structure CS. The second metal pad UMP may be electrically connected to the memory cell array 1 (in Figure 1 The second metal pad UMP may be in direct contact with the first metal pad LMP of the peripheral circuit structure PS and may be bonded to the first metal pad LMP of the peripheral circuit structure PS.

[0037] Figure 4 is a plan view of a semiconductor device according to some embodiments of the inventive concept. Figure 5 It is along Figure 4 A cross-sectional view taken along line AA' in FIG. Figure 6 It is along Figure 4 A cross-sectional view taken along line BB' in FIG.

[0038] refer to Figures 4 to 6 , a peripheral circuit insulating layer PIL may be disposed on the substrate SUB. The substrate SUB may have a plate shape, or may include a planar surface extending along a plane defined by the first direction D1 and the second direction D2.

[0039] In this specification, a first direction D1 is defined as a direction parallel to the upper surface of the substrate SUB. A second direction D2 is parallel to the upper surface of the substrate SUB and is defined as a direction perpendicular to the first direction D1. A third direction D3 is defined as a direction perpendicular to the upper surface of the substrate SUB, for example, a vertical direction.

[0040] The peripheral circuit insulating layer PIL may include an insulating material. As an example, the peripheral circuit insulating layer PIL may include nitride. In some embodiments of the present invention, reference is made to Figure 2 The described peripheral circuit structure PS may be disposed between the substrate SUB and the peripheral circuit insulating layer PIL. In addition, in some embodiments of the present inventive concept, an integrated circuit (eg, a logic element) may be disposed between the substrate SUB and the peripheral circuit insulating layer PIL.

[0041] The cell array structure CS may be disposed on the peripheral circuit insulation layer PIL. The cell array structure CS may include a memory cell including a vertical channel transistor. The cell array structure CS includes a bit line BL, a bit line contact DC, a back gate structure BGS, a gate structure GS, first and second work function adjustment patterns MW1 and MW2, a vertical channel pattern SP, a storage node contact BC, and a capacitor CAP.

[0042] A lower insulating layer DIL may be disposed on the peripheral circuit insulating layer PIL. For example, the peripheral circuit insulating layer PIL and the lower insulating layer DIL may be bonded by a wafer bonding process.

[0043] A bit line BL may be provided on the lower insulating layer DIL. The bit line BL may extend in a first direction D1, and a plurality of bit lines BL may be provided spaced apart from each other in a second direction D2. The bit line BL may include a metal pattern 110 and a polysilicon pattern 120 sequentially stacked on the lower insulating layer DIL. The metal pattern 110 may include a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.) and a metal (e.g., tungsten, titanium, tantalum, etc.).

[0044] A bitline contact DC may be provided on the bitline BL. The bitline contact DC may also be referred to herein as a first contact DC. The bitline contact DC may include a conductive material. The bitline contact DC may have a first work function. For example, the first work function may be 3.9 eV to 4.1 eV. The work function (or its value) of the patterns or components described herein may depend, for example, on the constituent materials and / or other characteristics thereof (such as, but not limited to, surface characteristics and doping levels).

[0045] A bit line insulation pattern BIL (refer to Figure 6 A plurality of bit line insulating patterns BIL may be provided. The bit line insulating patterns BIL may be arranged to be spaced apart from each other in the second direction D2 with the bit lines BL and the bit line contacts DC interposed therebetween.

[0046] A back gate structure BGS may be provided on the bit line BL by penetrating or extending into the bit line contact DC. The back gate structure BGS may be provided to improve electrical reliability by minimizing variations in the threshold voltage of the transistor including the vertical channel pattern SP, as will be described later. Multiple back gate structures BGS may be provided spaced apart from each other in the first direction D1. The back gate structure BGS may include a back gate electrode BGE, a back gate capping pattern BGC, and a back gate insulation pattern BGI.

[0047] A back-gate electrode (BGE) may be disposed below the back-gate structure (BGS). For example, the back-gate electrode (BGE) may include a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal (e.g., tungsten, titanium, tantalum, etc.), a conductive metal silicide, a conductive metal oxide, or a combination thereof. The back-gate electrode (BGE) may have a second work function. For example, the second work function may be 4.4 eV to 4.6 eV.

[0048] The back gate capping pattern BGC may be disposed on the back gate electrode BGE. For example, the back gate capping pattern BGC may include an insulating material such as silicon nitride.

[0049] The back gate insulation pattern BGI may surround the lower surface and side surfaces of the back gate electrode BGE and the side surfaces of the back gate capping pattern BGC. The term "surrounding" (or "covering" or "filling") as used herein does not necessarily mean completely surrounding, covering, or filling the element or layer. Instead, it may refer to partially surrounding, covering, or filling the element or layer, for example, discontinuously. The lower portion of the back gate insulation pattern BGI may contact the upper surface of the polysilicon pattern 120. For example, the back gate insulation pattern BGI may include at least one of silicon oxide, a high-dielectric material, or a combination thereof.

[0050] A first work function adjustment pattern MW1 and a first dielectric pattern DL1 may be provided on the bit line contact DC. The first work function adjustment pattern MW1 and the first dielectric pattern DL1 may be provided in plurality. The first work function adjustment patterns MW1 may be arranged to be spaced apart from each other in the first direction D1. The first dielectric patterns DL1 may be arranged to be spaced apart from each other in the first direction D1. The first work function adjustment pattern MW1 may contact the bit line contact DC. The first dielectric pattern DL1 may be provided on the first work function adjustment pattern MW1, and the first work function adjustment pattern MW1 may surround the lower surface and side surfaces of the first dielectric pattern DL1. The thickness TH of the first work function adjustment pattern MW1 may be 3Å to 10Å.

[0051] The first work function adjustment pattern MW1 may include a metal material different from the metal material of the gate electrode GE, which will be described later. For example, the first work function adjustment pattern MW1 may include at least one of aluminum oxide and lanthanum oxide. The first work function adjustment pattern MW1 may have a third work function. The third work function may be smaller than the second work function. The third work function may be an intermediate value between the first and second work functions. For example, the third work function may be 4.15 eV to 4.3 eV. For example, the first dielectric pattern DL1 may include a dielectric material such as hafnium oxide or zirconium oxide.

[0052] The gate structure GS may be disposed on the first work function adjusting pattern MW1. A plurality of gate structures GS may be disposed to be spaced apart from each other in the first direction D1. The gate structure GS may include a gate electrode GE, a gate dielectric layer 103, and a gate insulating pattern GI.

[0053] The gate electrode GE may be disposed on the first work function adjustment pattern MW1. The gate electrode GE may also be referred to as a front gate. For example, when viewed in a cross-sectional view, the gate electrode GE may have a "U"-like shape. The gate electrode GE may include, for example, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal (e.g., tungsten, titanium, tantalum, etc.), a conductive metal silicide, a conductive metal oxide, or a combination thereof. The gate electrode GE may have a second work function. For example, the second work function may be 4.4 eV to 4.6 eV.

[0054] The gate dielectric layer 103 may be disposed in the gate electrode GE. The gate electrode GE may surround the side surface and the lower surface of the gate dielectric layer 103. For example, the gate dielectric layer 103 may include a dielectric material, such as hafnium oxide or zirconium oxide.

[0055] The gate insulation pattern GI may surround the lower surface and side surfaces of the gate electrode GE. The lower portion of the gate insulation pattern GI may contact the first work function adjustment pattern MW1 and the first dielectric pattern DL1. The upper portion of the gate insulation pattern GI may contact the second work function adjustment pattern MW2. Unlike shown, according to some embodiments of the present inventive concept, the gate insulation pattern GI may not surround the lower surface of the gate electrode GE. For example, the gate insulation pattern GI may include at least one of silicon oxide, a high dielectric material, or a combination thereof.

[0056] A second work function adjustment pattern MW2 and a second dielectric pattern DL2 may be provided on the gate structure GS. A plurality of the second work function adjustment patterns MW2 and the second dielectric pattern DL2 may be provided so as to be spaced apart from each other in the first direction D1. The second dielectric pattern DL2 may be provided on the second work function adjustment pattern MW2. The second work function adjustment pattern MW2 may contact an upper portion of the gate insulation pattern GI, an upper surface of the gate electrode GE, and an upper surface of the gate dielectric layer 103. The thickness TH of the second work function adjustment pattern MW2 may be 3 Å to 10 Å.

[0057] The second work function adjustment pattern MW2 may include a metal material different from the metal material of the gate electrode GE. For example, the second work function adjustment pattern MW2 may include at least one of aluminum oxide and lanthanum oxide. The second work function adjustment pattern MW2 may have a third work function. For example, the third work function may be 4.15 eV to 4.3 eV. For example, the second dielectric pattern DL2 may include a dielectric material such as hafnium oxide or zirconium oxide.

[0058] The vertical channel pattern SP can be arranged on the bit line contact DC. A plurality of vertical channel patterns SP can be arranged to be spaced apart from each other in the first direction D1 and the second direction D2. The back gate structure BGS and the gate structure GS can be respectively arranged between a pair of vertical channel patterns SP. In this case, the above-mentioned first work function adjustment pattern MW1 and the second work function adjustment pattern MW2 can be respectively arranged to be adjacent to one end of the vertical channel pattern SP in the first direction D1. Specifically, one side or sidewall of each vertical channel pattern SP can be in contact with the first work function adjustment pattern MW1, the gate insulation pattern GI, and the second work function adjustment pattern MW2. The other side or opposite sidewall of each vertical channel pattern SP can be arranged on one side of the back gate structure BGS and can be in contact with the back gate insulation pattern BGI.

[0059] The vertical channel pattern SP and the bit line contact DC can form an ohmic contact. The lower portion of the vertical channel pattern SP can serve as a first source / drain region, the upper portion of the vertical channel pattern SP can serve as a second source / drain region, and the portion of the vertical channel pattern SP between the two source / drain regions can serve as a channel. The vertical channel pattern SP can include a single-crystal semiconductor material. As an example, the vertical channel pattern SP can include single-crystal silicon.

[0060] The channel insulating pattern 122 may be disposed on the bit line insulating pattern BIL (refer to Figure 6 The channel insulating pattern 122 may be disposed between the vertical channel patterns SP spaced apart from each other in the second direction D2. For example, the channel insulating pattern 122 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric material.

[0061] A storage node contact BC may be disposed on an upper surface of the vertical channel pattern SP. In this specification, the storage node contact BC may also be referred to as a second contact BC. The storage node contact BC and the vertical channel pattern SP may vertically overlap. A plurality of storage node contacts BC may be disposed spaced apart from one another in a first direction D1 and a second direction D2. The storage node contact BC may include a conductive material. The storage node contact BC and the vertical channel pattern SP may form an ohmic contact. The storage node contact BC may have a first work function. For example, the first work function may be 3.9 eV to 4.1 eV.

[0062] Landing pads LP may be disposed on storage node contacts BC. Storage node contacts BC may electrically connect the vertical channel pattern SP and the landing pads LP. A plurality of landing pads LP may be disposed spaced apart from one another in a first direction D1 and a second direction D2 and may be arranged in various shapes, such as a matrix, a zigzag, or a honeycomb shape. When viewed in a two-dimensional perspective view, each landing pad LP may have various shapes, such as a circular, oval, rectangular, square, diamond, or hexagonal shape.

[0063] The landing pad LP may include a conductive material. For example, the landing pad LP may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto.

[0064] A first upper insulating layer 130 may be disposed on the back gate structure BGS. Specifically, the first upper insulating layer 130 may be disposed between the storage node contacts BC to separate the storage node contacts BC or provide a space between the storage node contacts BC.

[0065] A second upper insulating layer 140 may be disposed on the first upper insulating layer 130. The second upper insulating layer 140 may be disposed between the landing pads LP to separate the landing pads LP.

[0066] The first upper insulating layer 130 and the second upper insulating layer 140 may include an insulating material. According to some embodiments, the first upper insulating layer 130 and the second upper insulating layer 140 may be a multi-layer including a plurality of insulating layers.

[0067] A capacitor CAP may be provided on the landing pad LP. A plurality of capacitors CAP may be provided. The plurality of capacitors CAP may be spaced apart from one another in the first direction D1 and the second direction D2. Each capacitor CAP may be connected to the vertical channel pattern SP via a corresponding landing pad LP and a storage node contact BC. The capacitor CAP may include a lower electrode, a dielectric layer, and an upper electrode, and may include various structures and / or materials capable of storing data.

[0068] Figure 7 It is along Figure 4 A cross-sectional view taken along line AA' is shown to illustrate a semiconductor device according to another embodiment of the present invention. Figure 5 The descriptions overlap the descriptions.

[0069] refer to Figure 7 The first work function adjustment pattern MW1 may be disposed between the bit line contact DC and the gate structure GS. Specifically, a lower surface of the first work function adjustment pattern MW1 may contact an upper surface of the bit line contact DC. An upper surface of the first work function adjustment pattern MW1 may contact a lower portion of the gate insulation pattern GI.

[0070] The second work function adjustment pattern MW2 may be disposed on the gate structure GS. Specifically, the lower surface of the second work function adjustment pattern MW2 may contact the upper surface of the gate insulation pattern GI, the upper surface of the gate dielectric layer 103, and the upper surface of the gate electrode GE. The height of the upper surface of the second work function adjustment pattern MW2 and the height of the upper surface of the vertical channel pattern SP may be substantially the same, i.e., substantially coplanar. The first work function adjustment pattern MW1 and the second work function adjustment pattern MW2 may include polycrystalline silicon doped with impurities (e.g., n-type). The first work function adjustment pattern MW1 and the second work function adjustment pattern MW2 may have a third work function. For example, the third work function may be 4.15 eV to 4.3 eV.

[0071] Figure 8 It is along Figure 4 The cross-sectional view taken along the line AA' is used to illustrate a semiconductor device according to another embodiment of the present invention. Figure 5 The descriptions overlap the descriptions.

[0072] refer to Figure 8 The third work function adjustment pattern MW3 and the fourth work function adjustment pattern MW4 may be disposed on the lower surface and the upper surface of the back gate electrode BGE, respectively. Specifically, the lower surface of the third work function adjustment pattern MW3 may contact the lower surface of the back gate insulation pattern BGI. The upper surface of the fourth work function adjustment pattern MW4 may contact the lower surface of the first upper insulating layer 130.

[0073] The back gate electrode BGE and the third and fourth work function adjustment patterns MW3 and MW4 have a first height H1 and a second height H2, respectively, in the third direction D3. The first height H1 may be 3 to 5 times the second height H2. For example, the first height H1 may be 100 to 120 nm. The second height H2 may be 20 to 40 nm.

[0074] The third work function adjustment pattern MW3 and the fourth work function adjustment pattern MW4 may include polysilicon doped with impurities (e.g., n-type). The third work function adjustment pattern MW3 and the fourth work function adjustment pattern MW4 may have a third work function. For example, the third work function may be 4.15 eV to 4.3 eV.

[0075] A semiconductor device according to an embodiment of the present invention may include a work function adjustment pattern between a gate electrode and a bit line contact, and a work function adjustment pattern between a gate electrode and a storage node contact. The work function of the work function adjustment pattern (e.g., a third work function) may have a value between the work function of the gate electrode (e.g., the second work function) and the work function of the bit line contact and the storage node contact (e.g., the first work function). Consequently, the metal resistance between the gate electrode and the bit line contact, and between the gate electrode and the storage node contact, can be reduced or mitigated, and leakage current of the gate electrode can be reduced. Consequently, the electrical characteristics and reliability of the semiconductor device can be improved.

[0076] 9A to 9H 1 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to some embodiments of the present invention. 9A to 9H It shows Figure 5 A cross-sectional view of a semiconductor device during manufacturing process is shown in FIG.

[0077] refer to Figure 9A , a first dummy substrate 100 a , a second dummy substrate 100 b , a dummy insulating layer 101 between the first dummy substrate 100 a and the second dummy substrate 100 b , a lower insulating layer DIL, a bit line BL, and a bit line contact DC may be provided.

[0078] Specifically, a dummy insulating layer 101 may be formed on a first dummy substrate 100a. The dummy insulating layer 101 may include an oxide. A lower insulating layer DIL and a bit line BL may be sequentially formed on the dummy insulating layer 101. Forming the bit line BL may include sequentially forming a metal pattern 110 and a polysilicon pattern 120 on the lower insulating layer DIL. Thereafter, a second dummy substrate 100b may be disposed on the bit line BL.

[0079] refer to Figure 9BMultiple back gate structures BGS may be formed on the bit lines BL. Specifically, the second dummy substrate 100b and the bit line contacts DC may be etched until the upper surface of the polysilicon pattern 120 is exposed, thereby forming multiple back gate holes or openings (not shown). Back gate insulation patterns BGI may be formed on the lower and side surfaces of the back gate holes (not shown). Back gate electrodes BGE and back gate capping patterns BGC may be sequentially formed in the remaining areas of the back gate holes (not shown), excluding the areas where the back gate insulation patterns BGI are formed.

[0080] refer to Figure 9C , a plurality of gate holes or openings HO may be formed on the bit line BL. The gate holes HO may define the gate holes to be formed. Figure 5 The gate structure GS described in the embodiment of the present invention is formed in the region of the gate structure GS. Forming the gate hole HO may include etching the second dummy substrate 100b until the upper surface of the bit line contact DC is exposed. With the formation of the gate hole HO, a plurality of vertical channel patterns SP may be formed from the second dummy substrate 100b, wherein the gate hole HO is located between the plurality of vertical channel patterns SP.

[0081] refer to Figure 9D A first work function adjustment pattern MW1 and a first dielectric pattern DL1 surrounded by the first work function adjustment pattern MW1 can be formed on the bit line contact DC. Forming the first work function adjustment pattern MW1 and the first dielectric pattern DL1 can include forming a first adjustment layer (not shown) covering the lower and side surfaces of the gate hole HO and a first dielectric layer (not shown) filling the interior of the first adjustment layer (not shown), and performing an etch-back process on the first adjustment layer (not shown) and the first dielectric layer (not shown). The etch-back process can remove upper regions of the first adjustment layer (not shown) and the first dielectric layer (not shown). As a result, the first work function adjustment pattern MW1 and the first dielectric pattern DL1 can be formed from the first adjustment layer (not shown) and the first dielectric layer (not shown), respectively.

[0082] refer to Figure 9E , a gate insulating layer GIL may be formed inside the gate hole HO. Specifically, the gate insulating layer GIL may be formed on the side surfaces and lower surface of the remaining portion of the gate hole HO except for the region where the first work function adjustment pattern MW1 and the first dielectric pattern DL1 are formed. The gate insulating layer GIL may be formed by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.

[0083] refer to Figure 9FA gate structure GS may be formed on the first work function adjustment pattern MW1 and the first dielectric pattern DL1. Forming the gate structure GS may include forming a gate electrode layer (not shown) to fill the gate hole HO, performing an etch-back process on the gate insulating layer GIL and the gate electrode layer (not shown) to form a gate insulating pattern GI and a gate electrode GE, and forming a gate dielectric layer 103 within the gate electrode GE. As the etch-back process is performed, upper regions of the gate electrode layer (not shown) and the gate insulating layer (GIL) may be removed. As a result, a gate electrode GE and a gate insulating pattern GI may be formed from the gate electrode layer (not shown) and the gate insulating layer GIL, respectively.

[0084] refer to Figure 9G , a second work function adjustment pattern MW2 and a second dielectric pattern DL2 may be sequentially formed on the gate structure GS. Figure 9D The second work function adjusting pattern MW2 and the second dielectric pattern DL2 are formed by a process substantially similar to the process of forming the first work function adjusting pattern MW1 and the first dielectric pattern DL1 .

[0085] A first upper insulating layer 130 may be formed on the back gate structure BGS, the gate structure GS, and the vertical channel pattern SP. A portion of the first upper insulating layer 130 may be removed to expose an upper surface of the vertical channel pattern SP. A storage node contact BC may be formed on an upper surface of the vertical channel pattern SP.

[0086] A second upper insulating layer 140 may be formed on the first upper insulating layer 130. A portion of the second upper insulating layer 140 may be removed to expose the upper surface of the storage node contact BC. A landing pad LP may be formed on the upper surface of the storage node contact BC. Thereafter, a capacitor CAP may be formed on the landing pad LP.

[0087] refer to Figure 9H , can be flipped Figure 9G The device formed in the first dummy substrate 100a is removed to expose the lower surface of the first dummy substrate 100a. Thereafter, the first dummy substrate 100a and the dummy insulating layer 101 can be removed. The removal of the first dummy substrate 100a and the dummy insulating layer 101 can be performed by back grinding and chemical and mechanical polishing processes. As the first dummy substrate 100a and the dummy insulating layer 101 are removed, the lower surface of the lower insulating layer DIL can be exposed.

[0088] Afterwards, although not shown, the device is flipped over again and can be bonded together by a wafer bonding process. Figure 2 The substrate SUB and the peripheral circuit insulating layer PIL described in the embodiment are bonded to the lower insulating layer DIL, thereby completing Figure 5 The semiconductor device shown in .

[0089] Figure 10A and Figure 10B 1 is a cross-sectional view showing a portion of a manufacturing process of a semiconductor device according to some embodiments of the present invention. Figure 10A and Figure 10B It shows Figure 7 A cross-sectional view of a portion of a manufacturing process of a semiconductor device is shown in cross section.

[0090] refer to Figure 9A 、 Figure 9B 、 Figure 9C and Figure 10A A first work function adjustment pattern MW1 may be formed in the gate hole HO. Forming the first work function adjustment pattern MW1 may include forming a first adjustment layer (not shown) filling the interior of the gate hole HO and performing an etch-back process on the first adjustment layer (not shown). The etch-back process may remove an upper region of the first adjustment layer (not shown). As a result, the first work function adjustment pattern MW1 may be formed from the first adjustment layer (not shown).

[0091] refer to Figure 10B , a gate structure GS may be formed on the first work function adjustment pattern MW1. The gate structure GS may be formed with Figure 9F Basically the same as described in .

[0092] The second work function adjusting pattern MW2 may be formed on the gate structure GS. The second work function adjusting pattern MW2 may fill an inner space of the gate hole HO except for the first work function adjusting pattern MW1 and the gate structure GS.

[0093] Afterwards, you can execute Figure 9G and Figure 9H A similar process is performed as described in Figure 7 The semiconductor device shown in .

[0094] Figure 11A and Figure 11B 1 is a cross-sectional view showing a portion of a manufacturing process of a semiconductor device according to some embodiments of the present invention. Figure 11A and Figure 11B It shows Figure 8 A cross-sectional view of a portion of a manufacturing process of a semiconductor device is shown in cross section.

[0095] refer to Figure 9A 、 Figure 9B and Figure 11A The second dummy substrate 100b and the bit line contacts DC may be etched until the upper surface of the polysilicon pattern 120 is exposed to form a plurality of back gate holes BHO. A back gate insulating pattern BGI may be formed on lower and side surfaces of the back gate holes BHO.

[0096] Thereafter, a third work function adjustment pattern MW3 may be formed in the inner space of the back gate hole BHO, excluding the back gate insulation pattern BGI. Forming the third work function adjustment pattern MW3 may include forming a third adjustment layer (not shown) filling the inner space of the back gate hole BHO and performing an etch-back process on the third adjustment layer (not shown). The etch-back process may remove an upper region of the third adjustment layer (not shown). As a result, the third work function adjustment pattern MW3 may be formed from the third adjustment layer (not shown).

[0097] refer to Figure 11B A back gate electrode BGE may be formed on the third work function adjustment pattern MW3. Forming the back gate electrode BGE may include forming a back gate electrode layer (not shown) filling the back gate hole BHO except for the region where the third work function adjustment pattern MW3 is formed, and performing an etch-back process on an electrode layer (not shown) on the back gate electrode layer (not shown) to form the back gate electrode BGE.

[0098] The fourth work function adjusting pattern MW4 may be formed on the back gate electrode BGE and in the remaining region of the back gate hole BHO except the region where the third work function adjusting pattern MW3 and the back gate electrode BGE are formed.

[0099] Afterwards, you can execute Figures 9C to 9H A similar process as described in Figure 8 The semiconductor device shown in .

[0100] A semiconductor device according to the present invention may include a work function adjustment pattern between a gate electrode and a bit line contact, and between a gate electrode and a storage node contact. The work function of the work function adjustment pattern (e.g., a third work function) may have a value between the work function of the gate electrode (e.g., the second work function) and the work function of the bit line contact and / or storage node contact (e.g., the first work function). Consequently, the metal resistance between the gate electrode and the bit line contact, and the metal resistance between the gate electrode and the storage node contact, can be reduced, and leakage current of the gate electrode can be reduced. Consequently, the electrical characteristics and reliability of the semiconductor device can be improved.

[0101] It will be understood that spatially relative terms such as "on," "upper," "upper surface," "below," "lower," "lower surface," "side surface," and the like may be represented by figure numerals and referenced to the accompanying drawings, unless otherwise indicated. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the drawings. For example, if the device in the drawings were turned over, elements described as "below" or "beneath" other elements or features would be oriented "above" the other elements or features. Thus, the term "below" may include both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0102] Although the embodiments are described above, it will be appreciated by those skilled in the art that many modifications and variations may be made without departing from the spirit and scope of the inventive concept as defined in the appended claims. Therefore, the exemplary embodiments of the inventive concept are to be considered in all respects as illustrative and not restrictive, and the scope of the inventive concept is to be indicated by the appended claims.

Claims

1. A semiconductor device comprising: substrate; A bit line extending along a first direction on the substrate; a vertical channel pattern on the bit line; a gate electrode adjacent to the vertical channel pattern in the first direction; a first work function adjustment pattern on the gate electrode; as well as a first contact, on the vertical channel pattern, wherein the first work function adjustment pattern is adjacent to one end of the vertical channel pattern in the first direction, and The first work function adjustment pattern includes a metal material different from a metal material of the gate electrode.

2. The semiconductor device according to claim 1, wherein The first work function adjustment pattern is on a lower portion of the gate electrode, The semiconductor device further includes a second work function adjustment pattern on an upper portion of the gate electrode opposite to the lower portion. The first work function adjustment pattern and the second work function adjustment pattern have respective work function values ​​lower than a work function value of the gate electrode.

3. The semiconductor device according to claim 2, wherein The first work function adjusting pattern and the second work function adjusting pattern include at least one of aluminum oxide or lanthanum oxide.

4. The semiconductor device according to claim 2, wherein The first work function adjusting pattern and the second work function adjusting pattern include polysilicon doped with impurities.

5. The semiconductor device according to claim 2, wherein The first contact is on a lower surface of the vertical channel pattern and contacts the first work function adjusting pattern on the bit line, The semiconductor device further includes a second contact on an upper surface of the vertical channel pattern opposite to the lower surface. The semiconductor device according to claim 5 , wherein: The first contact is a bit line contact that electrically connects the vertical channel pattern to the bit line, wherein the second contact is a storage node contact electrically connecting the vertical channel pattern to a storage node of the semiconductor device, and The respective work function values ​​of the first work function adjustment pattern and the second work function adjustment pattern are higher than the work function values ​​of the bit line contact and / or the storage node contact.

7. The semiconductor device according to claim 2, further comprising: a first dielectric pattern on the first work function adjustment pattern; a second dielectric pattern on the second work function adjustment pattern; as well as A gate insulating pattern extends around the gate electrode.

8. The semiconductor device according to claim 7, wherein A lower portion of the gate insulating pattern contacts the first work function adjusting pattern and the first dielectric pattern, and Wherein, an upper portion of the gate insulating pattern opposite to the lower portion contacts the second work function adjusting pattern.

9. The semiconductor device according to claim 7, wherein The first work function adjusting pattern and the second work function adjusting pattern have a thickness of 3Å to 10Å.

10. The semiconductor device according to claim 1, further comprising: A back gate structure extending on the bit line into the bit line contact, Wherein, the back gate structure includes a back gate electrode, and Wherein, the vertical channel pattern is arranged on one side of the back gate structure.

11. The semiconductor device according to claim 10, further comprising: a third work function adjustment pattern on the lower surface of the back gate electrode; and a fourth work function adjustment pattern on an upper surface of the back gate electrode opposite to the lower surface.

12. The semiconductor device according to claim 11, wherein Each of the third work function adjusting pattern and the fourth work function adjusting pattern includes polysilicon doped with impurities.

13. The semiconductor device according to claim 11, wherein The back gate electrode has a first height in a second direction perpendicular to the upper surface of the substrate, wherein each of the third work function adjustment pattern and the fourth work function adjustment pattern has a second height in the second direction, and The first height is 3 to 5 times the second height.

14. The semiconductor device according to claim 13, wherein The second height is 20 nm to 40 nm, and Wherein, the first height is 100 nm to 120 nm.

15. A semiconductor device comprising: substrate; a bit line on the substrate; a bit line contact on the bit line; vertical channel patterns and gate structures on the bit lines, wherein the gate structures are between the vertical channel patterns; a first work function adjustment pattern on the gate structure; and a storage node contact on the vertical channel pattern, Wherein, the gate structure includes a gate electrode, wherein the first work function adjustment pattern has a first work function, wherein the bit line contact and the storage node contact have a second work function, wherein the gate electrode has a third work function, and The value of the first work function is between the values ​​of the second work function and the third work function.

16. The semiconductor device according to claim 15, wherein The first work function adjustment pattern is on a lower portion of the gate structure, The semiconductor device further includes a second work function adjustment pattern, the second work function adjustment pattern being on an upper portion of the gate structure opposite to the lower portion, and The gate structure includes a gate insulation pattern extending around the gate electrode.

17. The semiconductor device according to claim 16, wherein One sidewall of the vertical channel pattern contacts the first work function regulating pattern, the gate insulating pattern, and the second work function regulating pattern.

18. A semiconductor device comprising: substrate; a bit line on the substrate; a bit line contact on the bit line; a gate structure, a work function adjustment pattern, and a vertical channel pattern, wherein on the bit line contact, the work function adjustment pattern includes a first work function adjustment pattern and a second work function adjustment pattern, the first work function adjustment pattern being on a lower portion of the gate structure, and the second work function adjustment pattern being on an upper portion of the gate structure opposite to the lower portion; a back gate structure extending on the bit line into the bit line contact; a storage node contact on one of the vertical channel patterns; a landing pad on the storage node contact; and capacitor, on the landing pad, Wherein, the gate structure includes a gate electrode, wherein the first work function adjustment pattern and the second work function adjustment pattern are adjacent to the bit line contact and the storage node contact, respectively; wherein the work function adjustment pattern has a work function of 4.15 eV to 4.3 eV, wherein the bit line contact and the storage node contact have a work function of 3.9 eV to 4.1 eV, and The gate electrode has a work function of 4.4 eV to 4.6 eV.

19. The semiconductor device according to claim 18, wherein The work function adjusting pattern includes polysilicon doped with impurities.

20. The semiconductor device according to claim 19, wherein An upper surface of the vertical channel pattern and an upper surface of the second work function adjusting pattern are coplanar.

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