Silicon carbide (sic) mosfet devices with improved gate oxide reliability and fabrication processes

Abstract

The present application relates to the field of MOS semiconductor technology, and discloses a silicon carbide (SiC) MOSFET device with improved gate oxide reliability, which is composed of a plurality of mutually juxtaposed MOS cells, the MOS cell comprising a drain, a semiconductor epitaxial layer, a gate, a gate oxide layer and a source, the semiconductor epitaxial layer comprising an N substrate layer, an N diffusion layer, a P+ layer, a P well layer and an N well layer, a high-K dielectric being provided between the gate and the P well layer, wherein one side of the high-K dielectric and between the source and the N well layer is provided with doped polysilicon; the high-K dielectric is one of hafnium dioxide, aluminum oxide or zirconium dioxide. Through the double-layer stacked structure of the high-K dielectric and the SiO2 gate oxide layer, the high dielectric constant of the high-K material is used to share the gate voltage, the electric field intensity of the SiO2 interface is significantly reduced, the gate leakage current is reduced by two orders of magnitude, and the degradation of the gate oxide layer caused by hot carrier injection is fundamentally inhibited.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of MOS semiconductor technology, and in particular to a silicon carbide (SiC) MOSFET device with improved gate oxide reliability and a preparation process thereof. BACKGROUND

[0002] The conventional SiO2 gate oxide layer has a low dielectric constant, which leads to a concentrated electric field strength, causing significant gate leakage current and hot carrier injection effect. Multiple high-temperature annealing processes exacerbate lattice defects and reduce the consistency of breakdown voltage. The JFET effect between cells and parasitic capacitance cause uneven electric field distribution during dynamic switching, accelerating the degradation and failure of the gate oxide layer, which is difficult to meet the stringent requirements of device lifetime in new energy vehicles, rail transportation and other fields.

[0003] A power MOSFET device with high-temperature stability and a preparation method thereof are disclosed in the prior art (publication number CN116759461A). The power MOSFET device includes a silicon carbide substrate, an N-type silicon carbide drift layer, a floating P+ type shielding ring, an N-type epitaxial layer, a JFET region, a P-well region, a polycrystalline gate layer, a gate oxide layer, an N+ type doped region, and a P+ type shielding region. The prior art has the following problems:

[0004] 1) The P+ type shielding region and the floating P+ shielding ring are used to reduce the electric field stress of the gate oxide layer in the static blocking state, but the uneven electric field distribution problem during dynamic switching is not solved, and the suppression of gate leakage current and hot carrier injection is limited.

[0005] 2) The source metal layer directly contacts the semiconductor, which easily causes distortion of the edge electric field of the gate oxide, increasing the on-resistance fluctuation.

[0006] 3) The JFET effect between cells and parasitic capacitance cause uneven electric field distribution during dynamic switching, accelerating the degradation and failure of the gate oxide layer. SUMMARY

[0007] The present application provides a silicon carbide (SiC) MOSFET device with improved gate oxide reliability and a preparation process thereof to solve the existing technical problems, solving the problem of uneven electric field distribution during dynamic switching of the MOS device, which accelerates the degradation and failure of the gate oxide layer.

[0008] To solve the above technical problems, according to one aspect of the present application, more specifically, a silicon carbide (SiC) MOSFET device with improved gate oxide layer reliability, the silicon carbide (SiC) MOSFET device is composed of a plurality of parallel MOS cells, the MOS cell includes a drain, a semiconductor epitaxial layer, a gate, a gate oxide layer, and a source, the semiconductor epitaxial layer includes an N substrate layer, an N diffusion layer, a P+ layer, a P well layer, and an N well layer, a high-K dielectric is provided between the gate and the P well layer, and a doped polysilicon is provided on one side of the high-K dielectric and between the source and the N well layer.

[0009] Further, the high-K dielectric is one of hafnium dioxide, aluminum oxide, or zirconium dioxide.

[0010] Further, the doped polysilicon is one of P-type polysilicon or low-concentration N-type polysilicon.

[0011] Further, a polysilicon layer is provided below the inside of the gate in a single MOS cell; the polysilicon layer is one of P-type polysilicon or N-type polysilicon.

[0012] Further, a suppression P- layer is provided below the inside of the gate, and the cross-sectional profile of the suppression P- layer is trapezoidal.

[0013] The top end of the suppression P- layer directly contacts the gate, and the bottom end of the suppression P- layer directly contacts the N diffusion layer.

[0014] Further, a plurality of N-type guard rings that do not contact each other are formed in the inside of the suppression P- layer by ion implantation, and the bottom end of the N-type guard ring directly contacts the N diffusion layer.

[0015] Further, an inner convex P- layer is provided on the surface of the semiconductor epitaxial layer and between two adjacent high-K dielectrics, and the cross-sectional profile of the inner convex P- layer is top thick and bottom thin.

[0016] Further, a plurality of N-type barrier rings that do not contact each other are provided in the inside of the inner convex P- layer, and the top end of the N-type barrier ring directly contacts the gate oxide layer.

[0017] A preparation process of a silicon carbide (SiC) MOSFET device with improved gate oxide layer reliability, comprising:

[0018] S1, epitaxially growing a low-concentration N diffusion layer on an N substrate layer;

[0019] S2, sequentially forming a P well layer, an N well layer, a P+ layer, and an inner convex P- layer by ion implantation and high-temperature annealing;

[0020] S3, implanting ions in the inner convex P- layer to form a plurality of N-type barrier rings;

[0021] S4, growing a gate oxide layer on the surface of the P-well layer by thermal oxidation; depositing a high-K medium between the gate and the P-well layer;

[0022] S5, depositing a doped polysilicon between the source and the N-well layer, wherein the doped polysilicon is P-type polysilicon or low-concentration N-type polysilicon;

[0023] S6, etching an electrode contact window to expose the source, the drain and the gate region;

[0024] S7, depositing a Ni, Ti or Al alloy layer and photoetching to form a source electrode, a gate electrode and a drain electrode.

[0025] The silicon carbide (SiC) MOSFET device with improved gate oxide layer reliability and the preparation process provided by the application have the following effects compared with the prior art:

[0026] 1. The double-layer stacked structure of the high-K medium and the SiO2 gate oxide layer is used to share the gate voltage by the high dielectric constant of the high-K material, significantly reduce the electric field intensity of the SiO2 interface, and reduce the gate leakage current by two orders of magnitude, thereby fundamentally inhibiting the gate oxide layer degradation caused by hot carrier injection.

[0027] 2. The vertical integration design of the N-type guard ring and the blocking ring is used to build a distributed depletion region below the gate, actively absorb the high-voltage peak in the switching process, reduce the electric field non-uniformity of the gate oxide layer to <5%, and improve the impact resistance and the life under high-frequency working conditions.

[0028] 3. The doped polysilicon is used to replace the traditional source metal contact, the carrier modulation effect of the P-type / low-concentration N-type polysilicon is used to effectively reduce the contact resistance of the source, and the gate oxide edge electric field distortion is eliminated, so that the on-resistance fluctuation rate is reduced by 40%.

[0029] 4. The single high-temperature annealing is used to activate the multi-zone injection layer at the same time, the traditional four-time annealing is simplified to one time, the lattice defect density is effectively reduced, the gate oxide layer interface state density is effectively optimized, and the breakdown voltage consistency is improved by >15%.

[0030] 5. The trapezoidal inhibition P-layer and the convex P-layer are used to control the morphology, the gradient doping and the inverted cone structure are used to reconstruct the longitudinal / lateral electric field distribution, so that the parasitic capacitance between cells is effectively reduced. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 It is a schematic diagram of example one in the application;

[0032] Figure 2 It is a schematic diagram of example two in the application;

[0033] Figure 3 is a schematic diagram of Example Three in the present application;

[0034] Figure 4 is a schematic diagram of Example Four in the present application;

[0035] Figure 5 is a schematic diagram of Example Five in the present application;

[0036] Figure 6 is a schematic diagram of Example Six in the present application.

[0037] In the figure: 1, drain; 2, gate; 3, gate oxide layer; 4, source; 5, N substrate layer; 6, N diffusion layer; 7, P+ layer; 8, P well layer; 9, N well layer; 10, doped polysilicon; 11, high-K dielectric; 12, polysilicon layer; 13, suppression P- layer; 14, N-type guard ring; 15, inner convex P- layer; 16, N-type blocking ring. DETAILED DESCRIPTION

[0038] In order to make the technical solutions of the present application clearer, the present application is further described in detail below in combination with the drawings and specific examples.

[0039] As shown in Figure 1 , 6 , the preparation process of a silicon carbide SiC MOSFET device with improved gate oxide layer reliability includes the following steps:

[0040] Step one, epitaxially grow a low-concentration N diffusion layer 6 on the N substrate layer 5; epitaxially grow a low-concentration N diffusion layer 6 on the N substrate layer 5 as a drift region, through accurate control of the doping concentration and thickness, while ensuring the breakdown voltage, provide a carrier transport basis for the subsequent multilayer structure, and lay the foundation for the high-voltage resistance of the device.

[0041] Step two, sequentially form a P well layer 8, an N well layer 9, a P+ layer 7, and an inner convex P- layer 15 by ion implantation and high-temperature annealing; simultaneously activate the ion implantation of the P well layer 8, the N well layer 9, the P+ layer 7, and the inner convex P- layer 15 by single high-temperature annealing, utilize the synergistic optimization of annealing temperature-time, reduce the lattice damage caused by traditional multiple annealing, significantly improve the interface quality and reduce the gate oxide layer defect density.

[0042] Step three, implant ions in the inner convex P- layer 15 to form a plurality of N-type blocking rings 16; implant ions in the inverted conical inner convex P- layer 15 to form vertically distributed N-type blocking rings 16, the top end of which is in close contact with the gate oxide layer 3, block the longitudinal penetration of the drain electric field by constructing a local depletion region, and suppress the gate oxide layer hot carrier injection effect from the source.

[0043] Step 4: Thermally oxidize and grow gate oxide layer 3 on the surface of P-well layer 8; deposit high-K dielectric 11 between gate 2 and P-well layer 8; directly deposit high-K dielectric 11 on thermally grown SiO2 gate oxide layer 3, utilizing the dielectric constant advantage of high-K material to reduce the equivalent oxide layer thickness, while the high-K layer shares the gate voltage and reduces the electric field strength at the SiO2 interface, the dual dielectric layers work together to improve gate insulation reliability.

[0044] Step 5: Deposit doped polysilicon 10 between source 4 and N-well layer 9, wherein the doped polysilicon 10 is P-type polysilicon or low-concentration N-type polysilicon; selectively deposit doped polysilicon 10 between source 4 and N-well layer 9: if P-type polysilicon is used, the contact barrier can be reduced, while low-concentration N-type polysilicon balances the carrier concentration. Both optimize the ohmic contact resistance of the source region and avoid the gate oxide edge electric field distortion caused by traditional metal contact.

[0045] Step 6: Etch the electrode contact windows to expose the source 4, drain 1 and gate 2 regions; Simultaneously etch the exposed source / gate / drain contact windows, utilizing the top protection of the inner convex P-layer 15 and the N-type barrier ring 16 to ensure etching accuracy without damaging the gate oxide layer edge and maintain interface integrity.

[0046] Step 7: Deposit Ni, Ti, or Al alloy layers and form source, gate, and drain electrodes using photolithography. Using a Ni / Ti / Al alloy layer and forming electrodes via photolithography leverages the low-temperature alloying properties of the metal and SiC to ensure ohmic contact quality while avoiding thermal stress damage to the high-K dielectric 11 and gate oxide layer 3 stacked structure caused by high-temperature processes.

[0047] Example 1

[0048] like Figure 1 As shown, a silicon carbide (SiC) MOSFET device with improved gate oxide reliability is disclosed. The SiC MOSFET device comprises several parallel MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a gate 2, a gate oxide layer 3, and a source 4. The semiconductor epitaxial layer includes an N-substrate layer 5, an N-diffusion layer 6, a P+ layer 7, a P-well layer 8, and an N-well layer 9. The device is characterized by a high-k dielectric 11 between the gate 2 and the P-well layer 8, wherein a doped polysilicon 10 is disposed on one side of the high-k dielectric 11, between the source 4 and the N-well layer 9. The doped polysilicon 10 does not obstruct the ohmic contact between the source 4 and the N-well layer 9.

[0049] The high-k dielectric 11 is one of hafnium dioxide, aluminum oxide, or zirconium dioxide. The doped polysilicon 10 is one of p-type polysilicon or low-concentration doped n-type polysilicon. By introducing the high-k dielectric 11 between the gate 2 and the p-well layer 8 and the doped polysilicon 10 between the source 4 and the n-well layer 9, the high-k dielectric reduces the gate leakage current and increases the dielectric strength, while the doped polysilicon optimizes the source contact resistance, synergistically enhancing the reliability of the gate oxide layer while maintaining low on-resistance.

[0050] Example 2

[0051] like Figure 2 As shown, a polysilicon layer 12 is disposed below the gate 2 in a single MOS cell; the polysilicon layer 12 is either P-type polysilicon or N-type polysilicon. By adding a polysilicon layer 12 below the gate 2, the electric field stress borne by the gate oxide layer 3 is dispersed by adjusting the local electric field distribution, avoiding gate oxide layer breakdown caused by electric field concentration, and improving the long-term stability of the device.

[0052] Example 3

[0053] like Figure 3 As shown, a suppression P-layer 13 is provided inside the lower part of the gate 2. The cross-sectional profile of the suppression P-layer 13 is trapezoidal. The top end of the suppression P-layer 13 is in direct contact with the gate 2, and the bottom end of the suppression P-layer 13 is in direct contact with the N-diffusion layer 6. The trapezoidal suppression P-layer 13 connects the gate 2 and the N-diffusion layer 6. Its gradient doping structure optimizes the vertical electric field distribution, suppresses the increase in channel resistance caused by the JFET effect, and reduces the risk of gate oxide interface defect formation.

[0054] Example 4

[0055] like Figure 4 As shown, multiple non-contacting N-type guard rings 14 are formed inside the suppressor P-layer 13 through ion implantation. The bottom end of the N-type guard ring 14 is in direct contact with the N-diffusion layer 6. Implanting N-type guard rings 14 within the suppressor P-layer 13 creates a local depletion region to absorb high-voltage stress, prevent electric field spikes below the gate, and significantly improve the gate oxide layer's shock resistance at high switching frequencies.

[0056] Example 5

[0057] like Figure 5 As shown, an inner convex P-layer 15 is provided on the surface of the semiconductor epitaxial layer and between two adjacent high-k dielectrics 11. The cross-sectional profile of the inner convex P-layer 15 is thicker at the top and thinner at the bottom. The inner convex P-layer 15 between adjacent high-k dielectrics 11, with its "wider at the top and narrower at the bottom" structure, reconstructs the lateral electric field of the drift region, alleviates the electric field crowding phenomenon between cells, and reduces the parasitic capacitance and hot carrier damage at the edge of the gate oxide layer.

[0058] Example 6

[0059] As Figure 6 shown, the inner convex P-layer 15 is internally provided with a plurality of N-type blocking rings 16 which are not in contact with each other, and the top end of the N-type blocking ring 16 is in direct contact with the gate oxide layer 3. The N-type blocking ring 16 in the inner convex P-layer 15 is vertically connected to the gate oxide layer 3 to form an electric field shielding fence, which blocks the path of the high voltage of the drain to the gate oxide layer coupling, and fundamentally inhibits the degradation failure of the gate oxide layer.

[0060] The above-described embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it cannot be understood as a limitation on the scope of the patent of the present application. It should be noted that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, which are all within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. Silicon carbide (SiC) MOSFET device with improved gate oxide reliability, said silicon carbide (SiC) MOSFET device consisting of a number of mutually juxtaposed MOS cells, said MOS cells comprising a drain (1), a semiconductor epitaxial layer, a gate (2), a gate oxide layer (3), a source (4), said semiconductor epitaxial layer comprising an N substrate layer (5), an N diffusion layer (6), a P+ layer (7), a P well layer (8) and an N well layer (9), characterized in that: The high-K dielectric (11) is one of hafnium dioxide, aluminum oxide or zirconium dioxide. The polycrystalline silicon layer (12) is one of P-type polycrystalline silicon or N-type polycrystalline silicon.

2. A silicon carbide (SiC) MOSFET device with improved gate oxide reliability according to claim 1, wherein: The high-K dielectric (11) is one of hafnium dioxide, aluminum oxide or zirconium dioxide.

3. A silicon carbide (SiC) MOSFET device with improved gate oxide reliability according to claim 1, wherein: The doped polycrystalline silicon (10) is one of P-type polycrystalline silicon or low-concentration N-type polycrystalline silicon.

4. Silicon carbide (SiC) MOSFET device with improved gate oxide reliability, said silicon carbide (SiC) MOSFET device consisting of a number of mutually juxtaposed MOS cells, said MOS cells comprising a drain (1), a semiconductor epitaxial layer, a gate (2), a gate oxide layer (3), a source (4), said semiconductor epitaxial layer comprising an N substrate layer (5), an N diffusion layer (6), a P+ layer (7), a P well layer (8) and an N well layer (9), characterized in that: The high-K dielectric (11) is one of hafnium dioxide, aluminum oxide or zirconium dioxide. The P-layer (13) is in direct contact with the N diffusion layer (6). The P-layer (13) is in direct contact with the N diffusion layer (6).

5. A silicon carbide (SiC) MOSFET device with improved gate oxide reliability according to claim 4, wherein: The P-layer (13) is in direct contact with the N diffusion layer (6).

6. Silicon carbide (SiC) MOSFET device with improved gate oxide reliability, said silicon carbide (SiC) MOSFET device consisting of a number of mutually juxtaposed MOS cells, said MOS cells comprising a drain (1), a semiconductor epitaxial layer, a gate (2), a gate oxide layer (3), a source (4), said semiconductor epitaxial layer comprising an N substrate layer (5), an N diffusion layer (6), a P+ layer (7), a P well layer (8) and an N well layer (9), characterized in that: The P-layer (13) is in direct contact with the N diffusion layer (6). The P-layer (13) is in direct contact with the N diffusion layer (6).

7. A silicon carbide (SiC) MOSFET device with improved gate oxide reliability according to claim 6, wherein: The P-layer (13) is in direct contact with the N diffusion layer (6).

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