A double-layer V-shaped nanowire structure, double-gate nanowire single-electron device and preparation method thereof

Abstract

The present application relates to the technical field of microelectronic manufacturing, and discloses a double-layer V-shaped nanowire structure, which comprises a base layer arranged on a substrate, and further comprises an upper nanowire and a lower nanowire which are grown in space on the base layer, the upper nanowire and the lower nanowire are fold line type nanowires with coincident horizontal projection at a fold point and located on the same plumb line, and the fold line type nanowire of the upper layer is disconnected at the fold point and has a gap. The present application grows two nanowires which are mutually staggered in space by single IPSLS, wherein the lower continuous silicon nanowire serves as a conductive channel, and the upper nanowire with a gap serves as a controllable depletion gate, so that the preparation process flow of the double-layer V-shaped nanowire structure is greatly simplified, and a plurality of quantum islands can be integrated to construct a compact quantum bit chain.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of microelectronic manufacturing. The present application provides a double-adjustable depletion gate SET device with a double-layer V-shaped silicon nanowire structure. More specifically, the present application provides a double-adjustable gate nanowire single-electron transistor device formed by single growth and a preparation method. BACKGROUND

[0002] Single-electron transistor (SET) as a quantum device based on Coulomb blockade effect, has revolutionary potential in next-generation quantum computing, high-precision sensing and ultra-low power electronics due to its ultra-low power consumption (single electron control) and ultra-high sensitivity (single charge detection). The core challenge of realizing high-performance SET devices is to precisely construct a "quantum island-tunnel junction" structure with a size of less than 10 nm, which requires the material to have atomic-level interface cleanliness, excellent crystal quality and diameter uniformity. Silicon nanowires (SiNWs) are considered as an ideal carrier for building SETs due to their natural compatibility with mainstream silicon-based processes, strong quantum confinement effect and controllable doping characteristics. However, the silicon nanowires grown by traditional preparation methods (such as vapor deposition VLS method) have the following bottlenecks: diameter fluctuation (>20%) leads to quantum island size dispersion; surface defect states are dense, causing random charge fluctuations; position disorder hinders high-density array integration.

[0003] The nanowires obtained by the prior art based on the "planar solid-liquid-solid" growth method have the advantages of planar or three-dimensional positioning, programmable morphology, controllable and high-diameter consistency, low cost, single crystal quality, low-temperature growth (<400°C) compatible with back-end integration, and can easily meet the needs of quantum islands.

[0004] Based on the above research results, a smaller size, lower cost, easier to grow, and higher integration density double-gate silicon-based nanowire quantum island single-electron transistor is explored to better serve the next generation of quantum computing technology and high-precision sensing and ultra-low power electronics, which is a technical problem that needs to be solved at present. SUMMARY

[0005] The present application provides a double-layer V-shaped nanowire structure, a double-gate nanowire single-electron device and a preparation method, which solves the technical problems of the prior art that silicon-based nanowire single-electron transistors cannot be positioned and integrated, and solves the technical problem that the current IPSLS technology requires multiple growths to prepare SET devices, and the process flow is complex, achieving the technical effects of simple process, low cost, positioning and high integration density of silicon nanowire single-electron transistors.

[0006] The application provides a double-layer V-shaped nanowire structure, comprising a base layer arranged on a substrate, characterized in that it further comprises an upper nanowire and a lower nanowire which are grown in space on the base layer, the upper nanowire and the lower nanowire are zigzag nanowires, the horizontal projections of the folding points of the upper nanowire and the lower nanowire coincide and are located on the same vertical line, and the upper zigzag nanowire is broken at the folding point to form a gap.

[0007] Preferably, the base layer is a double-layer silicon oxide step structure which is etched in an up-down staggered manner, the upper nanowire and the lower nanowire are grown in the V-shaped guide groove of the double-layer silicon oxide step structure, and the upper nanowire is broken at the folding point to form the gap along the guide groove.

[0008] The application further provides a double-gate nanowire single-electron device comprising the above double-layer V-shaped nanowire structure, characterized in that the surfaces of the two ends of the lower nanowire are sequentially deposited with a source electrode layer, a drain electrode layer and a dielectric layer from inside to outside, and the source electrode layer and the drain electrode layer are etched to form source electrode opening areas and drain electrode opening areas, and the two ends of the upper nanowire are sequentially deposited with a gate electrode layer and a gate dielectric layer from inside to outside, and the gate electrode layer is etched to form a gate electrode opening area.

[0009] Preferably, the thickness of the step of the double-layer silicon oxide step structure is greater than the sum of the diameter of the upper nanowire and the lower nanowire and the thickness of the electrode layer and the dielectric layer deposited on the surfaces of the upper nanowire and the lower nanowire.

[0010] Preferably, the thickness of the step is 100 nm, the diameter of the upper nanowire and the lower nanowire is 50 nm, and the thickness of the dielectric layer is 25 nm.

[0011] The application further discloses a preparation method of the above double-layer V-shaped nanowire structure, characterized in that it comprises the following steps:

[0012] In the first step, the side surface structure of the silicon oxide base layer is exposed by using photoetching and reaction coupled plasma etching technology to form a first step-shaped guide groove layer;

[0013] In the second step, the side surface structure of the silicon oxide base layer is exposed by using photoetching and reaction coupled plasma etching technology to cross the first step-shaped guide groove layer to form a second step-shaped guide groove layer, thereby obtaining a double-layer V-shaped guide groove;

[0014] In the third step, a catalytic metal area is positioned on the lower end of the double-layer V-shaped guide groove by using photoetching technology, and a metal film is deposited by using thermal evaporation deposition technology; a catalytic metal area is positioned on the upper end of the double-layer V-shaped guide groove which is farther away from the folding point than the lower end by using photoetching technology, and a metal film is deposited by using thermal evaporation deposition technology;

[0015] Fourthly, after the metal film is reduced into metal balls by hydrogen plasma in a PECVD device, the precursor is covered, and under the high temperature environment of vacuum and 300-350 DEG C, the metal balls absorb the precursor along the V-shaped guide channel on the etched silicon oxide substrate layer, the upper metal ball moves to the folding point, and the precursor at the folding point is temporarily unable to form a nanowire because it has been absorbed by the lower metal ball, and finally, the lower nanowire of the fold line type is grown along the lower V-shaped guide channel, and the upper nanowire is grown along the upper V-shaped guide channel and is disconnected at the folding point.

[0016] Preferably, the V-shaped guide channel has an included angle of 120-150 DEG.

[0017] The application further discloses a preparation method of the double-gate nanowire single-electron device.

[0018] Firstly, the nanowire electrode area is positioned at four ends of the double-layer V-shaped nanowire structure by using a photolithography technology, and the sample with the grown nanowire is removed from the native oxide layer on the surface of the nanowire by using a silicon oxide etching solution; and the nanowire electrode is linked to the four ends of the nanowire by using an electron beam evaporation deposition.

[0019] Secondly, the gate dielectric layer is deposited on the surface of the double-layer V-shaped nanowire structure by using an ALD technology, and the gate dielectric layer is deposited on the double-layer V-shaped nanowire structure without positioning and covering the whole surface.

[0020] Thirdly, the gate dielectric layer on the upper nanowire electrode is locally etched by using a photolithography and etching technology, so as to form the opening area of the double-gate nanowire single-electron device, and the voltage is applied to the source electrode, the drain electrode and the gate electrode formed by the nanowire electrode and the double-layer V-shaped nanowire.

[0021] Preferably, the source electrode layer and the drain electrode layer are respectively positioned and deposited at two ends of the lower nanowire of the double-layer V-shaped nanowire structure, and the gate electrode layer is positioned and deposited at two ends of the upper nanowire, so as to form the gate electrode of the double-gate nanowire single-electron device.

[0022] The technical scheme provided by the application has at least the following technical effects or advantages:

[0023] 1. The two spatially staggered nanowires are grown by using single IPSLS, the lower continuous silicon nanowire is used as a conductive channel, and the upper nanowire with a gap is used as a controllable depletion gate, so that the preparation process of the double-layer V-shaped nanowire structure is greatly simplified, a plurality of quantum islands can be integrated, and a compact quantum bit chain can be constructed.

[0024] 2. The application solves the technical problem of obtaining small-size double-adjustable depletion gate that can be positioned by single IPSLS growth, effectively improves the integration density of silicon nanowire double-adjustable depletion gate SET, reduces the production cost, and is suitable for silicon-based quantum devices.

[0025] 3. The application uses the lower nanowire to grow to the inflection point first and absorb the amorphous silicon at the inflection point in advance, and the upper nanowire automatically generates a double-layer space V-shaped nanowire structure gap when growing to the inflection point due to insufficient amorphous silicon supply, to prepare a double-adjustable gate SET device, avoiding high cost and large-scale integration due to the need to use high-precision lithography, and the silicon nanowire double-adjustable gate SET device has the ability to form a quantum island through electric field depletion on unetched continuous nanowires to avoid etching damage, solving the fundamental contradiction between quantum island precision, noise suppression and scalability in traditional SET. The design provides one of the most promising technical paths for the practicality of silicon-based quantum devices. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a preparation flow chart of a double-layer V-shaped nanowire structure in an embodiment of the application;

[0027] Figure 2 is a structure schematic diagram of a double-adjustable depletion gate SET prepared by using a double-layer V-shaped nanowire structure in an embodiment of the application;

[0028] Figure 3 is a logic schematic diagram of a double-adjustable depletion gate SET prepared by using a double-layer V-shaped nanowire structure in an embodiment of the application;

[0029] Figure 4 is a plane schematic diagram of a double-adjustable depletion gate SET prepared by using a double-layer V-shaped nanowire structure in an embodiment of the application;

[0030] In the figure: 101, double-layer V-shaped step; 102, lower nanowire; 103, upper nanowire; 104, silicon oxide substrate step structure after first etching; 105, step structure formed by silicon oxide substrate after second etching; 106, upper guiding channel metal indium thin film; 107, lower guiding channel metal indium thin film; 108, upper guiding channel indium ball; 109, lower guiding channel indium ball; 110, amorphous silicon precursor; 111, lower nanowire growing to the inflection point first; 112, upper nanowire not growing to the inflection point; 201, double-adjustable depletion gate SET device; 202, gate dielectric layer; 203, source and drain electrode layer; 204, gate electrode layer; 301, source and drain electrode opening area; 401, gate electrode opening area. DETAILED DESCRIPTION

[0031] Based on a single-growth planar nanowire structure, this invention first uses two upper nanowires as gates to control the underlying continuous nanowire. Then, using ALD deposition technology, the gate dielectric and electrode layers are deposited using a double-layer V-shaped nanowire structure to create a high-performance dual-controllable depletion gate SET device. Leveraging the topography programming and three-dimensional positioning capabilities of the double-layer V-shaped nanowires, this invention achieves low cost, uniform dimensions, low defects, and high density.

[0032] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0033] Example 1: This example provides a double-layer V-shaped nanowire structure and a preparation method, such as Figure 1 As shown: it includes a silicon oxide base layer arranged on a silicon substrate, and also includes an upper nanowire 103 and a lower nanowire 102 that are spatially dislocated and grown on a double-layer V-shaped step 101 of the silicon oxide base layer. The upper nanowire 103 and the lower nanowire 102 are V-shaped nanowires whose horizontal projections of the inflection points coincide and are located on the same plumb line. The upper nanowire is disconnected at the inflection point and there is a gap.

[0034] As a preferred embodiment of this invention, a double-layer silicon oxide step structure is formed by staggered cross-etching of the upper and lower silicon oxide base layers, and the upper nanowires and the lower nanowires are respectively grown in the V-shaped guide channel of the double-layer silicon oxide step structure. The upper nanowire grows along the guide channel and breaks at the inflection point to form the gap.

[0035] This embodiment also discloses a method for preparing the double-layer V-shaped nanowire structure, which includes the following steps:

[0036] In the first step, a silicon oxide layer is patterned on a single-sided polished substrate material having an upper silicon oxide layer having a thickness of more than 1 micron using photolithography technology, and then the silicon oxide layer is etched using inductively coupled plasma (ICP) etching technology to form a silicon oxide base layer step structure 104 after the first etching. In this embodiment, an etching depth of 100 nm is used as an example.

[0037] In the second step, the silicon oxide layer is patterned using photolithography, forming an angle with the pattern created in the first step. To ensure that the lower nanowires do not grow across the steps to the upper layer, the angle formed by the lower guide steps is controlled at 120 degrees. The silicon oxide layer is then etched using inductively coupled plasma (ICP) etching technology, forming a stepped structure 105 formed by the silicon oxide base layer after the second etching. In this embodiment, the etching depth is 100 nm.

[0038] Third step, using lithography technology to locate the metal indium region in the etched silicon oxide layer and the one end of the silicon oxide guide channel layer, using thermal evaporation deposition technology to deposit the upper layer guide channel metal indium film 106 far from the cross point of the upper layer channel, and deposit the lower layer guide channel metal indium film 107 close to the cross point of the lower layer channel; using the "plane solid-liquid-solid" growth method, after reducing the upper layer guide channel metal indium film 106 and the lower layer guide channel metal indium film 107 into the upper layer guide channel indium ball 108 and the lower layer guide channel indium ball 109 using hydrogen plasma in the PECVD equipment, cover the amorphous silicon precursor 110 film.

[0039] As preferred, the upper layer guide channel metal indium film of the embodiment is 45 microns away from the cross point, and the lower layer guide channel metal indium film is 40 microns away from the cross point.

[0040] Fourth step, in a vacuum and high temperature environment of 300-350°C, the upper layer guide channel indium ball 108 absorbs the amorphous silicon precursor a-Si along the etched silicon oxide guide channel layer to grow the crystalline silicon nanowire in the back end, and the lower layer guide channel indium ball 109 absorbs the amorphous silicon precursor a-Si along the etched silicon oxide guide channel layer to grow the crystalline silicon nanowire in the back end. The lower layer guide channel indium ball moves to the guide channel cross point and absorbs the amorphous silicon precursor a-Si to form the lower layer nanowire 111 that grows to the cross point first, and the upper layer guide channel indium ball has not grown to the cross point to form the upper layer nanowire 112 that has not grown to the cross point.

[0041] Fifth step, in a vacuum and high temperature environment of 300-350°C, the lower layer guide channel indium ball continues to absorb the amorphous silicon precursor a-Si along the etched silicon oxide guide channel layer to grow the crystalline silicon nanowire in the back end to form the lower layer nanowire 102, and the upper layer guide channel indium ball absorbs the amorphous silicon precursor a-Si along the etched silicon oxide guide channel layer to grow the crystalline silicon nanowire in the back end. When the upper layer guide channel indium ball moves to the cross point, it cannot form a nanowire temporarily because the amorphous silicon precursor a-Si at the cross point has been absorbed by the lower layer guide channel indium ball, and finally forms the upper layer nanowire 103 that is disconnected at the silicon oxide guide channel cross point.

[0042] Embodiment 2: The embodiment provides a double adjustable depletion gate SET device 201, as shown in the figure: including the double layer V-shaped nanowire structure described in embodiment 1, the surfaces of the two ends of the lower layer nanowire are sequentially deposited with the source electrode layer, the drain electrode layer and the gate dielectric layer 202 from inside to outside, and etched to form the source electrode opening area 301 and the drain electrode opening area 302, and the two ends of the upper layer nanowire are sequentially deposited with the gate electrode layer 204 and the gate dielectric layer 202 from inside to outside, and etched to form the gate electrode opening area 401. Figures 2-4

[0043] ​Preferably, in this embodiment, a gate dielectric layer 202 is deposited on the entire surface; the upper disconnected nanowires of the double-layer V-shaped nanowires constitute the gate of the dual-adjustable depletion gate SET device; the gate dielectric layer 202 is made of a high dielectric constant dielectric material, such as hafnium oxide, by ALD.

[0044] Preferably, the step thickness of the double-layer silicon oxide step structure in this embodiment is greater than the diameter of the upper and lower nanowires, plus the thickness of the electrode layer and dielectric layer deposited on their surfaces. More specifically, to ensure that the nanowires grow along the edge of the silicon oxide step layer without crossing the step, the step thickness is 100 nm, the diameters of the upper and lower nanowires are 50 nm, the dielectric layer thickness is 25 nm, and the distance between the fracture of the upper nanowire and the lower nanowire is 50 nm. Therefore, the high-k gate dielectric layer 202 deposited using ALD technology can ensure complete encapsulation of the nanowires, and the high-k gate dielectric layer can achieve good gate control of the silicon nanowires.

[0045] This embodiment also discloses a method for preparing the dual-controllable depletion gate SET device. First, the double-layer V-shaped nanowire structure in Example 1 is prepared by a planar solid-liquid-solid growth method. Then, the method further includes the following steps:

[0046] In the first step, near the four ends of the double-layer V-shaped nanowire, Figure 2 In the device structure shown, the source, drain, and gate electrode regions are first positioned using photolithography, and the areas outside the regions are covered with photoresist. The source, drain, and gate electrode layers are deposited using EBE technology, and then the metal layer outside the positioning areas is lift-off to obtain patterned source and drain electrode layers 203 and gate electrode layer 204.

[0047] In the second step, a gate dielectric layer 202 is deposited on the entire surface of the double-layer V-shaped nanowire structure and the source, drain, and gate electrode layers using ALD technology. The gate dielectric layer is deposited on the entire surface and wraps around the double-layer V-shaped nanowire structure and the source, drain, and gate electrode layers.

[0048] In the third step, the gate dielectric layer on the nanowire source, drain and gate electrodes is partially etched using photolithography and etching techniques to form the source and drain electrode opening regions 301 and the gate electrode opening region 401 in the dual-adjustable depletion gate SET device, so as to facilitate the application of source and drain voltages to the source and drain electrodes and the application of gate voltage to the gate electrode.

[0049] The application is based on a metal nanodroplet-induced self-organizing catalytic growth strategy, and can directly batch grow and prepare single-crystal nanowire structures with fine diameters by using a "top-down" etching method independent of high-precision photolithography technology. Through a new "planar solid-liquid-solid" nanowire growth mode, the nanowire growth is completely restricted and positioned at the edge of a planar step. By skillfully forming an angle between double-layer misoriented steps, a nanowire structure that can be accurately disconnected is formed, which provides a convenient and reliable high-integration structure for using nanowires as depletion gates to form small-size quantum islands. Through the structure or device of the application for preparing a double-adjustable depletion gate SET using nanowires, the problems of troublesome silicon nanowire quantum island manufacturing, inability to position, and difficulty in mass production are effectively solved, and the application potential of silicon nanowires in the future development of quantum computing field is greatly improved.

[0050] The above only describes the preferred embodiments of the present application, and it should be noted that those skilled in the art can make several improvements without departing from the principles of the present application, and these improvements should also be considered as the protection scope of the present application.

Claims

1. A double-layer V-shaped nanowire structure comprising a base layer disposed on a substrate, characterized in that, The upper layer nanowire and the lower layer nanowire grown on the substrate layer are fold line type nanowires, the fold points of the upper layer nanowire and the lower layer nanowire are horizontally projected to coincide and are located on the same plumb line, and the fold line type nanowire of the upper layer is broken at the fold point to have a gap.

2. The double-layer V-shaped nanowire structure of claim 1, wherein: The substrate layer is a double-layer silicon oxide step structure etched by upper and lower staggered intersection, the upper layer nanowire and the lower layer nanowire are respectively grown in the V-shaped guide channel of the double-layer silicon oxide step structure, and the upper layer nanowire is broken at the fold point to form the gap along the guide groove.

3. A double-gate nanowire single-electron device comprising the double-layer V-shaped nanowire structure of claim 1 or 2, characterized in that: The two end surfaces of the lower layer nanowire are sequentially deposited with a source electrode layer, a drain electrode layer and a dielectric layer from inside to outside and etched to form a source electrode opening area and a drain electrode opening area, and the two ends of the upper layer nanowire are sequentially deposited with a gate electrode layer and a dielectric layer from inside to outside and etched to form a gate electrode opening area.

4. The dual-gate nanowire single-electron device of claim 3, wherein: The step thickness of the double-layer silicon oxide step structure is greater than the sum of the diameter of the upper layer nanowire and the lower layer nanowire and the thickness of the electrode layer and the dielectric layer deposited on the surface thereof.

5. The double-gate nanowire single-electron device of claim 4, wherein the nanowire is a semiconductor nanowire. The step thickness is 100 nm, the diameter of the upper layer nanowire and the lower layer nanowire is 50 nm, and the dielectric layer thickness is 25 nm.

6. A method of fabricating a double-layer V-shaped nanowire structure, characterized by, The following steps are included: First step, the side surface structure of the silicon oxide substrate layer is exposed by using photoetching and reaction coupled plasma etching technology to form a first layer step-shaped guide channel layer; Second step, the side surface structure of the silicon oxide substrate layer is exposed by using photoetching and reaction coupled plasma etching technology to cross the first layer step-shaped guide channel layer to form a second layer step-shaped guide channel layer, and a double-layer V-shaped guide channel is obtained; Third step, a catalytic metal area is positioned on the lower end of the double-layer V-shaped guide channel by using photoetching technology, and a metal film is deposited by using thermal evaporation deposition technology; then a catalytic metal area is positioned on the upper end of the double-layer V-shaped guide channel which is farther from the fold point than the lower end by using photoetching technology, and a metal film is deposited by using thermal evaporation deposition technology; Fourth step, using the planar solid-liquid-solid growth method, after the metal film is reduced to a metal ball by using hydrogen plasma in the PECVD equipment, the precursor is covered, in a vacuum and high temperature environment of 300-350°C, the metal ball absorbs the precursor along the V-shaped guide channel on the etched silicon oxide substrate layer, the upper metal ball cannot form a nanowire temporarily when it moves to the fold point because the precursor at the fold point has been absorbed by the lower metal ball, and finally a fold line type lower layer nanowire grown along the lower layer V-shaped guide channel and an upper layer nanowire broken at the fold point and grown along the upper layer V-shaped guide channel are formed.

7. The method of claim 6, wherein the method further comprises: The V-shaped guide channel has an included angle in the range of 120°-150°.

8. A method of fabricating a double-gate nanowire single-electron device, suitable for use in the double-gate nanowire single-electron device of claim 3, comprising: The following steps are included: ​ First step, nanowire electrode areas are positioned on the four ends of the double-layer V-shaped nanowire structure by using photoetching technology, and the sample after growing the nanowire is removed from the original surface oxide layer of the nanowire by using a silicon oxide etching solution; nanowire electrodes are deposited by using electron beam evaporation to link the four ends of the nanowire; In the second step, a gate dielectric layer is deposited on the surface of the double-layer V-shaped nanowire structure by using ALD technology, and the gate dielectric layer is deposited on the double-layer V-shaped nanowire structure without positioning and uniformly. In the third step, the gate dielectric layer on the upper layer of the nanowire electrode is locally etched by using photolithography and etching technology to form an opening area of the double-gate nanowire single-electron device, so as to facilitate the voltage application to the source electrode, the drain electrode and the gate electrode formed by the nanowire electrode and the double-layer V-shaped nanowire.

9. The method of claim 8, wherein the method further comprises: The lower-layer nanowire of the double-layer V-shaped nanowire structure is respectively positioned and deposited with the source electrode layer and the drain electrode layer at both ends, and the upper-layer nanowire is positioned and deposited with the gate electrode layer at both ends to form the gate electrode of the double-gate nanowire single-electron device.

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