Integrated assembly containing two-dimensional material

Abstract

The invention relates to an integrated assembly containing a two-dimensional material. Some embodiments include an integrated assembly having a semiconductor material with a more doped region adjacent to a less doped region. A two-dimensional material is located between the more doped region and a portion of the less doped region. Some embodiments include an integrated assembly containing a semiconductor material, a metal-containing material over the semiconductor material, and a two-dimensional material between a portion of the semiconductor material and the metal-containing material. Some embodiments include a transistor having a first source / drain region, a second source / drain region, a channel region between the first source / drain region and the second source / drain region, and a two-dimensional material between the channel region and the first source / drain region.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the Chinese invention patent application with the invention name “Integrated assembly containing two-dimensional materials”, application number 202080064284.4, and application date July 23, 2020.

[0003] Related patent data

[0004] This application is related to U.S. patent application Ser. No. 16 / 542,078, filed on Aug. 15, 2019, entitled “Integrated Assemblies Containing Two-Dimensional Materials,” the entire contents of which are incorporated herein by reference. Technical Field

[0005] Integrated assemblies containing two-dimensional materials. Background Art

[0006] Integrated assemblies may include dopants or other materials that may diffuse or otherwise migrate problematically. For example, polysilicon may have different grain sizes, and this may enable dopants to diffuse to different depths within the polysilicon. The performance of highly integrated devices (e.g., transistors) may be affected by the diffusion depth of the dopant. Different depths of diffusion across an arrangement of integrated devices may problematically cause non-uniformity in the performance of the integrated devices; this may cause operational difficulties and even device failure. As another example, metal may migrate from a metal silicide (or another metal source) and problematically alter the electrical properties of nearby areas.

[0007] There is a need to develop structures that can be readily incorporated into integrated assemblies to mitigate or even prevent the problematic migration of dopants and other materials. Summary of the Invention

[0008] On the one hand, the present disclosure provides a transistor comprising: a first source / drain region; a second source / drain region; a channel region located between the first source / drain region and the second source / drain region; and a two-dimensional material located between the channel region and the first source / drain region, the two-dimensional material comprising one or more materials selected from the group consisting of: carbon, boron, tin, bismuth, molybdenum, platinum, tungsten and hafnium.

[0009] On the other hand, the present disclosure further provides a memory structure including the above-mentioned transistor, wherein the memory structure includes a storage element coupled to one of the first source / drain region and the second source / drain region, and includes a digital line coupled to the other of the first source / drain region and the second source / drain region.

[0010] On the other hand, the present disclosure further provides a transistor comprising: a first source / drain region; a second source / drain region; a channel region located between the first source / drain region and the second source / drain region, the first source / drain region, the second source / drain region and the channel region extending within a semiconductor material; and a two-dimensional material located between the channel region and the first source / drain region, wherein the semiconductor material is a polycrystalline material. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 11 is a diagrammatic cross-sectional side view of a region of an example integrated assembly.

[0012] Figure 12 is a diagrammatic representation of a region of an example memory array. DETAILED DESCRIPTION

[0013] Some embodiments include integrated assemblies having two-dimensional materials used in barrier regions to prevent undesired migration of dopants and other materials. Figures 1 to 12 Example embodiments are described.

[0014] refer to Figure 1 , integrated assembly 10 includes semiconductor material 12 having a first region 14 above a second region 16. The first region is more heavily doped than the second region. Dashed line 15 is provided to illustrate a substantial barrier between first region 14 and second region 16.

[0015] Semiconductor material 12 may comprise any suitable composition and, in some embodiments, may comprise, consist essentially of, or consist of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc., wherein the term III / V semiconductor material refers to a semiconductor material including elements selected from Groups III and V of the periodic table (where Groups III and V are legacy nomenclature and are now referred to as Groups 13 and 15). In some applications, semiconductor material 12 may comprise, consist essentially of, or consist of polycrystalline silicon.

[0016] Doped regions 14 of semiconductor material 12 may include any suitable dopant concentration; and in some embodiments may be heavily doped (ie, doped to at least about 10 20 atoms / cm 3The dopant in region 14 may be p-type or n-type and, in some embodiments, may include one or more of boron, phosphorus, arsenic, and the like.

[0017] Region 16 of semiconductor material 12 may be doped to a value less than or equal to about 10 18 atoms / cm 3 , or even less than or equal to about 10 16 atoms / cm 3 concentration; and in some embodiments may be inherently doped (or in other words, may be effectively undoped).

[0018] A problem that can occur in conventional assemblies is that dopants can migrate from region 14 into region 16. If semiconductor material 12 comprises a polycrystalline material (e.g., polysilicon), dopants can migrate along grain boundaries. Figure 1 In the illustrated embodiment of FIG. 1 , a barrier region 18 is provided to mitigate or even prevent undesired dopant migration. Specifically, the barrier region is provided between the more doped region 14 and a portion 20 of the less doped region 16 of the semiconductor material 12 .

[0019] Barrier region 18 includes a two-dimensional material 22. The term "two-dimensional material" refers to a material having one or more layers that have stronger forces within each layer (ionic, covalent, etc.) than along the edges of the layers (e.g., between adjacent layers). The forces along the edges of the layers (e.g., between adjacent layers) will typically be primarily van der Waals forces. Two-dimensional material 22 can include any suitable number of layers; in some embodiments, it can include a stack of 1 to 10 individual layers.

[0020] The two-dimensional material 22 may comprise any suitable composition and, in some embodiments, may comprise one or more of carbon, boron, germanium, silicon, tin, phosphorus, bismuth, molybdenum, platinum, tungsten, and hafnium. In certain applications, the two-dimensional material 22 may comprise one or more of graphene, graphyne, borophene, germanene, silicene, Si2BN, stanine, phosphorene, bismuthene, molybdenum disulfide, molybdenum diselenide, tungsten diselenide, and hafnium disulfide. In some embodiments, molybdenum sulfide may be advantageous because it can be very thin (less than 1 / 4"). ) to enable electrons to tunnel through the molybdenum sulfide. Furthermore, the band offset relative to polysilicon is small, so tunneling barriers can be small in configurations where molybdenum sulfide is immediately adjacent to polysilicon. In some embodiments, it may be advantageous to utilize molybdenum disulfide and / or molybdenum diselenide within the two-dimensional material 22 so that it can be easily manufactured as part of an integrated assembly.

[0021] An advantage of the two-dimensional material 22 is that it can block dopant migration while still allowing electrons to pass through it. Thus, even though the barrier region 18 is in place to block dopant migration from the more doped region 14 to the less doped portion 20, the portion 20 of the less doped region 16 remains electrically coupled to the more doped region 14.

[0022] The barrier region 18 may include a single two-dimensional material 22 (as shown) or may include a laminate of two or more different two-dimensional materials.

[0023] The barrier region 18 may be provided in any suitable location within the semiconductor material 12. Figure 1 In the embodiment of FIG, the barrier region 18 is offset from the boundary 15 of the more doped region 14 by an intervening region 24 of the semiconductor material 12. In other embodiments, the barrier region 18 may directly abut the more doped region 14 of the semiconductor material 12, such as Figure 2 Specifically, Figure 2 The integrated assembly 10a is shown with a barrier region 18 directly against the interface 15 along the bottom of the more doped region 14. The barrier region 18 can act as a barrier during dopant activation (rapid thermal processing, laser annealing, etc.) to constrain the desired junction depth.

[0024] In some embodiments, barrier region 18 may include two or more two-dimensional materials 22 that may be directly against each other or may be separated from each other by an intervening region of semiconductor material 12. For example, Figure 3 Assembly 10b is shown in which barrier region 18 includes a pair of two-dimensional materials 22a and 22b separated from each other by an intervening region 26 of semiconductor material 12. Two-dimensional materials 22a and 22b can be the same composition as one another, or they can be different compositions relative to one another. Two-dimensional materials 22a and 22b can have the same thickness as one another, or they can have different thicknesses relative to one another. An advantage of utilizing two two-dimensional materials in barrier region 18 is that if the first material is somewhat leaky for dopants entering barrier region 18, the second material can help prevent migration through barrier region 18.

[0025] In some embodiments, Figure 3 The barrier region 18 may be considered to include a first portion including the first two-dimensional material 22a and a second portion including the additional two-dimensional material 22b. The first portion may be considered to be separated from the second portion by an intervening region 26 of semiconductor material 12.

[0026] In some embodiments, in addition to or as an alternative to preventing the migration of dopants, barrier region 18 can also mitigate or prevent the migration of metal-containing materials. For example, Figure 4An assembly 10c is shown having a metal silicide 28 (or another metal-containing material) above a semiconductor material 12. In conventional configurations, metal can problematically migrate from the metal silicide (and / or from another metal-containing material) into the semiconductor material 12, thereby altering the electrical properties of the semiconductor material and / or altering the electrical properties of other materials (not shown) proximate to the semiconductor material. In the illustrated embodiment, a barrier region 18 is provided proximate to the metal-containing material 28. The barrier region 18 comprises a two-dimensional material 22 and can mitigate or prevent metal migration therethrough while enabling electrical coupling across the two-dimensional material (i.e., the barrier material). For example, in the illustrated embodiment, the barrier region 18 is located between a portion 20 of the semiconductor material 12 and the metal-containing material 28 and can prevent metal migration into the portion 20 while enabling electrical coupling between the portion 20 and the metal-containing material 28.

[0027] In some exemplary embodiments, metal-containing material 28 may include, consist essentially of, or consist of a metal silicide. For example, metal-containing material 28 may include, consist essentially of, or consist of cobalt silicide. Cobalt can be a problematic metal for migration, and two-dimensional material 22 within barrier region 18 can advantageously prevent undesirable migration of cobalt.

[0028] Figure 4 The configuration shows the barrier region 18 separated from the metal-containing material 28 by an intervening region 30 of semiconductor material 12. In other embodiments, the barrier region may be directly against the metal-containing material 28, such as Figure 5 As shown in FIG. 1 , relative to the example integrated assembly 10d.

[0029] Figures 1 to 5 The barrier region 18 can be used in any suitable integrated assembly. In some embodiments, the barrier region can be incorporated into an integrated transistor, as shown in FIG. Figures 6 to 11 described.

[0030] refer to Figure 6 , assembly 10e includes a transistor 32. Transistor 32 includes a first source / drain region 34, a second source / drain region 36, and a channel region 38 between the first source / drain region and the second source / drain region. Dashed lines 39 and 41 are provided to show the approximate boundaries of source / drain regions 34 and 36.

[0031] Source / drain regions 34 and 36 may be heavily doped with n-type dopants or p-type dopants (e.g., one or more of phosphorus, boron, and arsenic); and channel region 38 may be less heavily doped, or may even be intrinsically doped. It is desirable to prevent dopants from migrating from the heavily doped source / drain regions into the channel region.

[0032] Regions 34, 36, and 38 are within semiconductor material 12. Semiconductor material 12 may include the semiconductor material 12 described above with reference to Figure 1Any of the compositions described; and in some embodiments may include, consist essentially of, or consist of polycrystalline silicon.

[0033] Transistor 32 includes a conductive gate material 40 that forms a conductive gate 42 adjacent to channel region 38. Gate material 40 may include any suitable conductive composition, such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.).

[0034] Conductive gate 42 is spaced apart from channel region 38 by gate dielectric material 44. The gate dielectric material may comprise any suitable composition; and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

[0035] The transistor 32 includes a barrier region 18 between a channel region 38 and a first source / drain region 34. The barrier region 18 includes the Figure 1 The two-dimensional material 22 is described.

[0036] The transistors illustrated may represent numerous transistors extending across an integrated assembly. In some embodiments, semiconductor material 12 comprises polycrystalline silicon. The grain size may vary throughout the polycrystalline silicon, which may cause dopants to diffuse (or otherwise migrate) along grain boundaries. Dopants may migrate from source / drain regions 34 toward channel region 38, and the amount of migration may vary depending on the grain size within the various regions of polycrystalline semiconductor material 12. Therefore, it may be difficult to control the amount of migration across the transistors of the integrated assembly. Barrier region 18 may stop the migration of dopants at a predetermined level corresponding to the level of the barrier region, which may enable better control of the dopant distribution compared to conventional configurations.

[0037] The illustrated transistor 32 is within an integrated assembly that includes a digit line DL1 located beneath and electrically coupled to a source / drain region 36. The digit line comprises a conductive material 48. Material 48 may comprise any suitable conductive composition, such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.).

[0038] Digit line DL1 is supported by insulating material 50. Material 50 may comprise any suitable composition; and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

[0039] Transistor gate 42 is part of word line WL1 .

[0040] Word line WL1 is relative to Figure 6 The cross section extends into and out of the page, while the digital line DL1 runs along Figure 6 Thus, the word lines extend substantially orthogonally relative to the digit lines (wherein the term "substantially orthogonal" means orthogonal within reasonable tolerances for manufacturing and management).

[0041] The gate 42 may have any suitable configuration. Figure 6 In the illustrated embodiment of FIG, the gate extends along two sides of the channel region 38. In other embodiments, the gate may extend along only a single side of the channel region, along three sides of the channel region, or may extend completely around the channel region (i.e., may be part of a gate-all-around configuration). Furthermore, it should be understood that the embodiments may extend to any device geometry that may benefit from the barrier regions described herein, including finFET configurations, etc.

[0042] Insulating material 52 extends around gate 42. Insulating material 52 may comprise any suitable composition and, in some embodiments, may comprise, consist essentially of, or consist of silicon dioxide. In the illustrated embodiment, gate dielectric material 44 and insulating material 52 are combined to indicate that they may comprise the same composition as one another. In other embodiments, gate dielectric material 44 may comprise a different composition than insulating material 52.

[0043] Conductive material 54 is located over source / drain regions 34. Conductive material 54 may comprise any suitable composition and, in some embodiments, may comprise a metal-containing material (e.g., at least a portion of material 54 may comprise, consist essentially of, or consist of copper, platinum, titanium, tantalum, etc.) and / or a metal silicide (e.g., tantalum silicide, titanium silicide, cobalt silicide, etc.).

[0044] The memory element 56 is electrically coupled to the source / drain regions 34 through the conductive material 54. The memory element 56 can be any suitable device having at least two detectable states, and in some embodiments can be, for example, a capacitor, a resistive memory device, a conductive bridge device, a phase change memory (PCM) device, a programmable metallization cell (PMC), etc.

[0045] Storage element 56 and transistor 32 may together be comprised of memory structure 58. In some embodiments, memory structure 58 may be a dynamic random access memory (DRAM) cell, and storage element 56 may be a capacitor. The illustrated memory structure 58 may represent a large number of memory structures of a memory array.

[0046] In the illustrated embodiment, memory structure 58 is supported by base 60. Base 60 may comprise a semiconductor material; and may, for example, comprise, consist essentially of, or consist of single crystal silicon. Base 60 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction comprising a semiconducting material, including, but not limited to, bulk semiconducting material, such as a semiconducting wafer (alone or in an assembly including other materials), and a layer of semiconducting material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications, base 60 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, diffusion materials, insulator materials, and the like.

[0047] A gap is provided between the substrate 60 and the insulating material 50 to indicate that there may be other materials, structures, etc. disposed between the substrate 60 and the insulating material 50. Alternatively, the insulating material 50 may rest directly against the upper surface of the substrate 60.

[0048] Figure 6 The embodiment has similar Figure 1 The configuration of the first source / drain region 34 (i.e., the first source / drain region 34 is separated from the two-dimensional material 22 by the insertion region of the semiconductor material 12) is provided with an insertion region 24 between the first source / drain region 34 and the two-dimensional material 22. In other embodiments, the bottom of the source / drain region 34 may directly abut the two-dimensional material 22, such as Figure 7 As shown in the assembly 10f.

[0049] In some embodiments, in addition to or as an alternative to the barrier region disposed between the first source / drain region and the channel region, a barrier region 18 may be disposed between the second source / drain region 36 and the channel region 38. For example, Figure 8 Assembly 10 g is shown in which a first barrier region 18 a is disposed between the source / drain region 34 and the channel region 12 , and a second barrier region 18 b is disposed between the source / drain region 36 and the channel region 12 .

[0050] The first barrier region 18a comprises a first two-dimensional material 22a, and the second barrier region 18b comprises a second two-dimensional material 22b. Materials 22a and 22b may be compositionally identical to one another, or may be compositionally different relative to one another.

[0051] In the illustrated embodiment, barrier regions 18a and 18b are separated from source / drain regions 34 and 36 by insertion regions 24a and 24b. In other embodiments, one or both of insertion regions 24a and 24b may be omitted so that one or both of barrier regions 18a and 18b abut directly against adjacent source / drain regions.

[0052] In some embodiments, an additional barrier region may be provided within the channel region 38, such as Figure 9 Specifically, in addition to the third barrier region 18c in the channel region 38 included in the assembly 10h, Figure 9 The assembly 10h and Figure 8 The barrier region 18c includes a two-dimensional material 22c. The two-dimensional material 22c may be the same as one or both of the two-dimensional materials 22a and 22b, or may be different from both of the two-dimensional materials 22a and 22b. The two-dimensional material 22c within the channel region 38 may be used to prevent dopants or other materials from migrating across the channel region if such dopants or other materials could enter the channel region.

[0053] In some embodiments, an additional barrier region may be provided adjacent to the metal-containing material 54, such as Figure 10 Specifically, except that assembly 10i includes a fourth barrier region 18d directly adjacent to metal-containing material 54, Figure 10 The assembly 10i and Figure 9 The barrier region 18d includes a two-dimensional material 22d. The two-dimensional material 22d may be the same as one or more of the two-dimensional materials 22a, 22b, and 22c, or may be different from all of the two-dimensional materials 22a, 22b, and 22c. The two-dimensional material 22d may be used to prevent metal (e.g., cobalt) from migrating from the metal-containing material 54 into the semiconductor material 12 (and, in the embodiment shown, may be used to prevent metal from migrating into the source / drain regions 34).

[0054] Various embodiments may include any of the barrier regions 18a-18d, alone or in combination with any other of the barrier regions 18a-18d.

[0055] In some embodiments, one or more of the barrier regions 18a-18d may include two or more two-dimensional materials. The two-dimensional materials within individual barrier regions may be directly adjacent to each other or may be separated from each other by intervening regions of semiconductor material 12. Figure 11An integrated assembly 10j is shown having barrier regions 18a to 18d, each comprising two or more two-dimensional materials. Specifically, barrier region 18a comprises three two-dimensional materials 22a-1, 22a-2, and 22a-3; barrier region 18b comprises three two-dimensional materials 22b-1, 22b-2, and 22b-3; barrier region 18c comprises a pair of two-dimensional materials 22c-1 and 22c-2; and barrier region 18d comprises a pair of two-dimensional materials 22d-1 and 22d-2. The various two-dimensional materials may comprise any suitable composition and may, for example, comprise two or more two-dimensional materials relative to one another. Figure 1 The barrier material 22 may be any of the compositions described. Figure 11 Two or more of the two-dimensional materials may be the same composition as one another, and / or one or more of the two-dimensional materials may be a different composition than one or more other of the two-dimensional materials.

[0056] Memory structure 58 may be incorporated into a memory array, such as a DRAM array. Figure 12 Schematically illustrates a region of an example DRAM array 70. The DRAM array 70 includes a plurality of word lines (WL1 to WL4) and a plurality of digit lines (DL1 to DL4). The word lines can be considered to extend along the rows of the memory array, and the digit lines can be considered to extend along the columns of the memory array.

[0057] Memory structure 58 includes transistor 32. Gate 42 of the transistor is coupled to a word line. Source / drain region 36 of the transistor is coupled to a digit line, and source / drain region 34 of the transistor is coupled to storage element 56, which corresponds to a capacitor. Each of the capacitors is coupled to a reference voltage 72. The reference voltage can be any suitable reference voltage, including, for example, ground, VCC / 2, etc.

[0058] Each of the memory structures 58 is uniquely addressed by a combination of one of the word lines and one of the digit lines.

[0059] The assemblies and structures discussed above can be used within integrated circuits (where the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate) and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and special application modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

[0060] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method now known or to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0061] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. The terms are considered synonymous in this disclosure. The term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may be used within this disclosure to provide linguistic variations to simplify the premises in the following claims, and are not intended to indicate any significant chemical or electrical differences.

[0062] The terms "electrically connected" and "electrically coupled" may both be used in this disclosure. The terms are considered synonymous. One term in some cases and the other term in other cases may be used within this disclosure to provide linguistic variations to simplify the premise basis within the following claims.

[0063] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The description provided herein and the appended claims are directed to any structure having the described relationships between the various features, regardless of whether the structure is in the specific orientation of the drawings or rotated relative to such orientation.

[0064] Unless otherwise specified, the cross-sectional views of the accompanying illustrations only show features within the plane of the cross-section and not material behind the plane of the cross-section in order to simplify the drawings.

[0065] When a structure is referred to as being "on," "adjacent," or "against" another structure, the structure may be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on," "directly adjacent to," or "directly against" another structure, there are no intervening structures. The terms "directly below," "directly over," and the like do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment.

[0066] Structures (eg, layers, materials, etc.) may be referred to as "vertically extending" to indicate that the structures extend generally upward from an underlying base (eg, substrate). Vertically extending structures may or may not extend generally orthogonally relative to the upper surface of the base.

[0067] Some embodiments include an integrated assembly having a semiconductor material having a more doped region adjacent to a less doped region. A two-dimensional material is located between the more doped region and a portion of the less doped region.

[0068] Some embodiments include an integrated assembly containing a semiconductor material, a metal-containing material above the semiconductor material, and a two-dimensional material between a portion of the semiconductor material and the metal-containing material.

[0069] Some embodiments include a transistor having a first source / drain region, a second source / drain region, a channel region between the first source / drain region and the second source / drain region, and a two-dimensional material between the channel region and the first source / drain region.

[0070] As specified, the subject matter disclosed herein has been described in language more or less specific as to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include example embodiments. Accordingly, the claims are to be given the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A transistor comprising: a first source / drain region; a second source / drain region; a channel region located between the first source / drain region and the second source / drain region; as well as A two-dimensional material is located between the channel region and the first source / drain region, the two-dimensional material comprising one or more materials selected from the group consisting of: carbon, boron, tin, bismuth, molybdenum, platinum, tungsten, and hafnium. 2 . The transistor of claim 1 , wherein the two-dimensional material comprises a stack comprising 1 to 10 individual layers. 3 . The transistor of claim 1 , wherein the two-dimensional material comprises a thickness in the range of 0.5 nm to 5 nm. The transistor according to claim 1 , wherein the first source / drain region directly abuts the two-dimensional material. 5 . The transistor of claim 1 , wherein the first source / drain region is spaced apart from the two-dimensional material. 6 . The transistor of claim 1 , wherein the two-dimensional material is a first two-dimensional material, and the transistor further comprises a second two-dimensional material between the second source / drain region and the channel region. The transistor of claim 6 , further comprising a third two-dimensional material in the channel region. 8 . The transistor of claim 1 , wherein the first source / drain region, the second source / drain region, and the channel region extend within a semiconductor material.

9. The transistor of claim 1, wherein the two-dimensional material further comprises one or more of germanium, silicon, and phosphorus.

10. The transistor of claim 1, wherein the two-dimensional material comprises molybdenum. The transistor according to claim 1 , wherein the two-dimensional material comprises molybdenum disulfide and / or molybdenum diselenide.

12. A memory structure comprising the transistor of claim 1 , the memory structure comprising a storage element coupled to one of the first source / drain region and the second source / drain region, and comprising a digit line coupled to the other of the first source / drain region and the second source / drain region.

13. A transistor comprising: a first source / drain region; a second source / drain region; a channel region located between the first source / drain region and the second source / drain region, wherein the first source / drain region, the second source / drain region and the channel region extend within the semiconductor material; as well as A two-dimensional material is located between the channel region and the first source / drain region, wherein the semiconductor material is a polycrystalline material. The transistor of claim 13 , wherein the semiconductor material comprises polysilicon.

15. The transistor of claim 13 , wherein the two-dimensional material is a first two-dimensional region in a first portion of a blocking region; wherein the blocking region further comprises a second portion separated from the first portion by an intervening region of semiconductor material; and wherein the second portion comprises an additional two-dimensional region.

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