Fin type field effect transistor device and preparation method thereof

Abstract

The embodiment of the invention provides a fin type field effect transistor device and a preparation method thereof, and relates to the technical field of semiconductors, and the fin type field effect transistor device comprises a first substrate, a device layer and a covering layer which are stacked in sequence; the device layer comprises a plurality of field effect transistors; the field effect transistor comprises a fin, and a source electrode, a first spacing layer, a grid electrode, a second spacing layer and a drain electrode which are sequentially arranged along the extension direction of the fin, and the source electrode and the drain electrode are respectively arranged at two ends of the fin and are respectively connected with the fin; the side surfaces, covered by the covering layer, of the fin, the source electrode, the grid electrode and the drain electrode are flush with one another.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a fin field effect transistor device and a method for preparing the same. Background Art

[0002] In the Fin Field-Effect Transistor (FinFET) architecture, the gate is a forked structure similar to a fish fin. This design can significantly shorten the gate length of the transistor, resulting in the widespread application of the FinFET architecture. Consequently, those skilled in the art are keen to promote the advancement of FinFET device technologies. Summary of the Invention

[0003] The embodiments of the present application provide a fin field effect transistor device and a method for manufacturing the same to solve the problem of how to improve the fin field effect transistor device.

[0004] In order to solve the above technical problems, this application is implemented as follows: In a first aspect, an embodiment of the present application provides a fin field-effect transistor device.

[0005] The fin field-effect transistor device provided in an embodiment of the present application includes: a first substrate, a device layer, and a covering layer stacked in sequence; the device layer includes a plurality of field-effect transistors; the field-effect transistor includes: a fin and a source, a first spacer layer, a gate, a second spacer layer, and a drain arranged in sequence along the extension direction of the fin, the source and the drain are respectively arranged at both ends of the fin and are respectively connected to the fin; the side surfaces of the fin, the source, the gate, and the drain covered by the covering layer are flush with each other.

[0006] In a second aspect, an embodiment of the present application provides a method for preparing a fin field effect transistor device.

[0007] The preparation method of the fin field-effect transistor device provided in an embodiment of the present application includes: forming a device layer on a second substrate, wherein the device layer includes a plurality of field-effect transistors, and the field-effect transistors include: a fin and a source, a first spacer layer, a gate, a second spacer layer and a drain arranged in sequence along the extension direction of the fin, the source and the drain are respectively arranged at two ends of the fin and respectively connected to the fin; bonding the first substrate and the device layer to fix the device layer to the first substrate; thinning the second substrate and retaining the device layer so that the side surfaces of the fin, the source, the gate and the drain are exposed to the outer surface of the device layer.

[0008] At least one of the above technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects: In an embodiment of the present application, the sides of the fin, source, gate and drain covered by the covering layer are flush with each other, so that the source, gate and drain interconnections of the field effect transistor can be simultaneously brought out, which simplifies the steps of the connection electrode lead-out process and reduces the difficulty and complexity of the subsequent metal interconnection process, thereby improving the chip yield.

[0009] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0011] Figure 1 A schematic diagram of a FinFET device provided in an embodiment of the present application, showing a situation where the second dielectric layer on the sides of the first and second spacer layers is in a transparent state, and the first dielectric layer on the top of the FinFET device is in a transparent state; Figure 2 A schematic diagram of a fin field effect transistor device provided in an embodiment of the present application, showing Figure 1 FIG. 1 is a diagram showing a fin field effect transistor device, wherein the first dielectric layer and the connection electrode are hidden. Figure 3 A top view of a fin field effect transistor device provided in an embodiment of the present application; Figure 4 for Figure 3 A cross-sectional view of the FinFET device along section AA shown in FIG. Figure 5 for Figure 3 A cross-sectional view of the FinFET device along section BB shown in FIG; Figure 6 A flow chart of a method for manufacturing a fin field effect transistor device provided in an embodiment of the present application; Figure 7 A flow chart of a method for forming a device layer on a second substrate provided in an embodiment of the present application; Figure 8 A flow chart of a method for forming a fin, a first spacer layer, a dummy gate layer, and a second spacer layer on a second substrate provided in an embodiment of the present application; Figure 9A schematic diagram of a second substrate including an ion implantation layer provided in an embodiment of the present application; Figure 10 A schematic diagram of a second substrate having fins formed thereon provided in an embodiment of the present application; Figure 11 A schematic diagram of a second substrate provided in an embodiment of the present application, on which a fin, an isolation structure, a third dielectric layer, and a dummy gate layer are formed; Figure 12 for Figure 11 A left view of the second substrate with fins, isolation structures, a third dielectric layer and a dummy gate layer formed thereon is shown in FIG; Figure 13 for Figure 12 A cross-sectional view taken along CC section of the second substrate on which a fin, an isolation structure, a third dielectric layer and a dummy gate layer are formed is shown; Figure 14 The embodiment of this application provides Figure 10 Schematic diagram of removing part of the third dielectric layer and the fin based on the second substrate on which the fin, the isolation structure, the third dielectric layer and the dummy gate layer are formed; Figure 15 for Figure 14 A top view of a second substrate having fins, an isolation structure, a third dielectric layer and a dummy gate layer formed thereon; Figure 16 for Figure 15 A cross-sectional view along the DD section of the second substrate on which a fin, an isolation structure, a third dielectric layer and a dummy gate layer are formed; Figure 17 A schematic diagram of a second substrate provided in an embodiment of the present application, on which a fin, an isolation structure, a third dielectric layer, a dummy gate layer, a source electrode, and a drain electrode are formed; Figure 18 for Figure 17 A front view of a second substrate having fins, an isolation structure, a third dielectric layer, a dummy gate layer, a source and a drain formed thereon; Figure 19 A schematic diagram of a second substrate provided in an embodiment of the present application, on which a fin, an isolation structure, a third dielectric layer, a dummy gate layer, a source, a drain, and a second dielectric layer are formed; Figure 20 The embodiment of this application provides Figure 19 Schematic diagram of removing the dummy gate layer to form a gate trench on the basis of the second substrate on which the fin, isolation structure, third dielectric layer, dummy gate layer, source, drain and second dielectric layer are formed; Figure 21 A schematic diagram of a second substrate provided in an embodiment of the present application, on which a fin, an isolation structure, a third dielectric layer, a source, a drain, a second dielectric layer, and a gate are formed; Figure 22 for Figure 21 A top view of a second substrate having fins, an isolation structure, a third dielectric layer, a source, a drain, a second dielectric layer and a gate formed thereon; Figure 23 for Figure 22 A cross-sectional view of the second substrate along the EE section on which a fin, an isolation structure, a third dielectric layer, a source, a drain, a second dielectric layer and a gate are formed; Figure 24 A schematic diagram of a first substrate and a second substrate with a device layer formed thereon provided for the implementation of the present application, which shows the situation before bonding the first substrate and the second substrate; Figure 25 A situation in which the device layers of a first substrate and a second substrate are in a bonding state is provided for the implementation of the present application; Figure 26 A schematic diagram of a first substrate and a device layer provided for implementation of this application; Figure 27 for Figure 26 A top view of the first substrate and device layer is shown in FIG.

[0012] Description of reference numerals: 1-Fin field effect transistor device; 10-first substrate; 11-oxide layer; 20a-second substrate; 20b-ion implantation layer; 20-device layer; 21-field effect transistor; 211-fin; 212-source; 213-first spacer layer; 214-gate; 215-second spacer layer; 216-drain; 217-dummy gate layer; 218-second dielectric layer; 219-gate trench; 2110-isolation structure; 2111-third dielectric layer; 30 - covering layer; 31 - first dielectric layer; 311 - through hole; 32 - connecting electrode. DETAILED DESCRIPTION

[0013] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the specific embodiments of this application and the corresponding drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0014] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0015] In addition, although the terms used in this application are selected from well-known and commonly used terms, some terms mentioned in the specification of this application may be selected by the applicant at his or her discretion, and their detailed meanings are explained in the relevant parts of the description of this article.

[0016] Furthermore, it is required that the application be understood not only by the actual terms used but also by the meanings connoted by each term.

[0017] The following describes in detail the technical solutions provided by various embodiments of the present application in conjunction with the accompanying drawings.

[0018] The present application provides a Fin Field-Effect Transistor (FinFET) device. Figures 1 to 5 The fin field effect transistor device 1 provided in an embodiment of the present application includes: a first substrate 10, a device layer 20 and a cover layer 30 stacked in sequence.

[0019] The device layer 20 includes a plurality of field effect transistors 21. For example, the field effect transistors 21 may be P-type metal oxide semiconductor field effect transistors (Positive Channel Metal Oxide Semiconductor, abbreviated as PMOS) or N-type metal oxide semiconductor field effect transistors (Negative Channel Metal Oxide Semiconductor, abbreviated as NMOS).

[0020] The field-effect transistor 21 includes a fin 211 and a source 212, a first spacer 213, a gate 214, a second spacer 215, and a drain 216, which are sequentially arranged along the extension direction of the fin 211. In other words, the field-effect transistor 21 includes the fin 211, the source 212, the first spacer 213, the gate 214, the second spacer 215, and the drain 216. The source 212, the first spacer 213, the gate 214, the second spacer 215, and the drain 216 are sequentially arranged along the extension direction of the fin 211.

[0021] The source 212 and the drain 216 are respectively provided at both ends of the fin 211 and are respectively connected to the fin 211. The sides of the fin 211, the source 212, the gate 214, and the drain 216 that are covered by the cover layer 30 are flush with each other. In other words, the sides of the fin 211, the source 212, the gate 214, and the drain 216 that are facing away from the first substrate 10 are flush with each other.

[0022] In this way, in an embodiment of the present application, the sides of the fin 211, source 212, gate 214 and drain 216 covered by the covering layer 30 are flush with each other, so that the source 212, gate 214 and drain 216 of the field effect transistor 21 can be interconnected and led out at the same time, which simplifies the steps of the connection electrode lead-out process and reduces the difficulty and complexity of the subsequent metal interconnection process, thereby improving the chip yield.

[0023] It should be noted here that in the related art, the bottom surface of the fin is integrally connected to the substrate, and the field effect transistor is prone to leakage. However, with the solution provided in the embodiment of the present application, the surface of the fin 211 facing away from the first substrate 10 is exposed on the outer surface of the device layer 20, and it is not easy to form a leakage channel during operation. Since the leakage channel directly affects the power consumption and operating frequency response of the fin field effect transistor device 1, the solution provided in the embodiment of the present application can reduce the power consumption of the fin field effect transistor device 1 and improve the operating frequency response of the fin field effect transistor device 1.

[0024] In some embodiments, the gate 214 has a groove 2141. The portion of the fin 211 between the first spacer layer 213 and the second spacer layer 215 is accommodated in the groove 2141. In other words, Figure 4 Taking the illustrated orientation as an example, the left side, bottom side, and right side of the fin 211 are respectively surrounded by the gate 214. With the solution provided in the embodiment of the present application, since the left side, bottom side, and right side of the fin 211 are respectively surrounded by the gate 214, the gate 214's ability to control the channel is improved, solving the leakage channel problem of the fin field-effect transistor device in the related art, further reducing the power consumption of the chip and improving the frequency response.

[0025] In some embodiments, the cover layer 30 includes a first dielectric layer 31 and a plurality of connection electrodes 32. A plurality of through-holes 311 are defined in the first dielectric layer 31 at locations opposite the source electrode 212, the gate electrode 214, and the drain electrode 216. A connection electrode 32 is defined in each through-hole 311, and each connection electrode 32 is connected to a corresponding source electrode 212, gate electrode 214, and drain electrode 216.

[0026] For example, a first dielectric layer 31 can be provided on the side of the fin field effect transistor device 1 facing away from the first substrate 10, and through holes 311 penetrating the first dielectric layer 31 can be provided at positions of the first dielectric layer 31 opposite to the source 212, the gate 214 and the drain 216, respectively. Then, a connecting electrode 32 is provided in each through hole 311, so that each connecting electrode 32 is connected to the corresponding source 212, the gate 214 and the drain 216, respectively, so as to simplify the steps of the connecting electrode lead-out process, reduce the difficulty and complexity of the subsequent metal interconnection process, and thus improve the chip yield.

[0027] The present invention provides a method for preparing a fin field effect transistor device, which is used to prepare any one of the fin field effect transistor devices provided in the present invention. Figure 6 The method for preparing a fin field effect transistor device provided in an embodiment of the present application includes: In step 410, a device layer is formed on a second substrate, wherein the device layer includes a plurality of field effect transistors, and the field effect transistors include: a fin and a source, a first spacer layer, a gate, a second spacer layer and a drain arranged in sequence along the extension direction of the fin, and the source and the drain are respectively arranged at both ends of the fin and are respectively connected to the fin.

[0028] Step 420 , bonding the first substrate and the device layer to securely connect the device layer to the first substrate.

[0029] Step 430 , thinning the second substrate, retaining the device layer, so that the side surfaces of the fin, source, gate, and drain are exposed to the outer surface of the device layer.

[0030] Combine Figures 21 to 24 In the embodiment of the present application, a device layer 20 may be formed on the second substrate 20a. The device layer 20 includes a plurality of field-effect transistors 21. The field-effect transistors 21 include a fin 211 and a source 212, a first spacer layer 213, a gate 214, a second spacer layer 215, and a drain 216 sequentially arranged along the extension direction of the fin 211. The source 212 and the drain 216 are respectively arranged at both ends of the fin 211 and are respectively connected to the fin 211.

[0031] Furthermore, the first substrate 10 and the device layer 20 are bonded to ensure that the device layer 20 is fixedly connected to the first substrate 10 .

[0032] Furthermore, the second substrate 20 a is thinned, and the device layer 20 is retained, so that the side surfaces of the fin 211 , the source 212 , the gate 214 and the drain 216 are exposed to the outer surface of the device layer 20 .

[0033] refer to Figure 7In some embodiments, in step 410, a device layer is formed on a second substrate, wherein the device layer includes a plurality of field effect transistors, and the field effect transistors include: Step 411 : forming a fin, a first spacer layer, a dummy gate layer, and a second spacer layer on a second substrate, wherein both ends of the fin along its own extension direction are exposed to outer surfaces of the first spacer layer and the second spacer layer, respectively.

[0034] In step 412 , a source is formed at one end of the fin along its own extension direction, and a drain is formed at the other end.

[0035] In step 413 , a second dielectric layer is disposed on a side of the first spacer layer facing away from the second spacer layer, and on a side of the second spacer layer facing away from the first spacer layer.

[0036] In step 414 , the dummy gate layer is removed to form a gate trench.

[0037] Step 415 , forming a gate in the gate trench.

[0038] refer to Figures 14 to 21 In some embodiments, the device layer 20 may be formed on the second substrate 20 a in the following manner.

[0039] A fin 211 , a first spacer 213 , a dummy gate layer 217 and a second spacer 215 are formed on the second substrate 20 a , wherein both ends of the fin 211 along its own extension direction are exposed to outer surfaces of the first spacer 213 and the second spacer 215 .

[0040] Furthermore, a source 212 is formed at one end of the fin 211 along its own extending direction, and a drain 216 is formed at the other end.

[0041] Furthermore, a second dielectric layer 218 is disposed on a side of the first spacer layer 213 facing away from the second spacer layer 215 , and on a side of the second spacer layer 215 facing away from the first spacer layer 213 , respectively.

[0042] Furthermore, the dummy gate layer 217 is removed to form a gate trench 219 .

[0043] Furthermore, a gate 214 is formed in the gate trench 219 .

[0044] refer to Figure 8 In some embodiments, step 411 of forming a fin, a first spacer layer, a dummy gate layer, and a second spacer layer on a second substrate, wherein both ends of the fin along its own extension direction are exposed to outer surfaces of the first spacer layer and the second spacer layer, respectively, includes: Step 4111 , forming fins on a second substrate.

[0045] Step 4112: forming an isolation structure between adjacent fins, wherein a top surface of the isolation structure is lower than a top surface of the fin.

[0046] Step 4113, depositing a third dielectric layer on the top surface of the second substrate.

[0047] Step 4114 , depositing a dummy gate layer on the third dielectric layer.

[0048] In step 4115 , a first spacer layer and a second spacer layer are respectively formed on two opposite sides of the dummy gate layer along the extending direction of the fin.

[0049] Step 4116 , removing portions of the third dielectric layer that are not covered by the first spacer layer, the dummy gate layer, and the second spacer layer.

[0050] In step 4117 , the top portion of the fin not covered by the first spacer layer, the dummy gate layer, and the second spacer layer is removed, so that the top surface of the fin is lower than the top surface of the isolation structure.

[0051] refer to Figures 9 to 14 In some embodiments, the fin 211 , the first spacer layer 213 , the dummy gate layer 217 and the second spacer layer 215 may be formed on the second substrate 20 a in the following manner.

[0052] Fins 211 are formed on the second substrate 20 a .

[0053] Furthermore, an isolation structure 2110 is formed between adjacent fins 211 , wherein a top surface of the isolation structure 2110 is lower than a top surface of the fin 211 ; Further, a third dielectric layer 2111 is deposited on the top surface of the second substrate 20a; Further, a dummy gate layer 217 is deposited on the third dielectric layer 2111 ; Furthermore, a first spacer layer 213 and a second spacer layer 215 are respectively formed on two opposite sides of the dummy gate layer 217 along the extending direction of the fin 211 ; Further, the portion of the third dielectric layer 2111 not covered by the first spacer layer 213 , the dummy gate layer 217 and the second spacer layer 215 is removed; Furthermore, the top portion of the fin 211 not covered by the first spacer layer 213 , the dummy gate layer 217 and the second spacer layer 215 is removed, so that the top surface of the fin 211 is lower than the top surface of the isolation structure 2110 .

[0054] In some embodiments, step 420, bonding the first substrate and the device layer to fix the device layer to the first substrate, includes: performing a thermal oxidation process on the surface of the first substrate to form an oxide layer on the surface of the first substrate; and bonding the side of the first substrate provided with the oxide layer to the device layer to fix the device layer to the oxide layer.

[0055] For example, refer to Figure 24 and Figure 25 A thermal oxidation process may be performed on the surface of the first substrate 10 to form an oxide layer 11 on the surface of the first substrate 10. Further, the side of the first substrate 10 provided with the oxide layer 11 is bonded to the device layer 20 to securely connect the device layer 20 to the oxide layer 11.

[0056] In some embodiments, before forming the device layer on the second substrate, the preparation method further includes: performing ion implantation into a target depth of the second substrate to form an ion implantation layer in the second substrate.

[0057] For example, refer to Figure 9 , ion implantation is performed into a target depth of the second substrate 20 a to form an ion implantation layer 20 b in the second substrate 20 a.

[0058] In some embodiments, step 430 thins the second substrate, retains the device layer, and exposes the sides of the fin, source, gate, and drain to the outer surface of the device layer, including: peeling the second substrate from the ion implantation layer; thinning the second substrate after the peeling process, retains the device layer, and exposes the sides of the fin, source, gate, and drain to the outer surface of the device layer.

[0059] For example, refer to Figures 25 to 27 The second substrate 20a can be peeled off from the ion implantation layer 20b. The second substrate 20a can then be thinned after the peeling process, leaving the device layer 20, so that the side surfaces of the fin 211, source 212, gate 214, and drain 216 are exposed on the outer surface of the device layer 20.

[0060] In this way, ion implantation layer 20b can be made into a brittle layer by implanting ions at a target depth of second substrate 20a, thereby facilitating a stripping process of a portion of second substrate 20a through ion implantation layer 20b in a subsequent process flow.

[0061] In some embodiments, after thinning the second substrate, the method for preparing a fin field effect transistor device further includes: setting a first dielectric layer on the side of the device layer so that the device layer is located between the first substrate and the first dielectric layer; forming a plurality of through holes at positions of the first dielectric layer opposite to the source, gate, and drain; and setting a connecting electrode in each through hole so that each connecting electrode is connected to the source, gate, and drain respectively.

[0062] For example, refer to Figures 1 to 5First, a first dielectric layer 31 is disposed on the side of the device layer 20, so that the device layer 20 is located between the first substrate 10 and the first dielectric layer 31. A plurality of through holes 311 are formed in the first dielectric layer 31 at locations opposite to the source electrode 212, the gate electrode 214, and the drain electrode 216. A connecting electrode 32 is disposed in each through hole 311, so that each connecting electrode 32 is connected to the source electrode 212, the gate electrode 214, and the drain electrode 216, respectively.

[0063] To facilitate those skilled in the art to better implement the solutions provided in the embodiments of the present application, more detailed examples are provided below for reference by those skilled in the art.

[0064] refer to Figure 9 In some embodiments, before forming the device layer 20 on the second substrate 20a, a silicon dioxide layer can be grown on the second substrate 20a by a thermal oxidation process, and hydrogen ions can be implanted into the second substrate 20a using an ion implanter to form an ion implantation layer 20b in the second substrate 20a, and the ion implantation layer 20b is used as a bonding separation layer.

[0065] The second substrate 20a is a semiconductor substrate. The second substrate 20a can be a P-type, N-type, or undoped substrate. The second substrate 20a can be made of Si, Ge, SiC, GaAs, GaP, InP, InAs, InSb; or SiGe, GaAsP, AlGaAs, AlInAs, GaInAs, GaInP, or GaInAsP. After forming the ion implantation layer 20b, the silicon dioxide layer can be removed.

[0066] refer to Figure 10 and Figure 11 Furthermore, after forming the ion implantation layer 20b in the second substrate 20a, fins 211 can be formed on the second substrate 20a. A plurality of fins 211 are arranged at intervals on the second substrate 20a. The widths of the fins 211 can be the same or different, and the intervals between the fins 211 can be the same or different. The fins 211 can be classified according to the requirements of the NMOS and PMOS manufacturing processes.

[0067] After the fins 211 are formed on the second substrate 20 a , an isolation structure 2110 may be formed between adjacent fins 211 . The isolation structure 2110 is located between adjacent fins 211 and covers the lower portion of the fins 211 .

[0068] It should be noted that, for example, Figure 10 Based on the second substrate 20a shown in FIG, a semiconductor process is performed to obtain Figure 11 The steps shown for the second substrate 20a include: In step 1, an insulating dielectric material is deposited on the sides and top of the fin 211 using high-density plasma chemical vapor deposition (HDP-CVD) or flowable chemical vapor deposition (FCVD), followed by an annealing process. The insulating dielectric material can be an oxide (e.g., SiO) or a nitride (e.g., SiN or other materials).

[0069] In step 2, a planarization process, such as a chemical-mechanical polishing (CMP) process, is used to remove the insulating dielectric material that exceeds the upper end of the fin 211 .

[0070] In step three, an etch-back process is used to remove the insulating dielectric material covering the periphery of the upper end of the fin 211, so that the remaining insulating dielectric material forms an isolation structure 2110. Isolation structure 2110 is commonly referred to as shallow trench isolation (STI). Removal of the insulating dielectric material covering the periphery of the upper end of the fin 211 can be performed by wet etching, dry etching, or a combination of wet and dry etching.

[0071] In step 4, a dielectric material is deposited on the fin 211 by chemical vapor deposition (CVD) or atomic layer deposition (ALD) to form a third dielectric layer 2111 .

[0072] In step 5, a dummy gate material is deposited on the third dielectric layer 2111 using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). The dummy gate material can be amorphous silicon, polycrystalline silicon, or polycrystalline silicon germanium. After the dummy gate material is deposited, a planarization process can be performed.

[0073] Step six: forming a patterned dummy gate layer 217 and a third dielectric layer 2111 through a dummy gate patterning process.

[0074] Furthermore, after forming the patterned dummy gate layer 217 and the third dielectric layer 2111, a suitable spacer layer deposition and etching process can be used to form a first spacer layer 213 and a second spacer layer 215 on both sides of the dummy gate layer 217. For example, the first spacer layer 213 and the second spacer layer 215 can be made of materials such as SiO, SiN, SICN, SiOCN, SiC, SiOC, or SiON.

[0075] Furthermore, after forming the first spacer 213 and the second spacer 215 on both sides of the dummy gate layer 217 , a source 212 may be formed at one end of the fin 211 along its own extension direction, and a drain 216 may be formed at the other end.

[0076] It should be noted that, illustratively, the following method can be used: on the basis of forming the first spacer layer 213 and the second spacer layer 215 on both sides of the dummy gate layer 217, and then processing the dummy gate layer 217 through a semiconductor process to obtain the following: Figure 21 A second substrate 20a is shown.

[0077] In step 1, the top portion of the fin 211 located on the side of the first spacer layer 213 facing away from the second spacer layer 215 and the top portion of the fin 211 located on the side of the second spacer layer 215 facing away from the first spacer layer 213 are removed, so that the top surface of the fin 211 in this portion is slightly lower than the top surface of the isolation structure 2110. The removal method may be etching.

[0078] In step 2, a selective epitaxial process is used to grow source / drain strained materials on the etched fin 211 near the first spacer layer 213 and the second spacer layer 215 to form the source 212 and the drain 216. For P-type metal oxide semiconductor field effect transistors, the grown strained materials include but are not limited to: SiGe, SiGeB, Ge, InSb, GaSb or InGaSb. For N-type metal oxide semiconductor field effect transistors, the grown strained materials include but are not limited to: SiC, SiP, SiCP, InP, GaAs, AlAs, InAs, InAlAs, InGaAs or SiC / SiP. In addition, the strained layer can also be prepared by ion implantation of N-type or P-type materials.

[0079] In step three, a contact etch stop layer (CESL) is formed on the upper portion of the second substrate 20a, thereby forming a second dielectric layer 218. For example, the CESL can be deposited on the upper surface of the second substrate 20a using processes such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or atomic layer deposition. For example, the CESL covers the surfaces of the source 212, drain 216, isolation structure 2110, and fin 211 that are exposed outside the second substrate 20a. For example, the CESL can be made of SiN, SiC, SiOC, SiON, SiCN, SiOCN, or a combination thereof.

[0080] Furthermore, a second dielectric layer 218 may be deposited on the contact etch stop layer by using processes such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, fluid chemical vapor deposition, and spin coating. For example, the second dielectric layer 218 may be made of SiO, SiOC, silicon glass, BPSG, FSG, PSG, BSG, or a low-K material, wherein the low-K material may be BCB, FLARE, SILK, HSQ, or SiOF.

[0081] In step 4, a planarization process, such as a chemical mechanical polishing process, is used to remove the contact etch barrier layer and the second dielectric layer 218 deposited above the dummy gate layer 217 structure, thereby exposing the dummy gate layer 217 .

[0082] It should be noted that, for example, the following methods can be used to Figure 19 The second substrate 20a is processed by semiconductor process to obtain Figure 21 A second substrate 20a is shown.

[0083] Step 1: Use dry etching or dry and / or wet etching to remove the dummy gate layer 217 and form a gate trench 219. Figure 20 The gate trench 219 is divided into a left gate trench and a right gate trench. For example, the left gate trench is used to form the gate of a P-type metal oxide semiconductor field effect transistor; the right gate trench is used to form the gate of an N-type metal oxide semiconductor field effect transistor. Figure 20 Taking the shown orientation as an example, the trenches in the region where the two fins 211 (not marked) are located in the upper left corner are left gate trenches, and the trenches in the region where the two fins 211 (not marked) are located in the lower right corner are right gate trenches.

[0084] In step 2, a gate material layer is formed in gate trench 219 using processes such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition (PVD), and atomic layer deposition. The gate material layer generally consists of a dielectric layer, a work function layer, and a metal electrode layer. Gate materials for P-type work functions generally include TiN, WN, TaN, and conductive metal oxides. Gate materials for N-type work functions include Ta, TiAl, TiAlN, TaC, TaCN, TaSiN, TiSiN, and conductive metal oxides.

[0085] Step three: planarize and remove the excess gate material layer, and the remaining gate material layer forms the gate 214.

[0086] In the embodiment of the present application, the device layer 20 and the first substrate 10 may be bonded in the following manner.

[0087] Step 1: forming a silicon oxide layer on the surface of the first substrate 10 by a thermal oxidation process.

[0088] Step 2: Bonding and curing the device layer 20 and the first substrate 10.

[0089] In the embodiment of the present application, the second substrate 20a may be thinned in the following manner.

[0090] In step 1, the side of the second substrate 20 a facing away from the first substrate 10 is separated and removed along the ion implantation layer 20 b (bonding separation layer) by heat treatment.

[0091] In step 2, a planarization process is performed, in which a chemical mechanical polishing process is used to thin the side of the second substrate 20 a facing away from the first substrate 10 until the fin 211 , the source 212 , the gate 214 and the drain 216 are exposed.

[0092] In some embodiments, the connection electrode 32 may be formed as follows.

[0093] In step 1, a first dielectric layer 31 is deposited on the surface of the first substrate 10. The material may be SiO, SiN, SiOC, silicon glass, BPSG, FSG, PSG, BSG or a low-K material. The low-K material may be BCB, FLARE, SILK, HSQ or SiOF.

[0094] Step 2: Prepare through holes 311 on the first dielectric layer 31 by dry etching process according to the requirements of metal patterned interconnection; Step 3: depositing and filling corresponding electrode materials in the through hole 311 in sequence. For example, the electrode materials include a metal adhesion layer, a barrier layer, and a metal layer. Then, a planarization process is performed to expose the first dielectric layer 31, thereby removing excess metal materials and realizing the electrode extraction of the source / drain and gate. Step 4: metal interconnection process, designing the back-end multi-layer metal interconnection process according to the functional requirements of the FinFET device 1 .

[0095] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus.

[0096] Although the embodiments of the present application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the embodiments of the present application, and the scope of the embodiments of the present application is defined by the appended claims and their equivalents.

Claims

1. A fin field effect transistor device, characterized in that: include: A first substrate (10), a device layer (20), and a cover layer (30) stacked in sequence; The device layer (20) includes a plurality of field effect transistors (21); The field effect transistor (21) comprises: a fin (211), and a source (212), a first spacer layer (213), a gate (214), a second spacer layer (215), and a drain (216) sequentially arranged along an extension direction of the fin (211), wherein the source (212) and the drain (216) are respectively arranged at two ends of the fin (211) and are respectively connected to the fin (211); Side surfaces of the fin (211), the source (212), the gate (214), and the drain (216) that are covered by the covering layer (30) are flush with each other.

2. The fin field effect transistor device according to claim 1, wherein: The gate (214) has a groove (2141), and a portion of the fin (211) located between the first spacer layer (213) and the second spacer layer (215) is accommodated in the groove (2141).

3. The fin field effect transistor device according to claim 1, wherein: The covering layer (30) includes a first dielectric layer (31) and a plurality of connecting electrodes (32); a plurality of through holes (311) are respectively provided at locations of the first dielectric layer (31) that are opposite to the source electrode (212), the gate electrode (214), and the drain electrode (216); a connecting electrode (32) is provided in each of the through holes (311); and each of the connecting electrodes (32) is respectively connected to the source electrode (212), the gate electrode (214), and the drain electrode (216).

4. A method for preparing a fin field effect transistor device, characterized in that: The method for preparing the fin field effect transistor device comprises: A device layer (20) is formed on a second substrate (20a), wherein the device layer (20) includes a plurality of field effect transistors (21), and the field effect transistors (21) include: a fin (211), and a source (212), a first spacer layer (213), a gate (214), a second spacer layer (215), and a drain (216) sequentially arranged along an extension direction of the fin (211), the source (212) and the drain (216) being respectively arranged at two ends of the fin (211) and connected to the fin (211); Bonding the first substrate (10) and the device layer (20) to ensure that the device layer (20) is fixedly connected to the first substrate (10); The second substrate (20a) is thinned, the device layer (20) is retained, and the side surfaces of the fin (211), the source (212), the gate (214), and the drain (216) are exposed to the outer surface of the device layer (20).

5. The method for preparing a fin field effect transistor device according to claim 4, wherein: The device layer (20) is formed on the second substrate (20a), comprising: forming the fin (211), the first spacer layer (213), the dummy gate layer (217), and the second spacer layer (215) on the second substrate (20a), wherein two ends of the fin (211) along its own extension direction are exposed to the outer surfaces of the first spacer layer (213) and the second spacer layer (215), respectively; A source electrode (212) is formed at one end of the fin (211) along its own extension direction, and a drain electrode (216) is formed at the other end; A second dielectric layer (218) is respectively provided on a side of the first spacer layer (213) facing away from the second spacer layer (215), and a side of the second spacer layer (215) facing away from the first spacer layer (213); removing the dummy gate layer (217) to form a gate trench (219); A gate (214) is formed in the gate trench (219).

6. The method for preparing a fin field effect transistor device according to claim 5, wherein: The step of forming the fin (211), the first spacer layer (213), the dummy gate layer (217), and the second spacer layer (215) on the second substrate (20a) comprises: forming a fin (211) on the second substrate (20a); forming an isolation structure (2110) between adjacent fins (211), wherein a top surface of the isolation structure (2110) is lower than a top surface of the fin (211); depositing a third dielectric layer (2111) on the top surface of the second substrate (20a); Depositing a pseudo gate layer (217) on the third dielectric layer (2111); forming a first spacer layer (213) and a second spacer layer (215) on two opposite sides of the pseudo gate layer (217) along the extension direction of the fin (211); removing portions of the third dielectric layer (2111) that are not covered by the first spacer layer (213), the dummy gate layer (217), and the second spacer layer (215); The top portion of the fin (211) not covered by the first spacer layer (213), the pseudo gate layer (217) and the second spacer layer (215) is removed, so that the top surface of the fin (211) is lower than the top surface of the isolation structure (2110).

7. The method for preparing a fin field effect transistor device according to claim 4, wherein: The step of bonding the first substrate (10) and the device layer (20) to securely connect the device layer (20) to the first substrate (10) comprises: Performing a thermal oxidation process on the surface of the first substrate (10) to form an oxide layer (11) on the surface of the first substrate (10); The side of the first substrate (10) provided with the oxide layer (11) and the device layer (20) are bonded to ensure that the device layer (20) is fixedly connected to the oxide layer (11).

8. The method for preparing a fin field effect transistor device according to claim 4, wherein: Before forming the device layer (20) on the second substrate (20a), the preparation method further comprises: Ion implantation is performed at a target depth of the second substrate (20a) to form an ion implantation layer (20b) in the second substrate (20a).

9. The method for preparing a fin field effect transistor device according to claim 8, wherein: The thinning of the second substrate (20a) to retain the device layer (20) so that the side surfaces of the fin (211), the source (212), the gate (214), and the drain (216) are all exposed to the outer surface of the device layer (20) comprises: peeling off the second substrate (20a) from the ion implantation layer (20b); The second substrate (20a) after the stripping process is thinned, and the device layer (20) is retained, so that the side surfaces of the fin (211), the source (212), the gate (214), and the drain (216) are all exposed to the outer surface of the device layer (20).

10. The method for preparing a fin field effect transistor device according to claim 4, wherein: After thinning the second substrate (20a), the method for preparing the fin field effect transistor device further comprises: Disposing a first dielectric layer (31) on a side of the device layer (20) so that the device layer (20) is located between the first substrate (10) and the first dielectric layer (31); A plurality of through holes (311) are formed in portions of the first dielectric layer (31) that are opposite to the source electrode (212), the gate electrode (214), and the drain electrode (216); A connecting electrode (32) is provided in each through hole (311), so that each connecting electrode (32) is correspondingly connected to the source electrode (212), the gate electrode (214), and the drain electrode (216).

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