Solid-state imaging device, preparation method thereof and electronic equipment
By increasing the spacing between the sidewall isolation layers of the source/drain and the gate in solid-state imaging devices and using selective epitaxial growth and in-situ doping to prepare the source and drain extension regions, the GIDL problem was solved and the imaging performance and operating speed were improved.
Patent Information
- Application Number
- CN202410235229.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-29
- Publication Date
- 2025-09-05
AI Technical Summary
Gate-induced drain leakage (GIDL) is a problem in existing solid-state imaging devices, leading to performance degradation such as increased dark current and white defects.
By increasing the distance between the sidewall isolation layers at both ends of the source/drain and the gate, and combining the selective epitaxial growth method and in-situ doping method to prepare the source and drain, a regularly shaped source and drain extension region is formed, which reduces the generation of gate-drain overlap, and reduces the overlap capacitance and GIDL current.
It effectively reduces the GIDL current, improves the imaging performance of the solid-state imaging device, avoids the short channel effect, and increases the device operating speed.
Smart Images
Figure CN120603345A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of image sensing, and more specifically, to a solid-state imaging device, a preparation method thereof, and an electronic device. Background Art
[0002] A solid-state imaging device is a device used for optical imaging, converting optical images into electrical signals for storage, transmission, or display. Unlike vacuum imaging devices, which are encapsulated in a vacuum glass shell, solid-state imaging devices can perform optical image conversion, information storage, and signal output on their own. A CMOS image sensor (CIS) is a typical solid-state imaging device that integrates a metal-oxide semiconductor field-effect transistor (MOSFET) integrated circuit, including an array of image-sensitive cells.
[0003] However, gate-induced drain leakage (GIDL) exists in MOSFETs, which degrades the performance of solid-state imaging devices, such as increased dark current and white defects. Summary of the Invention
[0004] The present application provides a solid-state imaging device, a preparation method thereof, and an electronic device, which can reduce the GIDL current in the solid-state imaging device and improve the imaging performance of the solid-state imaging device.
[0005] In a first aspect, an embodiment of the present application provides a solid-state imaging device, which includes a transistor, wherein the transistor includes: a base material layer; a gate, which is located on the base material layer; a sidewall spacer, which is located on the base material layer, the sidewall spacer is adjacent to the gate and is located on both sides of the gate; a source and a drain, which are located on the base material layer and are respectively located on both sides of the sidewall spacer, the tops of the source and the drain are higher than the base material layer, and there is a gap between the side of the source close to the sidewall spacer and the sidewall spacer, and there is a gap between the side of the drain close to the sidewall spacer and the sidewall spacer.
[0006] According to the solid-state imaging device provided by the embodiment of the present application, the spacing between the source / drain and the sidewall isolation layers at both ends of the gate is increased, thereby reducing the possibility of the gate-drain overlap region of the transistor in the solid-state imaging device, and reducing the overlap capacitance and GIDL current.
[0007] In combination with the first aspect, in certain implementations of the first aspect, the distance between the side of the source electrode close to the sidewall isolation layer and the sidewall isolation layer, and the distance between the side of the drain electrode close to the sidewall isolation layer and the sidewall isolation layer are a first value, and the height of the portion of the source electrode and the drain electrode that is higher than the base material layer is a second value, and the second value is not greater than the first value.
[0008] In combination with the first aspect, in certain implementations of the first aspect, a second intermediate material layer is further included between the base material layer and the gate, and the tops of the source and the drain are higher than the second intermediate material layer.
[0009] In combination with the first aspect, in certain implementations of the first aspect, the spacing between the side of the source electrode close to the sidewall isolation layer and the sidewall isolation layer, and the spacing between the side of the drain electrode close to the sidewall isolation layer and the sidewall isolation layer are first values, and the height of the portion of the source electrode and the drain electrode that is higher than the second intermediate material layer is a third value, and the third value is not greater than the first value.
[0010] In the embodiment of the present application, the thickness of the first intermediate material layer can be controlled to control the distance between the source / drain structure and the sidewall spacer, and the height of the exposed portion of the source / drain structure can be controlled.
[0011] In combination with the first aspect, in certain implementations of the first aspect, the base material layer includes a first lightly doped drain structure and a second lightly doped drain structure, and the first lightly doped drain structure and the second lightly doped drain structure are respectively located on both sides of the gate and respectively located below the source and the drain.
[0012] According to the technical solution provided in the embodiment of the present application, the LDD structure is to set a low-doped drain region near the drain in the channel, or a shallow junction source / drain structure, so that the low-doped drain region also bears part of the voltage to suppress the short channel effect.
[0013] In combination with the first aspect, in certain implementations of the first aspect, the source and the drain are prepared by epitaxial growth and in-situ doping.
[0014] According to the technical solution provided in the embodiment of the present application, a regularly shaped source and drain extension region is formed, thereby avoiding the short channel effect.
[0015] In a second aspect, an embodiment of the present application provides an electronic device comprising the solid-state imaging device in the first aspect.
[0016] Optionally, the electronic device may be a camera, a digital camera, a video camera, a smart phone, a game console, a tablet, a wearable camera, a medical device (such as an endoscope), a beauty device, etc.
[0017] In a third aspect, an embodiment of the present application provides a method for preparing a solid-state imaging device, comprising: preparing a first transistor element, the first transistor element comprising a base material layer, a gate and a sidewall isolation layer, the gate and the sidewall isolation layer being located on the base material layer, the sidewall isolation layer being adjacent to the gate and being located on both sides of the gate; depositing a first intermediate material layer on the first transistor element, the first intermediate material layer comprising a first portion and a second portion, the first portion being located on an area of the base material layer not covered by the gate and the sidewall isolation layer, and the second portion being located on the gate and the sidewall material; processing a first trench and a second trench in the first portion, the first trench and the second trench being located on both sides of the second portion, and the bottoms of the first trench and the second trench being located on the base material layer; preparing a source and a drain in the first trench and the second trench, respectively, the tops of the source and the drain being higher than the base material layer; removing the first intermediate material layer to obtain a transistor in the solid-state imaging device.
[0018] According to the technical solution provided in the embodiment of the present application, by adding the step of depositing a first intermediate material layer in the processing process of the transistor, the spacing between the source / drain and the sidewall isolation layer at both ends of the gate is increased, thereby reducing the possibility of the generation of a gate-drain overlap region, and reducing the overlap capacitance and GIDL current.
[0019] In combination with the third aspect, in certain implementations of the third aspect, preparing the first transistor element includes: preparing the gate on the base material layer; and preparing the sidewall isolation layer on both sides of the gate.
[0020] In combination with the third aspect, in certain implementations of the third aspect, preparing the first transistor element includes: depositing a second intermediate material layer on the base material layer; preparing the gate on the second intermediate material layer; and preparing the sidewall isolation layer on both sides of the gate.
[0021] In combination with the third aspect, in certain implementations of the third aspect, preparing the source and the drain in the first trench and the second trench respectively includes: preparing the source and the drain on the first trench and the second trench respectively by epitaxial growth and in-situ doping.
[0022] According to the technical solution provided in the embodiment of the present application, a regularly shaped source and drain extension region is formed, thereby avoiding the short channel effect.
[0023] In combination with the third aspect, in certain implementations of the third aspect, after preparing the source and the drain, the method further includes: activating ions in the source and the drain by a heat treatment method.
[0024] In combination with the third aspect, in certain implementations of the third aspect, the process of the in-situ doping method is reverse doping.
[0025] According to the technical solution provided in the embodiment of the present application, the lateral diffusion of the source / drain in the prior art can be reduced, the series resistance and contact resistance between the source and drain can be reduced, and the operating speed of the device can be improved.
[0026] In combination with the third aspect, in certain implementations of the third aspect, the method also includes: preparing the first lightly doped drain structure and the second lightly doped drain structure by an epitaxial growth method, and the first lightly doped drain structure and the second lightly doped drain structure are respectively located on both sides of the gate and respectively located below the source and the drain.
[0027] According to the technical solution provided in the embodiment of the present application, the LDD structure is to set a low-doped drain region near the drain in the channel, or a shallow junction source / drain structure, so that the low-doped drain region also bears part of the voltage to suppress the short channel effect.
[0028] In combination with the third aspect, in certain implementations of the third aspect, processing the first groove and the second groove in the first part includes: using the second part as a mask, based on the first boundary and the second boundary connecting the first part and the second part, etching the first part on both sides of the second part to obtain the first groove and the second groove. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 This is a schematic structural block diagram of a solid-state imaging system provided in an embodiment of the present application.
[0030] Figure 2 Schematic diagram of a pixel structure of a solid-state imaging device provided in an embodiment of the present application.
[0031] Figure 3 This is a schematic diagram of a GIDL effect provided in an embodiment of the present application.
[0032] Figure 4 This is a schematic diagram of a current transistor structure provided in an embodiment of the present application.
[0033] Figure 5 This is a schematic diagram of a transistor processing technology provided in an embodiment of the present application.
[0034] Figure 6 This is a schematic diagram of another transistor processing technology provided in an embodiment of the present application.
[0035] Figure 7 This is a schematic diagram of another transistor processing technology provided in an embodiment of the present application.
[0036] Figure 8 This is a schematic diagram of another transistor processing technology provided in an embodiment of the present application.
[0037] Figure 9 This is a schematic diagram of a transistor structure provided in an embodiment of the present application. DETAILED DESCRIPTION
[0038] The technical solution in this application will be described below with reference to the accompanying drawings.
[0039] In the embodiments of this application, words such as "exemplary" and "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of the word "exemplary" is intended to present concepts in a concrete manner.
[0040] The business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field will know that with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.
[0041] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.
[0042] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: including the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.
[0043] Before introducing the embodiments, the terms involved in this application are described in detail.
[0044] 1. Solid-state imaging devices
[0045] A solid-state imaging device is a device used for optical imaging, converting optical images into electrical signals for storage, transmission, or display. Unlike vacuum imaging devices, solid-state imaging devices do not require a vacuum glass enclosure, a target for photoelectric image conversion, or electron beam scanning to output image signals. Solid-state imaging devices can inherently perform optical image conversion, information storage, and sequentially output video or image signals.
[0046] Common solid-state imaging devices include charge-coupled devices (CCDs) and complementary metal oxide semiconductor (CMOS) image sensors, which are widely used in various imaging devices, including digital cameras, video cameras, and mobile phone cameras. Photoelectric conversion is one of the core functions of solid-state imaging devices. When light strikes the device surface, photons excite electrons, causing them to transition to the conduction band energy level, forming a carrier current. This process converts the light signal into an electrical signal. After the signal is read out, the solid-state imaging device converts the charge signal into a voltage signal and amplifies it. In a CCD sensor, charge is transferred through the serial transmission structure of the charge-coupled device and then amplified by an amplifier circuit. In a CMOS sensor, each pixel has its own amplifier circuit. The charge is converted into a current signal by the photosensitive device, which is then converted into a voltage signal by the amplifier circuit for output.
[0047] The solid-state imaging device in the embodiments of the present application can be used in imaging systems, and can also be used in various electronic devices that include imaging systems, such as cameras, digital cameras, video cameras, smart phones, game consoles, tablets, wearable cameras, medical devices (such as endoscopes), beauty equipment, etc.
[0048] For ease of understanding, Figure 1 is a schematic structural block diagram of the imaging system 100 . Figure 1 The imaging system 100 includes a pixel array 110, a control circuit 120, a readout circuit 130, and a signal processing circuit 140. The pixel array 110 includes a plurality of pixels arranged in an array on an upper layer of a substrate. The embodiments of the present application do not limit the specific material of the substrate. The substrate may include a semiconductor material such as silicon or germanium. Alternatively, the substrate may include at least one or more photosensitive materials, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium gallium arsenide, indium phosphide, gallium in arsenide, indium antimonide, or a semiconductor-on-insulator. In a front-side illumination (FSI) imaging system, the pixel array 110 is directly connected to the substrate. In a back-side illumination (BSI) imaging system, a first metal wiring layer is provided between the pixel array 110 and the substrate. The first metal wiring layer includes at least one metal structure, which may be a metal wire or a metal block. The first metal wiring layer may also include an insulating dielectric material, and the embodiments of the present application do not limit the specific type of the dielectric material.
[0049] like Figure 1 As shown, pixel array 110 includes Ry rows and Cx columns of pixels, with each row including Cx pixels and each column including Ry pixels. Pixel array 110 is used to obtain image data of an object to be photographed. Control circuit 120 is used to control the pixel array, for example, by generating a shutter signal, thereby causing pixel array 110 to generate image data. Readout circuit 130 is used to read image data from pixel array 110. Signal processing circuit 140 is used to process the image data read by readout circuit 130.
[0050] Figure 2 2 is a schematic circuit diagram of a pixel structure 200 of a solid-state imaging device. Figure 2 The solid-state imaging device 200 includes a plurality of pixels, wherein one pixel includes at least one photodiode (PD) and at least one transfer gate device (TX).
[0051] Among them, PD converts electromagnetic waves into electric charges. The charges are selectively transferred to the floating diffusion (FD) via TX. FD is connected to the gate of the amplifier (amplifier device, AMP), and the output signal (voltage output, Vout) is transmitted to the signal line via the row select transistor (select device, SEL). The current source is connected between SEL and ground. Therefore, if the gates of TX and SEL are turned on, an output signal corresponding to the electrical signal from the PD is obtained on the signal line. The reset transistor (reset device, RST) selectively resets the charge accumulated in the FD. A dual conversion gain device (DCG) can be connected between RST and FD to achieve a high dynamic range by combining two types of gain. AVSS1 can be a ground voltage or a negative voltage ranging from -5.0 volts (volt, V) to 0V.
[0052] In some embodiments, the charge-to-voltage conversion is performed by an AMP using a source follower transistor (SF) with a gain equal to or less than 1. Alternatively, the charge-to-voltage conversion is performed by an AMP with a gain greater than 1, for example, in a differential amplification mode.
[0053] In some embodiments, RST, DCG, SEL, and AMP may be shared by at least two photodiodes.
[0054] In some embodiments, there may be more than two Vouts, and the electrical signals generated by at least two rows of pixels are read simultaneously.
[0055] In some embodiments, at least one of RST, DCG, AMP, SEL, and TX may be a positive channel metal oxide semiconductor (PMOS).
[0056] In some embodiments, AVDD1 and AVDD2 are the same. Alternatively, AVSS1 and AVSS2 are the same. AVDD1 and AVDD2 are positive analog power supplies used for power supply.
[0057] 2. GIDL
[0058] Gate-induced drain leakage (GIDL) is the primary off-state leakage mechanism in metal-oxide semiconductor field-effect transistors (MOSFETs), severely impacting device reliability. When the MOSFET gate is off (negative voltage applied to the N-type MOS gate and positive voltage applied to the P-type MOS gate) and the drain is connected to a voltage (positive voltage applied to the N-type MOS drain and negative voltage applied to the P-type MOS drain), the energy bands near the interface where the drain impurity diffusion layer overlaps with the gate (i.e., the gate-drain overlap region) undergo strong band bending, forming an inversion layer on the surface. The depletion layer becomes extremely narrow, allowing band-to-band tunneling (BTBT) between conduction band electrons and valence band holes, leading to drain leakage current. This leakage current determines the lower limit of the gate oxide thickness. As device dimensions continue to shrink, the lateral electric field within the device increases, increasing the probability of increased off-state leakage due to hot carrier effects. Figure 3 A schematic diagram of GIDL is shown, where Figure 3 (a) in FIG. 4 illustrates the location of the gate-drain overlap region.
[0059] exist Figure 2 The solid-state imaging component shown includes transistors such as TX, RST, and DCG, so these transistors may also be subject to the GIDL effect. Specifically, when the TX is in the off state, a negative bias voltage is usually applied to suppress dark current. However, the high voltage difference between the TX, RST, and DCG and the FD can cause the GIDL effect, that is, the generation of GIDL current, which in turn causes dark current and white defects such as dots or clusters in the FD area. Figure 2 The dotted boxes in the figure show the gate-drain overlap regions of transistors such as TX, RST, and DCG. That is, the gate-drain overlap regions of the above transistors may contain GIDL current, which ultimately affects the performance of the solid-state imaging device, such as causing increased dark current and white defects.
[0060] The magnitude of the GIDL current can be obtained according to the following formula:
[0061]
[0062] Among them, I D is the GIDL current, A and B are constants, E S is the maximum electric field strength, V DG is the voltage difference between the gate and drain, T OX is the gate oxide thickness in the gate-drain overlap region, and the constant 1.2 is the surface potential required to ensure BTBT, i.e., the amount of energy band bending. Figure 3 (b) shows the maximum electric field strength E S The area where it is located, that is, the drain surface covered by the gate edge.
[0063] As can be seen from the above formula, the magnitude of the GIDL current is related to the maximum electric field strength. Therefore, the following methods can be used to reduce the maximum electric field strength and thus the GIDL current: ① Use a lightly doped drain (LDD) structure; ② Reduce the overlap capacitance between the gate and drain; ③ Use an elevated source-drain structure.
[0064] It is worth noting that both sides of the gate can include Figure 3 The sidewall spacers shown may have an appropriate width. The sidewall spacers may be made of any appropriate material, such as silicon nitride. The sidewall spacers may serve as a mask for processing the raised source-drain structure to increase the distance between the source and drain and reduce the short channel effect caused by lateral diffusion during source-drain doping. In addition, in the embodiments of the present application, the names of the gate region, source region, and drain region may also be gate region, source region, and drain region, etc., and the present application does not limit the naming in the transistor.
[0065] In the embodiments of the present application, Figure 3 The base material layer shown may be disposed on a substrate at the bottom of the solid-state imaging device. The base material layer may include a semiconductor material such as silicon or germanium. Alternatively, the substrate may include at least one or more photosensitive materials, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium gallium arsenide, indium phosphide, gallium in arsenide, indium antimonide, or a semiconductor-on-insulator.
[0066] In the embodiment of the present application, a gate oxide layer (not shown) may be further included between the gate and the base material layer. Figure 3 (shown in Figure 2) to isolate the gate electrode from the base material layer, thereby preventing charge and current leakage. The gate oxide layer can be composed of any suitable dielectric material, such as silicon dioxide, silicon oxynitride, silicon nitride, etc. In other embodiments of the present application, the gate oxide layer can also include a high-k dielectric material such as hafnium oxide, hafnium zirconium oxide, etc., thereby achieving lower leakage current compared to traditional dielectric materials.
[0067] 3. LDD structure, elevated source-drain structure
[0068] Figure 4 FIG. 4 shows a transistor based on an LDD structure and an elevated source-drain structure. Figure 4As shown in (a) of FIG, the LDD structure is to set a low-doped drain region near the drain in the channel, or a shallow junction source / drain structure, so that the low-doped drain region also bears part of the voltage to suppress the short channel effect; Figure 4 As shown in (a) of Figure 1, a selective epitaxial growth (SEG) process can be used to form two sidewall spacers on either side of the gate and two elevated source / drain extension junctions. This alleviates the short channel effect, reduces the surface resistance of the source / drain and gate, and the maximum surface electric field strength, ultimately reducing the magnitude of the GIDL current. Furthermore, the selective epitaxial growth process can also reduce the overlap capacitance between the gate and drain.
[0069] Currently, after epitaxial growth is used to obtain an elevated source / drain structure, ion implantation is usually used to dope phosphorus, boron, or other materials to a specific depth into the source / drain structure. Heat treatment methods such as laser annealing are then used to activate the dopant ions and cause a specific degree of doping diffusion of the dopant.
[0070] However, if Figure 4 As shown in (b) of FIG, the edge portion of the epitaxially grown source / drain region at this stage will have a facet, resulting in the thickness of the edge portion being smaller than the other portion of the source / drain region. Figure 4 As shown in the shaded portion of (b) used to describe the dopant, when the ion implantation method is used, the depth of the dopant in the source / drain region is not the same, or in other words, the edge region has a smaller thickness, resulting in a deeper depth of the dopant in the edge region. Figure 4 As shown in (c), after the heat treatment method is used, the dopants at different depths will undergo a specific degree of doping diffusion, and the doping diffusion of the deeper dopants in the edge area will cause the source / drain area to form a protrusion-like structure, which will shorten the distance in the channel area and thus induce a short channel effect.
[0071] To address the aforementioned GIDL and short-channel effects, this application proposes a transistor structure and fabrication method for a solid-state imaging device. The transistor structure has a larger distance between the source and drain regions, mitigating the GIDL and short-channel effects. Figure 5 A transistor processing method according to an embodiment of the present application is shown, which includes steps 510 to 550.
[0072] Step 510: Prepare a first transistor element, which includes a base material layer, a gate, and a sidewall spacer layer.
[0073] Figure 5 A schematic diagram showing the structure of the first transistor element is shown.
[0074] like Figure 5 As shown in (a), the first transistor element may only include the above-mentioned base material layer, gate and sidewall spacers, wherein the gate and the sidewall spacers are located on the base material layer, and the sidewall spacers are adjacent to the gate and located on both sides of the gate.
[0075] Specifically, in step 510, the gate material can be processed on the base material layer first, and then the sidewall spacers on both sides of the gate can be processed. For example, the dielectric material of the gate can be obtained by thermal oxidation or wet chemical oxidation, and the electrode material of the gate can be obtained by depositing polysilicon using low pressure chemical vapor deposition (LPVCD). The thickness of the gate can be 100 to 2000 angstroms, preferably 500 to 1600 angstroms. Then, a layer of nitrogen spacer material can be deposited on the base material layer and the gate material, and the nitrogen spacer material can be anisotropically etched to finally form sidewall spacers at both ends of the gate. The thickness of the sidewall spacer can be greater than 1000 angstroms.
[0076] Optionally, in the gate material of the embodiment of the present application, a hard mask layer may also be included above the gate material. For example, the hard mask layer may be a metal mask, such as TiN, BN or Cu3N and other materials, which serves as a stop layer in the subsequent planarization step. The materials of each layer in the gate structure in the present application are not limited to the listed materials, and those skilled in the art can select as needed.
[0077] Alternatively, as Figure 5 As shown in (b), a second intermediate material layer, such as the gate oxide layer mentioned above, may be included between the gate and the base material layer. In other words, the second intermediate material layer may be deposited between the base material layer and the gate to form a gate oxide layer.
[0078] The deposition of the gate material and the second intermediate material layer can be performed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). When etching the hard mask layer, dry etching technology can be used, and reactive ion etching or dry anisotropic etching can be used to form the sidewall spacers. The deposition and etching methods in this step are commonly used in the art, and those skilled in the art can select them as needed, and will not be described in detail here.
[0079] Alternatively, as Figure 5 As shown in (c), step 510 may also include an LDD structure. For example, lightly doped ions (LDD ions) may be implanted and annealed on both sides of the gate material layer to form an LDD structure in the base material layer on both sides of the gate structure. The LDD structure may be implanted before the sidewall spacers are processed. At this time, the gate material may be used as a mask to implant ions to obtain the LDD structure. Figure 5 As shown in (c), the edge of the LDD structure is exactly at the same position as the edge of the gate material.
[0080] Step 520: Depositing a first intermediate material layer on the first transistor element.
[0081] For the convenience of description, the device obtained after step 520 is referred to as a second transistor element. Figure 6 A schematic diagram of a second transistor element is shown, wherein Figure 6 (a) to (c) correspond to Figure 5 The process of depositing the first intermediate material layer after (a) to (c) in FIG. Figure 6 As shown in (a) of FIG. 1 , the first intermediate material layer may include a first portion and a second portion. The first portion is located on an area of the base material layer not covered by the gate and the sidewall spacer, and the second portion is located on the gate and the sidewall material. For ease of description below, the boundaries connecting the first portion and the second portion are referred to as the "first boundary" and the "second boundary," respectively.
[0082] like Figure 6As shown in (b) and (c) of FIG. , a first portion of the first intermediate material layer is located on the second intermediate material layer. In embodiments of the present application, the material of the first intermediate material layer and the material of the second intermediate material layer can be different, thereby facilitating subsequent removal of the first intermediate material layer while retaining the second intermediate material layer. In other embodiments of the present application, the material of the first intermediate material layer and the material of the second intermediate material layer can also be the same, and during the subsequent etching process, a portion of the intermediate material layer can be retained by controlling the etching thickness. For example, when the second intermediate material layer is silicon dioxide, the first intermediate material layer can be made of a material different from silicon dioxide, such as silicon nitride.
[0083] Optionally, the thickness of the first intermediate material layer may be selected to be about 1000 angstroms, and the specific thickness may be determined according to the size of the transistor and the range of the source-drain spacing.
[0084] Step 530: Processing a first groove and a second groove in the first portion.
[0085] The first groove and the second groove are located on both sides of the second portion, and the bottoms of the first groove and the second groove are located on the base material layer. Figure 7 A schematic diagram of the first trench and the second trench is shown, wherein Figure 7 (a) to (c) correspond to Figure 6 Specifically, in the embodiment of the present application, the second portion is used as a mask, and based on the first boundary and the second boundary connecting the first portion and the second portion, the first portion is etched on both sides of the second portion to obtain the first groove and the second groove.
[0086] like Figure 7 As shown in (a) of FIG. 5 , when the second transistor element includes only the first intermediate material layer, step 530 may include machining a first trench and a second trench along the first boundary and the second boundary on both sides of the second portion, respectively, wherein the trenches penetrate the first intermediate material layer. In other words, the depth of the first trench and the second trench is greater than or equal to the thickness of the first intermediate material layer. For example, in an embodiment of the present application, the trench etching process of step 530 may include etching a certain depth on the base material layer after penetrating the first intermediate material layer.
[0087] like Figure 7 As shown in (b) and (c) of FIG, , when the second transistor element includes a first intermediate material layer and a second intermediate material layer, the first trench and the second trench may extend through the first intermediate material layer and the second intermediate material layer. In other words, the depth of the first trench and the second trench is greater than or equal to the total thickness of the first intermediate material layer and the second intermediate material layer.
[0088] In the embodiment of the present application, the method for etching the grooves may be laser etching, chemical etching, etc. The present application does not limit the method for etching the grooves, and those skilled in the art may select the method as needed.
[0089] Step 540: Prepare a source electrode and a drain electrode in the first trench and the second trench respectively, wherein the tops of the source electrode and the drain electrode are higher than the base material layer.
[0090] As mentioned above, in the embodiment of the present application, an elevated source / drain structure is also adopted, that is, the top of the source / drain is higher than the base material layer, or higher than the second intermediate material layer. Figure 8 A schematic diagram of preparing the source and drain electrodes is shown, wherein Figure 8 (a) to (c) correspond to Figure 7 The process of preparing the source / drain after (a) to (c).
[0091] like Figure 8 As shown in (a) in FIG, the top of the source and drain can be flush with the top of the first intermediate material layer, or can be lower than the top of the first intermediate material layer. Figure 8 As shown in (b) and (c), the top of the source and the drain can be flush with the top of the intermediate material layer composed of the first intermediate material layer and the second intermediate material layer, or can be lower than the top of the intermediate material layer composed of the first intermediate material layer and the second intermediate material layer.
[0092] Alternatively, in the embodiment of the present application, the source and drain can be prepared by selective epitaxial growth and in-situ doping. Different from the current ion injection method, the selective epitaxial growth method and in-situ doping method are as follows: the process of introducing doping gas to dope the source and drain while selective epitaxial growth is being performed, and in-situ activation of the doping elements is achieved. Figure 8 As shown in the shaded area in the figure, the depth of the dopant in the source and drain is basically the same, and there will be no Figure 4 The dopant depth in the edge area of the source / drain shown in (b) is deeper. Therefore, in the subsequent heat treatment process, the shape of the dopant in the area after thermal diffusion is more regular, and the Figure 4 The convex shape shown in (b).
[0093] Exemplarily, the source and drain materials may be silicon or polysilicon. In embodiments of the present application, phosphorus or arsenic gas is introduced during epitaxial growth for in-situ doping. For example, taking silicon as the material for the source and drain as an example for further explanation, the reaction gas for selective epitaxial growth may include at least one of silicon tetrachloride (SiCl4) or trichlorosilane (SiHCl3), silane (SiH4), and dichlorosilane (SiH2Cl2) carried by hydrogen (H2) and entering a reaction chamber containing a silicon substrate. A high-temperature chemical reaction is performed in the reaction chamber, causing the silicon-containing reaction gas to be reduced or thermally decomposed, and the generated silicon atoms to grow epitaxially on the silicon surface of the substrate.
[0094] In addition, the selective epitaxial growth method in the embodiments of the present application may also adopt any one of low-pressure chemical vapor deposition (LPCVD), ultra-low-pressure chemical vapor deposition (VLPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The selective epitaxial growth process can be performed in a UHV / CVD process chamber, for example, and the process temperature is approximately in the range of 550 to 880 degrees Celsius.
[0095] In an embodiment of the present application, step 540 can also adjust the doping concentration of the in-situ doping method. For example, the embodiment of the present application can first perform in-situ doping of the opposite type while the source and drain regions are selectively epitaxially grown, and then perform conventional source and drain formation. For example, when preparing NMOS, B, In or Tl can be selected for in-situ doping of the opposite type of source and drain, and when preparing PMOS, P or As can be selected for in-situ doping of the opposite type of source and drain. The present application is not limited to the above examples for the types of the above-mentioned dopants. Through the above-mentioned reverse doping method, the lateral diffusion of the source / drain in the prior art can be reduced, the series resistance and contact resistance between the source and drain can be reduced, and the device operation speed can be improved.
[0096] Optionally, in other embodiments of the present application, the in-situ doping concentration may be a gradient doping distribution. For example, in the epitaxially grown material, the dopants in the source and drain regions have different concentrations at different heights.
[0097] In getting Figure 8 After the source and drain regions are formed, step 540 can also involve a thermal treatment process to activate the dopant ions in the source / drain regions and extend the dopant ions in the source and drain regions into the base material layer, forming source / drain extension regions. Furthermore, the electron mobility in the channel region can be increased, thereby improving the electrical performance of the device. For example, the thermal treatment process can be thermal annealing, such as a laser annealing process or a rapid temperature ramp annealing process. Figure 9FIG2 shows a schematic diagram of the source and drain extension regions (shaded areas). In the embodiment of the present application, the doping diffusion degree of the dopant in the source and drain electrodes can be determined by appropriately selected process parameters of one or more annealing processes.
[0098] like Figure 9 As shown in (a), the source and drain extension regions may diffuse in the horizontal and vertical directions, for example, in the horizontal direction close to and away from the gate, and in the vertical direction close to the base material layer.
[0099] Since the dopants will diffuse toward the gate, when the bottom width of the sidewall spacer is small, the dopants may diffuse to the contact area between the gate and the sidewall spacer or even diffuse to under the gate through the thermal diffusion process, which will not only lead to a larger overlap capacitance between the gate and the drain but also a larger GIDL current.
[0100] However, in the embodiments of the present application Figure 9 In the transistor structure shown, compared to Figure 4 In the transistor structure shown, the spacing between the source and gate and the spacing between the drain and gate are larger. Figure 4 In the transistor structure shown, the spacing between the source and the gate and the spacing between the drain and the gate are the bottom widths of the sidewall spacers. Figure 9 In the transistor structure shown, due to the deposition of the first intermediate material layer, the spacing between the source and the gate and the spacing between the drain and the gate are the sum of the bottom width of the sidewall spacer and the thickness of the second portion of the first intermediate material layer, and the spacing value is larger. Figure 9 In the transistor material shown, even if the bottom width of the sidewall isolation layer is small, the thickness of the second portion of the first intermediate material layer reduces the possibility of the source and drain extension regions extending below the contact surface area between the gate and the sidewall isolation layer, thereby reducing the possibility of the generation of the gate-drain overlap region, as well as reducing the overlap capacitance and GIDL current.
[0101] Step 550: removing the first intermediate material layer to obtain a transistor in a solid-state imaging device.
[0102] Figure 9 (b), (c) and (d) show the transistor structure after removing the first intermediate material layer. Figure 9 As shown, the first intermediate material layer in the embodiment of the present application allows a certain distance between the source / drain structure and the sidewall spacers. Furthermore, the first intermediate material layer can also be used to construct a structure in which the source / drain is exposed, or in other words, a structure in which the source / drain extends beyond the base material layer or the second intermediate material layer.
[0103] If the distance between the source / drain structure and the sidewall spacer is a first value and the thickness of the first intermediate material layer is a second value, then the first value is greater than or equal to the second value. When the embodiment of the present application processes the first trench and the second trench based on the above-mentioned first boundary and the second boundary, the first value is the same as the second value. In addition, if the height of the exposed portion of the source / drain structure (the portion extending out of the base material layer or the second intermediate material layer) is a third value and the thickness of the first intermediate material layer is a second value, then the third value is less than or equal to the second value. In other words, when the source / drain structure is deposited in the embodiment of the present application, the top of the source / drain structure can be just flush with the top of the first intermediate material layer, in which case the third value is equal to the second value, or it can be lower than the top of the first intermediate material layer, in which case the third value is less than the second value. Therefore, in the embodiment of the present application, the thickness of the first intermediate material layer can be controlled to control the distance between the source / drain structure and the sidewall spacer, as well as the height of the exposed portion of the source / drain structure.
[0104] In an embodiment of the present application, by adding a step of depositing a first intermediate material layer in the processing technology of the transistor, the spacing between the source / drain and the sidewall isolation layer at both ends of the gate is increased, thereby reducing the possibility of the generation of a gate-drain overlap region, and reducing the overlap capacitance of the gate and drain and the GIDL current. In addition, the present application adopts a selective epitaxial growth process and an in-situ doping method when preparing the source / drain structure to form a regularly shaped source and drain extension region, thereby avoiding the short channel effect in the prior art. Ultimately, the electrical performance of the transistor obtained in the embodiment of the present application is better, thereby making the image sensing performance of the solid-state imaging device including the above-mentioned transistor better.
[0105] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.
Claims
1. A solid-state imaging device, characterized in that The solid-state imaging device includes a transistor, and the transistor includes: a base material layer; a gate, the gate being located on the base material layer; a sidewall spacer, the sidewall spacer being located on the base material layer, the sidewall spacer being adjacent to the gate and being located on both sides of the gate; A source electrode and a drain electrode, wherein the source electrode and the drain electrode are located on the base material layer and respectively on both sides of the sidewall isolation layer, the tops of the source electrode and the drain electrode are higher than the base material layer, there is a gap between the side of the source electrode close to the sidewall isolation layer and the sidewall isolation layer, and there is a gap between the side of the drain electrode close to the sidewall isolation layer and the sidewall isolation layer.
2. The solid-state imaging device according to claim 1, wherein The distance between the side of the source electrode close to the sidewall isolation layer and the sidewall isolation layer, and the distance between the side of the drain electrode close to the sidewall isolation layer and the sidewall isolation layer are a first value, and the height of the portion of the source electrode and the drain electrode that is higher than the base material layer is a second value, and the second value is not greater than the first value.
3. The solid-state imaging device according to claim 1, wherein The system further includes a second intermediate material layer disposed between the base material layer and the gate, and the tops of the source electrode and the drain electrode are higher than the second intermediate material layer.
4. The solid-state imaging device according to claim 3, wherein The distance between the side of the source electrode close to the sidewall isolation layer and the sidewall isolation layer, and the distance between the side of the drain electrode close to the sidewall isolation layer and the sidewall isolation layer are a first value, and the height of the portion of the source electrode and the drain electrode that is higher than the second intermediate material layer is a third value, and the third value is not greater than the first value.
5. The solid-state imaging device according to any one of claims 1 to 4, wherein The base material layer includes a first lightly doped drain structure and a second lightly doped drain structure. The first lightly doped drain structure and the second lightly doped drain structure are respectively located on both sides of the gate and respectively located below the source and the drain.
6. The solid-state imaging device according to any one of claims 1 to 5, wherein The source electrode and the drain electrode are prepared by epitaxial growth and in-situ doping.
7. An electronic device, characterized in that: The solid-state imaging device according to any one of claims 1 to 6 is included.
8. A method for preparing a solid-state imaging device, characterized in that: include: preparing a first transistor element, the first transistor element comprising a base material layer, a gate, and a sidewall spacer, wherein the gate and the sidewall spacer are located on the base material layer, and the sidewall spacer is adjacent to the gate and located on both sides of the gate; Depositing a first intermediate material layer on the first transistor element, the first intermediate material layer comprising a first portion and a second portion, the first portion being located on a region of the base material layer not covered by the gate and the sidewall spacer, and the second portion being located on the gate and the sidewall material; Processing a first groove and a second groove in the first portion, wherein the first groove and the second groove are located on both sides of the second portion, and the bottoms of the first groove and the second groove are located on the base material layer; preparing a source electrode and a drain electrode in the first trench and the second trench respectively, wherein the tops of the source electrode and the drain electrode are higher than the base material layer; The first intermediate material layer is removed to obtain the transistor in the solid-state imaging device.
9. The method according to claim 8, characterized in that The preparing the first transistor element comprises: preparing the gate on the base material layer; The sidewall isolation layers are formed on both sides of the gate.
10. The method according to claim 8, characterized in that The preparing the first transistor element comprises: depositing a second intermediate material layer on the base material layer; preparing the gate on the second intermediate material layer; The sidewall isolation layers are formed on both sides of the gate.
11. The method according to any one of claims 8 to 10, characterized in that The step of preparing a source electrode and a drain electrode in the first trench and the second trench, respectively, comprises: The source electrode and the drain electrode are respectively prepared on the first trench and the second trench by an epitaxial growth method and an in-situ doping method.
12. The method according to claim 11, characterized in that After preparing the source electrode and the drain electrode, the method further includes: Ions in the source and drain are activated by a heat treatment method.
13. The method according to claim 11 or 12, characterized in that The process of the in-situ doping method is reverse doping.
14. The method according to any one of claims 8 to 13, characterized in that The method further comprises: The first lightly doped drain structure and the second lightly doped drain structure are prepared by an epitaxial growth method. The first lightly doped drain structure and the second lightly doped drain structure are respectively located on both sides of the gate and respectively located below the source and the drain.
15. The method according to any one of claims 8 to 14, characterized in that Processing the first groove and the second groove in the first portion includes: Using the second portion as a mask, based on a first boundary and a second boundary connecting the first portion and the second portion, the first portion is etched on both sides of the second portion to obtain the first trench and the second trench.