Readout circuit for image sensing, readout system and solid-state imaging device
By introducing a current mirror circuit, a negative impedance transformation unit, and a charge/discharge acceleration unit into the CMOS image sensor, the problem of slow VSL signal establishment speed is solved, and a faster response speed is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-11
- Publication Date
- 2026-03-13
AI Technical Summary
Existing CMOS image sensors have a slow response speed when the pixel array output signal VSL is established from low to high, and cannot be effectively accelerated.
An image sensing readout circuit is employed, including a current mirror circuit unit, a negative impedance transformation unit, and a charge/discharge acceleration unit. The negative impedance transformation unit cancels out the effects of parasitic capacitance and resistance, and the charge/discharge acceleration unit provides charge/discharge current during VSL establishment.
It accelerates the VSL signal establishment speed and improves the response speed of the image sensor.
Smart Images
Figure CN223993710U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of image sensing readout technology, and in particular to an image sensing readout circuit, readout system and solid-state imaging device. Background Technology
[0002] In existing CMOS image sensors, the ADC (A / D Converter) consists of a load current source array, a comparator array, and a counter array. The load current source array provides constant current to the source followers of the pixel array. During signal readout from the pixel array, charge in the PD (Photon Diode) needs to be transferred to the FD (Floating Diffusion), causing the FD voltage to drop. This further reduces the output signal VSL (Vertical Signal Line) of the pixel array through the pixel SF (Source Follower).
[0003] During the readout process described above, the VSL descent process is affected by the parasitic resistance and capacitance of the metal traces and the equivalent output impedance of SF, which slows down the VSL descent process. This means that the entire image sensor needs to wait for the VSL to completely drop to a stable level during the readout process. The time consumed in this process is called the VSL settling time.
[0004] In current image sensor configurations, to accelerate VSL establishment time, the bias current of the load current source is often increased: on the one hand, the transconductance of the SF of the pixel array is increased to reduce its equivalent output impedance; on the other hand, during the establishment of large signals, increasing the bias current of the load current source can accelerate the establishment speed of large signals.
[0005] However, increasing the bias current of the load current source can usually only accelerate the fall-up setup process of the pixel array output signal VSL (Vertical Signal Line), and may not be able to respond when the pixel array output signal VSL is established from low level to high level. Summary of the Invention
[0006] The purpose of this invention is to address the shortcomings of existing technologies that cannot respond when the pixel array output signal VSL is established from a low level upwards, and to propose an image sensing readout circuit, readout system, and solid-state imaging device.
[0007] To achieve the above objectives, the present invention adopts the following technical solution:
[0008] The first aspect of this utility model provides a readout circuit for image sensing, comprising:
[0009] A pixel array unit, wherein the pixel array unit is used for photoelectric signal conversion;
[0010] A current mirror circuit unit is electrically connected to the pixel array unit and is used to provide bias current.
[0011] A negative impedance transformation unit is electrically connected to the current mirror circuit unit. The negative impedance transformation unit is used to generate a negative impedance to cancel out the parasitic impedance of the VSL itself.
[0012] A charge / discharge acceleration unit is used to provide charge / discharge current during the VSL fall-up setup process or the VSL rise-up setup process.
[0013] In some feasible solutions, the charge / discharge acceleration unit includes:
[0014] A rising voltage-to-current conversion circuit, one end of which is connected to a drain power supply voltage, is used to perform voltage-to-current conversion during the VSL rising setup process.
[0015] A falling voltage-to-current conversion circuit is used to perform voltage-to-current conversion during the VSL falling establishment process;
[0016] A switching circuit is provided, which is electrically connected to the rising voltage-to-current conversion circuit and the falling voltage-to-current conversion circuit respectively. The switching circuit is used to selectively connect the rising voltage-to-current conversion circuit and the falling voltage-to-current conversion circuit.
[0017] In some feasible solutions, the voltage-to-current conversion circuit includes:
[0018] The first P-channel field-effect transistor has a drain power supply voltage connected to one end, and is used to provide a current source.
[0019] The second P-channel field-effect transistor is also connected to a drain power supply voltage at one end, and is used to provide bias current.
[0020] A capacitor is disposed on one side of the second P-channel field-effect transistor and is electrically connected to the second P-channel field-effect transistor. The capacitor is a bypass capacitor of the second P-channel field-effect transistor.
[0021] The third P-channel field-effect transistor has a gate connected to a vertical signal line signal output node, and its source is connected to the second P-channel field-effect transistor.
[0022] The first N-channel field-effect transistor is connected to the second P-channel field-effect transistor, and the drain of the first N-channel field-effect transistor is connected to the third P-channel field-effect transistor.
[0023] The second N-channel field-effect transistor and the first N-channel field-effect transistor form a current mirror.
[0024] In some feasible solutions, the rising voltage-to-current conversion circuit includes:
[0025] A fifth N-channel field-effect transistor, wherein the fifth N-channel field-effect transistor is used for voltage-to-current conversion;
[0026] A sixth N-channel field-effect transistor, which is electrically connected to the fifth N-channel field-effect transistor, has a bias voltage connected to its gate, and is used as a bias current source for the fifth N-channel field-effect transistor.
[0027] A fourth P-channel field-effect transistor, wherein the fourth P-channel field-effect transistor is electrically connected to the fifth N-channel field-effect transistor;
[0028] A fifth P-channel field-effect transistor, which is electrically connected to the fourth P-channel field-effect transistor, and the fifth P-channel field-effect transistor and the fourth P-channel field-effect transistor form a current mirror;
[0029] A seventh N-channel field-effect transistor, which is electrically connected to the fifth P-channel field-effect transistor, has a bias voltage connected to its gate, and serves as a bias current source for the fifth P-channel field-effect transistor.
[0030] The second capacitor is electrically connected to the fifth N-channel field-effect transistor and serves as a bypass capacitor for the fifth N-channel field-effect transistor.
[0031] In some feasible solutions, the switching circuit includes:
[0032] The sixth P-channel field-effect transistor has a gate connected to CTRL and is electrically connected to the drain of the second N-channel field-effect transistor and the drain of the fifth P-channel field-effect transistor.
[0033] In some feasible solutions, the negative impedance transformation unit includes:
[0034] A first capacitor is electrically connected to the pixel array unit;
[0035] A third N-channel field-effect transistor, wherein the gate of the third N-channel field-effect transistor is electrically connected to a bias voltage;
[0036] The fourth N-channel field-effect transistor has its gate electrically connected to the pixel array unit, its drain connected to a power supply, and its source electrically connected to the drain of the third N-channel field-effect transistor.
[0037] One end of the first capacitor is electrically connected to the source of the fourth N-channel field-effect transistor, and the other end of the first capacitor is electrically connected to the current mirror circuit unit.
[0038] In some feasible solutions, the current mirror circuit unit further includes:
[0039] Two N-channel field-effect transistors are connected via a common source and common gate. The gate of the N-channel field-effect transistor connected via the common source and common gate is connected to a bias voltage. The source of the N-channel field-effect transistor connected via the common source and common gate is electrically connected to the pixel array unit, the negative impedance transformation unit, and the charge-discharge acceleration unit, respectively.
[0040] In some feasible solutions, the charge / discharge acceleration unit includes:
[0041] Rising voltage-to-current conversion circuit and / or falling voltage-to-current conversion circuit.
[0042] The second aspect of this utility model provides an image sensing readout system, which employs the image sensing readout circuit described in any one of the first aspects, and the readout system further includes:
[0043] Pixel driving module, the pixel driving module includes: multiple pixel array units;
[0044] A pixel noise detection module is electrically connected to the pixel driving module, and the pixel noise detection module is used to detect the pixel array units in the pixel driving module.
[0045] A reference ramp generation module, which is electrically connected to the pixel driving module;
[0046] The comparator is electrically connected to both the readout circuit and the reference ramp generation module.
[0047] A counter, which is electrically connected to the comparator;
[0048] A data transmission module is electrically connected to the counter.
[0049] The third aspect of this utility model provides a solid-state imaging device, which employs an image sensing readout circuit as described in any one of the first aspects or an image sensing readout system as described in the second aspect.
[0050] The beneficial effects of this utility model are as follows:
[0051] This invention utilizes a negative impedance transformation unit and a charge / discharge acceleration unit. The negative impedance transformation unit generates negative impedance to cancel out the parasitic capacitance and resistance that affect the VSL establishment speed, thereby accelerating the small-signal establishment speed. The charge / discharge acceleration unit selectively provides charge / discharge current in coordination with the VSL descent or rise establishment process to accelerate the large-signal establishment speed. In other words, this application can provide corresponding responses to the VSL descent or rise establishment process. Attached Figure Description
[0052] Figure 1 This is a schematic diagram of the working connection of an image sensing readout circuit provided in an embodiment of the present utility model;
[0053] Figure 2 This is a schematic diagram of the pixel array unit structure in the pixel driving module provided in this embodiment of the utility model;
[0054] Figure 3 This is a schematic diagram showing the connection between an image sensing readout circuit and a pixel array provided in an embodiment of the present invention;
[0055] Figure 4 This is a schematic diagram of the current mirror circuit unit connection of an image sensing readout circuit provided in an embodiment of the present invention;
[0056] Figure 5 This is a schematic diagram of the negative impedance transformation circuit that generates negative resistance in an image sensing readout circuit provided in an embodiment of the present utility model.
[0057] Figure 6 This is a schematic diagram of the VSL establishment process in an image sensing readout circuit provided in an embodiment of the present invention;
[0058] Figure 7 This is a schematic diagram showing the connection of the charge-discharge conversion unit in an image sensing readout circuit provided in an embodiment of this utility model. Detailed Implementation
[0059] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0060] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in this utility model embodiment are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.
[0061] In this utility model, unless otherwise explicitly specified and limited, the terms "connection," "fixing," etc., should be interpreted broadly. For example, "fixing" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.
[0062] Furthermore, if the embodiments of this utility model involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the meaning of "and / or" throughout the text includes three parallel solutions; for example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.
[0063] Reference Figures 1 to 7This invention addresses the shortcoming of existing technologies that fail to respond when the pixel array output signal VSL establishes itself from a low level upwards. In this first aspect, a readout circuit for image sensing is provided. This readout circuit utilizes a negative impedance transformation unit 1062 and a charge / discharge acceleration unit 1063. The negative impedance transformation unit 1062 generates a negative impedance to cancel out the parasitic capacitance 1102 and parasitic resistance 1101 that affect the VSL establishment speed, thereby accelerating the establishment speed of small signals. The charge / discharge acceleration unit 1063 selectively provides charge / discharge current during the VSL falling or rising establishment process, thereby accelerating the establishment speed of large signals. In other words, this application can respond appropriately to the VSL falling or rising establishment process.
[0064] Reference Figure 4 , Figure 5Specifically, the first aspect of this utility model provides a readout circuit for image sensing, comprising: a pixel array unit 100, a current mirror circuit unit 1061, a negative impedance transformation unit 1062, and a charge / discharge acceleration unit 1063. The pixel array unit 100 is used for photoelectric signal conversion; the current mirror circuit unit 1061 is electrically connected to the pixel array unit 100 and is used to provide bias current; wherein, the current mirror circuit unit 1061 may include: a common-source common-gate current mirror or two N-channel field-effect transistors. The current mirror circuit 1061 includes either a common-source, common-gate current mirror or two N-channel field-effect transistors (FETs). Specifically, the current mirror circuit 1061 can be composed of two N-channel FETs (i.e., N-channel FET 10611 and N-channel FET 10612) connected via a common-source, common-gate connection. The gates of the FETs are connected to a bias voltage, and the sources of the FETs are electrically connected to the pixel matrix unit 100, the negative impedance transformation unit 1062, and the charge / discharge acceleration unit 1063, respectively. That is, the gates of the two FETs are connected to VB2 and VB1, respectively, as the bias voltages for the common-source, common-gate current mirror. The vertical signal line output node VSL_OUT1103 is then connected to the negative impedance transformation unit 1062 and the charge / discharge acceleration unit 1063. It should be noted that the negative impedance transformation unit 1062 and the charge / discharge acceleration unit 1063 can be simultaneously connected to the vertical signal line output node VSL_OUT1103, or only one of them can be connected to the vertical signal line output node VSL_OUT1103. The negative impedance transformation unit 1062 is electrically connected to the current mirror circuit unit 1061. The negative impedance transformation unit 1062 is used to generate negative impedance to cancel out the parasitic impedance (parasitic capacitance 1101 or parasitic resistance 1102) of VSL itself. The charge / discharge acceleration unit 1063 is used to provide charge / discharge current during the VSL fall-down setup process or rise-down setup process.
[0065] Reference Figure 2 and Figure 3In this embodiment, multiple pixel array units 100 may be provided, each including: a photodiode 1001, an N-channel field-effect transistor 1002, an N-channel field-effect transistor 1003, an N-channel field-effect transistor 1004, and an N-channel field-effect transistor 1005. When illuminated, the photodiode 1001 performs photoelectric conversion, generating photoelectrons. During reset, the gate connection signal RST of the N-channel field-effect transistor 1003 is set high, the N-channel field-effect transistor 1003 is turned on, and the potential of the floating diffusion point FD (Floating Diffusion) 1006 is reset to a level slightly lower than the power supply VDD. Subsequently, the RST signal is set low, ending the reset operation. When signal reading is performed, the gate connection signal TX of the N-channel MOSFET 1002 is set high, and the N-channel MOSFET 1002 is turned on. Since the potential of the floating diffusion point FD1006 is higher than that of the positive terminal of the photodiode 1001, the photogenerated electrons generated by the photodiode 1001 move towards the floating diffusion point FD1006 through the N-channel MOSFET 1002, causing its voltage to drop. At this time, if the pixel row where the pixel unit 1000 is located is in the readout state, the gate connection signal SEL of the N-channel MOSFET 1005 is set high. The N-channel MOSFET 1004 is in the source follower state when the N-channel MOSFET 1005 is turned on. When the potential of the floating diffusion point FD1006 drops, it causes the voltage of the vertical signal line node VSL1007 to drop slightly less than the voltage change of the floating diffusion point FD1006. At this time, the voltage change of the vertical signal line node VSL1007 corresponds to the signal amount brought by the photogenerated electrons. Additionally, the parasitic resistance 1101 of the metal trace of the vertical signal line node VSL1007 can be represented by resistor R0, its parasitic capacitance 1102 can be represented by capacitor C0, the load current source can be represented by ideal current source 1104, and the vertical signal line output node connected to the load current source 1104 is VSL_OUT1103.
[0066] Reference Figure 5In this embodiment, to facilitate understanding of how the negative impedance transformation unit 1062 generates negative impedance to cancel out the parasitic impedance during the VSL rise or fall establishment process, the following explanation is provided: In this embodiment, the negative impedance transformation unit 1062 further includes: a first capacitor 10621, a third N-channel field-effect transistor 10622, and a fourth N-channel field-effect transistor 10623. The first capacitor 10621 is electrically connected to the pixel array unit 100; the gate of the third N-channel field-effect transistor 10622 is electrically connected to... A bias voltage is applied; the gate of the fourth N-channel field-effect transistor 10623 is electrically connected to the pixel array unit, the drain of the fourth N-channel field-effect transistor 10623 is connected to a power supply, and the source of the fourth N-channel field-effect transistor 10623 is electrically connected to the drain of the third N-channel field-effect transistor 10622; wherein, one end of the first capacitor 10621 is electrically connected to the source of the fourth N-channel field-effect transistor 10623, and the other end of the first capacitor 10621 is electrically connected to the current mirror circuit unit 1061. In this embodiment, within the negative impedance transformation unit 1062, the third N-channel field-effect transistor 10622 serves as the bias current source for the fourth N-channel field-effect transistor 10623; the fourth N-channel field-effect transistor 10623 functions as a source follower. The gate of the fourth N-channel field-effect transistor 10623 is connected to the vertical signal line output node VSL_OUT1103, the drain of the fourth N-channel field-effect transistor 10623 is connected to the power supply, and the source of the fourth N-channel field-effect transistor 10623 is connected to the drain of the third N-channel field-effect transistor 10622 and one end of the first capacitor 10621. The other end of the first capacitor 10621 is connected to the source of an N-channel field-effect transistor 10611 in the common-source common-gate current mirror circuit unit 1061. Therefore, in this embodiment, when the vertical signal line output node VSL_OUT1103 decreases to Vin = V1, assuming the input current is Iin and ignoring the body effect of the fourth N-channel field-effect transistor 10623 (e.g., connecting its substrate to the source), it can be considered that the transfer gain of the source follower is approximately 1. At this time, for the negative impedance transformation unit in this embodiment, the transconductance of one N-channel field-effect transistor 10611 in the common-source cascode current mirror circuit unit 1061 is gm1, and its source voltage change is Vx. The source voltage change of the fourth N-channel field-effect transistor 10623 is Vy, the output impedance of the third N-channel field-effect transistor 10622 is Ro, and the transconductance of the fourth N-channel field-effect transistor 10623 is gm2. Then, according to Kirchhoff's current-voltage theorem, we can obtain:
[0067] gm2*(Vin-Vy)+(Vx-Vy) / (1 / (s*C_NI))=Vy / Ro;
[0068] Iin=-gm1*Vx=(Vx-Vy) / (1 / (s*C_NI));
[0069] After transforming and simplifying the above system of equations, we can approximately obtain:
[0070] Zin=Vin / Iin=[gm1+gm1*gm2*Ro+s*C_NI*(gm2*Ro+gm1*Ro)] / gm1*gm2*Ro*s*C_NI;
[0071] In the formula, C_NI is the first capacitor. As can be seen from the above formula, at this time, the equivalent input impedance of the negative impedance transformation unit 1062 at low frequency is the sum of negative resistance and negative capacitance, and the equivalent input impedance at high frequency is negative resistance, but the resistance value is small. Therefore, gm2 and Ro can be reasonably designed according to the actual situation, so that the negative impedance transformation unit 1062 has a negative capacitance that can cancel the parasitic capacitance 1102, thereby accelerating the establishment speed of small signals.
[0072] Reference Figure 6 and Figure 7 In this embodiment, to facilitate understanding of how the charge / discharge acceleration unit 1063 can provide charge / discharge current for the VSL rising establishment process or the falling establishment process respectively, the following description is provided. Specifically, the charge / discharge acceleration unit 1063 includes: a rising voltage-to-current conversion circuit, a falling voltage-to-current conversion circuit, and a switching circuit. One end of the rising voltage-to-current conversion circuit is connected to the drain power supply voltage. The rising voltage-to-current conversion circuit is used to perform voltage-to-current conversion during the VSL rising establishment process. The falling voltage-to-current conversion circuit is used to perform voltage-to-current conversion during the VSL falling establishment process. The switching circuit is electrically connected to the rising voltage-to-current conversion circuit and the falling voltage-to-current conversion circuit respectively. The switching circuit is used to selectively connect the rising voltage-to-current conversion circuit and the falling voltage-to-current conversion circuit. In this embodiment, by configuring a switching circuit, a falling voltage-to-current conversion circuit, and a rising-falling voltage-to-current conversion circuit in the charging and discharging acceleration unit 1063, and by externally connecting the gate of the switching circuit to CTRL, and simultaneously electrically connecting the switching circuit to the rising voltage-to-current conversion circuit and the falling voltage-to-current conversion circuit respectively, the switching circuit is turned on when the vertical signal line node VSL1007 falls and turned off when the vertical signal line node VSL1007 rises.
[0073] Reference Figure 7Specifically, the voltage-to-current conversion circuit includes: a first P-channel field-effect transistor 10636, a second P-channel field-effect transistor 10631, a capacitor 10632, a third P-channel field-effect transistor 10633, a first N-channel field-effect transistor 10634, and a second N-channel field-effect transistor 10635. One end of the first P-channel field-effect transistor 10636 is connected to the drain power supply voltage, and the first P-channel field-effect transistor 10636 is used to provide a current source; one end of the second P-channel field-effect transistor 10631 is also connected to the drain power supply voltage, and the second P-channel field-effect transistor 10631 is used to provide bias current; the capacitor 10632 is disposed on one side of the second P-channel field-effect transistor 10631, and the capacitor 10632 is electrically connected to the second P-channel field-effect transistor 10631. The capacitor 10632 is a bypass capacitor of the second P-channel field-effect transistor 10631 (i.e., reducing the capacitance of the second P-channel field-effect transistor 10631). (Noise and voltage fluctuations generated by 31); the gate of the third P-channel field-effect transistor 10633 is connected to the vertical signal line signal output node VSL_OUT1103, and the source of the third P-channel field-effect transistor 10633 is connected to the second P-channel field-effect transistor 10631; the first N-channel field-effect transistor 10634 is connected to the second P-channel field-effect transistor 10631, and the drain of the first N-channel field-effect transistor 10634 is connected to the third P-channel field-effect transistor 10633; the second N-channel field-effect transistor 10635 and the first N-channel field-effect transistor 10634 form a current mirror. In this embodiment, the first P-channel field-effect transistor 10636 and the second P-channel field-effect transistor 10631 can act as current sources, and the capacitor 10632 can act as a bypass capacitor for the second P-channel field-effect transistor 10631. The second P-channel field-effect transistor 10631 is composed of the third P-channel field-effect transistor 10633 and the first N-channel field-effect transistor 10634. The gate of the third P-channel field-effect transistor 10633 is connected to the vertical signal line output node VSL_OUT1103. The drain of the third P-channel field-effect transistor 10633 is connected to the first N-channel field-effect transistor 10634. The first N-channel field-effect transistor 10634 and the second N-channel field-effect transistor 10635 form a current mirror, the ratio of which is determined by the ratio of the width-to-length ratio of the second N-channel field-effect transistor 10635 to the width-to-length ratio of the first N-channel field-effect transistor 10634. The current of the first P-channel field-effect transistor 10636, acting as a current source, is set to be slightly equal to the saturation current of the second N-channel field-effect transistor 10635.During the fall-out setup of the vertical signal line output node VSL_OUT1103, the gate voltage of the third P-channel field-effect transistor 10633 drops by ΔV. At this time, the third P-channel field-effect transistor 10633 acts as a source follower, and its source voltage will drop. At this time, the capacitor 10632, which acts as a bypass capacitor, acts as a current source to provide a transient current ΔI = C1 * dΔV / dt for the second P-channel field-effect transistor 10631. This transient current is amplified by the current mirror composed of the first N-channel field-effect transistor 10634 and the second N-channel field-effect transistor 10635. The amplification factor is as described above, which is the ratio of the width-to-length ratio of the second N-channel field-effect transistor 10635 to the first N-channel field-effect transistor 10634.
[0074] K=(W / L)_10635 / (W / L)_10634.
[0075] Therefore, it can be known that the transient output current generated by the drain of the second N-channel field-effect transistor 10635 is K*ΔI. Since the first P-channel field-effect transistor 10636 is set to constant current operation, this transient current K*ΔI will be provided by the load capacitor through the vertical signal line output node VSL_OUT1103. If the current source current is set to I, then in this embodiment, the current flowing out of the load capacitor during the large signal establishment period can be expressed as I+K*ΔI, and its magnitude can be adjusted by adjusting the capacitance value and the current mirror ratio K. Therefore, in this embodiment, the charge-discharge acceleration circuit 1063 accelerates the large signal establishment speed of the vertical signal line output node VSL_OUT1103 by increasing the transient current flowing out of the load capacitor during the large signal establishment period. It should be noted that under this operating condition, all field-effect transistors operate in saturation.
[0076] Specifically, the rising voltage-to-current conversion circuit includes: a fifth N-channel field-effect transistor 10637, a sixth N-channel field-effect transistor 106371, a fourth P-channel field-effect transistor 106373, a fifth P-channel field-effect transistor 106374, a seventh N-channel field-effect transistor 106372, and a second capacitor 106376. The fifth N-channel field-effect transistor 10637 is used for voltage-to-current conversion; the sixth N-channel field-effect transistor 106371 is electrically connected to the fifth N-channel field-effect transistor 10637, and the gate of the sixth N-channel field-effect transistor 106371 is connected to a bias voltage, serving as a bias current source for the fifth N-channel field-effect transistor 10637; the fourth P-channel field-effect transistor 106373 is connected to the fifth N-channel field-effect transistor 106374. The fifth P-channel field-effect transistor 10637 is electrically connected; the fifth P-channel field-effect transistor 106374 is electrically connected to the fourth P-channel field-effect transistor 106373, and the fifth P-channel field-effect transistor 106374 and the fourth P-channel field-effect transistor 106373 form a current mirror; the seventh N-channel field-effect transistor 106372 is electrically connected to the fifth P-channel field-effect transistor 106374, the gate of the seventh N-channel field-effect transistor 106372 is connected to a bias voltage, and the seventh N-channel field-effect transistor 106372 is used as a bias current source for the fifth P-channel field-effect transistor 106374; the second capacitor 106376 is electrically connected to the fifth N-channel field-effect transistor 10637, and the second capacitor 106376 is used as a bypass capacitor for the fifth N-channel field-effect transistor 10637. In this embodiment, the fifth N-channel field-effect transistor 10637 is used as a voltage-to-current converter in the charge-discharge acceleration circuit 1063; the sixth N-channel field-effect transistor 106371 serves as the bias current source for the fifth N-channel field-effect transistor 10637, with its gate connected to the bias voltage VB5; the fourth P-channel field-effect transistor 106373 and the fifth P-channel field-effect transistor 106374 form a current mirror, and the current flowing through the fifth N-channel field-effect transistor 106377 also flows through the fourth P-channel field-effect transistor 106373. The seventh N-channel field-effect transistor 106372 serves as the bias current source for the fifth P-channel field-effect transistor 106374, with its gate connected to the bias voltage VB6, and VB6 is designed such that the DC current of the seventh N-channel field-effect transistor 106372 is slightly equal to that of the fifth P-channel field-effect transistor 106374.In the aforementioned charge / discharge acceleration unit, the switching circuit includes a sixth P-channel field-effect transistor 106375, whose gate is connected to a CTRL. The sixth P-channel field-effect transistor is electrically connected to the drain of the second N-channel field-effect transistor and the drain of the fifth P-channel field-effect transistor 106374. This allows for selective switching of the rising voltage-to-current conversion circuit or the falling voltage-to-current conversion circuit based on the actual establishment of the VSL.
[0077] In this embodiment, a rising voltage-to-current conversion circuit is used. When the vertical signal line node VSL1007 rises, causing the vertical signal line node VSL_OUT1103 to rise, the fifth N-channel field-effect transistor 10637 operates as a source follower. When its source voltage rises by ΔV, the voltage difference between the two plates of the second capacitor 106376 increases. At this time, the change in the charging current of the second capacitor 106376 is: ΔI = C2 * dΔV / dt, where C2 is the second capacitor 106376. This part of ΔI also flows through the fourth P-channel field-effect transistor 106373, which forms a current mirror. This transient current is amplified by the current mirror formed by the fourth P-channel field-effect transistor 106373 and the fifth P-channel field-effect transistor 106374. The amplification factor is the ratio of the width-to-length ratio of the fourth P-channel field-effect transistor 106373 to the fifth P-channel field-effect transistor 106374.
[0078] K=(W / L)_106374 / (W / L)_106373;
[0079] As described above, the transient output current generated by the drain of the fifth P-channel field-effect transistor 106374 is K*ΔI. Since the seventh N-channel field-effect transistor 106372 is set to a constant current operating state, this transient current K*ΔI will charge the load capacitor through the vertical signal line node VSL_OUT1103. If the current flowing through the N-channel field-effect transistor 1004 of the pixel array unit 100 is I, then in this embodiment, the current flowing into the load capacitor during the rise-up setup of the vertical signal line node VSL_OUT1103 can be expressed as I+K*ΔI. Its magnitude can be adjusted by adjusting the capacitance of the bypass capacitor (i.e., the second capacitor 106376) and the current mirror ratio K. Therefore, in this embodiment, the charge-discharge acceleration circuit 1602 accelerates the setup speed of the vertical signal line node VSL_OUT1103 during the rise-up setup by increasing the transient current charging the load capacitor during the rise-up setup of the vertical signal line VSL_OUT1103.
[0080] Reference Figure 1The second aspect of this utility model provides an image sensing readout system, employing an image sensing readout circuit 106 as described in any one of the first aspects. The readout system further includes: a pixel driving module 101, a pixel noise detection module 102, and a reference ramp generation module 103. The pixel driving module 101 includes: a plurality of pixel array units 100, which are used for photoelectric conversion; the pixel noise detection module 102 is electrically connected to the pixel driving module 101 and is used to detect the pixel array units 100 in the pixel driving module 101; the reference ramp generation module 103 is electrically connected to the pixel driving module 101; a comparator 107 is electrically connected to the readout circuit 106 and the reference ramp generation module 103 respectively; a counter 108 is electrically connected to the comparator 107; and a data transmission module 109 is electrically connected to the counter 108. The readout system is equipped with a charge-discharge acceleration unit that can accelerate the establishment time of the vertical signal line node VSL1007, regardless of whether it is in the rising or falling establishment process.
[0081] It should be noted that in this readout system, the rising voltage-to-current conversion circuit and the falling voltage-to-current conversion circuit can coexist in the readout system, or they can exist independently. That is, the readout system includes both the rising voltage-to-current conversion circuit and / or the falling voltage-to-current conversion circuit.
[0082] In some implementations, the readout system can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad-hoc peer-to-peer networks), as well as any currently known or future-developed networks. The functionality described above herein can be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that can be used include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SOCs), complex programmable logic devices (CPLDs), and so on.
[0083] The third aspect of this utility model provides a solid-state imaging device, which employs an image sensing readout circuit as described in any one of the first aspects or an image sensing readout system as described in the second aspect. Specifically, in the solid-state imaging device, the VSL signal can be established by employing the aforementioned medium-current mirror circuit unit 1061, negative impedance transformation unit, and charge / discharge acceleration unit 1063. Simultaneously, the rising voltage-to-current transformation circuit and the falling voltage-to-current transformation circuit can accelerate the establishment time of the vertical signal line node VSL1007, whether it is a rising or falling establishment process, to meet imaging requirements.
[0084] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.
[0085] The above description is merely a selection of preferred embodiments of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in the embodiments of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in the embodiments of this disclosure.
Claims
1. A readout circuit for image sensing, characterized in that, The application relates to a pixel array unit for photoelectric signal conversion, a current mirror circuit unit electrically connected with the pixel array unit, the current mirror circuit unit being used for providing a bias current, a negative impedance conversion unit electrically connected with the current mirror circuit unit, the negative impedance conversion unit being used for generating a negative impedance to offset the parasitic impedance of VSL itself, and a charge and discharge acceleration unit used for providing a charge and discharge current in the VSL falling or rising establishment process. The charge and discharge acceleration unit comprises a rising voltage-current conversion circuit having one end connected with a drain source voltage, the rising voltage-current conversion circuit being used for voltage-current conversion in the VSL rising establishment process, a falling voltage-current conversion circuit used for voltage-current conversion in the VSL falling establishment process, and a switch circuit electrically connected with the rising voltage-current conversion circuit and the falling voltage-current conversion circuit respectively, the switch circuit being used for selecting the rising voltage-current conversion circuit and the falling voltage-current conversion circuit. The falling voltage-current conversion circuit comprises a first P-channel field effect transistor having one end connected with a drain source voltage, the first P-channel field effect transistor being used for providing a current source, a second P-channel field effect transistor also having one end connected with the drain source voltage, the second P-channel field effect transistor being used for providing a bias current, a capacitor arranged on one side of the second P-channel field effect transistor, the capacitor being electrically connected with the second P-channel field effect transistor, the capacitor C1 being a bypass capacitor of the second P-channel field effect transistor, a third P-channel field effect transistor having a gate connected with a vertical signal line signal output node, a source connected with the second P-channel field effect transistor, a first N-channel field effect transistor connected with the second P-channel field effect transistor and connected with a drain of the third P-channel field effect transistor, and a second N-channel field effect transistor connected with the first N-channel field effect transistor to form a current mirror. The rising voltage-current conversion circuit comprises a fifth N-channel field effect transistor used for voltage-current conversion, a sixth N-channel field effect transistor electrically connected with the fifth N-channel field effect transistor, the sixth N-channel field effect transistor having a gate connected with a bias voltage, the sixth N-channel field effect transistor being used as a bias current source of the fifth N-channel field effect transistor, and a fourth P-channel field effect transistor electrically connected with the fifth N-channel field effect transistor. 2. The readout circuit according to claim 1, wherein 3. The readout circuit according to claim 2, wherein 4. The readout circuit according to claim 3, wherein A fifth P-channel field effect transistor electrically connected with the fourth P-channel field effect transistor, and the fifth P-channel field effect transistor and the fourth P-channel field effect transistor constitute a current mirror; A seventh N-channel field effect transistor electrically connected with the fifth P-channel field effect transistor, a gate of the seventh N-channel field effect transistor being connected with a bias voltage, and the seventh N-channel field effect transistor being used as a bias current source of the fifth P-channel field effect transistor; A second capacitor electrically connected with the fifth N-channel field effect transistor, and the second capacitor being used as a bypass capacitor of the fifth N-channel field effect transistor.
5. The readout circuit according to claim 4, wherein The switch circuit comprises: A sixth P-channel field effect transistor, a gate of the sixth P-channel field effect transistor being connected with CTRL, and the sixth P-channel field effect transistor being electrically connected with a drain of the second N-channel field effect transistor and a drain of the fifth P-channel field effect transistor respectively.
6. The readout circuit according to claim 5, wherein The negative impedance conversion unit comprises: A first capacitor electrically connected with the pixel array unit; A third N-channel field effect transistor, a gate of the third N-channel field effect transistor being electrically connected with a bias voltage; A fourth N-channel field effect transistor, a gate of the fourth N-channel field effect transistor being electrically connected with the pixel array unit, a drain of the fourth N-channel field effect transistor being connected with a power supply, and a source of the fourth N-channel field effect transistor being electrically connected with a drain of the third N-channel field effect transistor; One end of the first capacitor is electrically connected with the source of the fourth N-channel field effect transistor, and the other end of the first capacitor is electrically connected with the current mirror circuit unit.
7. The readout circuit according to claim 6, wherein The current mirror circuit unit further comprises: Two N-channel field effect transistors connected through common-source and common-gate, a gate of the two N-channel field effect transistors being connected with a bias voltage, and a source of the two N-channel field effect transistors being electrically connected with the pixel array unit, the negative impedance conversion unit and the charge acceleration unit respectively.
8. The readout circuit according to claim 2, wherein The charge acceleration unit comprises: A rising voltage-current conversion circuit and / or a falling voltage-current conversion circuit.
9. A readout system for image sensing, characterized in that, An image sensing readout system using the readout circuit according to any one of claims 1 to 8, the readout system further comprising: A pixel driving module, the pixel driving module comprising a plurality of pixel array units; A pixel noise detection module, the pixel noise detection module being electrically connected with the pixel driving module, and the pixel noise detection module being used for detecting the pixel array units in the pixel driving module; A reference slope generation module, the reference slope generation module being electrically connected with the pixel driving module; A comparator, the comparator being electrically connected with the readout circuit and the reference slope generation module respectively; A counter, the counter being electrically connected with the comparator; A data transmission module, the data transmission module being electrically connected with the counter.
10. A solid-state imaging device, characterized by comprising: An image sensing readout system using the readout circuit according to any one of claims 1 to 8 or using the image sensing readout system according to claim 9.