BUCK circuit lower transistor driving circuit power supply, switching power supply chip

Abstract

The embodiment of the application provides a BUCK circuit lower tube driving circuit power supply, a BUCK circuit, and a switching power supply chip, the power supply comprises an error current generation module, an error current processing module, and a power supply output module, the error current processing module comprises an error voltage generation circuit, a transient load response capacitor, and a first CASCODE current mirror circuit, the error voltage generation circuit receives error current generated by the error current generation module to output error voltage, one end of the transient load response capacitor is connected with an output end of the error current processing module, the other end is connected with a gate of a common source end of the first CASCODE current mirror circuit, and the output end of the error voltage generation circuit serves as the output end of the error current processing module. The transient load response is good, the rising edge time of the power MOS tube is very short, the switching speed is fast, the cross-over loss is reduced, on the other hand, an external large-capacity capacitor is not needed, PIN pins are saved, and material cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of switching power supplies, and in particular to a power supply for a BUCK circuit lower transistor drive circuit, a BUCK circuit, and a switching power supply chip. Background Technology

[0002] In a BUCK synchronous rectifier circuit, the power MOSFET connected to the input terminal and the switching terminal is generally called the upper MOSFET; the power MOSFET connected to the switching terminal and the ground terminal is generally called the lower MOSFET.

[0003] When the switching power supply is working, the power MOSFET has a large C GS When the power MOSFET is switching at high speed, the drive power supply needs to provide a good power supply. This "good" generally includes: 1) the drive power supply can quickly provide power to the capacitor (C) of the power MOSFET when it needs to be turned on. GS Capacitor charging increases the rise time of the gate voltage of the power MOSFET, enabling the MOSFET to conduct at high speed, reducing crossover losses, and improving the overall system efficiency; 2) C GS Once the capacitor is fully charged, the power MOSFET can quickly reduce or stop the power supply, thereby reducing the overshoot voltage on the gate of the power MOSFET and preventing it from being damaged by high voltage.

[0004] To achieve high-performance power supply for the lower-side power MOSFET, a common practice is to add a large-capacity capacitor outside the chip. This capacitor is connected in parallel with the output of the lower-side drive power supply. When the lower-side power MOSFET requires a large transient current, this capacitor can provide a strong current output capability. Since the external large-capacity capacitor is much larger than the internal circuit, it can also stabilize the voltage of the lower-side drive power supply very well, thereby meeting the general requirements of the lower-side drive power supply.

[0005] While external capacitors can effectively solve the power supply problem for the lower-side power MOSFET, they also have several drawbacks: firstly, they require a chip pin, which can lead to a shortage of commonly used package pins in some situations, forcing the sacrifice of some very useful functions; secondly, using a relatively large external capacitor increases material costs, making it difficult to stand out in an increasingly competitive market. Summary of the Invention

[0006] To overcome the shortcomings of the prior art, this invention provides a power supply for the lower transistor drive circuit of a BUCK circuit, a BUCK circuit, and a switching power supply chip. This power supply has good transient load response and a very short rise time of the power MOSFET, thereby achieving fast conduction speed and reducing crossover losses. On the other hand, it eliminates the need for external large-capacity capacitors, saves pins, reduces material costs, and makes the finished power supply more competitive.

[0007] To achieve the above objectives, embodiments of the present invention provide a power supply for the lower transistor drive circuit of a BUCK circuit, including an error current generation module, an error current processing module, and a power output module.

[0008] The error current generation module generates an error current by utilizing the error between the output voltage and the reference voltage fed back by the power output module.

[0009] The error current processing module includes an error voltage generation circuit, a transient load response capacitor, and a first CASCODE current mirror circuit. The error voltage generation circuit receives the error current generated by the error current generation module and outputs an error voltage. One end of the transient load response capacitor is connected to the output terminal of the error current processing module, and the other end is connected to the gate of the common source terminal of the first CASCODE current mirror circuit. The output terminal of the error voltage generation circuit serves as the output terminal of the error current processing module.

[0010] The power output module is connected to the output terminal of the error current processing module, generates an output voltage using the error voltage, and feeds the output voltage back to the error current generation module.

[0011] Optionally, the error current processing module includes PMOS transistors PM7 and PM8, NMOS transistors NM9, NM10, NM11, and NM12, and a transient load response capacitor C1. PMOS transistors PM7 and PM8 form an error voltage generation circuit. The source of PMOS transistor PM7 is connected to the first input terminal of the error current processing module to input a sixth current I6. PMOS transistor PM8 is connected to the second input terminal of the error current processing module to input a seventh current I7. The sixth current I6 and the seventh current I7 are the error currents generated by the error current generation module. The gates of PMOS transistors PM7 and PM8 are connected to the drains of PMOS transistor PM8, the drain of NMOS transistor NM10, and the transient load response capacitor C1. One end of capacitor C1 is connected, and the drain of PMOS transistor PM8 serves as the output terminal of the error current generation circuit and also as the output terminal of the error current processing module; NMOS transistors NM9, NMOS transistor NM10, NMOS transistor NM11, and NMOS transistor NM12 constitute the first CASCODE current mirror circuit. The drain of NMOS transistor NM9 is connected to the drain of PMOS transistor PM7 and to the gate of NMOS transistor NM9 and the gate of NMOS transistor NM10. The source of NMOS transistor NM9 is connected to the drain and gate of NMOS transistor NM11 and to the gate of NMOS transistor NM12 and the other end of transient load response capacitor C1. The sources of NMOS transistor NM11 and NMOS transistor NM12 are grounded, and the drain of NMOS transistor NM12 is connected to the source of NMOS transistor NM10.

[0012] Optionally, the capacitance value of the transient load response capacitor C1 is in the range of 0.5pF to 10pF.

[0013] Optionally, it also includes a bias current generation module, which provides bias current to the error current generation module and the power output module.

[0014] Optionally, the bias current generation module includes a reference current source IREF, PMOS transistors PM1, PM2, NMOS transistors NM1, NMOS transistors NM2, NMOS transistors NM3, and NMOS transistors NM4. The NMOS transistors NM1, NM2, NM3, and NM4, together with the NMOS transistors NM5 and NM6 of the error current generation module, constitute a second CASCODE current mirror circuit. The second CASCODE current mirror circuit provides bias current to the power output module and the error current generation module. The PMOS transistors PM1 and PM2, together with the PMOS transistors PM3, PM4, PM5, and PM6 of the error current generation module, constitute a third CASCODE current mirror circuit. The third CASCODE current mirror circuit provides bias current to the error current generation module.

[0015] Optionally, one end of the reference current source IREF is connected to the operating voltage VDD, and the other end is connected to the gates of NMOS transistors NM3, NM4, and NM5, and the drain of NMOS transistor NM3. The source of NMOS transistor NM3 is connected to the gates of NMOS transistors NM1, NM2, and NM6, the drain of NMOS transistor NM1, and the power output module. The sources of NMOS transistors NM1 and NM2 are grounded. The drain of NMOS transistor NM2 and the source of NMOS transistor NM4 are connected. The source of PMOS transistor PM1 is connected to the power supply voltage VCC. The gate and drain of PMOS transistor PM1 are connected to the source of PMOS transistor PM2 and to the gates of PMOS transistors PM3 and PM5 in the error current generation module. The gate and drain of PMOS transistor PM2 are connected to the drain of NMOS transistor NM4 and to the gates of PMOS transistors PM4 and PM6 in the error current generation module.

[0016] Optionally, the error current generation module includes PMOS transistors PM3, PM4, PM5, PM6, NMOS transistors NM5, NM6, NM7, and NM8. The sources of PMOS transistors PM3 and PM5 are connected to the power supply voltage VCC. The gates of PMOS transistors PM3 and PM5 are connected. The drain of PMOS transistor PM3 is connected to the source of PMOS transistor PM4. The drain of PMOS transistor PM5 is connected to the source of PMOS transistor PM6. The gates of PMOS transistors PM4 and PM6 are connected. The drain of PMOS transistor PM4 is connected to the drain of NMOS transistor NM7. The gate of NMOS transistor NM7 is connected to the source of PMOS transistor PM4. The PMOS transistor PM6 is connected to an external reference voltage. The drain of the PMOS transistor PM6 is connected to the drain of the NMOS transistor NM8. The gate of the NMOS transistor NM8 is connected to the output voltage feedback terminal of the power output module. The sources of the NMOS transistors NM7 and NM8 are connected and connected to the drain of the NMOS transistor NM5. The source of the NMOS transistor NM5 is connected to the drain of the NMOS transistor NM6. The source of the NMOS transistor NM6 is grounded. The output terminal where the drain of the PMOS transistor PM4 is connected to the drain of the NMOS transistor NM7 serves as the first output terminal of the error current generation module, outputting the sixth current I6. The output terminal where the drain of the PMOS transistor PM6 is connected to the drain of the NMOS transistor NM8 serves as the second output terminal of the error current generation module, outputting the seventh current I7.

[0017] Optionally, NMOS transistors NM1, NM2, and NM6 are low-voltage MOS transistors of the same type, while NMOS transistors NM3, NM4, and NM5 are high-voltage MOS transistors of the same type. The channel width-to-length ratio of NMOS transistors NM1 and NM2 is 1:M, the channel width-to-length ratio of NMOS transistors NM3 and NM4 is 1:M, and the channel width-to-length ratio of NMOS transistors NM2 and NM6 is 1:N. The channel width-to-length ratio of NMOS transistors NM4 and NM5 is 1:N; PMOS transistors PM3, PM5, and PM1 are low-voltage MOS transistors of the same type, while PMOS transistors PM4, PM6, and PM2 are high-voltage MOS transistors of the same type. The channel width-to-length ratio of PMOS transistors PM1 and PM3 is 1:N, and the channel width-to-length ratio of PMOS transistors PM2 and PM4 is 1:N, where M and N are greater than or equal to 1.

[0018] This invention also provides a BUCK circuit, including a power MOSFET located at the switching terminal and the ground terminal, wherein the power supply of the gate drive circuit of the power MOSFET is the power supply of the lower transistor drive circuit of the BUCK circuit described above.

[0019] This invention also provides a switching power supply chip, including the BUCK circuit described above.

[0020] In summary, the beneficial effects of the present invention are as follows:

[0021] This invention provides a power supply for a BUCK circuit's lower transistor drive circuit, including an error current generation module, an error current processing module, and a power output module. The error current processing module includes an error voltage generation circuit, a transient load response capacitor, and a first CASCODE current mirror circuit. The error voltage generation circuit receives the error current generated by the error current generation module and outputs an error voltage. One end of the transient load response capacitor is connected to the output terminal of the error current processing module, and the other end is connected to the gate of the common source terminal of the first CASCODE current mirror circuit. The output terminal of the error voltage generation circuit serves as the output terminal of the error current processing module. This invention utilizes the first CASCODE current mirror circuit and the transient load response capacitor, resulting in good transient load response and a very short rise time for the power MOSFET, thereby achieving fast turn-on speed and reducing crossover losses. Furthermore, it eliminates the need for external large-capacity capacitors, saving pins, reducing material costs, and making the finished power supply more competitive.

[0022] To make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0023] Figure 1 The diagram shown is a schematic diagram of the circuit module structure of the power supply for the lower transistor drive circuit of the BUCK circuit according to an embodiment of the present invention.

[0024] Figure 2 The diagram shown is a schematic diagram of the power supply structure of the lower transistor drive circuit of the BUCK circuit according to an embodiment of the present invention.

[0025] Figure 3 The diagram shown is a waveform of the working state of the lower transistor drive circuit in the prior art BUCK circuit when powered.

[0026] Figure 4 The diagram shown is a waveform diagram of the working state of the lower transistor drive circuit of the BUCK circuit in an embodiment of the present invention when powered. Detailed Implementation

[0027] To facilitate understanding by those skilled in the art, the present invention will be further described in detail below with reference to specific embodiments.

[0028] This invention provides a power supply for the lower transistor drive circuit of a BUCK circuit. Please refer to [link / reference]. Figure 1 It includes a bias current generation module STAGE1, an error current generation module STAGE2, an error current processing module STAGE3, and a power output module STAGE4.

[0029] The bias current generation module STAGE1 provides bias current for the error current generation module and the power output module;

[0030] The error current generation module STAGE2 generates an error current by using the error between the output voltage and the reference voltage fed back by the power output module STAGE4.

[0031] The error current processing module STAGE3 includes an error voltage generation circuit, a transient load response capacitor, and a first CASCODE current mirror circuit. The error voltage generation circuit receives the error current generated by the error current generation module and outputs an error voltage. One end of the transient load response capacitor is connected to the output terminal of the error current processing module, and the other end is connected to the gate of the common source terminal of the first CASCODE current mirror circuit. The output terminal of the error voltage generation circuit serves as the output terminal of the error current processing module.

[0032] The power output module STAGE4 is connected to the output terminal of the error current processing module STAGE3. It generates an output voltage using the error voltage and feeds the output voltage back to the error current generation module STAGE2.

[0033] In this embodiment, please refer to Figure 2The bias current generation module STAGE1 includes a reference current source IREF, PMOS transistors PM1 and PM2, NMOS transistors NM1, NMOS transistors NM2, NMOS transistors NM3 and NMOS transistors NM4. One end of the reference current source IREF is connected to the operating voltage VDD, and the other end is connected to the gates of NMOS transistors NM3, NM4, and NM5, and the drain of NMOS transistor NM3. The source of NMOS transistor NM3 is connected to the gates of NMOS transistors NM1, NM2, and NM6, and the drain of NMOS transistor NM1. Connected to the power output module, the source of NMOS transistor NM1 and the source of NMOS transistor NM2 are grounded, the drain of NMOS transistor NM2 and the source of NMOS transistor NM4 are connected, the source of PMOS transistor PM1 is connected to the power supply voltage VCC, the gate and drain of PMOS transistor PM1 are connected to the source of PMOS transistor PM1 and are also connected to the gates of PMOS transistor PM3 and PMOS transistor PM5 of the error current generation module; the gate and drain of PMOS transistor PM2 are connected to the drain of NMOS transistor NM4 and are also connected to the gates of PMOS transistor PM4 and PMOS transistor PM6 of the error current generation module.

[0034] Please refer to Figure 2The error current generation module STAGE2 includes PMOS transistors PM3, PM4, PM5, PM6, NMOS transistors NM5, NM6, NM7, and NM8. The sources of PMOS transistors PM3 and PM5 are connected to the power supply voltage VCC. The gates of PMOS transistors PM3 and PM5 are connected. The drain of PMOS transistor PM3 is connected to the source of PMOS transistor PM4. The drain of PMOS transistor PM5 is connected to the source of PMOS transistor PM6. The gates of PMOS transistors PM4 and PM6 are connected. The drain of PMOS transistor PM4 is connected to the drain of NMOS transistor NM7. The gate of NMOS transistor NM7 is... The PMOS transistor PM6 is connected to an external reference voltage VREF. The drain of the PMOS transistor PM6 is connected to the drain of the NMOS transistor NM8. The gate of the NMOS transistor NM8 is connected to the output voltage feedback terminal of the power output module. The sources of the NMOS transistors NM7 and NM8 are connected and connected to the drain of the NMOS transistor NM5. The source of the NMOS transistor NM5 is connected to the drain of the NMOS transistor NM6. The source of the NMOS transistor NM6 is grounded. The output terminal where the drain of the PMOS transistor PM4 is connected to the drain of the NMOS transistor NM7 serves as the first output terminal of the error current generation module, outputting the sixth current I6. The output terminal where the drain of the PMOS transistor PM6 is connected to the drain of the NMOS transistor NM8 serves as the second output terminal of the error current generation module, outputting the seventh current I7.

[0035] The NMOS transistors NM1, NM2, NM3, NM4, NM5, and NM6 constitute a second CASCODE current mirror circuit, which provides bias current to the power output module. The PMOS transistors PM1, PM2, PM3, PM4, PM5, and PM6 constitute a third CASCODE current mirror circuit, which provides bias current to the error current generation module.

[0036] Since VDD is the internal power supply, it is usually a low-voltage power supply (less than 5V), and IREF is the reference current source used to provide the reference current, the magnitude of which is I1.

[0037] The NMOS transistors NM1, NM2, and NM6 are low-voltage MOS transistors of the same type, and the NMOS transistors NM3, NM4, and NM5 are high-voltage MOS transistors of the same type. The high-voltage MOS transistors of the same type can be used with the minimum allowable size to reduce the layout area.

[0038] In this embodiment, the channel width-to-length ratio of NMOS transistors NM1 and NM2 is 1:M, the channel width-to-length ratio of NMOS transistors NM3 and NM4 is 1:M, the channel width-to-length ratio of NMOS transistors NM2 and NM6 is 1:N, and the channel width-to-length ratio of NMOS transistors NM4 and NM5 is 1:N. NMOS transistors NM1 and NM2 are mainly used for current replication. The number of NMOS transistors NM1 can be greater than the number of NMOS transistors NM3. NMOS transistors NM3 and NM4 are used to withstand higher voltages and improve the accuracy of current replication. Using the second CASCODE current mirror circuit, ideally, the replicated current is: I2 = I1 * M.

[0039] Since the current flowing through PMOS transistors PM1 and PM2 is I2, and PMOS transistor PM1 is a low-voltage MOS transistor, the current matching accuracy is improved by using multiple low-voltage MOS transistors; PMOS transistor PM2 is a high-voltage MOS transistor, and similarly, in order to save area, PMOS transistor PM2 can be used with the minimum allowable size.

[0040] The embodiments of the present invention achieve high-precision current replication by using a large number of low-voltage MOSFETs, while using as few high-voltage MOSFETs as possible to reduce the area, thus achieving a balance between area and performance.

[0041] The channel width-to-length ratio of the different MOSFETs can be achieved using different methods. For example, when the channel lengths of NMOS transistors NM1 and NM2 are equal, but the width of NMOS transistor NM2 is M times the width of NMOS transistor NM1, a 1:M ratio can be achieved. Alternatively, when the basic dimensions of NMOS transistor NM1 and NMOS transistor NM2 are exactly the same, but NMOS transistor NM1 consists of m1 MOSFET cells connected in parallel, and NMOS transistor NM2 consists of m2 MOSFET cells connected in parallel, where m2 / m1 = M. Because the cell size of low-voltage MOSFETs is extremely small, even if multiple are used, they will not occupy a large area, and are much smaller than the size of high-voltage MOSFETs, which is beneficial for improving the accuracy of current replication.

[0042] In this embodiment, PMOS transistors PM3, PM5, and PM1 are low-voltage MOS transistors of the same type, while PMOS transistors PM4, PM6, and PM2 are high-voltage MOS transistors of the same type. The channel width-to-length ratio of PMOS transistors PM1 and PM3 is 1:N, and the channel width-to-length ratio of PMOS transistors PM2 and PM4 is also 1:N.

[0043] Since PMOS transistors PM3, PM5, and PM1 are all low-voltage MOS transistors of the same type, and there can be multiple PMOS transistors PM1, PMOS transistors PM3 and PM5 can use a relatively large number of low-voltage MOS transistor cells.

[0044] The channel width-to-length ratio of PMOS transistors PM4 and PM6 is 1:1, the channel width-to-length ratio of PMOS transistors PM2 and PM4 is 1:N, the channel width-to-length ratio of PMOS transistors PM3 and MP5 is 1:1, and the channel width-to-length ratio of PMOS transistors PM1 and PM3 is 1:N. Since PMOS transistors PM1, PM2, PM3, PM4, PM5, and PM6 constitute the third CASCODE current mirror circuit, the use of more low-voltage MOS transistors improves the accuracy of current replication, and the output impedance of this stage is increased, thereby achieving a greater open-loop gain and improving the accuracy of the output voltage.

[0045] The NMOS transistors NM7 and NM8 form a differential circuit. NMOS transistors NM7 and NM8 are low-voltage MOS transistors of the same type with a channel width-to-length ratio of 1:1. To achieve better matching, NMOS transistors NM7 and NM8 typically have a large number of low-voltage MOS transistor cells. Since the gate of NMOS transistor NM7 is connected to an external reference voltage VREF, and the gate of NMOS transistor NM8 is connected to the output voltage feedback terminal VFB of the power output module, when the two gate voltages of NMOS transistors NM7 and NM8 are different, different currents flow through them, resulting in different outputs I6 and I7, thus achieving voltage-to-current conversion.

[0046] Since the channel width-to-length ratio of NMOS transistor NM2 to NMOS transistor NM6 is 1:N, the channel width-to-length ratio of NMOS transistor NM4 to NMOS transistor NM5 is also 1:N.

[0047] If configured as described above, then:

[0048] I3 = I4 = I5 = I2 * N

[0049] When VREF = VFB, the system is in a steady state. At this time:

[0050]

[0051] When a small signal is superimposed on the system:

[0052]

[0053]

[0054] Where gm is the transconductance of NM7 and NM8, ΔV = VREF - VFB, I3 is the third current flowing through PMOS transistor PM3, I4 is the fourth current flowing through PMOS transistor PM5, I5 is the fifth current flowing through NMOS transistor NM5, I6 is the sixth current shunted from the third current I3 and output to the error current processing module through the first output terminal of the error current generation module, and I7 is the seventh current shunted from the fourth current I4 and output to the error current processing module through the second output terminal of the error current generation module.

[0055] In this embodiment, please refer to Figure 2The error current processing module includes PMOS transistors PM7 and PM8, NMOS transistors NM9, NM10, NM11, and NM12, and a transient load response capacitor C1. PMOS transistors PM7 and PM8 form an error voltage generation circuit. The source of PMOS transistor PM7 is connected to the first input terminal of the error current processing module to input a sixth current I6. PMOS transistor PM8 is connected to the second input terminal of the error current processing module to input a seventh current I7. The sixth current I6 and the seventh current I7 are the error currents generated by the error current generation module. The gates of PMOS transistors PM7 and PM8 are connected to the drains of PMOS transistor PM8, NMOS transistor NM10, and the transient load response capacitor C1. One end of 1 is connected, and the drain of the PMOS transistor PM8 serves as the output terminal of the error current generation circuit and also as the output terminal of the error current processing module; the NMOS transistors NM9, NMOS transistor NM10, NMOS transistor NM11, and NMOS transistor NM12 constitute the first CASCODE current mirror circuit. The drain of the NMOS transistor NM9 is connected to the drain of the NMOS transistor NM7 and to the gate of the NMOS transistor NM9 and the gate of the NMOS transistor NM10. The source of the NMOS transistor NM9 is connected to the drain and gate of the NMOS transistor NM11 and to the gate of the NMOS transistor NM12 and the other end of the transient load response capacitor C1. The sources of the NMOS transistors NM11 and NMOS transistor NM12 are grounded, and the drain of the NMOS transistor NM12 is connected to the source of the NMOS transistor NM10.

[0056] In this embodiment, the PMOS transistors PM7 and PM8 in the error voltage generation circuit are low-voltage MOS transistors of the same type, and their channel width-to-length ratio is 1:1. When the same current flows through them, i.e., when I6 and I7 are the same, the voltage V of PMOS transistor PM7 is... GS V with PMOS transistor PM8 GS Since the voltages are consistent, the voltage at the first output terminal V1 of the error current generation module is basically the same as the voltage at the second output terminal V2 of the error current generation module. Since the gate voltages of PMOS transistors PM7 and PM8 are low, the voltage at points V1 and V2 can be clamped, so that PMOS transistors NM7 and NM8 do not bear high voltage. Therefore, PMOS transistors NM7 and NM8 can be designed using low-voltage MOS transistors to save chip area.

[0057] The error voltage generation circuit receives the currents I6 and I7, compares the difference between these two currents, and then adjusts the output voltage V3 of the error current processing module. When the current I7 increases and the current I6 decreases, the V3 voltage increases; when the current I7 decreases and the current I6 increases, the V3 voltage decreases. The V3 voltage output by the error current processing module drives the gate of the source follower of the power supply output module.

[0058] In this embodiment, NMOS transistors NM9 to NM12 are all low-voltage MOS transistors of the same type and have a channel width-to-length ratio of 1:1. Furthermore, the NMOS transistors NM9 to NM12 form a first CASCODE current mirror to improve the accuracy of the current and increase the output impedance.

[0059] The transient load response capacitor C1 is used to improve the transient load response speed of the system. The capacitance value of the transient load response capacitor C1 ranges from 0.5pF to 10pF, and in one embodiment, it is 1pF.

[0060] In this embodiment, please refer to Figure 2 The power output module STAGE4 includes NMOS transistors NM13, NM14, and NM15, an upper voltage divider resistor RT, and a lower voltage divider resistor RB. The drains of NMOS transistors NM13 and NM15 are connected to the supply voltage VCC. The gate of NMOS transistor NM13 is connected to the output terminal of the error current processing module. The source of NMOS transistor NM13 is connected to the gate of NMOS transistor NM15 and the drain of NMOS transistor NM14. The source of NMOS transistor NM14 is grounded, and the gate of NMOS transistor NM14 is connected to the second CASCODE current mirror circuit. NMOS transistor NM14 provides bias current for NMOS transistor NM13. The source of NMOS transistor NM15 is connected to one end of the upper voltage divider resistor RT and serves as the output terminal of the power output module. The other end of the upper voltage divider resistor RT is connected to one end of the lower voltage divider resistor RB and serves as the output voltage feedback terminal of the power output module. The other end of the lower voltage divider resistor RB is grounded.

[0061] In this embodiment, NMOS transistor NM14, along with NM1, NM2, and NM6, are low-voltage MOS transistors of the same type, used to replicate the current in STAGE1. The channel width-to-length ratio of NMOS transistor NM1 to NMOS transistor NM14 can be set according to requirements. NMOS transistor NM14 provides bias current for NMOS transistor NM13. NMOS transistor NM13 is a source follower. NMOS transistor NM13 receives the V3 voltage output from the error current processing module and adjusts the V4 voltage, using the V4 voltage to drive NMOS transistor NM15. NMOS transistors NM13 and NMOS transistor NM15 are high-voltage MOS transistors of the same type, with NMOS transistor NM15 directly used to drive the load. The area required for NMOS transistor NM15 will vary depending on the load current. In this system, NMOS transistors NM13 and NM15 are driven sequentially, so NM13 is much smaller than NM15. Typically, the ratio of NM13 to NM15 is 1:10, but other suitable ratios can be selected in other embodiments. Because the overall system voltage gain is very high, the function of setting the GATE_VDD voltage can be implemented. The setting method is as follows:

[0062]

[0063] GATE_VDD is the output terminal of this power supply, used to power the lower transistor drive circuit.

[0064] This invention also provides a BUCK circuit, including a power MOSFET located at the switching terminal and the ground terminal, i.e., the lower MOSFET, and the power supply of the gate drive circuit of the lower MOSFET is the power supply of the lower MOSFET drive circuit of the BUCK circuit described above.

[0065] This invention also provides a switching power supply chip, including the BUCK circuit described above.

[0066] Please refer to Figure 3 The figure shows the waveforms of a conventional lower-transistor drive circuit (without an external capacitor) used in existing technology when powered by the lower-transistor drive circuit. The upper half represents the output voltage GATE_VDD, and the lower half represents the voltage at the GATE terminal of the power MOSFET. As can be seen from the figure, in a conventional lower-transistor drive circuit, the GATE_VDD voltage drops significantly during power transistor switching, resulting in a slow response time. Simultaneously, the voltage rise at the GATE terminal of the power transistor is slow, which can negatively impact the efficiency of the power supply system.

[0067] Please refer to Figure 4The figure shows the waveform of the BUCK circuit's lower transistor drive circuit when powered by the present invention. The upper part is the output voltage GATE_VDD, and the lower part is the voltage at the GATE terminal of the power MOSFET. As can be seen from the figure, compared with the power supply of the prior art lower transistor drive circuit, the power supply provided by the present invention has a lighter GATE_VDD voltage drop and a shorter drop time when the lower transistor power MOSFET switches, resulting in a very good response. At the same time, the voltage rise speed at the lower transistor GATE terminal is much faster than that of the prior art lower transistor drive circuit (without external capacitor), requiring only about 0.0000001s to rise from 0V to nearly 5V, while the prior art lower transistor drive circuit requires about 0.0000007s. This will greatly reduce the crossover loss of the switching power supply system.

[0068] Finally, it should be noted that any modification or equivalent substitution of some or all of the technical features based on the device structure and the technical solutions of the embodiments of the present invention, without departing from the corresponding technical solutions of the present invention, shall fall within the patent scope of the device structure and the embodiments of the present invention.

Claims

1. A BUCK circuit lower transistor drive circuit power supply, characterized by, The error current generation module, the error current processing module, and the power output module are connected in series. The error current generation module generates error current by using the error between the output voltage and the reference voltage fed back by the power output module. The error current processing module comprises an error voltage generation circuit, a transient load response capacitor, and a first CASCODE current mirror circuit. The power output module is connected to the output end of the error current processing module, generates output voltage by using the error voltage, and feeds back the output voltage to the error current generation module.

2. The BUCK circuit lower transistor drive circuit power supply according to claim 1, wherein The error current processing module comprises PMOS tube PM7, PMOS tube PM8, NMOS tube NM9, NMOS tube NM10, NMOS tube NM11, NMOS tube NM12, and transient load response capacitor C1.

3. The BUCK circuit lower transistor drive circuit power supply according to claim 2, wherein The capacitor value of the transient load response capacitor C1 ranges from 0.5 pF to 10 pF.

4. The BUCK circuit lower transistor drive circuit power supply according to claim 1, wherein The bias current generation module provides bias current for the error current generation module and the power output module.

5. The BUCK circuit lower transistor drive circuit power supply according to claim 4, wherein The bias current generation module comprises a reference current source IREF, a PMOS tube PM1, a PMOS tube PM2, an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3, an NMOS tube NM4, the NMOS tube NM1, the NMOS tube NM2, the NMOS tube NM3, and the NMOS tube NM4 and an NMOS tube NM5 and an NMOS tube NM6 of an error current generation module constitute a second CASCODE current mirror circuit, the second CASCODE current mirror circuit is used for providing bias currents for a power supply output module and the error current generation module, the PMOS tube PM1 and the PMOS tube PM2 and a PMOS tube PM3 and a PMOS tube PM4 and a PMOS tube PM5 and a PMOS tube PM6 of the error current generation module constitute a third CASCODE current mirror circuit, and the third CASCODE current mirror circuit is used for providing bias currents for the error current generation module.

6. The BUCK circuit lower transistor drive circuit power supply according to claim 5, wherein One end of the reference current source IREF is connected with a working voltage VDD, the other end is connected with a gate of an NMOS tube NM3, a gate of an NMOS tube NM4, a gate of an NMOS tube NM5, and a drain of the NMOS tube NM3, a source of the NMOS tube NM3 is connected with a gate of an NMOS tube NM1, a gate of an NMOS tube NM2, a gate of an NMOS tube NM6, a drain of the NMOS tube NM1, and a power supply output module, sources of the NMOS tube NM1 and the NMOS tube NM2 are grounded, a drain of the NMOS tube NM2 and a source of the NMOS tube NM4 are connected, a source of the PMOS tube PM1 is connected with a supply voltage VCC, a gate and a drain of the PMOS tube PM1 are connected with a source of a PMOS tube PM2 and are connected with a gate of a PMOS tube PM3 and a gate of a PMOS tube PM5 of the error current generation module, a gate and a drain of the PMOS tube PM2 are connected with a drain of the NMOS tube NM4 and are connected with a gate of a PMOS tube PM4 and a gate of a PMOS tube PM6 of the error current generation module.

7. The BUCK circuit lower transistor drive circuit power supply according to claim 6, wherein The error current generation module comprises PMOS PM3, PMOS PM4, PMOS PM5, PMOS PM6, NMOS NM5, NMOS NM6, NMOS NM7 and NMOS NM8, the source of PMOS PM3 and the source of PMOS PM5 are connected with the supply voltage VCC, the gate of PMOS PM3 and the gate of PMOS PM5 are connected, the drain of PMOS PM3 is connected with the source of PMOS PM4, the drain of PMOS PM5 is connected with the source of PMOS PM6, the gate of PMOS PM4 and the gate of PMOS PM6 are connected, the drain of PMOS PM4 is connected with the drain of NMOS NM7, the gate of NMOS NM7 is connected with the reference voltage, the drain of PMOS PM6 is connected with the drain of NMOS NM8, the gate of NMOS NM8 is connected with the output voltage feedback end of the power output module, the source of NMOS NM7 and the source of NMOS NM8 are connected and connected with the drain of NMOS NM5, the source of NMOS NM5 is connected with the drain of NMOS NM6, the source of NMOS NM6 is grounded, wherein the output end, at which the drain of PMOS PM4 and the drain of NMOS NM7 are connected, outputs the sixth current I6 as the first output end of the error current generation module, and the output end, at which the drain of PMOS PM6 and the drain of NMOS NM8 are connected, outputs the seventh current I7 as the second output end of the error current generation module.

8. The BUCK circuit lower transistor drive circuit power supply according to claim 7, wherein The NMOS NM1, NMOS NM2 and NMOS NM6 are low-voltage MOS tubes of the same type, the NMOS NM3, NMOS NM4 and NMOS NM5 are high-voltage MOS tubes of the same type, the ratio of the channel width-length ratio of the NMOS NM1 and the NMOS NM2 is 1:M, the ratio of the channel width-length ratio of the NMOS NM3 and the NMOS NM4 is 1:M, the ratio of the channel width-length ratio of the NMOS NM2 and the NMOS NM6 is 1:N, and the ratio of the channel width-length ratio of the NMOS NM4 and the NMOS NM5 is 1:N; the PMOS PM3, PMOS PM5 and PMOS PM1 are low-voltage MOS tubes of the same type, the PMOS PM4, PMOS PM6 and PMOS PM2 are high-voltage MOS tubes of the same type, the ratio of the channel width-length ratio of the PMOS PM1 and the PMOS PM3 is 1:N, the ratio of the channel width-length ratio of the PMOS PM2 and the PMOS PM4 is 1:N, wherein M and N are greater than or equal to 1.

9. A BUCK circuit, characterized by, The power MOS tube gate drive circuit comprises a power MOS tube located between a switch end and a ground end, and a power supply of the power MOS tube gate drive circuit is a power supply of the lower tube drive circuit of the BUCK circuit.

10. A switching power supply chip, characterized by comprising: The BUCK circuit comprises the BUCK circuit of claim 9. The BUCK circuit comprises the BUCK circuit of claim 9.

Images