A memristor-based four-quadrant analog multiplier circuit and control method

Abstract

The present invention discloses a four-quadrant analog multiplier circuit and a control method based on a memristor. The analog multiplier circuit based on a memristor mainly includes a sign conversion circuit, an external control circuit, a memristor control circuit, a Cascode current mirror circuit composed of NMOS transistors, and a Cascode current mirror circuit composed of PMOS transistors. Among them, the Cascode current mirror circuit composed of NMOS transistors and the memristor control circuit form a first-quadrant memristor analog multiplier circuit, and the Cascode current mirror circuit composed of PMOS transistors and the memristor control circuit form a second-quadrant memristor analog multiplier circuit. The sign conversion circuit mainly converts the input signal into a signal in the first and second quadrants and inputs the signal into the corresponding quadrant memristor analog multiplier circuit. After receiving a positive input signal, the external control circuit outputs the control voltage required by the memristor analog multiplier circuit. Compared with the existing analog multiplier circuit, the memristor analog multiplier has higher linearity and accuracy, and the circuit structure and operation process are relatively simple.

Description

Technical Field

[0001] This invention relates to the field of technology, specifically to a four-quadrant analog multiplier circuit and control method based on memristors. Background Technology

[0002] Memristors, as an emerging basic circuit component, are characterized by their small size, high integration, and low power consumption. They are mainly used in fields such as information storage, memristor logic circuits, and memristor neural networks.

[0003] To facilitate the application of memristors in various fields of circuit design, research on combining memristors with traditional circuits has also seen significant development.

[0004] Multipliers are a fundamental arithmetic circuit widely used in modern electronic circuits. Currently, with the increasing research into the novel circuit element memristor, digital multiplier circuits based on memristors are emerging in large numbers, offering lower latency and power consumption compared to traditional digital multipliers. However, research on analog multiplier circuits based on memristors is scarce. Most existing two-quadrant analog multiplier circuits utilize the square characteristic of MOSFETs to construct the multiplication relationship, resulting in a relatively complex operation process.

[0005] Other analog multipliers with relatively large input and output signals have relatively complex circuit structures.

[0006] Furthermore, existing two-quadrant analog multipliers primarily use voltage and current signals as input signals, which limits the range and types of input signals. Summary of the Invention

[0007] The purpose of this invention is to provide a four-quadrant analog multiplier circuit and control method based on memristors to solve the problems mentioned in the background art.

[0008] To achieve the above objectives, the present invention provides the following technical solution: a four-quadrant analog multiplier circuit based on memristors, comprising a sign conversion circuit, an external control circuit, a memristor control circuit, a Cascode current mirror circuit composed of NMOS transistors and a Cascode current mirror circuit composed of PMOS transistors;

[0009] Its features are:

[0010] The input of the sign conversion circuit receives two signals, and the output of the sign conversion circuit outputs a positive signal to the Cascode current mirror circuit composed of NMOS transistors and a negative signal to the Cascode current mirror circuit composed of PMOS transistors.

[0011] The input terminal of the external control circuit receives another positive signal;

[0012] The output terminal of the external control circuit outputs the first control voltage to the Cascode current mirror circuit and memristor control circuit composed of NMOS transistors.

[0013] The output of the memristor control circuit is coupled with a Cascode current mirror circuit composed of an NMOS transistor and a Cascode current mirror circuit composed of a PMOS transistor.

[0014] The Cascode current mirror circuit, composed of a memristor control circuit, an NMOS transistor, and a PMOS transistor, outputs positive and negative voltages.

[0015] Preferably, the input terminal of the sign conversion circuit is connected to two input signals, and the output terminal of the sign conversion circuit is connected to the input terminal of the Cascode current mirror circuit composed of two NMOS transistors and the Cascode current mirror circuit composed of PMOS transistors, and provides an input signal source for the external control circuit. The sign conversion circuit is used to convert the positive and negative signs of the two input signals into the corresponding signs of the first and second quadrants, and inputs the signal that is always positive after conversion into the external control circuit, and inputs the other positive or negative signal into the corresponding Cascode current mirror circuit composed of NMOS transistors and the Cascode current mirror circuit composed of PMOS transistors.

[0016] Preferably, the external control circuit determines the required external control voltage for the output based on the positive input signal;

[0017] The input terminals of the Cascode current mirror circuit composed of NMOS transistors and the Cascode current mirror circuit composed of PMOS transistors are connected to the output terminal of the sign conversion circuit. The output terminals of the Cascode current mirror circuit composed of NMOS transistors and the Cascode current mirror circuit composed of PMOS transistors are connected to the first and second control voltages of the external control circuit.

[0018] The memristors in the memristor control circuit are connected to the output terminals of the Cascode current mirror circuit composed of different MOS transistors, forming a memristor analog multiplier in the first and second quadrants. The memristor value in the memristor control circuit is the value of one of the positive signals output by the sign conversion circuit. The memristor value in the memristor control circuit is obtained by controlling the first to ninth control voltages of the external control circuit.

[0019] Preferably, the sign conversion circuit includes converting two negative signals into two positive signals when two negative signals are input, and inputting one of the positive values ​​into a Cascode current mirror circuit mainly composed of NMOS transistors, and inputting the other positive value into an external control circuit.

[0020] When two positive signals are input, no sign conversion is performed. Instead, one of the positive values ​​is directly input into the Cascode current mirror circuit, which is mainly composed of NMOS transistors, through the sign conversion circuit.

[0021] Input another positive value into the external control circuit;

[0022] When two signals, one positive and one negative, are input, no sign conversion is performed. The negative value is directly input to the Cascode current mirror circuit, which is mainly composed of PMOS transistors, through the sign conversion circuit, while the positive value is input to the external control circuit.

[0023] Preferably, the external control circuit includes a circuit operating mode, wherein the operating mode of the external control circuit is jointly controlled by the voltages of the first to eighth output terminals. The first output terminal is connected to the output terminal of the Cascode current mirror circuit composed of NMOS transistors and generates a first control voltage signal; the second output terminal is connected to the output terminal of the Cascode current mirror circuit composed of PMOS transistors and generates a second control voltage signal; the third output terminal is connected to the control terminal of the first PMOS transistor and generates a third control voltage signal.

[0024] The fourth output terminal is connected to the control terminal of the second PMOS transistor and generates a fourth control voltage signal; the fifth output terminal is connected to the control terminal of the third NMOS transistor and generates a fifth control voltage signal; the sixth output terminal is connected to the control terminal of the fourth NMOS transistor and generates a sixth control voltage signal; the seventh output terminal is connected to the control terminal of the fifth PMOS transistor and generates a seventh control voltage signal; and the eighth output terminal is connected to the control terminal of the sixth PMOS transistor and generates an eighth control voltage signal.

[0025] Preferably, the memristor control circuit includes a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, and a fixed voltage source, wherein one end of the first PMOS transistor is connected to the fixed voltage source, the control terminal of the first PMOS transistor is connected to a third control voltage signal, and the other end of the first PMOS transistor is connected to one end of the third NMOS transistor and one end of the fifth PMOS transistor;

[0026] One end of the second PMOS transistor is connected to a fixed voltage source, the control terminal of the second PMOS transistor is connected to a fourth control voltage signal, and the other end of the second PMOS transistor is connected to one end of a fourth NMOS transistor.

[0027] One end of the third NMOS transistor is connected to the other end of the first PMOS transistor and one end of the sixth PMOS transistor. The control terminal of the third NMOS transistor is connected to the fifth control voltage signal, and the other end of the third NMOS transistor is connected to ground.

[0028] One end of the fourth NMOS transistor is connected to one end of the second PMOS transistor and one end of the sixth PMOS transistor, the control terminal of the fourth NMOS transistor is connected to the sixth control voltage signal, and the other end of the fourth NMOS transistor is connected to ground;

[0029] One end of the fifth PMOS transistor is connected to the positive terminal of the memristor, the control terminal of the fifth PMOS transistor is connected to the seventh control voltage signal, and the other end of the fifth PMOS transistor is connected to one end of the first PMOS transistor and one end of the third NMOS transistor.

[0030] One end of the sixth PMOS transistor is connected to the negative terminal of the memristor and one end of the eighth NMOS transistor. The control terminal of the sixth PMOS transistor is connected to the eighth control voltage signal. The other end of the sixth PMOS transistor is connected to one end of the second PMOS transistor and one end of the fourth NMOS transistor.

[0031] When the memristor control circuit operates in a first-quadrant memristor analog multiplier, T5 and T6 are NMOS transistors, and their connection method is the same as that of PMOS transistors.

[0032] Preferably, the Cascode current mirror circuit composed of NMOS transistors includes a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, resistors R1, R2, and R3, wherein: one end of the seventh NMOS transistor is connected to one terminal of resistor R1, the control terminal of the seventh NMOS transistor is connected to the control terminal of the eighth NMOS transistor, and the other end of the seventh NMOS transistor is connected to one end of the ninth NMOS transistor; one end of the eighth NMOS transistor is connected to one end of resistor R3 and one end of the sixth PMOS transistor, the control terminal of the eighth NMOS transistor is connected to the control terminal of the seventh NMOS transistor, and the other end of the eighth NMOS transistor is connected to one end of the tenth NMOS transistor; one end of the ninth NMOS transistor is connected to one end of the seventh NMOS transistor. The control terminal of the ninth NMOS transistor is connected to the control terminal of the tenth NMOS transistor, and the other end of the ninth NMOS transistor is connected to ground; one end of the tenth NMOS transistor is connected to one end of the eighth NMOS transistor, the control terminal of the tenth NMOS transistor is connected to the control terminal of the ninth NMOS transistor, and the other end of the tenth NMOS transistor is connected to ground; one terminal of resistor R1 is connected to the first positive voltage signal output by the signal processing circuit and one end of the fifth PMOS transistor, and the other terminal of resistor R1 is connected to one end of the seventh NMOS transistor; one terminal of resistor R2 is connected to the first control voltage of the external control circuit, and the other terminal of resistor R2 is connected to the positive terminal of the memristor; one terminal of resistor R3 is connected to the negative terminal of the memristor, and the other terminal of resistor R3 is connected to the other end of the eighth NMOS transistor.

[0033] Preferably, the Cascode current mirror circuit (5), mainly composed of PMOS transistors, includes an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, resistors R4, R5, and R6, wherein:

[0034] One end of the eleventh PMOS transistor is connected to one terminal of resistor R4, the control terminal of the eleventh PMOS transistor is connected to the control terminal of the twelfth PMOS transistor, and the other end of the eleventh PMOS transistor is connected to one end of the thirteenth PMOS transistor.

[0035] One end of the twelfth PMOS transistor is connected to one end of resistor R6 and one end of the sixth PMOS transistor. The control terminal of the twelfth PMOS transistor is connected to the control terminal of the eleventh PMOS transistor. The other end of the twelfth PMOS transistor is connected to one end of the fourteenth PMOS transistor.

[0036] One end of the thirteenth PMOS transistor is connected to one end of the eleventh PMOS transistor, and the control terminal of the thirteenth PMOS transistor is connected to the control terminal of the fourteenth PMOS transistor. The other end of the thirteenth PMOS transistor is connected to ground. One end of the fourteenth PMOS transistor is connected to one end of the eleventh PMOS transistor, and the control terminal of the fourteenth PMOS transistor is connected to the control terminal of the thirteenth PMOS transistor. The other end of the fourteenth PMOS transistor is connected to ground. One terminal of resistor R4 is connected to the first negative voltage signal output by the signal processing circuit, and the other terminal of resistor R4 is connected to one end of the eleventh PMOS transistor. One terminal of resistor R5 is connected to the second control voltage of the external control circuit and one end of the fifth PMOS transistor, and the other terminal of resistor R5 is connected to the positive terminal of the memristor. One terminal of resistor R6 is connected to the negative terminal of the memristor, and the other terminal of resistor R6 is connected to the other end of the twelfth PMOS transistor.

[0037] A control method for a four-quadrant analog multiplier circuit based on memristors includes the following steps:

[0038] The symbol conversion circuit described above converts the two received actual signals into signals that can be multiplied in one quadrant or two quadrants.

[0039] The memristor value is obtained by controlling the change of a positive input signal through an external control circuit, which is then controlled by the third to eighth control voltages generated by the external control circuit.

[0040] The positive voltage signal converted by the sign conversion circuit can be received through a Cascode current mirror circuit composed of NMOS transistors, or the negative voltage signal converted by the sign conversion circuit can be received through a Cascode current mirror circuit composed of PMOS transistors.

[0041] The first and second control voltages output by the external control circuit control the Cascode current mirror circuit to perform a multiplication operation on the two input signals at its output terminal.

[0042] Compared with the prior art, the beneficial effects of the present invention are:

[0043] (1) The circuit structure is relatively simple, mainly composed of MOS transistors and memristors.

[0044] (2) The multiplication process is relatively simple, and the operations involved in the operation of the multiplier are relatively simple.

[0045] (3) It innovatively uses memristor value as an input signal of analog multiplier, which increases the range of input signals.

[0046] (4) The linearity and accuracy of this analog multiplier are high.

[0047] The above four aspects play a crucial role in the use of analog multipliers. Meanwhile, in the relevant control method, a received positive input signal is first converted using a formula by an external control circuit. Then, the external control circuit generates a control voltage, which in turn controls the memristor control circuit and the Cascode current mirror circuit, thereby achieving the multiplication of the two signals at the output of the Cascode current mirror circuit. Attached Figure Description

[0048] Figure 1 This is a structural diagram of a four-quadrant analog multiplier circuit based on memristors.

[0049] Figure 2 Provided by the present invention Figure 1 A schematic diagram of the symbol conversion circuit.

[0050] Figure 3 Provided by the present invention Figure 1 A schematic diagram of the external control circuit.

[0051] Figure 4 Provided by the present invention Figure 1 A schematic diagram of the memristor control circuit.

[0052] Figure 5 Provided by the present invention Figure 1 A schematic diagram of a Cascode current mirror circuit composed of NMOS transistors.

[0053] Figure 6 Provided by the present invention Figure 1 A schematic diagram of a Cascode current mirror circuit composed of PMOS transistors.

[0054] Figure 7 Provided in this invention Figure 4 and Figure 5 The circuit diagram after combination.

[0055] Figure 8 Provided in this invention Figure 4 and Figure 6 The circuit diagram after combination.

[0056] Figure 9 Provided in this invention Figure 1 Flowchart of the overall control method for the circuit.

[0057] Figure 1 The circuit consists of: 1. Symbol conversion circuit; 2. External control circuit; 3. Memristor control circuit; 4. Cascode current mirror circuit composed of NMOS transistors; 5. Cascode current mirror circuit composed of PMOS transistors. Detailed Implementation

[0058] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0059] Please see Figures 1-9 This invention provides a technical solution for a four-quadrant analog multiplier circuit and control method based on memristors: combining Figure 1As shown in the circuit diagram, the memristor-based four-quadrant analog multiplier circuit includes: a sign conversion circuit 1, an external control circuit 2, a memristor control circuit 3, a Cascode current mirror circuit 4 composed of NMOS transistors, and a Cascode current mirror circuit 5 composed of PMOS transistors. The sign conversion circuit 1 only needs to convert two negative signals into two positive signals. If the input signal is one positive and one negative, or two positive signals, no conversion is needed. Then, the external control circuit 2 determines the output external control voltage based on the input positive signal. The Cascode circuit composed of NMOS transistors receives the other positive signal, or the Cascode circuit composed of PMOS transistors receives the other negative signal. When the circuits are working, only one Cascode circuit will operate. The memristor control circuit 3 is controlled by an external control voltage to reach the value of the input positive signal. When the Cascode current mirror circuit 4, composed of NMOS transistors, is working, it uses the received positive signal as the input voltage at the circuit input terminal. Simultaneously, the external control voltage multiplies the memristor value and the input voltage at the output terminal of the current mirror circuit, resulting in a positive output voltage. When the Cascode current mirror circuit 5, composed of PMOS transistors, is working, it uses the received negative signal as the input voltage at the circuit input terminal. Simultaneously, the external control voltage multiplies the memristor value and the negative input voltage at the output terminal of the current mirror circuit, resulting in a negative output voltage. In this invention, combined with... Figure 2 Let's take a look. Figure 2 Provided by the present invention Figure 1 A schematic diagram of the symbol conversion circuit is shown. The symbol conversion circuit includes a symbol determination circuit and an absolute value circuit, wherein:

[0060] When both input signals are positive, no absolute value conversion is needed; the two signals are directly input to the external control circuit and the Cascode current mirror circuit composed of NMOS transistors. When one input signal is positive and the other is negative, no absolute value conversion is needed; the positive signal is directly input to the external control circuit, and the negative signal is input to the Cascode current mirror circuit composed of PMOS transistors. When both input signals are negative, the absolute value circuit converts the two signals into positive signals; one positive signal is input to the external control circuit, and the other signal is input to the Cascode current mirror circuit composed of NMOS transistors.

[0061] In this invention, combined with Figure 3 Let's take a look. Figure 3 Provided by the present invention Figure 1A schematic diagram of the external control circuit is shown. The external control circuit includes control modes, wherein: the control modes of the circuit include a first output terminal, a second output terminal, a third output terminal, a fourth output terminal, a fifth output terminal, a sixth output terminal, a seventh output terminal, and an eighth output terminal. The first output terminal is connected to the output terminal of the Cascode current mirror circuit composed of NMOS transistors and generates a first control voltage signal; the second output terminal is connected to the output terminal of the Cascode current mirror circuit composed of PMOS transistors and generates a second control voltage signal; the third output terminal is connected to the control terminal of the first PMOS transistor and generates a third control voltage signal; the fourth output terminal is connected to the control terminal of the second PMOS transistor and generates a fourth control voltage signal; the fifth output terminal is connected to the control terminal of the third NMOS transistor and generates a fifth control voltage signal; the sixth output terminal is connected to the control terminal of the fourth NMOS transistor and generates a sixth control voltage signal; the seventh output terminal is connected to the control terminal of the fifth PMOS transistor and generates a seventh control voltage signal; the eighth output terminal is connected to the control terminal of the sixth PMOS transistor and generates an eighth control voltage signal.

[0062] In this invention, combined with Figure 4 Let's take a look. Figure 4 Provided by the present invention Figure 1A schematic diagram of a memristor control circuit is shown. The memristor control circuit includes a first PMOS transistor T1, a second PMOS transistor T2, a third NMOS transistor T3, a fourth NMOS transistor T4, a fifth PMOS transistor T5, and a sixth PMOS transistor T6. Specifically: one end of the first PMOS transistor is connected to a fixed voltage source, and its control terminal is connected to a third control voltage signal; the other end of the first PMOS transistor is connected to one end of the third NMOS transistor and one end of the fifth PMOS transistor. One end of the second PMOS transistor is connected to a fixed voltage source, and its control terminal is connected to a fourth control voltage signal; the other end of the second PMOS transistor is connected to one end of the fourth NMOS transistor. One end of the third NMOS transistor is connected to the other end of the first PMOS transistor and one end of the sixth PMOS transistor; its control terminal is connected to the fifth control voltage signal. The third NMOS transistor... One end of the OS transistor is connected to ground; one end of the fourth NMOS transistor is connected to one end of the second PMOS transistor and one end of the sixth PMOS transistor; the control terminal of the fourth NMOS transistor is connected to the sixth control voltage signal; the other end of the fourth NMOS transistor is connected to ground; one end of the fifth PMOS transistor is connected to the positive terminal of the memristor; the control terminal of the fifth PMOS transistor is connected to the seventh control voltage signal; the other end of the fifth PMOS transistor is connected to one end of the first PMOS transistor and one end of the third NMOS transistor; one end of the sixth PMOS transistor is connected to the negative terminal of the memristor and one end of the eighth NMOS transistor; the control terminal of the sixth PMOS transistor is connected to the eighth control voltage signal; the other end of the sixth PMOS transistor is connected to one end of the second PMOS transistor and one end of the fourth NMOS transistor; the positive terminal of the memristor is connected to one end of the fifth PMOS transistor, and the negative terminal of the memristor is connected to one end of the sixth PMOS transistor;

[0063] When the memristor control circuit operates in the analog multiplier circuit of the first quadrant, T5 and T6 are NMOS transistors, and their connection method is the same as that of PMOS transistors.

[0064] The model description of the memristor of this invention is as follows:

[0065] v(t) = i(t)R(t);

[0066]

[0067]

[0068] in:

[0069]

[0070]

[0071]

[0072] R(t), v(t), and i(t) are the memristor value, voltage, and current at time t, respectively. on and R off These are the minimum and maximum memristor values.

[0073] ω(t) is the width of the doped region, D is the length of the memristor element, and μ v For ion mobility, This is a window function representing the nonlinear quantity in the memristor.

[0074] V T+ and V T- For positive and negative threshold voltages, i0, i on i off is a constant, and k is an intermediate variable.

[0075] Ignoring the MOSFET's on-state voltage, the quantitative relationship between time t, external voltage, control voltage, and memristor value can be derived from the memristor model as follows:

[0076]

[0077] The above formula expresses the precise relationship between the memristor's memristor value and the voltage application time t.

[0078] In this invention, an external control circuit receives the input positive signal, converts it using the formula described above, and then connects the specific voltage output by the external control circuit to the control terminal of the MOS transistor in the memristor control circuit, thereby controlling the memristor to obtain the required positive signal. The specific control process is as follows:

[0079] When the input positive signal is less than the initial memristor value, the rise time t required for the memristor is determined by the above formula. At this time, the first PMOS transistor T1 is turned off, the second PMOS transistor T2 is turned on, the third NMOS transistor T3 is turned on, the fourth NMOS transistor T4 is turned off, the fifth PMOS transistor is turned on, and the sixth PMOS transistor is turned on. The external control circuit controls the time t required for each MOS transistor to turn on or off. After the rise time t of the memristor value, the MOS transistor of the memristor control circuit is turned off, and the memristor value at this time is the required value.

[0080] When the input positive signal is greater than the initial memristor value, the time t required for the memristor to fall is determined by the above formula. At this time, the first PMOS transistor T1 is closed, the second PMOS transistor T2 is open, the third NMOS transistor T3 is open, the fourth NMOS transistor T4 is closed, the fifth PMOS transistor is closed, and the sixth PMOS transistor is closed. The time t required for each MOS transistor to close or open is controlled by the external control circuit. After the memristor value falls for time t, the MOS transistors of the memristor control circuit are disconnected, and the memristor value at this time is the required value.

[0081] In this invention, combined with Figure 5 Let's take a look. Figure 5 Provided by the present invention Figure 1 The diagram shows the structure of a Cascode current mirror circuit composed of NMOS transistors. This Cascode current mirror circuit includes a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, resistors R1, R2, and R3.

[0082] One end of the seventh NMOS transistor is connected to one terminal of R1, and the control terminal of the seventh NMOS transistor is connected to the control terminal of the eighth NMOS transistor. The other end of the seventh NMOS transistor is connected to one end of the ninth NMOS transistor. One end of the eighth NMOS transistor is connected to one end of resistor R3 and one end of the sixth PMOS transistor. The control terminal of the eighth NMOS transistor is connected to the control terminal of the seventh NMOS transistor, and the other end of the eighth NMOS transistor is connected to one end of the tenth NMOS transistor. One end of the ninth NMOS transistor is connected to one end of the seventh NMOS transistor, and the control terminal of the ninth NMOS transistor is connected to the control terminal of the tenth NMOS transistor. The other end of the transistor is connected to ground; one end of the tenth NMOS transistor is connected to one end of the eighth NMOS transistor, the control terminal of the tenth NMOS transistor is connected to the control terminal of the ninth NMOS transistor, and the other end of the tenth NMOS transistor is connected to ground; one terminal of resistor R1 is connected to the first positive voltage signal output by the signal processing circuit and one end of the fifth PMOS transistor, and the other terminal of resistor R1 is connected to one end of the seventh NMOS transistor; one terminal of R2 is connected to the first control voltage of the external control circuit, and the other terminal of R2 is connected to the positive terminal of the memristor; one terminal of R3 is connected to the negative terminal of the memristor, and the other terminal of R3 is connected to the other end of the eighth NMOS transistor;

[0083] In this invention, combined with Figure 6 Let's take a look. Figure 6 Provided by the present invention Figure 1 The diagram shows the structure of a Cascode current mirror circuit composed of PMOS transistors. The Cascode current mirror circuit includes an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, resistors R4, R5, and R6.

[0084] One end of the eleventh PMOS transistor is connected to one terminal of resistor R4, and the control terminal of the eleventh PMOS transistor is connected to the control terminal of the twelfth PMOS transistor. The other end of the eleventh PMOS transistor is connected to one end of the thirteenth PMOS transistor. One end of the twelfth PMOS transistor is connected to one end of resistor R6 and one end of the sixth PMOS transistor, and the control terminal of the twelfth PMOS transistor is connected to the control terminal of the eleventh PMOS transistor. The other end of the twelfth PMOS transistor is connected to one end of the fourteenth PMOS transistor. One end of the thirteenth PMOS transistor is connected to one end of the eleventh PMOS transistor, and the control terminal of the thirteenth PMOS transistor is connected to the control terminal of the fourteenth PMOS transistor. The other end of the thirteenth PMOS transistor is connected to ground; one end of the fourteenth PMOS transistor is connected to one end of the eleventh PMOS transistor, the control terminal of the fourteenth PMOS transistor is connected to the control terminal of the thirteenth PMOS transistor, and the other end of the fourteenth PMOS transistor is connected to ground; one terminal of resistor R4 is connected to the first negative voltage signal output by the signal processing circuit, and the other terminal of resistor R4 is connected to one end of the eleventh PMOS transistor; one terminal of resistor R5 is connected to one end of the PMOS transistor of the external control circuit, and the other terminal of resistor R5 is connected to the positive terminal of the memristor; one terminal of resistor R6 is connected to the negative terminal of the memristor, and the other terminal of resistor R6 is connected to the other end of the twelfth PMOS transistor.

[0085] Combination Figure 5 and Figure 6 Let's look at it this way: when the input signal is a positive signal, by... Figure 5 The Cascode current mirror circuit, composed of NMOS transistors, receives signals and begins operation; when the input signal is negative, it is controlled by... Figure 6 The Cascode current mirror circuit, composed of PMOS transistors, receives signals and begins operation. When a Cascode circuit starts operating, the input signal is treated as a voltage signal and applied to the input terminal of the circuit. At this time, the voltage drop across the MOS transistors is 2V. GS Therefore, the input current can be obtained as:

[0086]

[0087] set up:

[0088] VDD2=2V GS

[0089] Since the Cascode current mirror operates on the principle that the input current equals the output current, the output current is:

[0090]

[0091] When the memristor control circuit controls Rm to change to the input value, the voltage division of the output terminals Rm, R2, and R3 is as follows:

[0092]

[0093] Therefore, the multiplication output voltage is:

[0094]

[0095] The following is combined Figure 7 and Figure 8 The overall circuit structure of the memristor-based four-quadrant analog multiplier is explained in detail below:

[0096] When the input signal is two positive signals or two negative signals, such as Figure 7 The circuit shown begins operation by first using an external control circuit to calculate the value of a received positive signal using a formula. Then, external third-eighth control voltages control the memristor value to obtain this positive signal by changing the switching states of MOSFETs T1-T6. Next, the application time of VDD1 is controlled by a first external control voltage. Simultaneously with the application of the first external control voltage, another positive signal is connected to the input of the Cascode current mirror circuit. Figure 7 The input voltage is Vin1. Based on the principle that the currents across the current mirror circuit are equal, the output can obtain the value resulting from the multiplication of the two signals, and this value is positive. Figure 7 The output voltage Vout1.

[0097] When the input signal is two signals, one positive and one negative, such as Figure 8 The circuit shown begins operation by first using an external control circuit to calculate the required time for the memristor value to change from one of the received positive signals. External third-eighth control voltages then control the memristor value to match this positive signal by changing the switching states of MOSFETs T1-T6. Next, a second external control voltage controls the application time of VDD3. Simultaneously with the application of this second external control voltage, another negative signal is connected to the input of the Cascode current mirror circuit. Figure 8 The input voltage is Vin2. Based on the principle that the currents at both ends of the current mirror circuit are equal, the output can obtain the value resulting from the multiplication of the two signals, and this result is a negative value. For example... Figure 8 The output voltage Vout2.

[0098] This invention provides a control method for a four-quadrant analog multiplier based on memristors, combined with Figure 1 Let's take a look. Figure 9 The schematic flowchart of the control method based on a memristor four-quadrant analog multiplier provided by the present invention includes steps S1-S3, wherein:

[0099] In step S1, the positive input signal is converted into the control voltage output by the external control circuit through the formula transformation of R(t).

[0100] In step S2, the memristor value is adjusted to the same value as the input signal by the control output of the external control circuit.

[0101] In step S3, after the memristor value is adjusted, another input signal is connected to the corresponding Cascode current mirror circuit, and the first and second control voltages of the external control circuit are applied to the output terminal of the corresponding current mirror circuit. After multiplication, an output voltage is obtained at the output terminal.

[0102] In this invention, the input signal is first processed or input into the corresponding next-step circuit. Then, the third to sixth control voltages output by the external control circuit control the memristor control circuit according to the positive input signal, so that the memristor value takes the value of the positive input signal. Then, another positive or negative signal is connected to the corresponding Cascode current mirror circuit. The circuit that works for positive signals is a Cascode current mirror circuit composed of NMOS transistors, and the circuit that works for negative signals is a Cascode current mirror circuit composed of PMOS transistors. Finally, when the other input signal is positive, the first control voltage output by the external control circuit controls the Cascode current mirror circuit composed of NMOS transistors to perform a multiplication operation at the output terminal to obtain a positive output voltage. When the other input signal is negative, the second control voltage output by the external control circuit controls the Cascode current mirror circuit composed of PMOS transistors to perform a multiplication operation at the output terminal to obtain a negative output voltage.

[0103] The external control voltages specifically included in step S2 above are the third control voltage, the fourth control voltage, the fifth control voltage, the sixth control voltage, the seventh control voltage, and the eighth control voltage, wherein:

[0104] When the input signal received by the external control circuit is greater than the current memristor value, such as Figure 4 As shown, at this time, the third control voltage output is a high level voltage, controlling the T1 PMOS transistor to turn off; the fourth control voltage output is a low level voltage, controlling the T2 PMOS transistor to turn on; the fifth control voltage output is a high level voltage, controlling the T3 NMOS transistor to turn on; the sixth control voltage output is a low level voltage, controlling the T4 NMOS transistor to turn off; the seventh control voltage output is a low level voltage, controlling the T5 PMOS transistor to turn on; the eighth control voltage output is a low level voltage, controlling the T6 PMOS transistor to turn on, and after a certain period of time, all MOS transistors are turned off, thereby causing the memristor value to rise to the value of the input signal.

[0105] When the input signal received by the external control circuit is less than the current memristor value, such as Figure 4 As shown, at this time, the third control voltage output is a low level voltage, controlling the closing of T1 PMOS transistor; the fourth control voltage output is a high level voltage, controlling the opening of T2 PMOS transistor; the fifth control voltage output is a low level voltage, controlling the opening of T3 NMOS transistor; the sixth control voltage output is a high level voltage, controlling the closing of T4 NMOS transistor; the seventh control voltage output is a low level voltage, controlling the closing of T5 PMOS transistor; the eighth control voltage output is a low level voltage, controlling the closing of T6 PMOS transistor, and after a certain period of time, all MOS transistors are disconnected, thereby causing the memristor value to drop to the value of the input signal.

[0106] The external control voltages specifically included in step S3 above are the first control voltage and the second control voltage, wherein:

[0107] When the other input signal after the sign conversion circuit is positive, the Cascode current mirror circuit composed of NMOS transistors starts to work. After the memristor value is adjusted, the first control voltage is applied to the output terminal of the current mirror circuit, and a positive voltage is output after multiplication with the memristor value.

[0108] When the other input signal after the sign conversion circuit is negative, the Cascode current mirror circuit composed of PMOS transistors starts to work. After the memristor value is adjusted, the second control voltage is applied to the output terminal of the current mirror circuit, and a negative voltage is output after multiplication with the memristor value.

[0109] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0110] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A four-quadrant analog multiplier circuit based on memristor, comprising a sign conversion circuit (1), an external control circuit (2), a memristor control circuit composed of memristor, PMOS transistor and NMOS transistor (3), a Cascode current mirror circuit composed of NMOS transistor (4) and a Cascode current mirror circuit composed of PMOS transistor (5). Its features are: The input terminal of the sign conversion circuit (1) receives two input signals, and the output terminal of the sign conversion circuit (1) outputs a positive signal to the Cascode current mirror circuit (4) composed of NMOS transistors and outputs a negative signal to the Cascode current mirror circuit (5) composed of PMOS transistors. The input terminal of the external control circuit (2) receives another positive signal; The output terminal of the external control circuit (2) outputs the first control voltage to the Cascode current mirror circuit (4) composed of NMOS transistor and the memristor control circuit (3) composed of memristor, PMOS transistor and NMOS transistor. The output of the memristor control circuit (3) composed of memristor, PMOS transistor and NMOS transistor is coupled to the Cascode current mirror circuit (4) composed of NMOS transistor and the Cascode current mirror circuit (5) composed of PMOS transistor. The memristor control circuit (3) composed of memristors, PMOS transistors and NMOS transistors, the Cascode current mirror circuit (4) composed of NMOS transistors and the Cascode current mirror circuit (5) composed of PMOS transistors output positive and negative voltages.

2. A memristor-based four-quadrant analog multiplier circuit according to claim 1, characterized in that: The input terminal of the sign conversion circuit (1) is connected to two input signals. The output terminal of the sign conversion circuit (1) is connected to the input terminal of the Cascode current mirror circuit (4) composed of NMOS transistors and the Cascode current mirror circuit (5) composed of PMOS transistors and provides an input signal source for the external control circuit (2). The sign conversion circuit (1) is used to convert the positive and negative signs of the two input signals into the corresponding signs of the first and second quadrants, and input the signal that is always positive after conversion into the external control circuit (2), and input another positive or negative signal into the Cascode current mirror circuit (4) composed of NMOS transistors and the Cascode current mirror circuit (5) composed of PMOS transistors.

3. A four-quadrant analog multiplier circuit based on memristors according to claim 1, characterized in that: The external control circuit (2) determines the required external control voltage for the output based on the positive input signal; The input terminals of the Cascode current mirror circuit (4) composed of NMOS transistors and the input terminals of the Cascode current mirror circuit (5) composed of PMOS transistors are connected to the output terminals of the sign conversion circuit (1). The first output voltage source of the Cascode current mirror circuit (4) composed of NMOS transistors and the second output voltage source of the Cascode current mirror circuit (5) composed of PMOS transistors are connected to the first and second control voltages of the external control circuit (2). The memristors in the memristor control circuit (3) composed of memristors, PMOS transistors and NMOS transistors are respectively connected to the output terminals of the Cascode current mirror circuit composed of different MOS transistors, forming memristor analog multipliers in the first and second quadrants. The memristor value in the memristor control circuit (3) composed of memristors, PMOS transistors and NMOS transistors is the value of one of the positive signals output by the sign conversion circuit (1). The memristor value in the memristor control circuit (3) composed of memristors, PMOS transistors and NMOS transistors is obtained by the first to eighth control voltages of the external control circuit (2).

4. A four-quadrant analog multiplier circuit based on memristors according to claim 1, characterized in that: When two negative signals are input to the sign conversion circuit (1), the two negative signals are converted into two positive signals through the sign conversion circuit (1), and one of the positive values ​​is input into the Cascode current mirror circuit (4) composed of NMOS transistors, and the other positive value is input into the external control circuit (2); When two positive signals are input, no sign conversion is performed. One of the positive values ​​is directly input into the Cascode current mirror circuit (4) composed of NMOS transistors through the sign conversion circuit (1), and the other positive value is input into the external control circuit (2). When two signals, one positive and one negative, are input, no sign conversion is performed. The negative value is directly input into the Cascode current mirror circuit (5) composed of PMOS transistors through the sign conversion circuit (1), and the positive value is input into the external control circuit (2).

5. A four-quadrant analog multiplier circuit based on memristors according to claim 1, characterized in that: The first output terminal is connected to the first output voltage source of the Cascode current mirror circuit (4) composed of NMOS transistors, and generates a first control voltage signal; the second output terminal is connected to the second output voltage source of the Cascode current mirror circuit (5) composed of PMOS transistors, and generates a second control voltage signal. The third output terminal is connected to the control terminal of the first PMOS transistor and generates a third control voltage signal; the fourth output terminal is connected to the control terminal of the second PMOS transistor and generates a fourth control voltage signal; the fifth output terminal is connected to the control terminal of the third NMOS transistor and generates a fifth control voltage signal; the sixth output terminal is connected to the control terminal of the fourth NMOS transistor and generates a sixth control voltage signal; the seventh output terminal is connected to the control terminal of the fifth PMOS transistor and generates a seventh control voltage signal; and the eighth output terminal is connected to the control terminal of the sixth PMOS transistor and generates an eighth control voltage signal.

6. A four-quadrant analog multiplier circuit based on memristors according to claim 1, characterized in that: The memristor control circuit (3) composed of memristor, PMOS transistor and NMOS transistor includes a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor and a fixed voltage source, wherein one end of the first PMOS transistor is connected to the fixed voltage source, the control terminal of the first PMOS transistor is connected to the third control voltage signal, and the other end of the first PMOS transistor is connected to one end of the third NMOS transistor and one end of the fifth PMOS transistor; One end of the second PMOS transistor is connected to a fixed voltage source, the control terminal of the second PMOS transistor is connected to a fourth control voltage signal, and the other end of the second PMOS transistor is connected to one end of a fourth NMOS transistor. One end of the third NMOS transistor is connected to the other end of the first PMOS transistor and one end of the sixth PMOS transistor. The control terminal of the third NMOS transistor is connected to the fifth control voltage signal, and the other end of the third NMOS transistor is connected to ground. One end of the fourth NMOS transistor is connected to one end of the second PMOS transistor and one end of the sixth PMOS transistor, the control terminal of the fourth NMOS transistor is connected to the sixth control voltage signal, and the other end of the fourth NMOS transistor is connected to ground; One end of the fifth PMOS transistor is connected to the positive terminal of the memristor, the control terminal of the fifth PMOS transistor is connected to the seventh control voltage signal, and the other end of the fifth PMOS transistor is connected to one end of the first PMOS transistor and one end of the third NMOS transistor. One end of the sixth PMOS transistor is connected to the negative terminal of the memristor, the control terminal of the sixth PMOS transistor is connected to the eighth control voltage signal, and the other end of the sixth PMOS transistor is connected to one end of the second PMOS transistor and one end of the fourth NMOS transistor. When the memristor control circuit (3) composed of the memristor, PMOS transistor and NMOS transistor is working in the first quadrant, T5 and T6 should use NMOS transistors.

7. A four-quadrant analog multiplier circuit based on memristors according to claim 1, characterized in that: The Cascode current mirror circuit (4) composed of NMOS transistors includes a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, resistors R1, R2, and R3, wherein: one end of the seventh NMOS transistor is connected to one terminal of resistor R1, the control terminal of the seventh NMOS transistor is connected to the control terminal of the eighth NMOS transistor, and the other end of the seventh NMOS transistor is connected to one end of the ninth NMOS transistor; one end of the eighth NMOS transistor is connected to one end of resistor R3 and one end of the sixth PMOS transistor, the control terminal of the eighth NMOS transistor is connected to the control terminal of the seventh NMOS transistor, and the other end of the eighth NMOS transistor is connected to one end of the tenth NMOS transistor; one end of the ninth NMOS transistor is connected to one end of the seventh NMOS transistor. One end of the ninth NMOS transistor is connected to the control end of the tenth NMOS transistor, and the other end of the ninth NMOS transistor is connected to ground; one end of the tenth NMOS transistor is connected to one end of the eighth NMOS transistor, the control end of the tenth NMOS transistor is connected to the control end of the ninth NMOS transistor, and the other end of the tenth NMOS transistor is connected to ground; one pole of the resistor R1 is connected to the first input voltage source and one end of the fifth PMOS transistor, and the other pole of the resistor R1 is connected to one end of the seventh NMOS transistor; one pole of the resistor R2 is connected to the first control voltage of the external control circuit (2), and the other pole of the resistor R2 is connected to the positive terminal of the memristor; one pole of the resistor R3 is connected to the negative terminal of the memristor, and the other pole of the resistor R3 is connected to the other end of the eighth NMOS transistor.

8. A four-quadrant analog multiplier circuit based on memristors according to claim 1, characterized in that: The Cascode current mirror circuit (5) composed of PMOS transistors includes the eleventh PMOS transistor, the twelfth PMOS transistor, the thirteenth PMOS transistor, the fourteenth PMOS transistor, resistor R4, resistor R5, and resistor R6, wherein: One end of the eleventh PMOS transistor is connected to one terminal of resistor R4, the control terminal of the eleventh PMOS transistor is connected to the control terminal of the twelfth PMOS transistor, and the other end of the eleventh PMOS transistor is connected to one end of the thirteenth PMOS transistor. One end of the twelfth PMOS transistor is connected to one end of resistor R6 and one end of the sixth PMOS transistor, the control terminal of the twelfth PMOS transistor is connected to the control terminal of the eleventh PMOS transistor, and the other end of the twelfth PMOS transistor is connected to one end of the fourteenth PMOS transistor. One end of the thirteenth PMOS transistor is connected to one end of the eleventh PMOS transistor, and the control terminal of the thirteenth PMOS transistor is connected to the control terminal of the fourteenth PMOS transistor. The other end of the thirteenth PMOS transistor is connected to ground. One end of the fourteenth PMOS transistor is connected to one end of the eleventh PMOS transistor, and the control terminal of the fourteenth PMOS transistor is connected to the control terminal of the thirteenth PMOS transistor. The other end of the fourteenth PMOS transistor is connected to ground. One terminal of resistor R4 is connected to the second input voltage source, and the other terminal of resistor R4 is connected to one end of the eleventh PMOS transistor. One terminal of resistor R5 is connected to the second control voltage of the external control circuit and one end of the fifth PMOS transistor, and the other terminal of resistor R5 is connected to the positive terminal of the memristor. One terminal of resistor R6 is connected to the negative terminal of the memristor, and the other terminal of resistor R6 is connected to the other end of the twelfth PMOS transistor.

9. The control method for a four-quadrant analog multiplier circuit based on memristors according to claim 1, characterized in that: Includes the following steps: The symbol conversion circuit (1) converts the two received input signals into signals that can be multiplied in one quadrant or two quadrants. The external control circuit (2) converts the input signal into a positive signal, and the third to eighth control voltages of the external control circuit (2) generate the corresponding memristor value. The positive voltage signal converted by the sign conversion circuit (1) is received by the Cascode current mirror circuit (4) composed of NMOS transistors, or the negative voltage signal converted by the sign conversion circuit (1) is received by the Cascode current mirror circuit (5) composed of PMOS transistors. The first control voltage or the second control voltage output by the external control circuit (2) controls the Cascode current mirror circuit (4) composed of NMOS transistors or the Cascode current mirror circuit (5) composed of PMOS transistors to complete the multiplication operation.

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