A solar cell and a manufacturing method thereof, a photovoltaic module

Abstract

The application discloses a solar cell and a manufacturing method and a photovoltaic module thereof, and relates to the technical field of photovoltaics, which is used for reducing the risk of scratching the surface of a semiconductor substrate and a surface passivation layer, improving the passivation effect of the surface passivation layer on the semiconductor substrate, and further improving the conversion efficiency of the solar cell. The solar cell comprises a semiconductor substrate and a surface passivation layer. The semiconductor substrate comprises a textured morphology region. The textured morphology region is densely covered with a textured structure. The surface passivation layer is directly arranged on the textured morphology region. The textured morphology region comprises a non-plaque region and a plurality of plaque regions dispersed in the non-plaque region. In the thickness direction of the semiconductor substrate, the height of the plaque region is less than the height of the non-plaque region. The photovoltaic module comprises the solar cell. The manufacturing method of the solar cell is used for manufacturing the solar cell.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and in particular to a solar cell, its manufacturing method, and a photovoltaic module. Background Technology

[0002] A solar cell is a device that converts solar energy into electrical energy. Specifically, when a solar cell is in operation, sunlight shines on the semiconductor pn junction, forming new electron-hole pairs. Under the influence of the built-in electric field of the pn junction, photogenerated holes flow to the p-region, and photogenerated electrons flow to the n-region. When the circuit is connected, an electric current is generated. A doped semiconductor layer and a chemically passivated surface layer can be formed on the surface of the solar cell's semiconductor substrate to reduce the number of surface defects and lower the carrier recombination rate on the semiconductor substrate surface, thus improving the efficiency of the solar cell. Furthermore, to improve light absorption and utilization, the surface of the semiconductor substrate is generally designed with a textured morphology; and since doped semiconductor layers generally have strong parasitic absorption, the doped semiconductor layer can be omitted, and a surface passivation layer can be used directly to passivate the semiconductor substrate.

[0003] However, existing solar cells suffer from low conversion efficiency during mass production. Summary of the Invention

[0004] The purpose of this invention is to provide a solar cell and its manufacturing method, as well as a photovoltaic module, which reduces the risk of scratches on the textured surface region and surface passivation layer of the semiconductor substrate, thereby improving the passivation effect of the surface passivation layer on the semiconductor substrate and thus improving the conversion efficiency of the solar cell.

[0005] To achieve the above objectives, the present invention provides a solar cell comprising: a semiconductor substrate and a surface passivation layer. The semiconductor substrate includes a textured region. The textured region contains a densely distributed textured structure. The surface passivation layer is directly disposed on the textured region. The textured region includes non-patterned regions and a plurality of patchy regions dispersed within the non-patterned regions. Along the thickness direction of the semiconductor substrate, the height of the patchy regions is less than the height of the non-patterned regions.

[0006] With the above technical solution, in the solar cell provided by this invention, the semiconductor substrate includes a textured region. This textured region is densely covered with textured structures, giving it a large specific surface area. This not only provides a high light-trapping effect but also increases the contact area between the surface passivation layer and the textured region, facilitating the stable deposition of the surface passivation layer on the textured region and enhancing its adhesion. Furthermore, the textured region includes non-patch areas and several patch areas dispersed within the non-patch areas. The patch areas refer to patch areas exhibiting a tower-like morphology formed by multiple textured structures within the textured region. The patch areas are closed patterns with clear boundaries between the patch areas and the non-patch areas. In the above scenario, when the height of the patch areas within the textured surface region is smaller, the patch areas are positioned further inward, while the taller non-patch areas within the textured surface region are positioned further outward. Compared to the previous situation where the entire textured surface region was in contact with the manufacturing and / or transfer equipment, this reduces the contact area between the textured surface region and the manufacturing and / or transfer equipment, decreasing the likelihood of scratches on the surface passivation layer. Therefore, the presence of smaller patch areas can reduce the risk of scratches on some textured structures (i.e., textured structures located within the patch areas) during other processing and / or transfer after texturing and before surface passivation treatment of at least the textured surface region of the semiconductor substrate to form a surface passivation layer. This reduces damage to the textured structure, decreases the number of defects in the textured surface region, and improves the yield of battery production. This is especially beneficial for high-efficiency batteries, further improving battery production yield.

[0007] As one possible implementation, at least one patch region is polygonal or elongated in shape.

[0008] When using the above technical solution, at least one patch region can be polygonal in shape, such as a quadrilateral, pentagon, or hexagon. In this case, the patch region presents a discretely distributed pyramidal base morphology. Alternatively, at least one patch region can also be elongated, in which case the patch region presents a patch region composed of multiple pyramidal base morphologies overlapping each other along approximately the same direction. It is evident that the patch region can have various morphologies, which can reduce manufacturing difficulty. Simultaneously, different patch regions have different ranges, allowing the morphology of the patch region to be set according to actual needs. This enables control over the distribution of smaller patch regions within the textured surface region. This is beneficial in minimizing the risk of scratching the textured surface region and the surface passivation layer on the semiconductor substrate during the manufacturing process, while preventing contact between the textured surface region and the passivation layer located on the patch region and the manufacturing equipment and / or transfer equipment. This also improves the passivation effect of the surface passivation layer on the semiconductor substrate.

[0009] As one possible implementation, multiple patch regions spaced apart along a first direction form a patch column. Multiple patch columns are arranged within the textured surface region, with different columns spaced apart along a second direction. The second direction intersects the first direction. In this case, the distribution of different patch regions is relatively regular, preventing the semiconductor substrate and the surface passivation layer from being difficult to isolate from the contact surfaces of the manufacturing equipment and / or transfer equipment during the corresponding manufacturing process due to excessive concentration of patch regions in a certain area of ​​the textured surface region. This effectively reduces the risk of scratching the textured surface region and the surface passivation layer included in the semiconductor substrate. Furthermore, the relatively regular distribution of different patch regions also helps to improve the macroscopic flatness of different areas of the textured surface region, effectively improving the uniform deposition of the surface passivation layer on the textured surface region and enhancing the passivation effect.

[0010] As one possible implementation, at least one patch region has a one-dimensional size greater than or equal to 15 μm and less than or equal to 50 μm.

[0011] When the above technical solution is adopted, at least one patch region has a one-dimensional size within the above range. This helps to prevent the area proportion of the patch region with a smaller height within the textured morphology region from being too small due to the one-dimensional size of the patch region being too small. This would result in most of the surface height of the textured morphology region and the side of the surface passivation layer corresponding to the textured morphology region being relatively high, making it easier for them to come into contact with the manufacturing equipment and / or transfer equipment during the corresponding manufacturing process. This reduces the risk of the textured morphology region and surface passivation layer of the semiconductor substrate being scratched. Furthermore, it can also prevent the degree of planarization treatment of the part of the surface corresponding to the textured morphology region of the semiconductor substrate before texturing due to the one-dimensional size of the patch region being too small. This helps to make the part of the surface have a certain degree of macroscopic flatness, so that the dimensional uniformity of the textured structure obtained after texturing the part of the surface is higher. This is beneficial to improve the deposition quality of the surface passivation layer on the textured morphology region and improve the passivation effect of the surface passivation layer. Furthermore, it can prevent the large one-dimensional size of the patch region from causing a large area proportion of the patch region within the textured surface region and / or a large proportion of a certain area within the textured surface region. This would make it difficult for most of the surface of the semiconductor substrate and the surface passivation layer corresponding to the patch region to be isolated from the manufacturing equipment and / or transfer equipment during the corresponding manufacturing process by the taller non-patch region, effectively reducing the risk of scratching the textured surface region and surface passivation layer included in the semiconductor substrate. Moreover, because the taller non-patch region is located on the outside, it is easier for it to come into contact with the manufacturing equipment and / or transfer equipment. Therefore, it can also prevent the contact force per unit area such as clamping or squeezing when manufacturing equipment and / or transfer equipment come into contact in the non-patterned area due to the excessively large one-dimensional size of the patch area, which would result in a smaller area proportion of the non-patterned area. This reduces the risk of scratching the non-patterned area corresponding to the semiconductor substrate and the surface passivation layer. At the same time, it can also prevent the excessively large one-dimensional size of the patch area from causing the surface of the semiconductor substrate to be planarized to an excessive degree. This is beneficial for the semiconductor substrate to have a larger light absorption depth in the part corresponding to the textured morphology area, thereby improving the light utilization rate of the semiconductor substrate.

[0012] As one possible implementation, the ratio of the one-dimensional size of the patch region to the one-dimensional size of the velvet structure is greater than or equal to 4 and less than or equal to 60.

[0013] When the above technical solution is adopted, the ratio of the one-dimensional size of the patch region to the one-dimensional size of the textured structure is within the aforementioned range. This prevents the one-dimensional size of the patch region from being too small and / or the one-dimensional size of the textured structure from being too large due to an excessively small ratio. In this case, the size of the textured structure is relatively small, which can reduce the surface roughness of the textured morphology region, improve the conformal difference of the surface passivation layer on the top and base of the textured structure, and further improve the passivation effect of the surface passivation layer on the semiconductor substrate. In addition, it can also prevent the one-dimensional size of the patch region from being too large and / or the one-dimensional size of the textured structure from being too small due to an excessively large ratio. This is beneficial for reducing the light reflectivity of the corresponding textured morphology region and increasing the light absorption rate of the semiconductor substrate in the corresponding textured morphology region. The beneficial effects of preventing the one-dimensional size of the patch region from being too large or too small can be referred to the above text and will not be repeated here.

[0014] As one possible implementation, within the velvety morphology region, and in a unit area of ​​300μm×300μm, the number of patch regions is greater than or equal to 6 and less than or equal to 25.

[0015] With the above technical solution, the number of patch areas distributed per unit area is within the aforementioned range. This helps prevent the patch areas from being too concentrated in a certain area of ​​the textured surface region due to an excessive number of patch areas, or the patch areas accounting for a large proportion of the area of ​​the textured surface region. This would make it difficult to separate the textured surface region and the surface passivation layer from the contact surface of the manufacturing equipment and / or transfer equipment through the contact surface of the non-patch area with a larger height, thus reducing the risk of scratching the textured surface region and the surface passivation layer. At the same time, it can also reduce the contact force such as clamping or squeezing per unit area when the manufacturing equipment and / or transfer equipment come into contact in the non-patch area, thus reducing the risk of scratching the semiconductor substrate and the non-patch area corresponding to the surface passivation layer. In addition, it can prevent the area separated from the manufacturing equipment and / or transfer equipment by the patch area from the surface of the semiconductor substrate and the surface passivation layer due to the small number of patch areas, thus reducing the risk of the semiconductor substrate and the surface passivation layer being scratched. At the same time, it can also prevent the surface of the corresponding textured area of ​​the semiconductor substrate from being too smoothed due to the large number of patch areas, which is conducive to the semiconductor substrate having a larger light absorption depth in the corresponding textured area, thereby improving the light utilization rate of the semiconductor substrate.

[0016] As one possible implementation, the textured surface structure is a pyramidal structure. In this case, the pyramidal structure has a good light-trapping effect, which is beneficial to improving the conversion efficiency of the solar cell.

[0017] As one possible implementation, at least one of the velvet structures has a one-dimensional dimension greater than or equal to 0.1 μm and less than or equal to 4 μm.

[0018] When the above technical solution is adopted, the one-dimensional size of the textured structure is within the aforementioned range. This helps to prevent the specific surface area of ​​the textured morphology region from being too small due to the one-dimensional size of the textured structure being too small, thus ensuring that the textured morphology region has a high light-trapping effect. In addition, it can also prevent the textured morphology region from having a large undulation due to the one-dimensional size of the textured structure being too large, thereby reducing the deposition quality difference of the surface passivation layer in different regions of the textured structure and improving the passivation effect of the surface passivation layer.

[0019] As one possible implementation, the height difference between at least one patchy region and a non-patchy region is less than 4 μm.

[0020] With the above technical solution, the height difference between the patchy area and the non-patchy area is relatively small, which is conducive to improving the flatness of the part of the surface of the corresponding textured morphology area of ​​the semiconductor substrate within the standard scale range of the conformal film layer. This is conducive to improving the one-dimensional size uniformity of the textured structure in different parts of the textured morphology area after texturing, thereby improving the deposition uniformity of the surface passivation layer on the textured morphology area and improving the passivation effect of the surface passivation layer.

[0021] As one possible implementation, in the velvety morphology region, the velvety structure located within the patchy region is defined as the first velvety structure, and the velvety structure located at the boundary between the patchy and non-patchy regions is defined as the boundary velvety structure. The velvety structure located within the non-patchy region is the second velvety structure. Specifically, the one-dimensional dimension of at least one boundary velvety structure is greater than the one-dimensional dimension of the first and second velvety structures; and / or, the one-dimensional dimension of at least one boundary velvety structure is greater than or equal to 1.8 μm and less than or equal to 2.5 μm; and / or, the one-dimensional dimension of at least one first velvety structure and / or the second velvety structure is greater than or equal to 0.9 μm and less than or equal to 1.5 μm.

[0022] When the above technical solution is adopted, the size of the one-dimensional dimension of the textured structure and its corresponding light-trapping wavelength have a certain matching relationship. When the one-dimensional dimension of the interface textured structure is different from that of the first textured structure and the second textured structure, it is beneficial to make the textured morphology region have a high light-trapping effect for light of different wavelengths, thereby improving the light absorption rate of the semiconductor substrate.

[0023] As one possible implementation, in the velvety morphology region, the velvety structure located at the boundary between the patchy and non-patchy regions is defined as the boundary velvety structure. Furthermore, the boundary velvety structure is a pyramid-shaped structure, and the length of the side edge of the boundary velvety structure facing the non-patchy region is less than the length of its own side edge facing the patchy region.

[0024] When the above technical solution is adopted, because the top of the pyramid-shaped structure is sharper than its own side surface, compared with the multi-layered pyramid-shaped structure with sharp apex angles at the junction of the patch area and the non-patch area, when the length of the side edge of the junction textured structure facing the non-patch area is less than the length of its own side edge facing the patch area, the number of sharp apex angles at the junction of the patch area and the non-patch area can be reduced. This is beneficial to reduce the undulation at the junction, improve the coverage of the surface passivation layer at the junction of the patch area and the non-patch area, solve the problem in the prior art that the surface flatness requirement is high when the atomic layer deposition process is used to form the surface passivation layer, and the specific surface area is too large at the junction, resulting in poor deposition uniformity of the surface passivation layer at the junction, and improve the passivation effect of the surface passivation layer at the junction.

[0025] As one possible implementation, the surface passivation layer includes at least one of an oxide layer, a nitride layer, an oxide-oxygen nitride layer, and a carbide layer. In this case, there are various options for the surface passivation layer material, which helps improve the applicability of the solar cell provided by this invention in different application scenarios. Furthermore, surface passivation layers deposited via atomic layer deposition, such as alumina or molybdenum oxide layers, require a high degree of surface smoothness. The presence of patchy regions leads to greater uniformity in the height of adjacent textured surfaces, and the transition at the boundary between patchy and non-patchy regions is achieved through the sides of a long pyramidal structure, reducing the number of sharp corners and decreasing the surface undulation at the boundary. This improves the deposition uniformity of surface passivation layers deposited via atomic layer deposition, such as alumina or molybdenum oxide layers, and enhances the passivation effect of the surface passivation layer.

[0026] As one possible implementation, the semiconductor substrate includes opposing first and second surfaces. A textured surface region is located at least on the first surface. Furthermore, the solar cell also includes a doped semiconductor layer. The doped semiconductor layer is disposed on the surface of the first surface in a region excluding the textured surface region, and / or, the doped semiconductor layer is disposed on the second surface.

[0027] As one possible implementation, the surface of the region on the semiconductor substrate where the doped semiconductor layer is disposed is a polished morphology region, and the polished morphology region is provided with a tower-like structure. Furthermore, when both the polished morphology region and the textured morphology region are located on the first surface, the one-dimensional dimension of the tower-like structure is smaller than the one-dimensional dimension of the patch region.

[0028] When the one-dimensional size of the tower-shaped structure is smaller than that of the patch region, it indicates that after forming a doped semiconductor layer on a portion of the semiconductor substrate and before texturing a portion of the surface of the textured region of the semiconductor substrate, a planarization process is further performed on a portion of the surface of the textured region of the semiconductor substrate. This not only removes the damaged portion of the textured region of the semiconductor substrate and reduces the carrier recombination rate, but also improves the dimensional uniformity of the textured structure after texturing and enhances the deposition uniformity of the surface passivation layer in the textured region.

[0029] As one possible implementation, the doped semiconductor layer includes a first doped semiconductor portion and a second doped semiconductor portion, which are alternately distributed along a first surface and have opposite doping types. In the polished morphology region, the surface of the region where the first doped semiconductor portion is disposed is designated as a first region, and the surface of the region where the second doped semiconductor portion is disposed is designated as a second region. Along the direction from the second surface to the first surface, the height of the first region is greater than the height of the second region. Specifically, the one-dimensional dimension of the tower-like structure located in the first region is smaller than the one-dimensional dimension of the tower-like structure located in the second region; and / or, the ratio of the one-dimensional dimension of the tower-like structure located in the second region to the one-dimensional dimension of the tower-like structure located in the first region is greater than 1 and less than or equal to 3.

[0030] When the height of the first region is greater than the height of the second region, and the one-dimensional dimension of the tower-like structure in the first region is smaller than the one-dimensional dimension of the tower-like structure in the second region, it indicates that after the first doped semiconductor portion is formed on a portion of the semiconductor substrate, and before the second doped semiconductor portion is formed on a portion of the surface of the semiconductor substrate corresponding to the second region, the surface of the semiconductor substrate corresponding to the second region is further planarized. This not only removes the damage caused by the patterning process of the first doped semiconductor portion at the second region of the semiconductor substrate, reducing the carrier recombination rate, but also helps to improve the carrier collection efficiency of the second doped semiconductor portion and improve the conversion efficiency of the solar cell.

[0031] Furthermore, the ratio of the one-dimensional dimension of the tower-like structure in the first region to the one-dimensional dimension of the tower-like structure in the second region is within the aforementioned range. This helps to prevent the degree of planarization treatment on the part of the semiconductor substrate corresponding to the second region from being too small, or even from not being planarized at all. This helps to reduce the carrier recombination rate in the second region and improve the carrier collection efficiency of the second doped semiconductor section. It also prevents the degree of planarization treatment on the part of the second region from being too large, so that the semiconductor substrate corresponding to the second region and the textured morphology region have a larger light absorption depth and improve the light utilization rate of the semiconductor substrate.

[0032] As one possible implementation, the solar cell is a back-contact cell. The textured region is located in a portion of the first surface and the second surface of the semiconductor substrate. Furthermore, the doped semiconductor layer includes a first doped semiconductor portion and a second doped semiconductor portion, which are alternately distributed parallel to the first surface and have opposite doping types. The textured region on the first surface is disposed between the first doped semiconductor portion and the second doped semiconductor portion.

[0033] With the above technical solution, the solar cell is a back-contact cell, which can reduce the light utilization rate on the front side of the cell and improve the conversion efficiency of the solar cell. Furthermore, the textured morphology region can not only be located on the second surface of the semiconductor substrate, improving the light trapping effect on the front side of the cell and the passivation effect of the surface passivation layer on the front side of the cell, preventing scratches on the surface passivation layer, but the textured morphology region can also be located between the first doped semiconductor portion and the second doped semiconductor portion. This increases the bifaciality of the back-contact cell and improves the deposition quality of the surface passivation layer between the first and second doped semiconductor portions, enhancing the resistivity of the surface passivation layer between the first and second doped semiconductor portions, effectively preventing charge loss from the back side of the cell, and improving the conversion efficiency of the solar cell.

[0034] In a second aspect, the present invention provides a photovoltaic module comprising: a cell string and an encapsulation layer. The cell string is formed by electrically connecting multiple solar cells as provided in the first aspect and its various implementations; the encapsulation layer covers the surface of the cell string.

[0035] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0036] Thirdly, the present invention provides a method for manufacturing a solar cell, the method comprising: first, providing a semiconductor substrate; next, sequentially performing a first planarization treatment and a texturing treatment on a portion of the surface of the semiconductor substrate to form a textured region on the semiconductor substrate; the textured region includes non-patch regions and a plurality of patch regions dispersed within the non-patch regions; along the thickness direction of the semiconductor substrate, the height of the patch regions is less than the height of the non-patch regions; next, directly forming a surface passivation layer on the textured region.

[0037] As one possible solution, at least an atomic layer deposition process is used to form a surface passivation layer on the textured surface region.

[0038] As one possible implementation, the semiconductor substrate includes a first surface and a second surface opposite to each other. The textured surface region is located at least on the first surface. Furthermore, after providing the semiconductor substrate, the method for manufacturing the solar cell further includes: forming a doped semiconductor layer on the second surface, and / or on the surface of a region on the first surface other than the textured surface region.

[0039] The beneficial effects of the third aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0040] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0041] Figure 1 This is a longitudinal cross-sectional view of a first structure of a solar cell provided in an embodiment of the present invention;

[0042] Figure 2 This is a longitudinal cross-sectional view of a second structure of a solar cell provided in an embodiment of the present invention;

[0043] Figure 3 This is a longitudinal cross-sectional schematic diagram of a third structure of a solar cell provided in an embodiment of the present invention;

[0044] Figure 4 This is a longitudinal cross-sectional view of a fourth structure of a solar cell provided in an embodiment of the present invention;

[0045] Figure 5 A longitudinal cross-sectional view of the fifth structure of a solar cell provided in an embodiment of the present invention;

[0046] Figure 6 A longitudinal cross-sectional view of a sixth structure of a solar cell provided in an embodiment of the present invention;

[0047] Figure 7 A longitudinal cross-sectional view of the seventh structure of a solar cell provided in an embodiment of the present invention;

[0048] Figure 8 A longitudinal cross-sectional view of the eighth structure of a solar cell provided in an embodiment of the present invention;

[0049] Figure 9 A longitudinal cross-sectional view of the ninth structure of a solar cell provided in an embodiment of the present invention;

[0050] Figure 10 A longitudinal cross-sectional view of the tenth structure of a solar cell provided in an embodiment of the present invention;

[0051] Figure 11 This is a SEM image of the structure of a solar cell in a patch region provided in an embodiment of the present invention;

[0052] Figure 12 A 3D microscope image of the structure of a solar cell in a patch region provided in an embodiment of the present invention;

[0053] Figure 13 A 3D microscope image of the structure of a solar cell in a partially textured area, provided in an embodiment of the present invention.

[0054] Reference numerals: 11 is semiconductor substrate, 12 is surface passivation layer, 13 is textured morphology region, 14 is non-patch region, 15 is patch region, 16 is first textured structure, 17 is boundary textured structure, 18 is second textured structure, 19 is doped semiconductor layer, 20 is first doped semiconductor section, 21 is second doped semiconductor section, 22 is first region, 23 is second region, and 24 is interface passivation layer. Detailed Implementation

[0055] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0056] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0057] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0058] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0059] Firstly, the present invention provides a solar cell. The solar cell can be a double-contact cell or a back-contact cell. The embodiments of the present invention do not specifically limit the type of solar cell.

[0060] like Figures 1 to 5 As shown, the solar cell provided in this embodiment of the invention includes: a semiconductor substrate 11 and a surface passivation layer 12. The semiconductor substrate 11 includes a textured surface region 13. Figure 5 As shown, the velvety morphology region 13 is densely covered with velvety structures. For example... Figures 1 to 5 As shown, the surface passivation layer 12 is directly disposed on the textured surface region 13.

[0061] The surface passivation layer is used to passivate defects, dangling bonds, etc., on the surface of the semiconductor substrate. The surface passivation layer can be a chemical passivation layer, but is not limited to chemical passivation; it can also have a fixed charge. In some embodiments, the surface passivation layer can also simultaneously have an anti-reflection effect.

[0062] like Figures 1 to 5 As shown, the textured surface region 13 includes non-patch regions 14 and a plurality of patch regions 15 dispersed within the non-patch regions 14. Along the thickness direction of the semiconductor substrate 11, the height of the patch regions 15 is less than the height of the non-patch regions 14. It is understood that this is for illustrative purposes only. Figures 1 to 5 Only one patch area is shown, but the actual area is not limited to this.

[0063] A patchy region is formed by multiple velvety structures within a velvety morphology region. Specifically, patchy regions are generally distinguished in 3D or SEM microscopic images by their lower height compared to other regions (i.e., non-patchy regions), thus presenting a pattern. For example... Figure 11 The SEM image shown contains quadrilateral block patterns. For example... Figure 12 and Figure 13 The blue block pattern shown in the 3D diagram.

[0064] The inventors of this application discovered that high-efficiency batteries, due to the removal of the doped semiconductor layer beneath the surface passivation layer, become more sensitive to scratches on the battery surface. Previously, the presence of the doped semiconductor layer meant that even with scratches, the layer could provide some passivation, and the reduction in battery efficiency was not significant. However, in high-efficiency batteries without the doped semiconductor layer, scratches on the surface passivation layer directly expose the semiconductor substrate, leading to the formation of severe recombination centers. While these recombination centers might not be a major factor in low-efficiency batteries, in high-efficiency batteries, they become the weakest link limiting battery efficiency. In other words, the higher the battery efficiency, the greater the impact of these recombination centers on battery efficiency.

[0065] The inventors of this application further discovered that when the textured surface region contains smaller patch areas (i.e., the patch areas are depressions), the surface of the patch areas is further inward, while the surface of the non-patch areas is further outward. Compared to the previous method where the entire textured surface region was in contact with the manufacturing and / or transfer equipment, this reduces the contact area between the textured surface region and the manufacturing and / or transfer equipment, thus lowering the probability of scratches on the surface passivation layer. Based on this, the presence of smaller patch areas can reduce the risk of scratches on some textured structures (i.e., textured structures located within the patch areas) during other operations and / or transfer processes after texturing and before surface passivation treatment is performed on at least the textured surface region of the semiconductor substrate to form a surface passivation layer. This reduces damage to the textured structure, decreases the number of defects in the textured surface region, and improves the yield of battery production. This is especially beneficial for high-efficiency batteries.

[0066] In the actual manufacturing process, before forming the surface passivation layer, at least a portion of the surface of the semiconductor substrate corresponding to the textured morphology area is first planarized, and then this portion of the surface is texturized to obtain patchy and non-patchy areas. Specifically, after planarization, the deep line marks on the original semiconductor substrate leave behind patchy rudimentary areas that are internally flat but lower in height than other areas. In the subsequent texturizing process, by controlling the size of the formed textured structure and the texturizing time, a dense network of small textured structures is created, without completely destroying the planarization marks, thus allowing the patchy rudimentary areas to develop into patchy areas. It is understandable that the one-dimensional dimension of the textured structure formed by the planarization process cannot be too small, and the one-dimensional dimension of the textured structure during texturizing cannot be too large; otherwise, it will be difficult to form patchy areas.

[0067] The one-dimensional size of the patch region, the depth and distribution density of deep lines in the original semiconductor substrate, the control of polishing morphology, and the control of textured surface structure can be adjusted by those skilled in the art according to the actual situation.

[0068] This process ensures that the patchy area has a certain area proportion within the textured surface region, and that the textured surface region has a certain degree of flatness. Simultaneously, it achieves relatively complete removal of damage and defects from the original semiconductor substrate while maintaining low weight reduction. It also facilitates high dimensional uniformity of the textured structure on both the non-patchy and patchy surfaces, resulting in greater height consistency. Furthermore, retaining a larger textured structure after the flattening process further ensures relatively complete removal of damage and defects from the original semiconductor substrate while maintaining low weight reduction. Moreover, the smaller one-dimensional textured structure formed after texturing further improves the uniformity of the surface passivation layer deposition.

[0069] In practical applications, the distribution range of the textured morphology region on the semiconductor substrate is not specifically limited in the embodiments of the present invention. It can be determined according to the type of solar cell, the formation range of the doped semiconductor layer used to collect charge carriers in the solar cell, and the requirements for the formation range of the surface passivation layer on the semiconductor substrate in the actual application scenario. No specific limitation is made here.

[0070] For example, such as Figures 1 to 4 As shown, the semiconductor substrate 11 includes a first surface and a second surface opposite to each other. A textured surface region 13 is located at least on the first surface. Furthermore, the solar cell also includes a doped semiconductor layer 19. The doped semiconductor layer 19 is disposed on the surface of the first surface in a region other than the aforementioned textured surface region 13, and / or, the doped semiconductor layer 19 is disposed on the second surface.

[0071] In this configuration, the first surface of the semiconductor substrate can correspond to the front side (the side directly exposed to light) of the solar cell, while the second surface of the semiconductor substrate corresponds to the back side of the solar cell. Alternatively, the first surface of the semiconductor substrate can also correspond to the back side of the solar cell, while the second surface of the semiconductor substrate corresponds to the front side of the solar cell. The correspondence between the first and second surfaces of the semiconductor substrate and the front and back sides of the solar cell, respectively, as well as the placement of the doped semiconductor layer on the semiconductor substrate, can be determined based on the type of solar cell.

[0072] In the case of a double-sided contact solar cell, the first side of the semiconductor substrate can correspond to either the front or back side of the solar cell. For example... Figure 2 As shown, the doped semiconductor layer 19 can be disposed only on the surface of the first surface, excluding the textured area 13. Alternatively, as... Figure 1 As shown, the doped semiconductor layer 19 can also be disposed only on the second surface. Alternatively, as... Figure 6 As shown, the doped semiconductor layer 19 can be disposed both on the surface of the first surface (excluding the textured area 13) and on the second surface. Specifically, when the doped semiconductor layer 19 is also disposed on the second surface, as... Figure 1As shown, the doped semiconductor layer 19 can be disposed entirely on the second surface, or as... Figure 4 and Figure 6 As shown, it can also be set in a local area of ​​the second surface (in which case the doping types of the doped semiconductor layer 19 on the first surface and the doped semiconductor layer 19 on the second surface are opposite). Secondly, as... Figure 4 As shown, the textured surface region 13 can also be located on the surface of the second surface other than the region where the doped semiconductor layer 19 is disposed, or the textured surface region 13 can be located only on the first surface.

[0073] In the case of a back-contact solar cell, the first surface of the semiconductor substrate can correspond to either the front or back surface of the solar cell. For example... Figures 7 to 9 As shown, a doped semiconductor layer 19 is disposed on one side of the first and second surfaces of the semiconductor substrate 11, corresponding to the back side of the cell. Furthermore, the doped semiconductor layer 19 includes a first doped semiconductor portion 20 and a second doped semiconductor portion 21, which are alternately spaced along a direction parallel to the back side of the solar cell and have opposite doping types. In this case, as... Figure 9 As shown, the textured surface region 13 can be disposed only on one side of the semiconductor substrate 11 corresponding to the front side of the battery. Alternatively, as... Figure 7 As shown, the textured surface region 13 can also be disposed only on one side of the semiconductor substrate 11 corresponding to the back side of the battery, and between the first doped semiconductor portion 20 and the second doped semiconductor portion 21. Alternatively, as... Figure 8 As shown, the textured morphology region 13 is located in both the side of the semiconductor substrate 11 corresponding to the front side of the battery and the side of the semiconductor substrate 11 corresponding to the back side of the battery, and the textured morphology region 13 located on the back side of the battery is disposed between the first doped semiconductor portion 20 and the second doped semiconductor portion 21.

[0074] It is worth noting that, such as Figure 8As shown, in the case of a back-contact solar cell, when the textured morphology region 13 is located on both the side corresponding to the front of the cell in the first and second surfaces of the semiconductor substrate 11 and the side corresponding to the back of the cell in the first and second surfaces, the light utilization rate on the front side of the cell can be reduced, thereby improving the conversion efficiency of the solar cell. Furthermore, the textured morphology region 13 can not only be located on the side of the semiconductor substrate 11 corresponding to the front of the cell, improving the light trapping effect on the front of the cell and the passivation effect of the surface passivation layer 12 on the front of the cell, preventing scratches on the surface passivation layer 12, but the textured morphology region 13 can also be disposed between the first doped semiconductor portion 20 and the second doped semiconductor portion 21. This increases the bifaciality of the back-contact cell and improves the deposition quality of the surface passivation layer 12 between the first and second doped semiconductor portions, enhancing the resistivity of the surface passivation layer 12 between the first and second doped semiconductor portions, effectively preventing charge loss from the back of the cell, and improving the conversion efficiency of the solar cell.

[0075] Regarding the doped semiconductor layer, the material of the doped semiconductor layer can include any semiconductor material such as silicon, germanium-silicon, or germanium. For example, the doped semiconductor layer can include a doped crystalline silicon layer (such as at least one of a polycrystalline silicon layer, a monocrystalline silicon layer, a nanocrystalline silicon layer, and a microcrystalline silicon layer). When the solar cell is a double-sided contact cell, the materials of the two doped semiconductor layers located on the front and back sides of the cell can be the same or different. Furthermore, when the solar cell is a back-contact cell, the materials of the first doped semiconductor portion and the second doped semiconductor portion of the doped semiconductor layer can be the same or different.

[0076] like Figures 7 to 9 As shown, the doped semiconductor layer 19 can be directly disposed on the semiconductor substrate 11. Alternatively, as... Figure 10 As shown, the solar cell may further include an interface passivation layer 24 located between the doped semiconductor layer 19 and the semiconductor substrate 11. The material and thickness of the interface passivation layer 24 can be set according to the material of the doped semiconductor layer 19 and actual needs. For example, when the doped semiconductor layer is a doped polycrystalline silicon layer, the interface passivation layer is a tunneling passivation layer. The material of the tunneling passivation layer may include materials such as silicon oxide, aluminum oxide, or titanium oxide. Another example: when the material of the doped semiconductor layer may include at least one of doped amorphous silicon, doped nanocrystalline silicon, and doped microcrystalline silicon, the interface passivation layer is at least one of intrinsic amorphous silicon, intrinsic nanocrystalline silicon, and intrinsic microcrystalline silicon.

[0077] For example, a solar cell is a double-contact cell, where the doped semiconductor layer disposed on the surface of the first side of the semiconductor substrate (excluding the textured area) and / or on the second side is a doped crystalline silicon layer. The solar cell also includes a tunneling passivation layer located between the doped semiconductor layer and the semiconductor substrate.

[0078] For example, in a back-contact solar cell, the first and second doped semiconductor portions of the doped semiconductor layer are both doped crystalline silicon layers. The solar cell also includes a tunneling passivation layer located between the doped crystalline silicon layer and the semiconductor substrate.

[0079] As for the height difference between the patchy area and the non-patchy area in the textured morphology region, it can be set according to the actual application scenario's requirements for scratch resistance and deposition uniformity of the surface passivation layer, light trapping requirements of the textured morphology region, and thickness requirements of different areas of the semiconductor substrate.

[0080] For example, the height difference between at least one patchy region and a non-patterned region is less than 4 μm. For instance, the height difference between at least one patchy region and a non-patterned region can be 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, 3 μm, 3.5 μm, or 4 μm, etc. In this case, the relatively small height difference between the patchy region and the non-patterned region is beneficial for improving the flatness of a portion of the surface of the semiconductor substrate corresponding to the textured morphology region within the conformal scale standard range of the film layer. This, in turn, helps improve the one-dimensional dimensional uniformity of the textured structure in different parts of the textured morphology region after texturing, thereby improving the deposition uniformity of the surface passivation layer on the textured morphology region and enhancing the passivation effect of the surface passivation layer.

[0081] As for the morphology and size of the velvet structure in the velvet morphology area, the morphology and size of the patch area, and the distribution of different patch areas, these can be set according to actual needs.

[0082] For example, such as Figure 5 As shown, the textured surface structure is a pyramidal structure. In this case, the pyramidal structure has a good light-trapping effect, which is beneficial to improving the conversion efficiency of the solar cell. In addition, when the textured surface morphology region 13 has a pyramidal structure, the one-dimensional dimension of the textured surface structure can refer to the side length of the base, the length of the base diagonal, the length of the side edge, or the height of the pyramidal structure.

[0083] For example, when the textured surface region has a pyramidal textured structure, at least one dimension of the textured surface structure can be greater than or equal to 0.1 μm and less than or equal to 4 μm. For instance, the one-dimensional dimension of the textured surface structure can be 0.1 μm, 0.5 μm, 0.9 μm, 1 μm, 1.2 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.8 μm, 2 μm, 2.2 μm, 2.5 μm, 3 μm, 3.5 μm, or 4 μm, etc. In this case, the one-dimensional dimension of the textured surface structure being within the above range helps to prevent the specific surface area of ​​the textured surface region from being too small due to the one-dimensional dimension being too small, thus resulting in a higher light-trapping effect in the textured surface region. Furthermore, it can also prevent the textured surface region from having a large undulation due to the one-dimensional dimension being too large, reducing the deposition quality difference of the surface passivation layer in different regions of the textured surface structure and improving the passivation effect of the surface passivation layer.

[0084] The textured structures on different parts of the textured surface region can have approximately the same size. This results in high dimensional uniformity among the different textured structures, improving the deposition quality of the passivation layer on the textured surface region. Alternatively, since the one-dimensional size of the textured structure and its corresponding light-trapping wavelength have a certain degree of matching, at least some textured structures can have different one-dimensional dimensions than the rest. This ensures that the textured surface region has a high light-trapping effect for different wavelengths of light, improving the light absorption rate of the semiconductor substrate. The distribution of textured structures with different one-dimensional dimensions can be set according to actual needs.

[0085] In practical applications, because the height of the patchy area is less than the height of the non-patchy area, the interface between these two areas has a certain angle relative to the surface of the non-patchy area. At this time, the one-dimensional size of the textured structure on the interface can be adjusted to match the one-dimensional size of the textured structure on the rest of the textured surface by adjusting the tilt angle of the interface and the height difference between the patchy and non-patchy areas. For example... Figure 11 As shown, in the velvet morphology region, the velvet structure located within the patchy region is defined as the first velvet structure 16, the velvet structure located at the boundary between the patchy and non-patchy regions is defined as the boundary velvet structure 17, and the velvet structure located within the non-patchy region is the second velvet structure 18. In this case, exemplarily, as shown... Figure 11 As shown, in the velvet structure of the velvet morphology region 13, the one-dimensional dimension of the boundary velvet structure 17 can be larger than the one-dimensional dimension of the first velvet structure 16 and the second velvet structure 18.

[0086] The difference in one-dimensional size of the textured surface in different regions can be determined based on the angle between the interface and the surface of the non-patch area, the height difference between the patch area and the non-patch area, and the morphology of the textured surface; no specific limitations are made here.

[0087] For example, the one-dimensional dimension of at least one interfacial velvet structure can be greater than or equal to 1.8 μm and less than or equal to 2.5 μm. For instance, the one-dimensional dimension of at least one interfacial velvet structure can be 1.8 μm, 1.85 μm, 1.9 μm, 2 μm, 2.05 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, or 2.5 μm, etc.

[0088] For example, the one-dimensional dimension of at least one first velvet structure and / or second velvet structure is greater than or equal to 0.9 μm and less than or equal to 1.5 μm. For instance, the one-dimensional dimension of at least one first velvet structure and / or second velvet structure can be 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.25 μm, 1.3 μm, 1.35 μm, 1.4 μm, 1.45 μm, or 1.5 μm, etc.

[0089] In some cases, such as Figure 11 As shown, when the interfacial velvet structure 17 is a pyramidal structure, the length of the side edge of the interfacial velvet structure 17 facing the non-patch area 14 can be less than the length of its side edge facing the patch area 15. In this case, because the top of the pyramid-shaped structure is sharper than its own side surface, compared with the multi-layered pyramid-shaped structure with sharp apex of the interface textured structure 17 at the junction of the patch area 15 and the non-patch area 14, when the length of the side edge of the interface textured structure 17 facing the non-patch area 14 is less than the length of its own side edge facing the patch area 15, the number of sharp apex at the junction of the patch area 15 and the non-patch area 14 can be reduced. This is beneficial to reduce the degree of undulation at the junction, improve the coverage of the surface passivation layer 12 at the junction of the patch area 15 and the non-patch area 14, solve the problem in the prior art that the surface passivation layer 12 has high requirements for the flatness of the deposition surface and the large specific surface area at the junction, resulting in poor deposition uniformity of the surface passivation layer 12 at the junction, and improve the passivation effect of the surface passivation layer 12 at the junction.

[0090] Alternatively, it could be a pyramid-shaped structure located at the boundary between patchy and non-patchy areas, where the side edges of different textured structures are roughly the same length, and the sides and top of the textured structures at the boundary together form the side of the patchy area.

[0091] Regarding the morphology of the plaque area, for example, such as Figure 13As shown, at least one patch region 15 can be polygonal or elongated. The polygon can be a regular or irregular quadrilateral, pentagon, hexagon, or octagon, etc. The corners of the polygon can be sharp or rounded. The elongated shape can be formed by multiple polygons overlapping each other along approximately the same direction. The shape of the elongated shape can be determined based on the shape and number of the included polygons, as well as the overlap between different polygons; no specific limitation is made here. In this case, at least one patch region 15 can present a discretely distributed base-like morphology. Alternatively, at least one patch region 15 can also be elongated, in which case the patch region 15 presents as a patch region 15 formed by multiple base-like morphologies overlapping each other along approximately the same direction. It is evident that the patch region 15 can have various morphologies, which can reduce manufacturing difficulty. At the same time, different patch regions 15 have different ranges, and the morphology of the patch region 15 can be set according to actual needs. This allows for the control of the distribution of the smaller patch regions 15 in the textured morphology region 13. This helps to reduce the risk of the textured morphology region 13 and the surface passivation layer 12 of the semiconductor substrate 11 being scratched to a large extent, while preventing the portion of the textured morphology region 13 and the surface passivation layer 12 located on the patch region 15 from coming into contact with the manufacturing equipment and / or transfer equipment during the corresponding manufacturing process. This is beneficial to improving the passivation effect of the surface passivation layer 12 on the semiconductor substrate 11.

[0092] The morphology of different patch areas can be the same or different. Furthermore, different patch areas can be randomly distributed within the velvety morphology area; or, as... Figure 13 As shown, multiple patch regions 15 arranged at intervals along a first direction form a patch column. Multiple patch columns are provided within the textured surface region 13, with different columns distributed at intervals along a second direction. The second direction intersects the first direction. In this case, the distribution of different patch regions 15 is relatively regular, preventing the semiconductor substrate 11 and the surface passivation layer 12 from being unable to be located inside the surface of that region due to excessive concentration of patch regions 15 in a certain area of ​​the textured surface region 13. This would make it difficult to isolate the semiconductor substrate 11 and the surface passivation layer 12 from the contact surface of the manufacturing equipment and / or transfer equipment during the corresponding manufacturing process through the higher non-patch regions 14, effectively reducing the risk of scratching the textured surface region 13 and the surface passivation layer 12 included in the semiconductor substrate 11. Furthermore, the relatively regular distribution of different patch regions 15 also helps to improve the macroscopic flatness of different areas of the textured surface region 13, effectively improving the uniform deposition of the surface passivation layer 12 on the textured surface region 13 and enhancing the passivation effect. Furthermore, the embodiments of the present invention do not specifically limit the directions referred to by the second direction and the first direction, and can set them according to actual needs. For example, the second direction and the first direction can be perpendicular.

[0093] For example, within the velvety morphology region, and within a unit area of ​​300μm × 300μm, the number of patch regions can be greater than or equal to 6 and less than or equal to 25. For instance, within the velvety morphology region, the number of patch regions distributed per unit area can be 6, 8, 10, 12, 15, 18, 20, 22, or 25, etc. In this case, the distribution of the number of patchy areas per unit area is within the aforementioned range. This helps prevent the patchy areas from being too concentrated in a certain region of the textured surface area due to an excessive number of patchy areas, or the patchy areas accounting for a large proportion of the area of ​​the textured surface area. This would make it difficult for the textured surface area and the surface passivation layer to be separated from the contact surface of the manufacturing equipment and / or transfer equipment through the contact surface of the non-patchy area with a relatively large height, thus reducing the risk of the textured surface area and the surface passivation layer being scratched. At the same time, it can also reduce the contact force such as clamping or squeezing per unit area when the manufacturing equipment and / or transfer equipment come into contact in the non-patchy area, thus reducing the risk of the semiconductor substrate and the non-patchy area corresponding to the surface passivation layer being scratched. In addition, it can prevent the area separated from the manufacturing equipment and / or transfer equipment by the patch area from the surface of the semiconductor substrate and the surface passivation layer due to the small number of patch areas, thus reducing the risk of the semiconductor substrate and the surface passivation layer being scratched. At the same time, it can also prevent the surface of the corresponding textured area of ​​the semiconductor substrate from being too smoothed due to the large number of patch areas, which is conducive to the semiconductor substrate having a larger light absorption depth in the corresponding textured area, thereby improving the light utilization rate of the semiconductor substrate.

[0094] For example, the one-dimensional size of at least one patch region can be greater than or equal to 15 μm and less than or equal to 50 μm. For instance, the one-dimensional size of at least one patch region can be 15 μm, 20 μm, 25 μm, 30 μm, 32 μm, 35 μm, 38 μm, 40 μm, 42 μm, 45 μm, 48 μm, or 50 μm, etc. In this case, having at least one patch region with a one-dimensional size within the aforementioned range helps prevent the area proportion of the patch region with a smaller height within the textured morphology region from being too small due to the one-dimensional size of the patch region being too small. This would result in most of the surface height of the textured morphology region and the side of the surface passivation layer corresponding to the textured morphology region being relatively high, making it easier for them to come into contact with the manufacturing equipment and / or transfer equipment during the corresponding manufacturing process, thus reducing the risk of scratching the textured morphology region and surface passivation layer included in the semiconductor substrate. Furthermore, it also prevents the degree of planarization treatment of the part of the surface corresponding to the textured morphology region of the semiconductor substrate before texturing due to the one-dimensional size of the patch region being too small. This helps to give the part of the surface a certain degree of macroscopic flatness, resulting in higher dimensional uniformity of the textured structure obtained after texturing this part of the surface, thereby improving the deposition quality of the surface passivation layer on the textured morphology region and enhancing the passivation effect of the surface passivation layer. Furthermore, it can prevent the large one-dimensional size of the patch region from causing a large area proportion of the patch region within the textured surface region and / or a large proportion of a certain area within the textured surface region. This would make it difficult for most of the surface of the semiconductor substrate and the surface passivation layer corresponding to the patch region to be isolated from the manufacturing equipment and / or transfer equipment during the corresponding manufacturing process by the taller non-patch region, effectively reducing the risk of scratching the textured surface region and surface passivation layer included in the semiconductor substrate. Moreover, because the taller non-patch region is located on the outside, it is easier for it to come into contact with the manufacturing equipment and / or transfer equipment. Therefore, it can also prevent the contact force per unit area such as clamping or squeezing when manufacturing equipment and / or transfer equipment come into contact in the non-patterned area due to the excessively large one-dimensional size of the patch area, which would result in a smaller area proportion of the non-patterned area. This reduces the risk of scratching the non-patterned area corresponding to the semiconductor substrate and the surface passivation layer. At the same time, it can also prevent the excessively large one-dimensional size of the patch area from causing the surface of the semiconductor substrate to be planarized to an excessive degree. This is beneficial for the semiconductor substrate to have a larger light absorption depth in the part corresponding to the textured morphology area, thereby improving the light utilization rate of the semiconductor substrate.

[0095] It should be noted that the one-dimensional dimension of a patch region can be determined based on its shape. For example, the one-dimensional dimension of a patch region can be the side length or diagonal length of a polygon. Additionally, when at least one patch region is elongated, the one-dimensional dimension can refer to the side lengths at both ends of the elongated shape, or it can refer to the width of the elongated shape. Alternatively, when the elongated shape is composed of multiple polygons overlapping each other along approximately the same direction, the one-dimensional dimension of the patch region can also be the side length or diagonal length of a single polygon after the elongated shape has been broken down into multiple polygons.

[0096] For example, the ratio of the one-dimensional dimension of the patch region to the one-dimensional dimension of the textured structure can be greater than or equal to 4 and less than or equal to 60. For instance, the ratio can be 4, 6, 8, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, or 60. In this case, the ratio of the one-dimensional dimension of the patch region to the one-dimensional dimension of the textured structure is within the above range, which can prevent the one-dimensional dimension of the patch region from being too small and / or the one-dimensional dimension of the textured structure from being too large due to an excessively small ratio. At this time, the size of the textured structure is relatively small, which can reduce the surface roughness of the textured morphology region, improve the conformal difference of the surface passivation layer on the top and base of the textured structure, and further improve the passivation effect of the surface passivation layer on the semiconductor substrate. In addition, it can prevent the one-dimensional size of the patch region from being too large and / or the one-dimensional size of the textured structure from being too small due to an excessively large ratio. This helps to reduce the light reflectivity of the corresponding textured morphology region and improve the light absorption rate of the corresponding textured morphology region of the semiconductor substrate. As for the beneficial effects of preventing the one-dimensional size of the patch region from being too large or too small, please refer to the previous text, which will not be repeated here.

[0097] Regarding the surface passivation layer, the embodiments of the present invention do not specifically limit the material and thickness of the surface passivation layer.

[0098] For example, the surface passivation layer may include at least one of an oxide layer, a nitride layer, an oxide oxynitride layer, and a carbide layer. In this case, there are many possible materials for the surface passivation layer, which helps to improve the applicability of the solar cell provided by the embodiments of the present invention in different application scenarios. In addition, surface passivation layers such as alumina layers or molybdenum oxide layers deposited by atomic layers have high requirements for the flatness of the deposition surface. Due to the presence of patchy regions, the height consistency of adjacent textured structures is higher, and at the boundary between patchy and non-patchy regions, the transition is achieved through the side of a long pyramid structure, reducing the number of sharp corners and the degree of surface undulation at the boundary. This helps to improve the deposition uniformity of surface passivation layers such as alumina layers or molybdenum oxide layers deposited by atomic layers, and improve the passivation effect of the surface passivation layer.

[0099] Optionally, the material of the surface passivation layer may include at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, and molybdenum oxide.

[0100] Furthermore, the surface passivation layer and the textured surface region are in direct contact, with no other film layers such as doped semiconductor layers or intrinsic semiconductor layers between them. Additionally, on the surface of the semiconductor substrate with the textured surface region, there are no other film layers such as doped semiconductor layers or intrinsic passivation layers on the side of the surface passivation layer facing away from the semiconductor substrate; in the case of the battery terminal, the surface passivation layer is the outermost film layer on the side of the semiconductor substrate with the textured surface region. Secondly, the surface passivation layer may be located only on the textured surface region; or, when a doped semiconductor layer is also formed on the surface of the semiconductor substrate with the textured surface region, the surface passivation layer may extend to cover the side of the doped semiconductor layer facing away from the semiconductor substrate.

[0101] The surface morphology of the region on the semiconductor substrate where the doped semiconductor layer is located can be customized according to actual needs. For example, the surface of the region on the semiconductor substrate where the doped semiconductor layer is located can be textured to increase the contact area between the doped semiconductor layer and the electrode material, thereby reducing the contact resistance. Another example: Figures 1 to 4 ,as well as Figures 6 to 10 As shown, the surface of the region on the semiconductor substrate 11 where the doped semiconductor layer is disposed is a polished morphology region, and the polished morphology region is provided with a tower-like structure. This configuration makes the surface of the region on the semiconductor substrate 11 where the doped semiconductor layer 19 is disposed relatively flat, which is beneficial to improving the deposition quality of the doped semiconductor layer 19 on the surface of this region and improving the passivation effect of the doped semiconductor layer.

[0102] For example, when both the polished morphology region and the textured morphology region are located on the first surface, the one-dimensional dimension of the tower-like structure can be smaller than the one-dimensional dimension of the patch region. In this case, when the one-dimensional dimension of the tower-like structure is smaller than the one-dimensional dimension of the patch region, it indicates that after forming a doped semiconductor layer on a portion of the semiconductor substrate, and before texturing a portion of the surface corresponding to the textured morphology region of the semiconductor substrate, a planarization process is further performed on a portion of the surface corresponding to the textured morphology region of the semiconductor substrate. This not only removes the damaged portion at the textured morphology region of the semiconductor substrate and reduces the carrier recombination rate, but also helps to improve the dimensional uniformity of the textured structure after texturing and improve the deposition uniformity of the surface passivation layer in the textured morphology region.

[0103] The one-dimensional dimensions of the tower-like structures in the polished morphology region, and the size differences between the tower-like structures in the polished morphology region and the patchy areas in the textured morphology region, can be determined based on the deposition requirements of the doped semiconductor layer, the deposition quality requirements of the surface passivation layer, and the thickness requirements of the corresponding textured morphology region of the semiconductor substrate in the actual application scenario. Furthermore, the size relationship of the one-dimensional dimensions of different tower-like structures in the polished morphology region can be set according to the structure of the doped semiconductor layer and actual needs, and is not specifically limited here.

[0104] When the doped semiconductor layer includes the first doped semiconductor portion and the second doped semiconductor portion as described above, such as Figure 10 As shown, in the polished morphology region, the surface of the region where the first doped semiconductor portion is disposed is defined as the first region 22, and the surface of the region where the second doped semiconductor portion is disposed is defined as the second region 23. Based on this, the height of the first region 22 can be greater than or equal to the height of the second region 23 along the direction from the second surface to the first surface. When the height of the first region 22 is greater than the height of the second region 23, the carrier recombination rate at the surface of the second region 23 can be reduced, thereby improving the carrier collection efficiency of the second doped semiconductor portion.

[0105] Furthermore, for example, when the height of the first region is greater than the height of the second region, the one-dimensional dimension of the tower-like structure located in the first region can be smaller than the one-dimensional dimension of the tower-like structure located in the second region. In this case, it indicates that after forming the first doped semiconductor portion on a portion of the semiconductor substrate, and before forming the second doped semiconductor portion on a portion of the surface of the semiconductor substrate corresponding to the second region, a planarization process is further performed on the portion of the surface of the semiconductor substrate corresponding to the second region. This not only removes the damage caused by the patterning process of the first doped semiconductor portion at the second region of the semiconductor substrate, reducing the carrier recombination rate, but also helps to improve the carrier collection efficiency of the second doped semiconductor portion, thereby improving the conversion efficiency of the solar cell.

[0106] For example, the ratio of the one-dimensional dimension of the tower-like structure in the second region to the one-dimensional dimension of the tower-like structure in the first region is greater than 1 and less than or equal to 3. For instance, the ratio of the one-dimensional dimension of the tower-like structure in the second region to the one-dimensional dimension of the tower-like structure in the first region can be 1.2, 1.5, 1.8, 2, 2.2, 2.5, 2.8, or 3, etc. In this case, the ratio of the one-dimensional dimension of the tower-like structure in the first region to the one-dimensional dimension of the tower-like structure in the second region is within the above range. This helps prevent the surface planarization treatment of the semiconductor substrate corresponding to the second region from being too small, or even not being performed at all, thus reducing the carrier recombination rate in the second region and improving the carrier collection efficiency of the second doped semiconductor section. It also prevents the surface planarization treatment of the second region from being too large, resulting in a larger light absorption depth in the semiconductor substrate corresponding to the second region and the textured surface region, thereby improving the light utilization rate of the semiconductor substrate.

[0107] Secondly, embodiments of the present invention provide a photovoltaic module, which includes: a battery string and an encapsulation layer. The battery string is formed by electrically connecting multiple solar cells as provided in the first aspect and its various implementations; the encapsulation layer covers the surface of the battery string.

[0108] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0109] Thirdly, embodiments of the present invention provide a method for manufacturing a solar cell, the method comprising: first, providing a semiconductor substrate; next, sequentially performing a first planarization treatment and a texturing treatment on a portion of the surface of the semiconductor substrate to form a textured region on the semiconductor substrate; the textured region includes non-patch regions and a plurality of patch regions dispersed within the non-patch regions; along the thickness direction of the semiconductor substrate, the height of the patch regions is less than the height of the non-patch regions; next, directly forming a surface passivation layer on the textured region.

[0110] It should be noted that the structure and materials of the solar cells manufactured using the manufacturing method provided in the embodiments of the present invention can be referred to the description of the structure and materials of the solar cells provided in the first aspect above, and will not be repeated here.

[0111] For example, the formation of a semiconductor substrate may include: slicing a semiconductor rod using a cutting process (e.g., diamond wire cutting) to form the semiconductor substrate; multiple cutting lines are distributed on the surface of the semiconductor substrate. In this case, before performing the first planarization and texturing processes on a portion of the surface corresponding to the textured area of ​​the semiconductor substrate, the approximate position of the patchy area recessed into the semiconductor substrate relative to the surface of the non-patterned area can be pre-defined by forming recessed cutting lines on the surface of the semiconductor substrate. In other words, by adjusting parameters such as the recess depth and length of the cutting lines during the semiconductor substrate formation process, the spacing between adjacent cutting lines, and the processing parameters of the first planarization and texturing processes performed after the semiconductor substrate is formed, it is easy to form a patchy area at the position of the cutting lines after the first planarization and texturing processes, thereby improving the dimensional uniformity of the textured structure while reducing the manufacturing difficulty of the solar cell.

[0112] In actual manufacturing processes, a semiconductor substrate can be defined as comprising a first surface and a second surface opposite to each other. For example, a textured surface region is located at least on the first surface of the semiconductor substrate; and after providing the semiconductor substrate, the method for manufacturing a solar cell further includes: forming a doped semiconductor layer on the second surface, and / or on the surface of a region on the first surface excluding the textured surface region. Based on this, the manufacturing sequence and process of the textured surface region can be determined according to the type of solar cell and the formation range of the textured surface region and the doped semiconductor layer on the semiconductor substrate.

[0113] For example, in the case of a double-sided contact solar cell, a deposition and doping process can be used to form a monolithically formed doped semiconductor layer on the first surface of the semiconductor substrate. Next, laser etching and / or wet etching processes can be used, and under the protection of a corresponding mask, the doped semiconductor layer can be patterned. Then, wet etching processes can be used, and under the protection of a corresponding mask, the first surface of the semiconductor substrate can be sequentially subjected to a first planarization and texturing process to obtain a textured surface region. As for the second surface of the semiconductor substrate, another monolithically formed doped semiconductor layer can be formed (this other doped semiconductor layer can be formed using deposition and doping processes), or another doped semiconductor layer can be formed on a local area of ​​the second surface (the formation process of this other doped semiconductor layer can refer to the manufacturing process of the doped semiconductor layer on the first surface; if the second surface also includes a textured surface region, after forming the other doped semiconductor layer, wet etching processes can be used, and under the protection of a corresponding mask, the surface of the area of ​​the second surface exposed outside the other doped semiconductor layer can be subjected to a first planarization and texturing process to obtain a textured surface region).

[0114] For example, when the manufactured solar cell is a back-contact cell, the doped semiconductor layer includes a first doped semiconductor portion and a second doped semiconductor portion spaced apart along a direction parallel to the back surface of the solar cell. Based on this, the first doped semiconductor portion and the second doped semiconductor portion can be formed on one side of the semiconductor substrate corresponding to the back surface of the cell, respectively, in accordance with the method described above for forming a doped semiconductor layer on a local area of ​​the first surface of the semiconductor substrate. Next, depending on the formation range of the textured area on the semiconductor substrate, a process such as wet etching is used to sequentially perform a first planarization process and a texturing process on only the surface of the semiconductor substrate corresponding to the front surface of the cell, or only the surface of the semiconductor substrate corresponding to the back surface of the cell located between the first doped semiconductor portion and the second doped semiconductor portion, or both the surface of the semiconductor substrate corresponding to the front surface of the cell and the surface of the semiconductor substrate corresponding to the back surface of the cell located between the first doped semiconductor portion and the second doped semiconductor portion, to obtain the textured area.

[0115] Next, after forming the textured morphology region, an atomic layer deposition process can be used to form a surface passivation layer on the textured morphology region.

[0116] The beneficial effects of the third aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0117] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0118] The embodiments of the present invention have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A solar cell, characterized in that, include: A semiconductor substrate, the semiconductor substrate including a textured region; the textured region is densely covered with textured structures; A surface passivation layer is directly applied to the textured surface area. The textured surface region includes a non-patch region and a plurality of patch regions discretely distributed within the non-patch region; the patch region is a closed pattern formed by a plurality of textured structures, and the height of the patch region is less than the height of the non-patch region along the thickness direction of the semiconductor substrate; the patch region is formed at the location of the cutting line marks of the original semiconductor substrate after sequentially undergoing a first planarization process and a texturing process.

2. The solar cell according to claim 1, characterized in that, At least one of the patch areas is polygonal or elongated in shape.

3. The solar cell according to claim 1, characterized in that, Multiple patch regions arranged at intervals along a first direction form a patch column; multiple columns of the patch column are arranged within the velvety morphology region, and different columns of the patch column are distributed at intervals along a second direction; the second direction intersects the first direction.

4. The solar cell according to claim 1, characterized in that, At least one of the patch regions has a one-dimensional size greater than or equal to 15 μm and less than or equal to 50 μm; And / or, the ratio of the one-dimensional dimension of the patch region to the one-dimensional dimension of the velvet structure is greater than or equal to 4 and less than or equal to 60; And / or, within the velvety morphology region, and in a unit area of ​​300μm×300μm, the number of the patch regions is greater than or equal to 6 and less than or equal to 25.

5. The solar cell according to claim 1, characterized in that, The velvet structure is a pyramid-shaped structure; And / or, at least one of the velvet structures has a one-dimensional dimension greater than or equal to 0.1 μm and less than or equal to 4 μm.

6. The solar cell according to claim 1, characterized in that, The height difference between at least one of the patch areas and the non-patch areas is less than 4 μm.

7. The solar cell according to claim 1, characterized in that, In the velvet morphology region, the velvet structure located in the patch region is defined as the first velvet structure, the velvet structure located at the boundary between the patch region and the non-patch region is defined as the boundary velvet structure, and the velvet structure located in the non-patch region is the second velvet structure. Wherein, at least one of the one-dimensional dimensions of the interfacial velvet structure is larger than the one-dimensional dimensions of the first velvet structure and the second velvet structure; And / or, at least one of the interface textured structures has a one-dimensional dimension greater than or equal to 1.8 μm and less than or equal to 2.5 μm; And / or, at least one of the first velvet structures and / or the second velvet structure has a one-dimensional dimension greater than or equal to 0.9 μm and less than or equal to 1.5 μm.

8. The solar cell according to claim 1, characterized in that, In the velvet morphology region, the velvet structure located at the boundary between the patchy region and the non-patchy region is defined as the boundary velvet structure; The boundary velvet structure is a pyramid-shaped structure, and the length of the side edge of the boundary velvet structure facing the non-patch area is less than the length of its own side edge facing the patch area.

9. The solar cell according to any one of claims 1 to 8, characterized in that, The surface passivation layer includes at least one of an oxide layer, a nitride layer, a oxynitride layer, and a carbide layer.

10. The solar cell according to any one of claims 1 to 8, characterized in that, The semiconductor substrate includes a first surface and a second surface opposite to each other; the textured surface region is located at least on the first surface; The solar cell further includes a doped semiconductor layer; the doped semiconductor layer is disposed on the surface of the first surface in a region other than the textured morphology region, and / or the doped semiconductor layer is disposed on the second surface.

11. The solar cell according to claim 10, characterized in that, The surface of the region on the semiconductor substrate where the doped semiconductor layer is disposed is a polished morphology region, and the polished morphology region is provided with a tower-shaped structure; When both the polished morphology region and the velvety morphology region are located on the first surface, the one-dimensional dimension of the tower-based structure is smaller than the one-dimensional dimension of the patch region.

12. The solar cell according to claim 11, characterized in that, The doped semiconductor layer includes a first doped semiconductor portion and a second doped semiconductor portion that are alternately distributed along a first surface and have opposite doping types. In the polished morphology region, the surface of the region where the first doped semiconductor portion is disposed is designated as the first region, and the surface of the region where the second doped semiconductor portion is disposed is designated as the second region; along the direction from the second surface to the first surface, the height of the first region is greater than the height of the second region; Wherein, the one-dimensional dimension of the tower-shaped structure located in the first region is smaller than the one-dimensional dimension of the tower-shaped structure located in the second region; And / or, the ratio of the one-dimensional dimension of the tower base structure located in the second region to the one-dimensional dimension of the tower base structure located in the first region is greater than 1 and less than or equal to 3.

13. The solar cell according to claim 10, characterized in that, The solar cell is a back-contact cell; the textured surface region is located in a portion of the first surface and the second surface of the semiconductor substrate; The doped semiconductor layer includes a first doped semiconductor portion and a second doped semiconductor portion that are alternately distributed along a first surface and have opposite doping types; the textured region located on the first surface is disposed between the first doped semiconductor portion and the second doped semiconductor portion.

14. A photovoltaic module, characterized in that, include: A battery string, wherein the battery string is formed by electrically connecting a plurality of solar cells as described in any one of claims 1 to 13; And an encapsulation layer that covers the surface of the battery string.

15. A method for manufacturing a solar cell, characterized in that, include: Provide semiconductor substrates; The surface of the semiconductor substrate has cutting lines; A portion of the surface of the semiconductor substrate is sequentially subjected to a first planarization process and a texturing process to form a textured morphology region on the semiconductor substrate; the textured morphology region is densely covered with textured structures; the textured morphology region includes non-patch regions and a plurality of patch regions discretely distributed within the non-patch regions; the patch regions are closed patterns formed by a plurality of textured structures, and along the thickness direction of the semiconductor substrate, the height of the patch regions is less than the height of the non-patch regions; The patchy area is formed at the location of the cutting line after sequentially undergoing a first leveling process and a texturing process; A surface passivation layer is formed directly on the velvety morphology area.

16. The method for manufacturing a solar cell according to claim 15, characterized in that, At least an atomic layer deposition process is used to form the surface passivation layer on the textured surface region.

17. The method for manufacturing a solar cell according to claim 15, characterized in that, The semiconductor substrate includes a first surface and a second surface opposite to each other; the textured surface region is located at least on the first surface; After providing the semiconductor substrate, the method for manufacturing the solar cell further includes: forming a doped semiconductor layer on the second surface and / or on the surface of the first surface in a region other than the textured morphology region.

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