A solar cell and a manufacturing method thereof, a photovoltaic module

Abstract

The application discloses a solar cell and a manufacturing method and a photovoltaic module thereof, and relates to the technical field of photovoltaics, and is used for improving the passivation effect of an amorphous silicon layer on a semiconductor substrate, and is beneficial to improving the conversion efficiency of the solar cell. The solar cell comprises a semiconductor substrate and an amorphous silicon layer. The semiconductor substrate comprises a first surface-textured region. The amorphous silicon layer is arranged on the first surface-textured region. The first surface-textured region comprises a non-plaque region and a plurality of plaque regions which are dispersed in the non-plaque region. The height of the non-plaque region is different from that of the plaque region along the thickness direction of the semiconductor substrate. The photovoltaic module comprises the solar cell. The manufacturing method of the solar cell is used for manufacturing the solar cell.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell, a manufacturing method thereof, and a photovoltaic module. BACKGROUND

[0002] A solar cell is a device capable of converting light energy of the sun into electric energy. Specifically, when the solar cell is in a working state, sunlight is shone on a p-n junction of the solar cell, forming new hole-electron pairs. Under the action of a built-in electric field in the p-n junction, the photo-generated holes flow to the p region, and the photo-generated electrons flow to the n region. After the circuit is connected, an electric current can be generated. The amorphous silicon layer has better passivation effect than the polycrystalline silicon layer, which is conducive to improving the efficiency of the solar cell. In order to improve the light absorption and utilization, the surface morphology of the silicon substrate under the amorphous silicon layer is designed into a textured morphology.

[0003] However, the existing solar cell still needs to further improve the conversion efficiency. SUMMARY

[0004] The present application aims to provide a solar cell, a manufacturing method thereof, and a photovoltaic module, for improving the passivation effect of the amorphous silicon layer on the semiconductor substrate, and for improving the conversion efficiency of the solar cell.

[0005] In order to achieve the above-mentioned purpose, in a first aspect, the present application provides a solar cell, comprising a semiconductor substrate and an amorphous silicon layer. The semiconductor substrate comprises a first textured morphology region. The first textured morphology region is densely covered with a textured structure. The amorphous silicon layer is arranged on the first textured morphology region. The first textured morphology region comprises a non-plaque region and a plurality of plaque regions dispersed in the non-plaque region. The height of the non-plaque region is different from that of the plaque region along the thickness direction of the semiconductor substrate.

[0006] In the solar cell provided by the application, the semiconductor substrate comprises a first textured surface region, and the first textured surface region comprises a non-plaque region and a plurality of plaque regions dispersed in the non-plaque region. The plaque region refers to a plaque region similar to a tower base topography presented by a plurality of textured structures included in the first textured surface region. The plaque region is a closed figure, and there is a clear boundary between the plaque region and the non-plaque region. Based on this, the first textured surface region can have a higher height consistency of adjacent textured structures due to the presence of the plaque region, so that when an amorphous silicon layer is deposited on the first textured surface region, the flow of the deposition gas to each region of the first textured surface region can be uniformly distributed, the conformality of the amorphous silicon layer on the first textured surface region (i.e., the amorphous silicon layer can follow the undulations of the surface of the first textured surface region, and the undulation degree of the amorphous silicon layer on different regions of the first textured surface region is substantially the same as the undulation degree of the surface of the first textured surface region itself) is improved, the formation quality of the amorphous silicon layer on the first textured surface region is improved, and then the passivation effect of the amorphous silicon layer on the semiconductor substrate is improved. At the same time, it is also beneficial to reduce the contact resistance between the amorphous silicon layer and the conductive material (metal electrode or transparent conductive layer) and reduce transmission loss.

[0007] As a possible implementation scheme, the shape of the at least one plaque region is polygonal or long strip-shaped.

[0008] In the above technical solution, the shape of the at least one plaque region can be polygonal, such as quadrilateral, pentagonal or hexagonal, at this time, the plaque region presents a plaque region of a discrete distribution of a tower base topography. Alternatively, the shape of the at least one plaque region can also be long strip-shaped, at this time, the plaque region presents a plaque region in which a plurality of tower base topographies are overlapped in substantially the same direction. It can be seen that the plaque region can have various topographies, which can reduce the manufacturing difficulty. At the same time, different plaque regions have different ranges, and the topography of the plaque region can be set according to actual needs, thereby regulating the flatness of the first textured surface region within the scale standard range of film layer conformality, and effectively improving the conformality of the amorphous silicon layer on the first textured surface region.

[0009] As a possible implementation scheme, a plurality of plaque regions arranged at intervals along a first direction form a plaque column. A plurality of plaque columns are arranged in the first textured surface region; different columns of plaque columns are arranged at intervals along a second direction; and the second direction intersects the first direction. In this case, the distribution of different plaque regions is more regular, which is beneficial to improve the flatness of different regions of the first textured surface region within the scale standard range of film layer conformality, effectively improve the conformality of the amorphous silicon layer on the first textured surface region, and reduce the contact resistance of different regions of the amorphous silicon layer.

[0010] As a possible implementation scheme, the one-dimensional size of the at least one plaque region is greater than or equal to 30 μm and less than or equal to 50 μm.

[0011] In the above technical solution, the one-dimensional size of the patch region is within the range, which prevents the one-dimensional size of the patch region from being too small, and thus prevents the flattening treatment of the part of the semiconductor substrate corresponding to the first textured morphology region from being too small before the texturing treatment of the part of the semiconductor substrate corresponding to the first textured morphology region, so that the part of the semiconductor substrate corresponding to the first textured morphology region has a large flatness within the scale standard range of the film layer conformality, and thus the size uniformity of the textured structures of different parts of the first textured morphology region is higher after the texturing treatment, and thus the conformality of the amorphous silicon layer on the first textured morphology region is improved, the passivation effect of the amorphous silicon layer is improved, and the contact resistance of the amorphous silicon layer is reduced. In addition, the one-dimensional size of the patch region can also be prevented from being too large, and thus the flattening treatment of the part of the semiconductor substrate corresponding to the first textured morphology region is prevented from being too large, so that the part of the semiconductor substrate corresponding to the first textured morphology region has a large light absorption depth, and the light utilization rate of the semiconductor substrate is improved.

[0012] As a possible implementation, the ratio of the one-dimensional size of the patch region to the one-dimensional size of the textured structure of the first textured morphology region is greater than or equal to 10 and less than or equal to 60.

[0013] In the above technical solution, the ratio of the one-dimensional size of the patch region to the one-dimensional size of the textured structure of the first textured morphology region is within the range, which prevents the one-dimensional size of the patch region from being too small and / or the one-dimensional size of the textured structure from being too large due to the ratio being too small, and thus improves the size uniformity of the textured structure on the first textured morphology region, reduces the surface roughness of the first textured morphology region, improves the difference in conformality of the amorphous silicon layer on the top and base of the textured structure, further improves the passivation effect of the amorphous silicon layer on the semiconductor substrate, reduces the contact resistance between the amorphous silicon layer and the conductive material, and reduces the transmission loss. In addition, the one-dimensional size of the patch region can also be prevented from being too large and / or the one-dimensional size of the textured structure from being too small due to the ratio being too large, the etching degree of the flattening treatment of the part of the semiconductor substrate corresponding to the first textured morphology region is reduced, the part of the semiconductor substrate corresponding to the first textured morphology region has a large light absorption depth, and the light reflectivity of the part corresponding to the first textured morphology region is reduced, and thus the light absorption rate of the semiconductor substrate corresponding to the first textured morphology region is improved.

[0014] As a possible implementation, within the first textured morphology region and in a unit area of 300 μm x 300 μm, the number of patch regions is greater than or equal to 6 and less than or equal to 25.

[0015] In the above technical solution, the distribution quantity of the patch area in unit area is within the above range, which prevents the surface relief pattern distribution from being too dense due to the large distribution quantity of the patch area and the height difference between the patch area and the non-patch area, further improves the flatness of the first textured pattern area within the scale standard range of the film layer conformation, improves the passivation effect of the amorphous silicon layer, and reduces the contact resistance of the amorphous silicon layer. In addition, the degree of the surface flattening treatment of the part of the semiconductor substrate corresponding to the first textured pattern area is prevented from being too large due to the small distribution quantity of the patch area, the part of the semiconductor substrate corresponding to the first textured pattern area has a large light absorption depth, and the light utilization rate of the semiconductor substrate is improved.

[0016] As a possible implementation, the first textured pattern area has a pyramid structure. In this case, the pyramid structure has good light trapping effect, which helps to improve the conversion efficiency of the solar cell.

[0017] As a possible implementation, the one-dimensional size of the at least one textured structure is greater than or equal to 0.9 μm and less than or equal to 2.5 μm.

[0018] In the above technical solution, the one-dimensional size of the textured structure is within the above range, which prevents the specific surface area of the first textured pattern area from being too small due to the small one-dimensional size of the textured structure, makes the first textured pattern area have high light trapping effect, prevents the relief degree of the first textured pattern area from being too large due to the large one-dimensional size of the textured structure, reduces the deposition quality difference of the amorphous silicon layer in different regions of the textured structure, improves the conformation of the amorphous silicon layer on the first textured pattern area, improves the passivation effect of the amorphous silicon layer, and reduces the contact resistance of the amorphous silicon layer.

[0019] As a possible implementation, the height of the patch area is less than the height of the non-patch area.

[0020] As a possible implementation, the height difference between the at least one patch area and the non-patch area is less than 3 μm.

[0021] In the above technical solution, the height difference between the patch area and the non-patch area is relatively small, which helps to improve the flatness of the part of the semiconductor substrate corresponding to the first textured pattern area within the scale standard range of the film layer conformation, thereby improving the uniformity of the one-dimensional size of the textured structure of different parts of the first textured pattern area after the texturing treatment, further improving the conformation of the amorphous silicon layer on the first textured pattern area, improving the passivation effect of the amorphous silicon layer, and reducing the contact resistance of the amorphous silicon layer.

[0022] As a possible implementation scheme, in the first surface texturing area, the surface texture structure located in the plaque area is defined as a first surface texture structure, the surface texture structure located at the junction of the plaque area and the non-plaque area is defined as a junction surface texture structure, and the surface texture structure located in the non-plaque area is a second surface texture structure. The one-dimensional size of at least one junction surface texture structure is greater than the one-dimensional size of the first surface texture structure and the second surface texture structure; and / or, the one-dimensional size of at least one junction surface texture structure is greater than or equal to 1.8 μm and less than or equal to 2.5 μm; and / or, the one-dimensional size of at least one first surface texture structure and / or second surface texture structure is greater than or equal to 0.9 μm and less than or equal to 1.5 μm.

[0023] In the case of the above technical solution, the one-dimensional size of the surface texture structure has a certain matching with the corresponding light trapping wavelength, and when the one-dimensional size of the junction surface texture structure is different from the one-dimensional size of the first surface texture structure, the first surface texturing area has a higher light trapping effect for light of different wavelengths, thereby improving the light absorption rate of the semiconductor substrate.

[0024] As a possible implementation scheme, in the first surface texturing area, the surface texture structure located at the junction of the plaque area and the non-plaque area is defined as a junction surface texture structure, and the junction surface texture structure is a pyramid structure, and the length of the side edge of the junction surface texture structure facing the non-plaque area is less than the length of the side edge of the junction surface texture structure facing the plaque area.

[0025] In the case of the above technical solution, because the top of the pyramid structure is sharper than the side surface, compared with the case where the junction surface texture structure at the junction of the plaque area and the non-plaque area is a multi-layer pyramid structure with a sharp top corner, when the length of the side edge of the junction surface texture structure facing the non-plaque area is less than the length of the side edge of the junction surface texture structure facing the plaque area, the number of sharp top corners can be reduced, which is conducive to reducing the degree of fluctuation at the junction of the plaque area and the non-plaque area, improving the coverage of the amorphous silicon layer at the junction of the plaque area and the non-plaque area, improving the conformality of the amorphous silicon layer at the junction, and improving the passivation effect of the amorphous silicon layer at the junction.

[0026] As a possible implementation scheme, the amorphous silicon layer includes an intrinsic silicon layer and a doped silicon layer located on the side of the intrinsic silicon layer away from the semiconductor substrate. In this case, the passivation effect of the amorphous silicon layer on the semiconductor substrate can be further improved, and at least the carrier recombination rate at the first surface texturing area can be reduced.

[0027] As a possible implementation scheme, the solar cell further includes a doped semiconductor layer; the doped semiconductor layer and the amorphous silicon layer are located on the same side of the semiconductor substrate, and the conductive types of the doped semiconductor layer and the amorphous silicon layer are opposite. In this case, the solar cell is a back contact cell, which can reduce the light utilization rate on the front side of the cell and improve the conversion efficiency of the solar cell.

[0028] As a possible implementation, the semiconductor substrate is provided with a region of the doped semiconductor layer, and the region of the doped semiconductor layer has a polishing topography. The amorphous silicon layer also extends to cover part of the doped crystalline silicon layer.

[0029] As a possible implementation, the polishing topography is provided with a tower base structure. The one-dimensional size of the tower base structure is less than the one-dimensional size of the patch region; and / or, the one-dimensional size of the tower base structure is greater than or equal to 10 μm and less than or equal to 20 μm; and / or, the ratio of the one-dimensional size of the patch region to the one-dimensional size of the tower base structure is greater than or equal to 1.5 and less than 4.

[0030] In the case of the above technical solution, when the one-dimensional size of the tower base structure is less than the one-dimensional size of the patch region, it indicates that after forming the doped semiconductor layer on part of the semiconductor substrate, and before performing the texturing process on the part of the semiconductor substrate corresponding to the first texturing topography, the part of the semiconductor substrate corresponding to the first texturing topography is further subjected to a planarization process. This not only removes the damaged part of the semiconductor substrate corresponding to the first texturing topography, reduces the carrier recombination rate, and improves the carrier collection capability of the amorphous silicon layer; but also helps to improve the size uniformity of the textured structure after the texturing process, and improve the conformality of the amorphous silicon layer in the first texturing topography.

[0031] In addition, the one-dimensional size of the tower base structure is within the above range, which helps to prevent the planarization process of the semiconductor substrate from being too small before the doped semiconductor layer is formed, thereby reducing the roughness of the semiconductor substrate surface and improving the formation quality of the doped semiconductor layer on the polishing topography. It can also prevent the planarization process of the semiconductor substrate from being too large, which helps to make the semiconductor substrate have a large light absorption depth and mechanical strength.

[0032] As for the beneficial effects of the ratio of the one-dimensional size of the patch region to the one-dimensional size of the tower base structure within the above range, the application principles can be referred to the application principles of the beneficial effects of preventing the one-dimensional size of the tower base structure from being too large or too small, and preventing the one-dimensional size of the patch region from being too large or too small, which are described above, and will not be repeated here.

[0033] As a possible implementation, the amorphous silicon layer includes a crystallization region, and the orthogonal projection of the crystallization region on the semiconductor substrate is located within the first texturing topography. In this case, the part of the amorphous silicon layer located in the crystallization region is not completely crystallized, but the crystallization degree of the part of the amorphous silicon layer located in the crystallization region is higher than that of the remaining part of the amorphous silicon layer, which helps to improve the conductivity and effective doping concentration of the amorphous silicon layer on the first texturing topography, reduce the contact resistance and transmission loss, and improve the contact performance.

[0034] As a possible implementation, the solar cell further comprises a transparent conductive layer, the transparent conductive layer is arranged on the side of the amorphous silicon layer away from the semiconductor substrate.

[0035] In the case of the above technical solution, when the amorphous silicon layer has good conformality on the first texturing morphology region, the transparent conductive layer deposited on the amorphous silicon layer also has high conformality, which is conducive to reducing the contact resistance between the transparent conductive layer and the amorphous silicon layer and improving the contact performance.

[0036] In a second aspect, the present application provides a photovoltaic module, comprising: a cell string and an encapsulation layer. The cell string is formed by electrically connecting a plurality of solar cells as provided in the first aspect and various implementation manners thereof; and the encapsulation layer covers the surface of the cell string.

[0037] The beneficial effects of the second aspect and various implementation manners thereof in the present application can be analyzed with reference to the beneficial effects in the first aspect and various implementation manners thereof, which will not be described here again.

[0038] In a third aspect, the present application provides a manufacturing method of a solar cell, comprising: first, forming a semiconductor substrate. Next, sequentially performing first planarization treatment and texturing treatment on at least part of the surface of the semiconductor substrate to form a first texturing morphology region on the semiconductor substrate; the first texturing morphology region comprises a non-mottling region and a plurality of mottling regions dispersed in the non-mottling region; the height of the non-mottling region is different from that of the mottling region along the thickness direction of the semiconductor substrate. Next, forming an amorphous silicon layer on the first texturing morphology region.

[0039] As a possible implementation, forming a semiconductor substrate comprises: performing slicing treatment on a semiconductor rod material by using a cutting process to form the semiconductor substrate; a plurality of cutting line marks are distributed on the surface of the semiconductor substrate. Next, performing second planarization treatment on the surface of the semiconductor substrate.

[0040] In the case of the above technical solution, in the actual manufacturing process, before performing first planarization treatment and texturing treatment on the part of the surface of the semiconductor substrate corresponding to the first texturing morphology region, the approximate position of the mottling region recessed into the semiconductor substrate relative to the surface of the non-mottling region can be preset by forming recessed cutting line marks on the surface of the semiconductor substrate, in other words, by adjusting the recessed depth of the cutting line marks and the processing parameters of the second planarization treatment, the first planarization treatment and the texturing treatment, it is easy to form the mottling region at the position of the line mark after the second planarization treatment, the first planarization treatment and the texturing treatment, thereby improving the uniformity of the texturing structure size while reducing the manufacturing difficulty of the solar cell.

[0041] As a possible implementation, the total etching depth of the second planarization treatment and the first planarization treatment on the part of the semiconductor substrate corresponding to the first textured morphology region is less than the recess depth of the at least one scribe line mark in the semiconductor substrate.

[0042] As a possible implementation, after forming the semiconductor substrate, before sequentially performing the first planarization treatment and the texturing treatment on at least part of the surface of the semiconductor substrate, the method for manufacturing the solar cell further comprises: forming a doped semiconductor layer on the part of the surface of the semiconductor substrate corresponding to the amorphous silicon layer; the doped semiconductor layer and the amorphous silicon layer are opposite in conductive type.

[0043] The beneficial effects of the third aspect and various implementations thereof in the present application can be analyzed with reference to the beneficial effects of the first aspect and various implementations thereof, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0044] The accompanying drawings, which are included to provide a further understanding of the present application, form a part of the present application and are included to further explain the present application and, together with the description, serve to explain the present application. The present application is not limited by the accompanying drawings. In the drawings:

[0045] Figure 1 A longitudinal sectional view of a first structure of a solar cell according to an embodiment of the present application;

[0046] Figure 2 A longitudinal sectional view of a second structure of a solar cell according to an embodiment of the present application;

[0047] Figure 3 A longitudinal sectional view of a third structure of a solar cell according to an embodiment of the present application;

[0048] Figure 4 A longitudinal sectional view of a fourth structure of a solar cell according to an embodiment of the present application;

[0049] Figure 5 A longitudinal sectional view of a fifth structure of a solar cell according to an embodiment of the present application;

[0050] Figure 6 An SEM image of a solar cell according to an embodiment of the present application at a spot region;

[0051] Figure 7 An SEM image of a solar cell according to an embodiment of the present application at the junction of a spot region and a non-spot region Figure 1 ;

[0052] Figure 8 A schematic diagram of the distribution relationship between the textured structure and the spot region in a solar cell according to an embodiment of the present application;

[0053] Figure 9 SEM of a solar cell according to an embodiment of the present application at the junction of a spot region and a non-spot region Figure 2 ;

[0054] Figure 10 3D microscope image of a partial region of a first textured region of a solar cell according to an embodiment of the present application

[0055] Figure 11 3D microscope image of another partial region of a first textured region of a solar cell according to an embodiment of the present application

[0056] Figure 12 Longitudinal sectional view of a sixth structure of a solar cell according to an embodiment of the present application

[0057] Figure 13 Longitudinal sectional view of a seventh structure of a solar cell according to an embodiment of the present application

[0058] Figure 14 SEM of a solar cell according to an embodiment of the present application at a partial amorphous silicon layer

[0059] Figure 15 Longitudinal sectional view of an eighth structure of a solar cell according to an embodiment of the present application

[0060] Figure 16 Longitudinal sectional view of a ninth structure of a solar cell according to an embodiment of the present application

[0061] Reference numeral 11 is a semiconductor substrate, 12 is an amorphous silicon layer, 13 is a non-spot region, 14 is a spot region, 15 is an intrinsic silicon layer, 16 is a doped silicon layer, 17 is a doped semiconductor layer, 18 is an interface passivation layer, 19 is a crystallization region, and 20 is a transparent conductive layer. DETAILED DESCRIPTION

[0062] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. It should be understood, however, that the description which follows is merely illustrative and is not intended to limit the scope of the present application. Further, in the following description, descriptions of well-known structures and techniques are omitted to avoid obscuring the concept of the present application.

[0063] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0064] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0065] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0066] In a first aspect, embodiments of the present invention provide a solar cell. The solar cell can be a bifacial cell or a back-contact cell. Embodiments of the present invention do not specifically limit the type of solar cell.

[0067] like Figure 1 As shown, the solar cell provided in this embodiment of the invention includes: a semiconductor substrate 11 and an amorphous silicon layer 12. The semiconductor substrate 11 includes a first textured surface region. Figure 1 As shown, the first textured morphology region is densely covered with textured structures. An amorphous silicon layer 12 is disposed on the first textured morphology region.

[0068] like Figure 1 As shown, the first textured surface region includes a non-patterned region 13 and a plurality of patchy regions 14 dispersed within the non-patterned region 13. The non-patterned region 13 and the patchy regions 14 have different heights along the thickness direction of the semiconductor substrate 11.

[0069] The first velvety morphology region comprises multiple velvety structures forming a closed patch region. Specifically, the patch region 14 is generally distinguishable in 3D or SEM microscopic images due to its different elevation from other regions (i.e., non-patch region 13), and presents a closed blocky pattern. Figure 6 The hexagonal block pattern shown in the SEM image. For example... Figure 10 The blue block pattern shown in the 3D microscope image, and Figure 11 The purple block pattern shown in the 3D microscope image.

[0070] The inventors of this application discovered that when there are patchy areas in the first textured morphology region, the height consistency of adjacent textured structures is higher. That is, the height of textured structures in the short range within non-patchy areas is more consistent, and the height of textured structures within patchy areas is more consistent. As a result, when depositing the amorphous silicon layer 12 on the first textured morphology region, the flow rate of the deposition gas to each region of the first textured morphology region can be evenly distributed, improving the conformality of the amorphous silicon layer 12 on the first textured morphology region, improving the formation quality of the amorphous silicon layer 12 on the first textured morphology region, and thus improving the passivation effect of the amorphous silicon layer 12 on the semiconductor substrate 11. At the same time, it also helps to reduce the contact resistance between the amorphous silicon layer 12 and the conductive material (metal electrode or transparent conductive layer), reduce transmission loss, and improve the conversion efficiency of the solar cell.

[0071] In the actual manufacturing process, before forming the amorphous silicon layer, at least a portion of the surface of the semiconductor substrate corresponding to the first textured morphology region is first planarized, and then this portion of the surface is texturized to obtain patchy and non-patchy regions. After planarization, the deep line marks on the original semiconductor substrate leave behind patchy rudimentary regions that are internally flat but have a height difference from other areas. In the subsequent texturizing process, by controlling the size of the formed textured structure and the texturizing time, a dense network of small textured structures is formed, without completely destroying the planarization marks, thus allowing the patchy rudimentary regions to form patchy regions. It is understandable that the one-dimensional size of the textured structure formed by planarization cannot be too small, and the one-dimensional size of the textured structure during texturizing cannot be too large; otherwise, it will be difficult to form patchy regions.

[0072] The one-dimensional size of the patch region, the depth and distribution density of deep lines in the original semiconductor substrate, the control of polishing morphology, and the control of textured surface structure can be adjusted by those skilled in the art according to the actual situation.

[0073] It is worth noting that the original semiconductor substrate with deep line marks is sequentially subjected to the planarization treatment and the texturing treatment, so that the first textured morphology region formed has greater flatness within the scale standard range of film layer conformality, while damage to the original semiconductor substrate and defects are removed more completely under the condition of low weight reduction; and the textured structure on the surface of the non-mottling region and on the tower base main surface (the tower base top surface when the height of the mottling region is greater than the height of the non-mottling region, and the tower base bottom surface when the height of the mottling region is less than the height of the non-mottling region) of the mottling region has higher size uniformity and higher height consistency.

[0074] The larger texture structure retained after the planarization treatment can further ensure that damage to the original semiconductor substrate and defects are removed more completely under the condition of low weight reduction; and the smaller one-dimensional size textured structure formed after the texturing treatment can further make the amorphous silicon layer have better conformality.

[0075] In actual application, the distribution range of the first textured morphology region on the semiconductor substrate is not specifically limited in the embodiments of the present application, and can be determined according to the type of the solar cell and the requirement for the formation range of the amorphous silicon layer on the semiconductor substrate in the actual application scenario, which is not specifically limited here.

[0076] For example, as shown in FIG. 1, the semiconductor substrate 11 corresponding to the front side (the light directly irradiated surface) of the solar cell can include the first textured morphology region. Figures 1 to 3 As shown in FIG. 2, the semiconductor substrate 11 corresponding to the back side of the solar cell can include the first textured morphology region. Figures 1 to 3 As shown in FIG. 3, the semiconductor substrate 11 corresponding to the front side and the back side of the solar cell can include the first textured morphology region. Figure 4 As shown in FIG. 4, the first textured morphology region can be a local region in the front side and / or the back side of the semiconductor substrate 11.

[0077] For example, as shown in FIG. 5, the semiconductor substrate 11 corresponding to the back side of the solar cell can include the first textured morphology region (for example, the back side of the back contact solar cell is provided with an amorphous silicon layer for collecting carriers). Figure 5 As shown in FIG. 6, the semiconductor substrate 11 corresponding to the front side of the solar cell can include the first textured morphology region (for example, the front side of the back contact solar cell is provided with a passivation layer including an amorphous silicon layer).

[0078] As shown in FIG. 7, the semiconductor substrate 11 corresponding to the front side and the back side of the solar cell can include the first textured morphology region.Figures 1 to 5 As shown, the height of the at least one patch region can be less than the height of the non-patch region.

[0079] Alternatively, the height of the at least one patch region can be greater than the height of the non-patch region.

[0080] As for the height difference between the two regions, it can be set according to the requirements for the conformality of the amorphous silicon layer, the light-trapping requirements for the first texturing region, and the thickness requirements for different regions of the semiconductor substrate according to the actual application scenario.

[0081] For example, the height difference between the at least one patch region and the non-patch region can be 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, or 3 μm, etc. In this case, the height difference between the patch region and the non-patch region is relatively small, which is conducive to improving the flatness of the part of the surface of the semiconductor substrate corresponding to the first texturing region within the dimensional standard range of the film layer conformality, thereby improving the one-dimensional size uniformity of the texturing structure of different parts of the first texturing region after the texturing process, and further improving the conformality of the amorphous silicon layer on the first texturing region, improving the passivation effect of the amorphous silicon layer, and reducing the contact resistance of the amorphous silicon layer.

[0082] As for the morphology and size of the texturing structure of the first texturing region, the morphology and size of the patch region, and the distribution of different patch regions, they can be set according to actual requirements.

[0083] For example, as shown in FIG. 1, the first texturing region can have a plurality of patch regions 14, and the patch regions 14 can be distributed in the first texturing region in a staggered manner. Figures 1 to 5 As shown, the texturing structure of the first texturing region can be a pyramid structure. In this case, the pyramid structure has good light-trapping effect, which is conducive to improving the conversion efficiency of the solar cell. In addition, when the texturing structure of the first texturing region is a pyramid structure, the one-dimensional size of the texturing structure can refer to the length of the base side, the length of the base diagonal, the length of the side edge, or the height of the pyramid structure, etc.

[0084] Exemplarily, in the case that the first rough surface morphology region has pyramid-shaped rough surface structures, the one-dimensional size of the rough surface structures can be 0.9 μm and less than or equal to 2.5 μm. For example, the one-dimensional size of the rough surface structures can be 0.9 μm, 1 μm, 1.2 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.8 μm, 2 μm, 2.2 μm or 2.5 μm, etc. In this case, the one-dimensional size of the rough surface structures is within the above range, which is beneficial to prevent the specific surface area of the first rough surface morphology region from being too small due to the one-dimensional size of the rough surface structures being too small, and thus the first rough surface morphology region has a higher light-trapping effect. In addition, it can also prevent the first rough surface morphology region from having a larger fluctuation degree due to the one-dimensional size of the rough surface structures being too large, reduce the difference in deposition quality of the amorphous silicon layer on different regions of the rough surface structures, improve the conformality of the amorphous silicon layer on the first rough surface morphology region, improve the passivation effect of the amorphous silicon layer, and reduce the contact resistance of the amorphous silicon layer.

[0085] The sizes of the rough surface structures on different parts of the first rough surface morphology region can be substantially the same, in which case the uniformity of the sizes of the different rough surface structures is higher, which can improve the deposition quality of the amorphous silicon layer on the first rough surface morphology region. Alternatively, due to the size of the one-dimensional size of the rough surface structures and the matching of the corresponding light-trapping wavelength, the one-dimensional size of at least part of the rough surface structures (such as the junction between the patch region and the non-patch region) can be different from the one-dimensional size of the rough surface structures on the rest of the region, so as to facilitate the first rough surface morphology region to have a higher light-trapping effect for light of different wavelengths, and improve the light absorption rate of the semiconductor substrate. The distribution of the rough surface structures with different one-dimensional sizes can be set according to actual needs.

[0086] In actual application, due to the height difference between the patch region and the non-patch region, the junction between the two regions has a certain angle relative to the surface of the non-patch region, in which case the one-dimensional size of the rough surface structures on the junction between the patch region and the non-patch region can be adjusted by adjusting the inclination angle of the junction between the patch region and the non-patch region and the height difference between the patch region and the non-patch region, and the size relationship with the one-dimensional size of the rough surface structures on the surface of the rest of the first rough surface morphology region. In the first rough surface morphology region, the rough surface structures in the patch region are defined as first rough surface structures, the rough surface structures at the junction between the patch region and the non-patch region are defined as junction rough surface structures, and the rough surface structures in the non-patch region are defined as second rough surface structures. In this case, exemplarily, as shown in FIGS. 1A and 1B, the one-dimensional size of the junction rough surface structures can be greater than the one-dimensional size of the first rough surface structures and the second rough surface structures. Figure 6 and Figure 7 In the rough surface structures of the first rough surface morphology region, the one-dimensional size of the junction rough surface structures can be greater than the one-dimensional size of the first rough surface structures and the second rough surface structures.

[0087] The difference in one-dimensional size of the textured surface in different regions can be determined based on the angle between the interface and the surface of the non-patch area, the height difference between the patch area and the non-patch area, and the morphology of the textured surface; no specific limitations are made here.

[0088] For example, the one-dimensional dimension of at least one interfacial velvet structure can be greater than or equal to 1.8 μm and less than or equal to 2.5 μm. For instance, the one-dimensional dimension of at least one interfacial velvet structure can be 1.8 μm, 1.85 μm, 1.9 μm, 2 μm, 2.05 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, or 2.5 μm, etc.

[0089] For example, the one-dimensional dimension of at least one first velvet structure and / or second velvet structure is greater than or equal to 0.9 μm and less than or equal to 1.5 μm. For instance, the one-dimensional dimension of at least one first velvet structure and / or second velvet structure can be 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.25 μm, 1.3 μm, 1.35 μm, 1.4 μm, 1.45 μm, or 1.5 μm, etc.

[0090] In some cases, such as Figures 6 to 9 As shown, when the interface textured structure is a pyramidal structure, the length of the side edge of the interface textured surface facing the non-patch region 13 can be less than the length of its side edge facing the patch region 14. In this case, because the top of the pyramidal structure is sharper than its own side surface, compared with a multi-layered pyramidal structure with sharp apex angles at the interface textured surface at the junction of patch region 14 and non-patch region 13, when the length of the side edge of the interface textured surface facing the non-patch region 13 is less than the length of its own side edge facing the patch region 14, the number of sharp apex angles can be reduced. This is beneficial for reducing the undulation at the junction of patch region 14 and non-patch region 13, improving the coverage of the amorphous silicon layer 12 on the side of patch region 14, increasing the conformality of the amorphous silicon layer 12 on the side of patch region 14, and improving the passivation effect of the amorphous silicon layer 12 on the side of patch region 14. It should be noted that... Figure 6 and Figure 7 The red dotted line in the middle, and Figure 9 The black dashed lines in the diagram roughly indicate the boundary between patch area 14 and non-patch area 13.

[0091] Alternatively, it could be a pyramid-shaped structure located at the boundary between patchy and non-patchy areas, where the side edges of different textured structures are roughly the same length, and the sides and top of the textured structures at the boundary together form the side of the patchy area.

[0092] Regarding the morphology of the plaque area, for example, such as Figure 6 , Figure 10 and Figure 11As shown, the shape of the at least one patch region 14 can be polygonal or strip-shaped. The polygonal shape can be regular or irregular quadrilateral, pentagon, hexagon, octagon, etc. The corners of the polygonal shape can be sharp or rounded. The strip-shaped can be formed by a plurality of polygonal shapes overlapping each other in the same direction. The shape of the strip-shaped can be determined by the shape, number, and overlapping of the polygonal shapes, which is not limited here. In this case, the at least one patch region 14 can be a patch region with a discrete distribution of tower base shapes. Alternatively, the shape of the at least one patch region 14 can be strip-shaped, in which case the patch region 14 is a patch region with a plurality of tower base shapes overlapping each other in the same direction. As can be seen, the patch region 14 can have various shapes, which can reduce the manufacturing difficulty. At the same time, different patch regions have different ranges, and the shape of the patch region 14 can be set according to actual needs, thereby regulating the flatness of the first textured surface in the scale standard range of the film layer conformality, effectively improving the conformality of the amorphous silicon layer 12 on the first textured surface.

[0093] The shapes of different patch regions can be the same or different. In addition, the different patch regions can be randomly distributed in the first textured surface, or a plurality of patch regions spaced apart along the first direction form a patch column. The first textured surface can be provided with a plurality of patch columns, and the different patch columns are spaced apart along the second direction. The second direction and the first direction intersect. In this case, the distribution of different patch regions is relatively regular, which is beneficial to improve the flatness of different regions of the first textured surface in the scale standard range of the film layer conformality, effectively improve the conformality of the amorphous silicon layer on the first textured surface, and reduce the contact resistance of different regions of the amorphous silicon layer. In addition, the directions of the second direction and the first direction are not limited by the embodiments of the present application, and can be set according to actual needs. For example, the second direction and the first direction can be perpendicular.

[0094] For example, the number of the distribution of the patch region in the first textured surface region and in a unit area of 300 μm x 300 μm can be greater than or equal to 6 and less than or equal to 25. For example, the number of the distribution of the patch region in the unit area in the first textured surface region can be 6, 8, 10, 12, 15, 18, 20, 22 or 25, etc. In this case, the number of the distribution of the patch region is in the above range, which is beneficial to prevent the surface relief distribution from being too dense due to the number of the distribution of the patch region being too large, and further improve the flatness of the first textured surface region in the dimensional standard range of the film layer conformality, which is beneficial to improve the passivation effect of the amorphous silicon layer and reduce the contact resistance of the amorphous silicon layer. In addition, it can also prevent the degree of the surface flattening treatment of the part of the semiconductor substrate corresponding to the first textured surface region from being too large due to the number of the distribution of the patch region being too small, which is beneficial to make the part of the semiconductor substrate corresponding to the first textured surface region have a larger light absorption depth and improve the light utilization rate of the semiconductor substrate.

[0095] For example, the one-dimensional size of the at least one patch region can be greater than or equal to 30 μm and less than or equal to 50 μm. For example, the one-dimensional size of the at least one patch region can be 30 μm, 32 μm, 35 μm, 38 μm, 40 μm, 42 μm, 45 μm, 48 μm or 50 μm, etc. In this case, the one-dimensional size of the at least one patch region is in the above range, which is beneficial to prevent the degree of the surface flattening treatment of the part of the semiconductor substrate corresponding to the first textured surface region from being too small due to the one-dimensional size of the patch region being too small, which is beneficial to make the part of the surface have a larger flatness in the dimensional standard range of the film layer conformality, so that the size uniformity of the textured surface structure of different parts of the first textured surface region is higher after the texturing treatment, and further improve the conformality of the amorphous silicon layer on the first textured surface region, improve the passivation effect of the amorphous silicon layer, and be beneficial to reduce the contact resistance of the amorphous silicon layer. In addition, it can also prevent the degree of the surface flattening treatment of the part of the semiconductor substrate corresponding to the first textured surface region from being too large due to the one-dimensional size of the patch region being too large, which is beneficial to make the part of the semiconductor substrate corresponding to the first textured surface region have a larger light absorption depth and improve the light utilization rate of the semiconductor substrate.

[0096] It should be noted that the one-dimensional size of the patch region can be determined according to its shape. For example, the one-dimensional size of the patch region can be the length of a side or a diagonal of a polygon, etc. In addition, when the shape of the at least one patch region is a long strip formed by a plurality of polygons overlapping each other in substantially the same direction, the one-dimensional size of the patch region can be the length of a side at both ends of the long strip in the length direction, or can also be the width of the long strip, or can also be the length of a side or a diagonal of a single polygon after the long strip is disassembled into a plurality of polygons.

[0097] For example, the ratio of the one-dimensional dimension of the patch region to the one-dimensional dimension of the textured structure in the first textured region can be greater than or equal to 10 and less than or equal to 60. For instance, the ratio can be 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, or 60. In this case, the ratio of the one-dimensional dimension of the patch region to the one-dimensional dimension of the textured structure in the first textured region is within the above range. This prevents the one-dimensional dimension of the patch region from being too small and / or the one-dimensional dimension of the textured structure from being too large due to an excessively small ratio. This improves the dimensional uniformity of the textured structure in the first textured region while reducing the surface roughness of the first textured region, improving the conformal differences of the amorphous silicon layer on the top and base of the textured structure, further enhancing the passivation effect of the amorphous silicon layer on the semiconductor substrate, and simultaneously reducing the contact resistance between the amorphous silicon layer and the conductive material, thus reducing transmission loss. In addition, it can prevent the one-dimensional size of the patch region from being too large and / or the one-dimensional size of the textured structure from being too small due to the excessive ratio. It can also reduce the etching degree of the part of the semiconductor substrate corresponding to the first textured morphology region by the planarization process, so that the part of the semiconductor substrate corresponding to the first textured morphology region has a larger light absorption depth, while helping to reduce the light reflectivity of the part corresponding to the first textured morphology region and improve the light absorption rate of the semiconductor substrate corresponding to the first textured morphology region.

[0098] For amorphous silicon layers, such as Figure 1 As shown, the amorphous silicon layer 12 may consist only of the doped silicon layer 16. Alternatively, as... Figure 12 As shown, the amorphous silicon layer 12 may include an intrinsic silicon layer 15 and a doped silicon layer 16 located on the side of the intrinsic silicon layer 15 away from the semiconductor substrate 11; in this case, the passivation effect of the amorphous silicon layer 12 on the semiconductor substrate 11 can be further improved, at least reducing the carrier recombination rate at the first textured morphology region.

[0099] The conductivity type of the doped silicon layer included in the amorphous silicon layer can be set according to actual needs, and is not specifically limited here. For example, the conductivity type of the doped silicon layer can be the opposite or the same as the conductivity type of the semiconductor substrate.

[0100] In some cases, such as Figure 12 and Figure 13 As shown, the solar cell provided in this embodiment of the invention may further include a doped semiconductor layer 17. Furthermore, the doped semiconductor layer 17 has the opposite conductivity type to the amorphous silicon layer 12. The location of the doped semiconductor layer 17 on the semiconductor substrate 11 can be determined according to the type of solar cell and actual needs, and is not specifically limited here.

[0101] like Figure 13As shown in the figure, in the case of a double-sided contact solar cell, one of the amorphous silicon layer 12 and the doped semiconductor layer 17 is arranged on the front side of the semiconductor substrate 11, and the other is arranged on the back side of the semiconductor substrate 11.

[0102] Alternatively, as shown in the figure, in the case of a back contact solar cell, both the amorphous silicon layer 12 and the doped semiconductor layer 17 are arranged on the back side of the semiconductor substrate 11. In this case, the solar cell provided by the embodiment of the present application is a back contact solar cell, which can reduce the influence of the light-shielding electrode structure on the light utilization rate on the front side, and further improve the photoelectric conversion efficiency of the solar cell. At this time, the amorphous silicon layer 12 and the doped semiconductor layer 17 can be spaced apart in a direction parallel to the back side of the semiconductor substrate 11; or, as shown in the figure, the amorphous silicon layer 12 can also extend to cover part of the doped semiconductor layer 17 on the side away from the semiconductor substrate 11, which can reduce the etching amount of the selective etching of the amorphous silicon material used to manufacture the amorphous silicon layer 12 and arranged in an integral layer when forming the amorphous silicon layer 12, and is conducive to improving the manufacturing efficiency of the solar cell. Figure 12 Figure 12

[0103] In addition, the surface topography of the region of the semiconductor substrate provided with the doped semiconductor layer can be set according to the setting position of the doped semiconductor layer on the semiconductor substrate, the material of the doped semiconductor layer, and the actual demand, which is not specifically limited here.

[0104] For example, in the case of a double-sided contact solar cell and the doped semiconductor layer is arranged on the back side of the semiconductor substrate, the surface of the region of the semiconductor substrate provided with the doped semiconductor layer can be a flat surface, which is conducive to improving the deposition quality of the doped semiconductor layer.

[0105] For example, in the case of a double-sided contact solar cell and the doped semiconductor layer is arranged on the front side of the semiconductor substrate, the surface of the region of the semiconductor substrate provided with the doped semiconductor layer can be a textured surface, which can improve the light trapping effect of the front side of the semiconductor substrate and improve the conversion efficiency of the solar cell.

[0106] For example, in the case of the amorphous silicon layer and the doped semiconductor layer being arranged on the same side of the semiconductor substrate, as shown in the figure, the surface of the region of the semiconductor substrate 11 provided with the doped semiconductor layer 17 can be a polished topography region, which is conducive to improving the deposition quality and passivation effect of the doped semiconductor layer 17 and reducing the carrier recombination rate. In addition, the polished topography region is provided with a tower base-like structure. Figure 12

[0107] ​​​Exemplarily, the one-dimensional size of the tower-like structure can be smaller than the one-dimensional size of the patch region. In this case, after forming the doped semiconductor layer on the partial region of the semiconductor substrate, and before performing the texturing treatment on the partial surface of the semiconductor substrate corresponding to the first texturing topography region, further performing the planarization treatment on the partial surface of the semiconductor substrate corresponding to the first texturing topography region can not only remove the damaged part of the semiconductor substrate corresponding to the first texturing topography region, reduce the carrier recombination rate, and improve the carrier collection capability of the amorphous silicon layer, but also facilitate improving the size uniformity of the texturing structure after the texturing treatment, and improving the conformality of the amorphous silicon layer in the first texturing topography region.

[0108] As for the one-dimensional size of the tower-like structure in the polishing topography region, and the size difference between the tower-like structure in the polishing topography region and the patch region in the first texturing topography region, they can be determined according to the deposition requirement of the doped semiconductor layer, the conformality requirement of the amorphous silicon layer, and the thickness requirement of the semiconductor substrate corresponding to the first texturing topography region in the actual application scenario, which are not limited here.

[0109] Exemplarily, the one-dimensional size of the tower-like structure can be greater than or equal to 10 μm and less than or equal to 20 μm. For example, the one-dimensional size of the tower-like structure can be 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm, or 20 μm, etc. In this case, the one-dimensional size of the tower-like structure is within the above range, which is beneficial to preventing the planarization treatment degree of the semiconductor substrate from being too small before forming the doped semiconductor layer, reducing the roughness of the semiconductor substrate surface, and improving the formation quality of the doped semiconductor layer on the polishing topography region. It can also prevent the planarization treatment degree of the semiconductor substrate from being too large, which is beneficial to making the semiconductor substrate have a larger light absorption depth and mechanical strength.

[0110] Exemplarily, the ratio of the one-dimensional size of the patch region to the one-dimensional size of the tower-like structure can be greater than or equal to 1.5 and less than 4. For example, the ratio of the one-dimensional size of the patch region to the one-dimensional size of the tower-like structure can be 1.5, 1.8, 2, 2.2, 2.5, 2.8, 3, 3.2, 3.5, 3.8, or 4, etc. The application principle of the beneficial effects in this case can refer to the application principle of the beneficial effects of preventing the one-dimensional size of the tower-like structure from being too large or too small, and preventing the one-dimensional size of the patch region from being too large or too small, which are not described here again.

[0111] From the material aspect, the materials of the parts of the amorphous silicon layer can all be amorphous silicon materials. Alternatively, as shown in FIG. 2B, the materials of the parts of the amorphous silicon layer can be different. Figure 14As shown, the amorphous silicon layer 12 can also include a crystallization region 19, the crystallization degree of the portion of the amorphous silicon layer 12 located in the crystallization region 19 is greater than the crystallization degree of the portion of the amorphous silicon layer 12 located in the remaining portion. It should be noted that the crystallization region does not mean that the region is completely crystallized, but only means that the crystallization degree of the region is greater than the crystallization degree of other regions. The orthographic projection of the crystallization region 19 of the amorphous silicon layer 12 on the semiconductor substrate 11 is located in the first textured region. In this case, the conductivity and effective doping concentration of the amorphous silicon layer 12 located on the first textured region are improved, the contact resistance and transmission loss are reduced, and the contact performance is improved. The specific distribution position of the crystallization region 19 in the amorphous silicon layer 12 can be set according to actual needs. For example, the portion of the amorphous silicon layer 12 located on the top of at least part of the textured structure is the crystallization region 19, and / or the portion of the amorphous silicon layer 12 located on the local region of the side of at least part of the textured structure is the crystallization region 19. The difference between the crystallization degree of the crystallization region 19 and the remaining portion in the amorphous silicon layer 12 can be set according to actual needs, which is not limited here.

[0112] The greater the crystallization degree referred to in the embodiment of the present application can mean the greater the crystallization rate, the greater the grain size and / or the greater the number of grains. For example, the crystallization region of the amorphous silicon layer can contain a small amount of nanocrystalline silicon portion, but the content of the nanocrystalline silicon portion is very small, such as less than 5%, which is known in the art. The crystallization region with a greater crystallization degree in the amorphous silicon layer generates a crystal lattice ordered grain, and the crystallization degree is increased, while the remaining portion with a smaller crystallization degree is still an amorphous silicon material without a grain generated after being treated by a laser or the like.

[0113] As for the doped semiconductor layer, the material of the doped semiconductor layer can be the same as or different from the material of the amorphous silicon layer. When the material of the doped semiconductor layer is different from the material of the amorphous silicon layer, the material of the doped semiconductor layer can include any semiconductor material different from the amorphous silicon layer. For example, the doped semiconductor layer can include a doped crystalline silicon layer (such as at least one of a polycrystalline silicon layer, a single crystal silicon layer, a nanocrystalline silicon layer and a microcrystalline silicon layer). At this time, the material of the doped semiconductor layer has a plurality of possible examples, which is conducive to improving the applicability of the solar cell provided by the embodiment of the present application in different application scenarios.

[0114] As shown in Figure 12 and Figure 13 , the doped semiconductor layer 17 can be directly arranged on the semiconductor substrate 11. Alternatively, as shown in Figure 15As shown, the solar cell may further include an interface passivation layer 18 located between the doped semiconductor layer 17 and the semiconductor substrate 11. The material and thickness of the interface passivation layer 18 can be set according to the material of the doped semiconductor layer 17 and actual needs. For example, when the doped semiconductor layer is a doped polycrystalline silicon layer, the interface passivation layer is a tunneling passivation layer. The material of the tunneling passivation layer may include materials such as silicon oxide, aluminum oxide, or titanium oxide. Another example: when the material of the doped semiconductor layer may include at least one of doped amorphous silicon, doped nanocrystalline silicon, and doped microcrystalline silicon, the interface passivation layer is at least one of intrinsic amorphous silicon, intrinsic nanocrystalline silicon, and intrinsic microcrystalline silicon.

[0115] Optionally, in the case of a back-contact solar cell provided in the embodiments of the present invention, the amorphous silicon layer includes an intrinsic silicon layer and a doped silicon layer, and the doped semiconductor layer includes a tunneling passivation layer and a doped crystalline silicon layer.

[0116] It should be noted that when the conductivity type of the doped silicon layer included in the amorphous silicon layer is the same as the conductivity type of the semiconductor substrate, the solar cell includes the aforementioned doped semiconductor layer. Conversely, when the conductivity type of the doped silicon layer included in the amorphous silicon layer is opposite to the conductivity type of the semiconductor substrate, the solar cell may or may not include the aforementioned doped semiconductor layer.

[0117] In some cases, such as Figure 16 As shown, the solar cell may further include a transparent conductive layer 20, which is disposed on the side of the amorphous silicon layer 12 facing away from the semiconductor substrate 11. In this case, the transparent conductive layer 20 can reduce the work function difference between the amorphous silicon layer 12 and the metal electrode, thereby reducing transmission loss. Secondly, when the amorphous silicon layer 12 has good conformability in the first textured morphology region, the transparent conductive layer 20 deposited on the amorphous silicon layer 12 also has high conformability, which helps to reduce the contact resistance between the transparent conductive layer 20 and the amorphous silicon layer 12 and improve contact performance.

[0118] The material and thickness of the transparent conductive layer can be set according to actual needs and are not specifically limited here. Additionally, the transparent conductive layer can be disposed only on the side of the amorphous silicon layer facing away from the semiconductor substrate. Alternatively, in the case of a back-contact solar cell, the transparent conductive layer can also cover the side of the doped semiconductor layer facing away from the semiconductor substrate, and the portion of the transparent conductive layer that is only in electrical contact with the doped semiconductor layer and the portion that is only in electrical contact with the amorphous silicon layer are electrically insulated to prevent leakage.

[0119] Secondly, embodiments of the present invention provide a photovoltaic module, which includes: a battery string and an encapsulation layer. The battery string is formed by electrically connecting multiple solar cells as provided in the first aspect and its various implementations; the encapsulation layer covers the surface of the battery string.

[0120] The beneficial effects of the second aspect and various implementations thereof in the embodiments of the present application can be analyzed with reference to the beneficial effects in the first aspect and various implementations thereof, which will not be described herein again.

[0121] In a third aspect, the embodiments of the present application provide a manufacturing method of a solar cell. The manufacturing method of the solar cell comprises: first, forming a semiconductor substrate. Next, sequentially performing first planarization treatment and texturing treatment on at least part of the surface of the semiconductor substrate to form a first texturing morphology region on the semiconductor substrate; the first texturing morphology region comprises a non-mottling region and a plurality of mottling regions dispersed in the non-mottling region; the height of the non-mottling region is different from that of the mottling region along the thickness direction of the semiconductor substrate. Next, forming an amorphous silicon layer on the first texturing morphology region.

[0122] It should be noted that the structure and material information of the solar cell manufactured by the manufacturing method provided by the embodiments of the present application can be referred to the description of the structure and material of the solar cell provided by the first aspect above, which will not be described herein again.

[0123] In the actual manufacturing process, the process of forming the semiconductor substrate and the first texturing morphology region can be determined according to the type of the solar cell to be manufactured and the height relationship between the non-mottling region and the mottling region in the first texturing morphology region.

[0124] For example, in the case where the height of the mottling region is less than that of the non-mottling region, forming the semiconductor substrate can comprise: slicing the semiconductor rod material by using a cutting process (for example, a diamond wire cutting process) to form the semiconductor substrate; the surface of the semiconductor substrate is distributed with a plurality of cutting line marks. The recess depth of the cutting line marks and the distribution between the cutting line marks have certain influence on the distribution and recess depth of the mottling region. Next, the surface of the semiconductor substrate can be subjected to second planarization treatment by using a wet etching process or the like. In this case, in the actual manufacturing process, before the first planarization treatment and the texturing treatment are performed on the part of the surface of the semiconductor substrate corresponding to the first texturing morphology region, the approximate position of the mottling region recessed into the semiconductor substrate relative to the surface of the non-mottling region can be preset by forming recessed cutting line marks on the surface of the semiconductor substrate, in other words, by adjusting the recess depth of the cutting line marks in the process of forming the semiconductor substrate and the processing parameters of the second planarization treatment, and the processing parameters of the first planarization treatment and the texturing treatment performed after the formation of the semiconductor substrate, it is easy to form the mottling region at the position of the cutting line marks after the second planarization treatment, the first planarization treatment and the texturing treatment, thereby improving the uniformity of the texturing structure size while reducing the manufacturing difficulty of the solar cell.

[0125] Exemplarily, the total etching depth of the second planarization process and the first planarization process on the portion of the semiconductor substrate corresponding to the first texturing region can be less than the recessed depth of the at least one scribe line mark in the semiconductor substrate. In this case, the second planarization process can be prevented from over-etching the semiconductor substrate corresponding to the first texturing region, while it is also beneficial to control the depth and size of the patch region by controlling the setting position and the recessed depth of the scribe line mark, the processing parameters of the second planarization process, the first planarization process and the texturing process, and the like, so that the amorphous silicon layer has better conformality and reduced contact resistance.

[0126] After the first texturing region is formed, exemplarily, in the case where the manufactured solar cell is a bifacial contact solar cell, a process such as chemical vapor deposition can be used to form an amorphous silicon layer covering the first texturing region. If the first texturing region is only a partial region of the front surface and / or the back surface of the semiconductor substrate, after the amorphous silicon layer is formed, a process such as laser or wet etching can be used to selectively etch the amorphous silicon layer to remove the portion of the amorphous silicon layer not corresponding to the first texturing region.

[0127] In addition, in the case where the manufactured solar cell is a bifacial contact solar cell, if the solar cell further includes a doped semiconductor layer, the doped semiconductor layer can be formed on the side of the semiconductor substrate away from the amorphous silicon layer before or after the amorphous silicon layer is formed, at least by using a doping process.

[0128] Exemplarily, in the case where the manufactured solar cell is a back contact solar cell, if the amorphous silicon layer and the doped semiconductor layer are spaced apart along a direction parallel to the first surface, the amorphous silicon layer and the doped semiconductor layer can be formed respectively by using the above-mentioned way of forming the amorphous silicon layer on the first texturing region when the first texturing region is a partial region of the back surface of the semiconductor substrate. If the amorphous silicon layer extends to cover part of the doped semiconductor layer, after forming the doped semiconductor layer on the back surface of the semiconductor substrate by using a deposition process and a doping process, a process such as laser or wet etching can be used to selectively remove part of the doped semiconductor layer to expose the region of the semiconductor substrate used to manufacture the first texturing region. Then, at least the region of the semiconductor substrate used to manufacture the first texturing region is sequentially subjected to the first planarization process and the texturing process under the masking effect of the corresponding mask layer, so that part of the region of the back surface forms the first texturing region. Subsequently, the amorphous silicon layer can be formed by using the above-mentioned way.

[0129] In addition, after the amorphous silicon layer is formed, a laser irradiation process can also be used to crystallize at least part of the amorphous silicon layer, so that the amorphous silicon layer includes a crystallization region with a larger degree of crystallization. The parameters of the laser irradiation process can be set according to actual needs, which are not limited here.

[0130] AsFigure 16 As shown, after forming the amorphous silicon layer 12, a transparent conductive layer 20 can also be formed on the side of the amorphous silicon layer 12 away from the semiconductor substrate 11 by using a physical vapor deposition process or the like. The material and thickness of the transparent conductive layer 20 can refer to the foregoing, and will not be described herein again.

[0131] The beneficial effects of the third aspect and various implementation manners thereof in the embodiments of the present application can refer to the beneficial effect analysis in the first aspect and various implementation manners thereof, and will not be described herein again.

[0132] The embodiments of the present application also provide the following two specific embodiments and four comparative examples to specifically illustrate the working performance of the solar cell provided by the embodiments of the present application:

[0133] Embodiment 1

[0134] The solar cell provided by the embodiment 1 is manufactured by the following steps:

[0135] Step 1: Clean the back surface of the silicon substrate with an alkaline solution with a mass fraction of 10% to remove porous silicon; and polish the back surface of the silicon substrate using a polishing additive to roughen the line marks on the back surface of the silicon substrate and form a tower base structure with a side length of 10 μm to 20 μm.

[0136] Step 2: Prepare a tunneling oxide layer and an N-type polysilicon layer on the back surface of the polished silicon substrate.

[0137] Step 3: Deposit a dielectric mask layer SiN on the surface of the N-type polysilicon layer after high-temperature doping. x The thickness of the dielectric mask layer is 40 nm.

[0138] Step 4: Patternize the dielectric mask layer using a laser to expose part of the area on the back surface, so as to facilitate the subsequent formation of a P region.

[0139] Step 5: Remove the dielectric mask wrapped on the front surface of the silicon substrate when forming the dielectric mask layer by using an HF solution, so that the electrical conductivity is controlled at 25 S / m.

[0140] Step 6: Perform polishing treatment on the surface of the area on the back surface of the silicon substrate exposed outside the N-type polysilicon layer by using a NaOH-H2O-ADD (additive) solution system. The treatment temperature is 70°C, and the process time is 350 s, so as to remove the laser mask damage and make the surface of the area on the back surface of the silicon substrate exposed outside have a better large tower base structure (with a side length of 35 μm to 40 μm) in flatness;

[0141] Then, the front side and the area of the back side of the silicon substrate are textured by using an ADD:NaOH:DIW system, in which the mass percentage concentration of the additive ADD is 0.5%, the mass percentage concentration of NaOH is 1.85%, the processing temperature is 80°C, and the processing time is 420s. After the texturing, the size of the pyramid-shaped structure at the junction of the patch region and the non-patch region is 1.8μm to 2.5μm. The size of the pyramid-shaped structure in the patch region is 0.9μm to 1.5μm. The height of the patch region is less than the height of the non-patch region, and the height difference between them is greater than 1.5μm. The size of the patch region is 37μm to 42μm. Further efficient post-SC1 cleaning is performed by using NaOH-H2O2-H2O (the ratio of the three is 1:2:5) at a processing temperature of 65°C for 180s to remove the residual additive, and then the silicon substrate is cleaned by O3 and HCl to remove the organic matter remaining on the surface of the silicon substrate.

[0142] Step seven, the medium mask layer and the residual organic matter on the back side of the silicon substrate are removed by using 8%wt hydrofluoric acid, and dehydration is simultaneously achieved, and the processing time is 600s.

[0143] Step eight, an aluminum oxide and silicon nitride stack is prepared on the front side of the silicon substrate.

[0144] Step nine, an intrinsic amorphous silicon layer and a P-type doped amorphous layer are sequentially deposited on the back side of the silicon substrate by using PECVD. The thickness of the intrinsic amorphous silicon layer is 15nm, and the thickness of the P-type doped amorphous layer is 20nm.

[0145] Step ten, the intrinsic amorphous silicon layer and the P-type doped amorphous layer on at least part of the N-type doped polysilicon layer are removed by patterning the intrinsic amorphous silicon layer and the P-type doped amorphous layer by using a laser.

[0146] Step eleven, at least part of the P-type doped amorphous silicon layer is crystallized by using a laser to improve the contact.

[0147] Step twelve, a transparent conductive layer is deposited on the back side of the silicon substrate by using PVD.

[0148] Step thirteen, the transparent conductive layer in the gap region is removed by etching to insulate the transparent conductive layer electrically connected to the N-type polysilicon layer and the transparent conductive layer electrically connected to the P-type doped amorphous silicon layer, so as to prevent leakage and short circuit.

[0149] Step fourteen, a conductive silver paste is printed on the transparent conductive layer covering the N-type polysilicon layer and the P-type doped amorphous silicon layer by using a screen printing process, and is solidified to form a silver electrode.

[0150] Example 2

[0151] The solar cell provided in Example 2 is the same as the solar cell provided in Example 1 except that the polishing treatment in Step 6 is performed for 450 s and the edge length of the tower base structure formed is 37 μm to 40 μm.

[0152] Comparative Example 1

[0153] The solar cell provided in Comparative Example 1 is the same as the solar cell provided in Example 1 except that the texturing process is not performed after the polishing treatment in Step 6 and Step 7 is directly performed. It was observed that the P region of the solar cell provided in Comparative Example 1 did not have a plaque region.

[0154] Comparative Example 2

[0155] The solar cell provided in Comparative Example 2 is the same as the solar cell provided in Example 1 except that the polishing treatment in Step 6 is not performed and the texturing process is directly performed. It was observed that the P region of the solar cell provided in Comparative Example 2 did not have a plaque region.

[0156] Comparative Example 3

[0157] The solar cell provided in Comparative Example 3 is the same as the solar cell provided in Example 1 except that the polishing treatment in Step 6 is performed for 700 s and the edge length of the tower base structure formed is 45 μm to 65 μm. It was observed that the P region of the solar cell provided in Comparative Example 3 did not have a plaque region.

[0158] Comparative Example 4

[0159] The solar cell provided in Comparative Example 4 is the same as the solar cell provided in Example 1 except that the texturing process in Step 6 is performed for 650 s and the size of the texturing structure formed is large (size is greater than 2.5 μm). It was observed that the P region of the solar cell provided in Comparative Example 4 did not have a plaque region.

[0160] Table 1 Test parameters of the solar cells provided in Examples 1 and 2 and Comparative Examples 1 to 4

[0161] Sample Photoelectric conversion efficiency (%) Open circuit voltage (V) Short current density (mA / cm2) Fill factor (%) Reflectance (%) Example 1 26.775 0.7489 41.953 85.226 9.2 Example 2 26.845 0.7493 41.972 85.364 9.1 Comparative Example 1 26.623 0.7492 41.876 85.151 48 Comparative Example 2 26.231 0.7402 41.915 84.153 9.2 Comparative Example 3 26.645 0.7499 41.73 85.146 9.9 Comparative Example 4 26.734 0.7492 41.922 84.923 10.5

[0162] It should be noted that the data in Table 1 are obtained by selecting 10,000 solar cells as samples from the corresponding solar cell product lines of Example 1 and 2, and Comparative Examples 1 to 4, respectively. The data in the table are obtained by testing 10,000 samples in each example and calculating the average. In the above case, it can be seen from the data in Table 1 that, in Comparative Example 1, the surface of the area on the back surface of the silicon substrate exposed outside the N-type polysilicon layer is polished without texturing, and in this case, the passivation effect of the intrinsic amorphous silicon layer and the P-type doped amorphous silicon layer is improved, the open circuit voltage of the cell is not significantly different, but the parasitic absorption of the intrinsic amorphous silicon layer and the P-type doped amorphous silicon layer is increased, and the contact between the P-type doped amorphous silicon layer and the conductive structure and the light trapping of the back surface are affected, resulting in a significant decrease in the short circuit current of the cell, and thus the conversion efficiency of the cell has no advantage. In Comparative Example 2, the polishing process is not adopted in Step 6, and the direct texturing process is adopted, and in this case, the laser damage layer is not removed completely, resulting in serious carrier recombination in the area on the back surface of the silicon substrate exposed outside the N-type polysilicon layer, and the open circuit voltage and the short circuit current of the cell are decreased, and thus the conversion efficiency of the cell has no advantage. In Comparative Example 3, the size of the polishing tower base structure is too large, resulting in a low etching rate and poor light trapping effect in the subsequent texturing process due to the small number of nucleation sites, and thus the conversion efficiency of the cell has no advantage. In Comparative Example 4, the texturing time is not controlled properly, resulting in a large size of the pyramid structure, and thus the passivation effect of the intrinsic amorphous silicon layer and the P-type doped amorphous silicon layer is poor, and the cell performance is poor. In Example 1 and 2, the size of the tower base structure is controlled properly during the polishing process, and the size of the pyramid structure formed during the texturing process is controlled properly on this basis, which can reduce the reflectivity, increase the light absorption, and improve the passivation effect of the intrinsic amorphous silicon layer and the P-type doped amorphous silicon layer, and thus the cell performance is improved.

[0163] In the above description, the patterning, etching and other technical details of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions and the like with the required shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0164] The embodiments of the present application are described above. However, these embodiments are only for a clearer illustration, and are not intended to limit the scope of the present application. The scope of the present application is defined by the appended claims and their equivalents. Without departing from the scope of the present application, those skilled in the art can make various substitutions and modifications, which should fall within the scope of the present application.

Claims

1. A solar cell, characterized by, The solar cell comprises: a semiconductor substrate comprising a first texturing region; the first texturing region is densely provided with a plurality of texturing structures; an amorphous silicon layer disposed on the first texturing region; wherein the first texturing region comprises a non-plaque region and a plurality of plaque regions discretely distributed in the non-plaque region; the plaque region is a closed pattern formed by a plurality of the texturing structures, and the height of the non-plaque region is different from that of the plaque region along the thickness direction of the semiconductor substrate; the plaque region is formed after a cutting line mark position of an original semiconductor substrate is subjected to a first planarization treatment and a texturing treatment in sequence.

2. The solar cell according to claim 1, characterized in that, At least one of the plaque regions has a polygonal or strip shape.

3. The solar cell according to claim 1, characterized in that, A plurality of the plaque regions arranged along a first direction form a plaque column; the first texturing region is provided with a plurality of the plaque columns; the plaque columns in different columns are arranged along a second direction; the second direction intersects the first direction.

4. The solar cell according to claim 1, wherein At least one of the plaque regions has a one-dimensional size greater than or equal to 30 μm and less than or equal to 50 μm; and / or, a ratio of the one-dimensional size of the plaque region to the one-dimensional size of the texturing structure is greater than or equal to 10 and less than or equal to 60; and / or, in the first texturing region, and in a unit area of 300 μm x 300 μm, the number of the plaque regions is greater than or equal to 6 and less than or equal to 25.

5. The solar cell of claim 1, wherein The texturing structure is a pyramid-shaped structure; and / or, at least one of the texturing structures has a one-dimensional size greater than or equal to 0.9 μm and less than or equal to 2.5 μm.

6. The solar cell of claim 1, wherein The height of the plaque region is less than that of the non-plaque region.

7. The solar cell according to claim 6, characterized in that, The height difference between at least one of the plaque regions and the non-plaque region is less than 3 μm.

8. The solar cell of claim 6, wherein, In the first texturing region, the texturing structures located in the plaque region are defined as first texturing structures, and the texturing structures located at the junction of the plaque region and the non-plaque region are defined as junction texturing structures; the texturing structures located in the non-plaque region are second texturing structures; at least one of the junction texturing structures has a one-dimensional size greater than that of the first texturing structures and the second texturing structures; and / or, at least one of the junction texturing structures has a one-dimensional size greater than or equal to 1.8 μm and less than or equal to 2.5 μm; and / or, at least one of the first texturing structures and / or the second texturing structures has a one-dimensional size greater than or equal to 0.9 μm and less than or equal to 1.5 μm.

9. The solar cell of claim 6, wherein, In the first texturing region, the texturing structures located at the junction of the plaque region and the non-plaque region are defined as junction texturing structures; the junction texturing structure is a pyramid-shaped structure, and the length of the side edge of the junction texturing structure facing the non-plaque region is less than that of the side edge of the junction texturing structure facing the plaque region.

10. The solar cell of claim 1, wherein, The amorphous silicon layer comprises an intrinsic silicon layer and a doped silicon layer located on the side of the intrinsic silicon layer away from the semiconductor substrate.

11. The solar cell according to any one of claims 1 to 10, wherein The solar cell further comprises a doped semiconductor layer; the doped semiconductor layer and the amorphous silicon layer are located on the same side of the semiconductor substrate, and the conductive types of the doped semiconductor layer and the amorphous silicon layer are opposite.

12. The solar cell of claim 11, wherein, The semiconductor substrate is provided with a region surface of the doped semiconductor layer as a polishing topography region, and the doped semiconductor layer comprises a doped crystalline silicon layer. The amorphous silicon layer further extends to cover part of the doped crystalline silicon layer.

13. The solar cell of claim 12, wherein, The polishing topography region is provided with a tower base-like structure. The one-dimensional size of the tower base-like structure is smaller than the one-dimensional size of the plaque region. The one-dimensional size of the tower base-like structure is greater than or equal to 10 μm and less than or equal to 20 μm. The ratio of the one-dimensional size of the plaque region to the one-dimensional size of the tower base-like structure is greater than or equal to 1.5 and less than 4.

14. The solar cell of claim 1, wherein, The amorphous silicon layer comprises a crystallization region, and the orthogonal projection of the crystallization region on the semiconductor substrate is located in the first textured topography region.

15. The solar cell of claim 1, wherein, The solar cell further comprises a transparent conductive layer, which is arranged on the side of the amorphous silicon layer away from the semiconductor substrate.

16. A photovoltaic module, characterized by It comprises: a cell string formed by electrically connecting a plurality of solar cells according to any one of claims 1-15; and a packaging layer covering the surface of the cell string.

17. A method for manufacturing a solar cell, characterized by, It comprises: providing a semiconductor substrate; the surface of the semiconductor substrate has a cutting line mark; sequentially performing a first planarization treatment and a texturing treatment on at least part of the surface of the semiconductor substrate to form a first textured topography region on the semiconductor substrate; the first textured topography region comprises a non-plaque region and a plurality of plaque regions distributed discretely in the non-plaque region; the plaque region is a closed pattern formed by a plurality of textured structures, and the height of the non-plaque region and the plaque region is different along the thickness direction of the semiconductor substrate; the plaque region is formed after the cutting line mark position is sequentially subjected to the first planarization treatment and the texturing treatment; forming an amorphous silicon layer on the first textured topography region.

18. The method of manufacturing a solar cell according to claim 17, wherein After forming the semiconductor substrate, before sequentially performing a first planarization treatment and a texturing treatment on at least part of the surface of the semiconductor substrate, the manufacturing method of the solar cell further comprises: forming a doped semiconductor layer on the part of the surface of the semiconductor substrate corresponding to the amorphous silicon layer; the conductive type of the doped semiconductor layer and the amorphous silicon layer is opposite.

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