Display device and method for manufacturing display device

Abstract

A display device and a method for manufacturing the same are provided. The display device includes a substrate including a pixel circuit; a pixel electrode connected to the pixel circuit; an insulating layer disposed on the pixel electrode; a through electrode penetrating the insulating layer and connected to the pixel electrode; a bottom bonding electrode and an upper bonding electrode sequentially disposed on the through electrode and the insulating layer; and a light emitting element disposed on the upper bonding electrode. The through electrode has a recess whose upper surface is recessed downward. A lower surface of the bottom bonding electrode follows a surface profile of the insulating layer and the through electrode disposed below, and an upper surface of the bottom bonding electrode is flat. The bottom bonding electrode includes an oxide layer.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0030432 filed in the Korean Intellectual Property Office on March 4, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display device and a method for manufacturing the display device. Background Art

[0003] The importance of display devices has gradually increased with the development of multimedia. In response, various display devices, such as liquid crystal display devices and light-emitting display devices, are being developed. Among these, light-emitting display devices may include display panels containing light-emitting elements. Display panels can be applied to various types of electronic devices, including portable electronic devices and televisions, as well as virtual reality (VR) devices and augmented reality (AR) devices.

[0004] Aspects and features of the disclosed embodiments are to provide a method of manufacturing a display device, which can increase manufacturing efficiency of a display panel including a light emitting element.

[0005] It will be understood that this background section is intended, in part, to provide a useful context for understanding the technology. However, this background section may also include ideas, concepts, or realizations that were not part of what was known or understood by those skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the Invention

[0006] According to the embodiment, a display device minimizing disconnection between a pixel electrode and a light emitting element and a method for manufacturing the display device may be provided.

[0007] However, the aspects of the disclosure are not limited to the aspects set forth herein. The above and other aspects of the disclosure will become more apparent to those skilled in the art to which the disclosure pertains by referring to the detailed description of the disclosure given below.

[0008] According to an embodiment, a display device may include: a substrate including a pixel circuit; a pixel electrode connected to the pixel circuit; an insulating layer provided on the pixel electrode; a through electrode penetrating the insulating layer and connected to the pixel electrode; a bottom bonding electrode and an upper bonding electrode sequentially provided on the through electrode and the insulating layer; and a light-emitting element provided on the upper bonding electrode. The through electrode may have a groove whose upper surface is recessed downward. The lower surface of the bottom bonding electrode may follow the surface contours of the insulating layer and the through electrode provided thereunder, and the upper surface of the bottom bonding electrode is flat. The bottom bonding electrode may include an oxide layer between the layers.

[0009] In an embodiment, the lower surface of the bottom bonding electrode may have a downwardly protruding protrusion corresponding to the recessed groove of the through electrode.

[0010] In an embodiment, the bottom bonding electrode may include a first bottom bonding electrode and a second bottom bonding electrode formed of different materials, the second bottom bonding electrode being disposed on the first bottom bonding electrode. An oxide layer may be disposed between a plurality of layers of the first bottom bonding electrode.

[0011] In an embodiment, the first and second bottom bonding electrodes may be made of a material selected from the group consisting of titanium (Ti), nickel (Ni), platinum (Pt), tin (Sn), gold (Au), aluminum (Al), and tungsten (W).

[0012] In an embodiment, the upper and lower surfaces of the upper bonding electrode may be flat.

[0013] In embodiments, the upper bonding electrode may be formed of one or more layers.

[0014] In an embodiment, the display device may further include a barrier film surrounding a side surface of the through electrode.

[0015] In an embodiment, the barrier film may include a material that prevents movement of metal ions forming the through-electrodes.

[0016] In an embodiment, the upper bonding electrode and the bottom bonding electrode may protrude outward from the light emitting element.

[0017] In an embodiment, the display device may further include: a first insulating layer surrounding the light emitting element and the sides of the bottom bonding electrode and the upper bonding electrode; a reflective layer arranged on the sides of the light emitting element; a second insulating layer surrounding the light emitting element and the sides of the bottom bonding electrode and the upper bonding electrode on the reflective layer and the first insulating layer; and a common electrode arranged on the upper portion of the light emitting element.

[0018] In an embodiment, the display device may further include: a lens-type optical structure on the light emitting element layer including the light emitting element and the common electrode.

[0019] According to an embodiment, a method for manufacturing a display device may include the following steps: providing a backplane substrate, the backplane substrate including a pixel electrode connected to a pixel circuit and an insulating layer arranged on the pixel electrode; forming a through electrode, the through electrode penetrating the insulating layer and connected to the pixel electrode; flattening the top surface of the insulating layer and the through electrode; applying a first conductive bonding material to the top surface of the through electrode; flattening the first conductive bonding material to form an oxide layer on the top surface of the through electrode; forming a bottom bonding electrode layer by additionally coating a second conductive bonding material on the first conductive bonding material having the oxide layer formed thereon; providing a base substrate having an upper bonding electrode layer and a plurality of semiconductor layers; bonding the base substrate and the backplane substrate and removing the base substrate; and forming a plurality of light-emitting elements by etching the plurality of semiconductor layers.

[0020] In an embodiment, planarizing the top surfaces of the insulating layer and the through electrodes, planarizing the first conductive bonding material to form an oxide layer on the top surfaces of the through electrodes, and removing the base substrate may include a chemical mechanical polishing (CMP) process.

[0021] In an embodiment, planarizing the top surfaces of the insulating layer and the through-electrode may include forming a groove recessed downward on the through-electrode.

[0022] In an embodiment, a lower surface of the bottom bonding electrode layer may have a downwardly protruding protrusion corresponding to the recessed groove of the through electrode, and an upper surface layer of the bottom bonding electrode may be flat.

[0023] In an embodiment, the method may further include forming a bonding electrode by etching the bottom bonding electrode layer and the upper bonding electrode layer.

[0024] In an embodiment, the step of forming a bottom bonding electrode layer by additionally coating a second conductive bonding material on a first conductive bonding material on which an oxide layer is formed may include: forming a first bottom bonding electrode layer by additionally coating the first conductive bonding material on the first conductive bonding material on which an oxide layer is formed; and forming a second bottom bonding electrode layer on the first bottom bonding electrode layer by coating a second conductive bonding material different from the first conductive bonding material.

[0025] In an embodiment, the method may further include forming an insulating layer and a reflective layer surrounding side surfaces of the light emitting element.

[0026] In an embodiment, the method may further include: forming a common electrode on the light emitting element.

[0027] In an embodiment, the method may further include: forming a lens-type optical structure on the light emitting element layer including the light emitting element and the common electrode.

[0028] Therefore, it is possible to increase manufacturing efficiency and improve yield of a display panel including a light emitting element and a display device including the display panel.

[0029] However, the disclosed effects are not limited to the aforementioned effects, and various other effects are included in the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the disclosure will become more apparent by describing in detail embodiments of the disclosure with reference to the accompanying drawings.

[0031] Figure 1 is a schematic perspective view showing a display device according to one embodiment.

[0032] Figure 2 It shows Figure 1 A schematic plan view of an embodiment of area A.

[0033] Figure 3 is a diagram showing the display panel and Figure 2 Schematic cross-sectional view of an embodiment of a cross section corresponding to line X1 - X1 ′ in FIG.

[0034] Figure 4 It shows Figure 3 An enlarged schematic cross-sectional view of an example of an interlayer insulating layer and a through-electrode.

[0035] Figure 5 It shows Figure 3 An enlarged schematic cross-sectional view of an example of an interlayer insulating layer, a through electrode, and a bonding electrode.

[0036] Figure 6 It shows Figure 3 FIG. 1 is an enlarged schematic cross-sectional view of another example of an interlayer insulating layer and a through-electrode.

[0037] Figure 7 is a schematic cross-sectional view showing a light emitting element according to one embodiment.

[0038] Figure 8 is a flowchart illustrating a method for manufacturing a display device according to one embodiment.

[0039] Figures 9 to 25 is a schematic diagram for illustrating a method of manufacturing a display panel according to one embodiment.

[0040] Figure 26 is a schematic cross-sectional view for illustrating voids that may occur if a planarization process is not performed on a bottom bonding electrode.

[0041] Figure 27 is a schematic diagram illustrating a virtual reality device including a display device according to an embodiment.

[0042] Figure 28 is a schematic diagram illustrating a smart device including a display device according to an embodiment.

[0043] Figure 29 is a diagram schematically illustrating an example of a vehicle including a display device according to an embodiment.

[0044] Figure 30 is a diagram schematically illustrating an example of a transparent display device including a display device according to an embodiment. DETAILED DESCRIPTION

[0045] Embodiments will now be described more fully below with reference to the accompanying drawings. However, the embodiments may be provided in different forms and should not be construed as limiting. Throughout the disclosure, like reference numerals indicate like components. In the accompanying drawings, the thickness of layers and regions may be exaggerated for clarity.

[0046] For the purpose of describing the disclosed embodiments, some of the components not related to the description may not be provided.

[0047] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being “directly on” another element, there may be no intervening elements present.

[0048] In addition, the phrase "in a plan view" means when viewing an object portion from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic cross-section taken by vertically cutting an object portion from the side. The term "superimposed" or its variations means that a first object can be above or below or to one side of a second object, and vice versa. In addition, the term "superimposed" can include stacking, stacking, facing or facing, extending over, covering or partially covering, or any other suitable term as will be appreciated and understood by a person of ordinary skill in the art. The expression "not superimposed" can include meanings such as "separated from" or "offset from" or "offset from" and any other suitable equivalents as will be appreciated and understood by a person of ordinary skill in the art. The terms "facing" and "facing" can mean that a first object can be directly or indirectly opposite to a second object. In the case where a third object is between the first and second objects, the first and second objects, although still facing each other, can be understood to be indirectly opposite to each other.

[0049] For ease of description, spatially relative terms such as "below," "under," "down," "above," "up," etc. may be used herein to describe the relationship between one element or component and another element or component as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, where the device shown in the accompanying drawings is flipped over, a device that is "below" or "beneath" another device may be placed "above" the other device. Thus, the illustrative term "below" may include both a below position and an above position. The device may also be oriented in other directions, and thus the spatially relative terms may be interpreted differently depending on the orientation.

[0050] When an element is referred to as being “connected” or “coupled” to another element, the element may be “directly connected” or “directly coupled” to the other element, or “electrically connected” or “electrically coupled” to the other element with one or more intervening elements interposed therebetween. It will also be understood that when the terms “comprises,” “having,” “includes,” and / or variations thereof are used, they may specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0051] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element or to facilitate description and explanation thereof. For example, when discussing a "first element" in the specification, it may be referred to as a "second element" or a "third element," and the "second element" and "third element" may be named in a similar manner without departing from the teachings herein.

[0052] As used herein, the terms "about" or "approximately" are inclusive of the stated value and mean within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and errors associated with measurement of the particular quantity (e.g., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0053] In the specification and claims, for the purposes of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunction or disjunction sense and may be understood to be equivalent to "and / or". In the specification and claims, for the purposes of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one of the group of..." For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0054] Unless otherwise defined or implied, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless explicitly defined in the specification.

[0055] Figure 1 is a schematic perspective view showing a display device according to one embodiment. Figure 2 It shows Figure 1 A schematic plan view of an embodiment of area A. Figure 3 is a diagram showing the display panel and Figure 2 Schematic cross-sectional view of an embodiment of a cross section corresponding to line X1 - X1 ′ in FIG. Figure 4 It shows Figure 3 An enlarged schematic cross-sectional view of an example of an interlayer insulating layer and a through-electrode. Figure 5 It shows Figure 3 An enlarged schematic cross-sectional view of an example of an interlayer insulating layer, a through electrode, and a bonding electrode.

[0056] Figures 1 to 3 An embodiment in which the display device 10 is an LEDoS (Light Emitting Diode on Silicon) is shown, in which the light emitting diode is provided as a light emitting element LE on a semiconductor circuit board formed by a semiconductor process using a silicon wafer (for example, the backplane substrate 110 of the display panel 100 in which the pixel circuit PXC and the like are formed is formed based on a silicon wafer). However, the device including the light emitting element LE according to the embodiment is not limited thereto. For example, the light emitting element LE manufactured according to the embodiment may be applied to display devices of different types and / or structures, or may be applied to devices of different types and / or structures such as lighting devices. As an example, referring to Figures 4 to 25 The described embodiments may also be applied to manufacturing devices including other types and / or structures of light emitting elements LE.

[0057] exist Figures 1 to 3 , the first direction DR1 may indicate a horizontal direction of the display panel 100, and the second direction DR2 may indicate a vertical direction of the display panel 100. The third direction DR3 may indicate a thickness direction of the display panel 100.

[0058] Reference Figure 1 and Figure 2 , a display device 10 according to one embodiment may include a display panel 100 including a display area DA and a non-display area NDA.

[0059] The display panel 100 may have a rectangular planar shape having long sides in the first direction DR1 and short sides in the second direction DR2. However, the planar shape of the display panel 100 is not limited thereto, and the display panel 100 may have another shape. For example, the display panel 100 may have a polygonal, circular, elliptical, or other non-rectangular planar shape other than a rectangular shape.

[0060] The display area DA may be an area where an image is displayed, and the non-display area NDA may be an area where no image is displayed. In one embodiment, the planar shape of the display area DA may follow the planar shape of the display panel 100. Figure 1 , the planar shape of the display area DA is shown as a rectangle. The display area DA may be provided in the central area of ​​the display panel 100. The non-display area NDA may be provided around the display area DA. In one example, the non-display area NDA may surround the display area DA.

[0061] The display area DA may include pixels PX. Each pixel PX may include at least two light emitting elements LE.

[0062] In one embodiment, each pixel PX may include three light emitting elements LE. For example, each pixel PX may include a first light emitting element LE1, a second light emitting element LE2, and a third light emitting element LE3. The number and / or type of light emitting elements LE provided to a pixel PX may vary in different embodiments.

[0063] In one embodiment, each pixel PX may include a light emitting element LE that emits light of different colors. For example, the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may emit light of different colors.

[0064] The first light emitting element LE1 may emit first light. The first light may be red light. For example, a main peak wavelength (R peak) of the first light may be approximately 600 nm to approximately 750 nm, but the embodiment is not limited thereto.

[0065] The second light emitting element LE2 may emit a second light. The second light may be green light. For example, the main peak wavelength (G peak) of the second light may be approximately 480 nm to approximately 560 nm, but the embodiment is not limited thereto.

[0066] The third light emitting element LE3 may emit a third light. The third light may be blue light. For example, the main peak wavelength (B peak) of the third light may be approximately 370 nm to approximately 460 nm, but the embodiment is not limited thereto.

[0067] In another embodiment, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may emit light of the same color as one another. A light conversion layer including a light conversion element (e.g., quantum dots) may be disposed on at least one of the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3. The light conversion element is configured to convert light of one color (or a corresponding wavelength band) emitted by the at least one light-emitting element LE into light of another color (or a corresponding wavelength band).

[0068] In one embodiment, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 of each pixel PX may be sequentially arranged in the first direction DR1. In one embodiment, the first light-emitting element LE1 may be arranged in the second direction DR2. The second light-emitting element LE2 may be arranged in the second direction DR2. The third light-emitting element LE3 may be arranged in the second direction DR2. For example, in each pixel column extending along the second direction DR2, the first light-emitting element LE1, the second light-emitting element LE2, or the third light-emitting element LE3 may be arranged. In addition, the arrangement structure of the pixels PX and the light-emitting elements LE arranged in the pixels PX may vary in different embodiments.

[0069] In one embodiment, the light emitting elements LE may be arranged at substantially equal intervals in the display area DA, but the embodiment is not limited thereto. For example, the positions and / or array pitches of the light emitting elements LE may vary according to the embodiment.

[0070] In one embodiment, the size (e.g., area) of the light-emitting elements LE may be substantially the same as one another. For example, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may have substantially the same size. However, embodiments are not limited thereto, and the size of each light-emitting element LE and / or the area of ​​the light-emitting region corresponding to the light-emitting element LE may vary in different embodiments.

[0071] In one embodiment, the light emitting elements LE may have a circular planar shape, but the embodiment is not limited thereto. For example, the light emitting elements LE may have a rectangular shape, another polygonal shape, an elliptical shape, or any other polygonal, elliptical, or irregular shape. In addition, the light emitting elements LE may have substantially the same planar shape as each other, or may have different planar shapes for each group.

[0072] The non-display area NDA may include a first common voltage supply area CVA1 , a second common voltage supply area CVA2 , a first pad area PDA1 , a second pad area PDA2 , and a peripheral area PHA.

[0073] The first common voltage supply area CVA1 may be provided between the first pad area PDA1 and the display area DA. The second common voltage supply area CVA2 may be provided between the second pad area PDA2 and the display area DA. Each of the first common voltage supply area CVA1 and the second common voltage supply area CVA2 may include a common electrode (e.g., Figure 3 The common electrode CE in the display area DA may extend to the first common voltage supply area CVA1 and the second common voltage supply area CVA2 and may be electrically connected to the common electrode connection portion CVS. A common voltage may be supplied to the common electrode through the common electrode connection portion CVS.

[0074] The common electrode connection portion CVS may be provided in the common voltage supply area (eg, the first common voltage supply area CVA1 and / or the second common voltage supply area CVA2) of the non-display area NDA. The common electrode connection portion CVS may include a conductive material (eg, a metal material such as aluminum (Al)). Figure 1 and Figure 2 The display device 10 is shown with the common electrode connection portion CVS disposed in the non-display area NDA, but the embodiment is not limited thereto. For example, the common electrode connection portion CVS may be disposed in the display area DA. In one example, the common electrode connection portion CVS may be disposed in a pixel region or between pixel regions.

[0075] The common electrode connection portion CVS of the first common voltage supply area CVA1 may be electrically connected to one of the first pads PD1 of the first pad area PDA1. For example, the common electrode connection portion CVS of the first common voltage supply area CVA1 may be supplied with a common voltage from one of the first pads PD1 of the first pad area PDA1.

[0076] The first pad PD1 may be disposed in the first pad area PDA1. The first pad PD1 may be connected to a circuit board (not shown) through a conductive connection member. For example, the first pad PD1 may be electrically connected to a circuit pad disposed on the circuit board through wiring.

[0077] The common electrode connection portion CVS of the second common voltage supply area CVA2 may be electrically connected to one of the second pads of the second pad area PDA2. For example, the common electrode connection portion CVS of the second common voltage supply area CVA2 may be supplied with a common voltage from one of the second pads of the second pad area PDA2. In one embodiment, the display panel 100 may not include the second common voltage supply area CVA2.

[0078] The first pad area PDA1 may be disposed at one side (eg, an upper side) of the display panel 100. The first pad area PDA1 may include a first pad PD1 connected to an external circuit board.

[0079] The second pad area PDA2 may be provided on the other side (eg, the lower side) of the display panel 100. The second pad area PDA2 may include a second pad connected to an external circuit board. In one embodiment, the display panel 100 may not include the second pad area PDA2.

[0080] The second pad may be disposed in the second pad area PDA2 of the non-display area NDA. The second pad may be connected to a circuit board (not shown) via a conductive connection member. For example, the second pad may be electrically connected to a circuit pad disposed on the circuit board via wiring.

[0081] The peripheral area PHA may be a non-display area NDA that does not include the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad area PDA1, and the second pad area PDA2. The peripheral area PHA may surround the display area DA and the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad area PDA1, and the second pad area PDA2.

[0082] Reference Figure 3 The display panel 100 may include a backplane substrate 110 and a light emitting element layer 120. In one embodiment, the display panel 100 may further include an optical structure (or light emitting structure) (eg, a lens-type optical structure LS) disposed on the light emitting element layer 120.

[0083] The display panel 100 may further include additional components according to embodiments. For example, the display panel 100 may further include a light conversion layer for converting the color and / or wavelength of light emitted from at least some of the light emitting elements LE and / or a color filter layer for controlling the emission of a specific color of light from each of the light emitting areas EA.

[0084] The display panel 100 may include emission areas EA located within the display area DA. Each of the emission areas EA may include at least one light-emitting element LE. For example, the emission areas EA may include a first emission area EA1 having at least one first light-emitting element LE1, a second emission area EA2 having at least one second light-emitting element LE2, and a third emission area EA3 having at least one third light-emitting element LE3. In one embodiment, first light, second light, and third light may be emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively.

[0085] The backplane substrate 110 may include a display area DA including an emission area EA. In one embodiment, the backplane substrate 110 may be a semiconductor circuit board formed by a semiconductor process using a silicon wafer. For example, a silicon wafer may be used as a base member for forming the display panel 100.

[0086] The backplane substrate 110 may include a pixel circuit PXC and a pixel electrode PXE disposed in the display area DA, as well as a circuit insulating film INS1 and interlayer insulating layers INS2 and INS3. For example, at least one light-emitting element LE may be disposed in each light-emitting area EA of the display panel 100, and the backplane substrate 110 may include a pixel circuit PXC and a pixel electrode PXE electrically connected to each of the light-emitting elements LE disposed in each light-emitting area EA.

[0087] The pixel circuits PXC may be disposed in the display area DA corresponding to an area where each pixel PX and / or the emission area EA is formed. In one embodiment, each of the pixel circuits PXC may include a complementary metal oxide semiconductor (CMOS) circuit formed using a semiconductor process.

[0088] Each of the pixel circuits PXC may include at least one transistor formed by a semiconductor process. In addition, each of the pixel circuits PXC may further include at least one capacitor formed by a semiconductor process.

[0089] In one embodiment, a circuit insulating film INS1 may be provided on the pixel circuit PXC. The circuit insulating film INS1 may be made of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0090] The pixel electrodes PXE may be disposed on the circuit insulating film INS1. The pixel electrodes PXE may be connected to the pixel circuits PXC via contact holes penetrating the circuit insulating film INS1. Each of the pixel electrodes PXE may be electrically connected to the pixel circuits PXC. For example, the pixel electrodes PXE and the pixel circuits PXC may be connected in a one-to-one correspondence. Each of the pixel circuits PXC may apply a pixel voltage to the pixel electrode PXE connected thereto. Each of the pixel electrodes PXE may receive a pixel voltage from the pixel circuits PXC. The pixel electrodes PXE may include a conductive material (e.g., a metal material such as aluminum (Al)).

[0091] One or more interlayer insulating layers INS2 and INS3 may be disposed on the pixel electrode PXE. In one embodiment, the interlayer insulating layers INS2 and INS3 may include a first interlayer insulating layer INS2 and a second interlayer insulating layer INS3.

[0092] A first interlayer insulating layer INS2 may be disposed on the pixel electrode PXE, and a second interlayer insulating layer INS3 may be disposed on the first interlayer insulating layer INS2 .

[0093] The first and second interlayer insulating layers INS2 and INS3 may be formed of the same material, but the embodiment is not limited thereto. The first and second interlayer insulating layers INS2 and INS3 may be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0094] The backplane substrate 110 may also include Figure 1 and Figure 2 In one embodiment, the backplane substrate 110 may further include a common electrode connection portion CVS, a first pad PD1 and / or a second pad located in the non-display area NDA.

[0095] The light-emitting element layer 120 may include a bottom bonding electrode BBE, an upper bonding electrode UBE, a light-emitting element LE, element insulation layers INS4 and INS5, a reflective layer RF, and a common electrode CE. In one embodiment, the light-emitting element layer 120 may further include an organic film ORL disposed around the light-emitting element LE and / or a third interlayer insulation layer INS6 disposed on the common electrode CE.

[0096] In one embodiment, the light emitting element layer 120 may further include additional components. For example, the light emitting element layer 120 may further include a reflective layer and / or a light blocking layer disposed between the light emitting elements LE and / or on the sides of the light emitting elements LE.

[0097] The first and second interlayer insulating layers INS2 and INS3 may have contact holes CH therethrough, and thus, the pixel electrodes PXE may be exposed by the contact holes CH.

[0098] Reference Figure 4 The through electrode TRE is disposed inside the contact hole CH. For example, the through electrode TRE may fill the contact hole CH and directly contact the pixel electrode PXE exposed by the contact hole CH.

[0099] The through-electrode TRE may have an upper surface recessed below a reference line (zero line), and specifically, the center of the through-electrode TRE may have a recessed groove (e.g., in a disk shape) lower than the edge. The reference line may be an extension line of the planarized surface of the second interlayer insulating layer INS3.

[0100] The through-electrode TRE may include a conductive material. In one embodiment, the through-electrode TRE may be made of a metal material such as copper (Cu).

[0101] Reference Figure 5 The bottom bonding electrode BBE may be disposed on the second interlayer insulating layer INS3 and the through-electrode TRE. The bottom bonding electrode BBE may be connected to the pixel electrode PXE through the through-electrode TRE.

[0102] The bottom bonding electrode BBE's lower surface can follow the contour of the lower structure, and its upper surface can be flat. For example, the bottom bonding electrode BBE's lower surface can have a protrusion that protrudes downwardly corresponding to the concave shape of the through electrode TRE. Thus, the bottom bonding electrode BBE can be formed to fill the concave groove of the through electrode TRE.

[0103] In one embodiment, the bottom bonding electrode BBE may include a first bottom bonding electrode BBE1 and a second bottom bonding electrode BBE2 stacked on each other. The first bottom bonding electrode BBE1 may be disposed on the interlayer insulating layers INS2 and INS3 , and the second bottom bonding electrode BBE2 may be disposed on the first bottom bonding electrode BBE1 .

[0104] The first bottom bonding electrode BBE1 may have a lower surface with a protrusion protruding downward corresponding to the concave shape of the through electrode TRE, and an upper surface BOE (see FIG. Figure 13 ) can be formed to be flat. On the other hand, both the upper surface and the lower surface of the second bottom bonding electrode BBE2 can be formed to be flat.

[0105] The first bottom bonding electrode BBE1 can be composed of a single layer of conductive material. For example, the first bottom bonding electrode BBE1 can include a barrier layer made of at least one of Ti, Ni, Pt, Sn, Au, Al, and W. In one embodiment, the first bottom bonding electrode BBE1 can be titanium (Ti). The first bottom bonding electrode BBE1 can include an oxide layer. For example, the first bottom bonding electrode BBE1 can be formed of two layers, and the oxide layer can be included at the interface between the layers.

[0106] The second bottom bonding electrode BBE2 may include at least one of Ti, Ni, Pt, Sn, Au, Al, and W. In one embodiment, the second bottom bonding electrode BBE2 may be gold (Au).

[0107] In one embodiment, the second bottom bonding electrode BBE2 may be formed of a different material from the first bottom bonding electrode BBE1 , but is not limited thereto.

[0108] The upper bonding electrode UBE of one or more layers may be disposed on the bottom bonding electrode BBE. The upper and lower surfaces of the upper bonding electrode UBE may be flat.

[0109] The upper bonding electrode UBE may include a conductive bonding material suitable for bonding or adhering the light emitting element LE to the bottom bonding electrode BBE.

[0110] The upper bonding electrode UBE may be a single-layer or multi-layer electrode including Ti, Ni, Pt, Sn, Au, Al, or other metal materials (eg, bonding metal).

[0111] In one embodiment, the upper bonding electrode UBE may include a first upper bonding electrode UBE1 and a second upper bonding electrode UBE2. The first upper bonding electrode UBE1 may directly contact the bottom bonding electrode BBE. The second upper bonding electrode UBE2 may be disposed on the first upper bonding electrode UBE1. The first upper bonding electrode UBE1 may include at least one of Ti, Ni, Pt, Sn, Au, and Al. In one embodiment, the first upper bonding electrode UBE1 may be gold (Au). The second upper bonding electrode UBE2 may include at least one of Ti, Ni, Pt, Sn, Au, Al, and W. In one embodiment, the second upper bonding electrode UBE2 may be titanium (Ti).

[0112] In one embodiment, the upper bonding electrode (UBE) is disclosed as having two electrode layers, but is not limited thereto. For example, the upper bonding electrode (UBE) may be formed as a single layer containing at least one of Ti, Ni, Pt, Sn, Au, and Al. In other embodiments, the upper bonding electrode (UBE) may include three electrode layers. For example, the upper bonding electrode (UBE) may include a first electrode layer made of Sn, a second electrode layer made of Au, and a third electrode layer made of Ti.

[0113] The light emitting element LE may be provided on the upper bonding electrode UBE.

[0114] One end of the light emitting element LE may be electrically connected to the pixel electrode PXE through the upper bonding electrode UBE and the bottom bonding electrode BBE, and the other end of the light emitting element LE may be electrically connected to the common electrode CE.

[0115] The pixel electrode PXE can be connected to each pixel circuit PXC. The pixel electrode PXE can be individually provided in each emission area EA and can be electrically connected to the light-emitting element LE located in each emission area EA. Therefore, the light-emitting element LE provided in each emission area EA can be individually and / or independently controlled.

[0116] The light emitting element LE may include a semiconductor layer grown on a semiconductor substrate (e.g., a wafer substrate) by epitaxial growth. For example, the light emitting element LE may include a first semiconductor layer doped with a first conductive type dopant, a second semiconductor layer doped with a second conductive type dopant, and an active layer between the first and second semiconductor layers.

[0117] The light emitting element LE may be formed of an epitaxial thin film of a wafer die separated from an epitaxial wafer and may be patterned in a unit region corresponding to each display panel 100 to form individual light emitting areas EA. A detailed description of the structure and manufacturing method of the light emitting element LE according to the embodiment will be described later.

[0118] In one embodiment, the first insulating layer INS4 may be provided to surround the light emitting element LE and the bonding electrodes BBE and UBE. The first insulating layer INS4 may have an opening on the top surface of the light emitting element LE. Thus, at least a portion of the top surface of the light emitting element LE may be exposed by the opening of the first insulating layer INS4. The first insulating layer INS4 may be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0119] A reflective layer RF may be further provided on the first element insulating layer INS4 on the sides of the light-emitting element LE and the bonding electrodes BBE and UBE. The reflective layer RF may be used to reflect light emitted from the light-emitting element LE in a downward, leftward, rightward, or lateral direction, rather than an upward direction. The reflective layer RF may include a highly reflective metal material such as aluminum (Al).

[0120] A second insulating layer INS5 may be provided on the reflective layer RF to surround the light emitting element LE and the bonding electrodes BBE and UBE. The second insulating layer INS5 may have an opening on the top surface of the light emitting element LE. The opening of the second insulating layer INS5 may overlap with the opening of the first insulating layer INS4. Thus, at least a portion of the top surface of the light emitting element LE may be exposed by the opening of the second insulating layer INS5 and the opening of the first insulating layer INS4. The second insulating layer INS5 may be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0121] The organic film ORL may be disposed around the light-emitting elements LE. As an example, the organic film ORL may be disposed between the light-emitting areas EA to surround the light-emitting areas EA in which the light-emitting elements LE are disposed, and may surround the light-emitting elements LE and the bonding electrodes BBE and UBE. In one embodiment, the organic film ORL may be a filler that fills the gaps between the light-emitting elements LE. The organic film ORL may expose a portion (e.g., the upper surface) of the light-emitting elements LE.

[0122] The organic film ORL may include an insulating material. For example, the organic film ORL may be a single layer or multiple layers of an organic insulating material including acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or other organic insulating materials.

[0123] The common electrode CE may be disposed on the top portion of the light-emitting element LE that is not covered by the organic film ORL. In one embodiment, the common electrode CE may be disposed entirely in the display area DA to cover the light-emitting element LE and the organic film ORL. The common electrode CE may be a common layer commonly formed and / or connected to the light-emitting element LE in the display area DA and the pixel PX including the light-emitting element LE.

[0124] The common electrode CE can be electrically connected to the Figure 1 and Figure 2 The common electrode CE may be supplied with the common voltage through the common electrode connection portion CVS in the first common voltage supply area CVA1 and / or the second common voltage supply area CVA2.

[0125] The common electrode CE may include a transparent conductive material capable of transmitting light. For example, the common electrode CE may be made of indium tin oxide (ITO), indium zinc oxide (IZO), or other transparent conductive materials. In one embodiment, it may serve as the cathode electrode (or anode electrode) of the light-emitting element LE.

[0126] The third interlayer insulating layer INS6 may be provided on the common electrode CE. For example, the third interlayer insulating layer INS6 may be a cap layer provided entirely in the display area DA to cover the common electrode CE. The third interlayer insulating layer INS6 may include, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y ), inorganic insulating materials such as aluminum nitride (AlN) or any other insulating materials.

[0127] In one embodiment, the display panel 100 may include a lens type optical structure LS disposed on the light emitting element layer 120. In addition, the display panel 100 may further include a protection layer PRL covering the lens type optical structure LS.

[0128] A lens-type optical structure LS may be disposed in each light-emitting area EA so as to overlap the light-emitting element LE. In one embodiment, the lens-type optical structure LS may be an optical structure in the form of a convex lens disposed on top of the light-emitting element LE, but the type and / or shape of the optical structure is not limited thereto. By disposing the lens-type optical structure LS on top of the light-emitting element LE, the light output characteristics of the pixel PX may be adjusted and / or improved.

[0129] The lens type optical structure LS may be formed of a transparent material to allow light incident from the light emitting element LE to transmit. For example, the lens type optical structure LS may be formed of glass, plastic, ceramic, or other materials, and may be formed of an optical material having a high refractive index.

[0130] The protective layer PRL may be provided on the lens type optical structure LS to cover the lens type optical structure LS. The protective layer PRL may be formed of a transparent and durable material (e.g., plastic or organic glass, optical glass, ceramic, etc.), but is not particularly limited thereto as long as the material is suitable for protecting the lens type optical structure LS. Figure 3 The embodiment in which the protective layer PRL has a curve corresponding to the shape of the lens type optical structure LS is shown, but the embodiment is not limited thereto. For example, the protective layer PRL may be formed in a shape that can flatten the top surface of the display panel 100 on which the lens type optical structure LS is formed.

[0131] Figure 6 It shows Figure 3 FIG. 1 is an enlarged schematic cross-sectional view of another example of an interlayer insulating layer and a through-electrode.

[0132] Reference Figure 6 , which is consistent with the reference Figure 4 The illustrated example may be different at least in that a barrier film BR surrounding the through electrode TRE may be further provided on the inner surface of the contact hole CH. Figure 6 , the barrier film BR may include a material such as SiN to prevent movement of metal ions forming the through electrode TRE.

[0133] Figure 7 is a schematic cross-sectional view showing a light emitting element according to one embodiment.

[0134] Reference Figure 7 The light emitting element LE may include a first semiconductor layer SEM1, an active layer MQW, and a second semiconductor layer SEM2 sequentially arranged and / or stacked along a third direction DR3. In one embodiment, the light emitting element LE may further include a contact electrode CTE disposed at an end portion. For example, the light emitting element LE may further include a contact electrode CTE disposed at an end portion where the first semiconductor layer SEM1 is located.

[0135] The light emitting element LE may further include additional layers according to embodiments. For example, the light emitting element LE may further include an electron blocking layer disposed between the first semiconductor layer SEM1 and the active layer MQW and / or a superlattice layer disposed between the active layer MQW and the second semiconductor layer SEM2.

[0136] In one embodiment, the light emitting element LE may be an inorganic light emitting element made of an inorganic material. For example, the light emitting element LE may be an inorganic light emitting diode formed of a nitride semiconductor material such as GaN, AlGaN, InGaN, AlInGaN, AlN, or InN, a phosphide semiconductor material such as GaP, GaInP, AlGaP, AlGaInP, AlP, or InP, or any other inorganic material.

[0137] The contact electrode (CTE) may be disposed and / or formed at an end of the light-emitting element LE where the first semiconductor layer (SEM1) is disposed. For example, the contact electrode (CTE) may be disposed and / or formed on a surface of the first semiconductor layer (SEM1). The contact electrode (CTE) may be an electrode that protects the first semiconductor layer (SEM1) and smoothly connects the first semiconductor layer (SEM1) to at least one circuit element, electrode, wiring, and / or conductive layer. The contact electrode (CTE) may include a metal, a metal oxide, or other conductive material.

[0138] The first semiconductor layer SEM1 may be disposed on the contact electrode CTE. In one embodiment, the first semiconductor layer SEM1 may include a nitride semiconductor material or a phosphide semiconductor material. For example, the first semiconductor layer SEM1 may include a nitride semiconductor material including at least one of GaN, AlGaN, InGaN, AlInGaN, AlN, and InN, or a phosphide semiconductor material including at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. The first semiconductor layer SEM1 may also include other materials.

[0139] The first semiconductor layer SEM1 may include a semiconductor material doped with a first conductive type dopant. For example, the first semiconductor layer SEM1 may include GaN (eg, p-GaN) doped with a first conductive dopant (eg, p-type dopant) such as Mg, Zn, Ca, Sr, or Ba.

[0140] The active layer MQW may be disposed on the first semiconductor layer SEM1. The active layer MQW may emit light by recombination of electron-hole pairs according to an electrical signal applied through the first and second semiconductor layers SEM1 and SEM2. For example, the active layer MQW may be a light emitting layer of the light emitting element LE.

[0141] The active layer MQW may include a material having a single or multiple quantum well structure. When the active layer MQW includes a material having a multiple quantum well structure, the active layer MQW may have a structure in which well layers and barrier layers are alternately stacked. The active layer MQW may also include other Group III to Group V semiconductor materials depending on the wavelength band of the emitted light.

[0142] In one embodiment, the active layer MQW may include a nitride semiconductor material or a phosphide semiconductor material. For example, the active layer MQW may include a nitride semiconductor material including at least one of GaN, AlGaN, InGaN, InGaAlN, AlN, InN, and AlInN, or a phosphide semiconductor material including at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. For example, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but the embodiment is not limited thereto. When the active layer MQW includes InGaN, the color of light emitted from the light-emitting element LE can be controlled by adjusting the indium (In) content. The active layer MQW may also include other materials.

[0143] In one embodiment, Figure 2The active layers MQW of the first, second, and third light-emitting elements LE1, LE2, and LE3 shown in FIG may emit light of the same color (e.g., blue light). In another embodiment, the active layers MQW of the first, second, and third light-emitting elements LE1, LE2, and LE3 may emit light of different colors (e.g., red light, green light, and blue light, respectively).

[0144] The second semiconductor layer SEM2 may be disposed on the active layer MQW. In one embodiment, the second semiconductor layer SEM2 may include a nitride semiconductor material or a phosphide semiconductor material. For example, the second semiconductor layer SEM2 may include a nitride semiconductor material including at least one of GaN, AlGaN, InGaN, AlInGaN, AlN, and InN, or a phosphide semiconductor material including at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. The second semiconductor layer SEM2 may also include other materials.

[0145] The second semiconductor layer SEM2 may include a semiconductor material doped with a second conductive type dopant. For example, the second semiconductor layer SEM2 may include GaN (eg, n-GaN) doped with a second conductive dopant (eg, n-type dopant) such as Si, Ge, Se, Sn, etc.

[0146] In one embodiment, the first semiconductor layer SEM1 and the second semiconductor layer SEM2 may have different thicknesses in the thickness direction of the light emitting element LE (e.g., the third direction DR3). For example, the second semiconductor layer SEM2 may be thicker than the first semiconductor layer SEM1 in the thickness direction of the light emitting element LE. Therefore, the active layer MQW may be positioned closer to the first end (e.g., the p-type end) of the light emitting element LE where the first semiconductor layer SEM1 is disposed, than to the second end (e.g., the n-type end) of the light emitting element LE where the second semiconductor layer SEM2 is disposed.

[0147] In one embodiment, the light-emitting element LE may be a vertical micro-LED that extends and / or is stacked in the third direction DR3. For example, the light-emitting element LE may be a micro-LED having a length in the first direction DR1, a length in the second direction DR2, and a length in the third direction DR3, each of which is tens to hundreds of micrometers (μm). In one embodiment, the length of the light-emitting element LE in the first direction DR1, the length in the second direction DR2, and the length in the third direction DR3 may each be approximately 100 μm or less.

[0148] In one embodiment, the light emitting element LE may include Figure 7For example, the light emitting element LE may be patterned by vertical etching and may have a rectangular or square cross-sectional shape in which the width of the top surface and the width of the lower surface are substantially equal.

[0149] The shape of the light emitting element LE may vary in different embodiments. For example, the light emitting element LE may have a cross-sectional shape in which the width of the top surface and the width of the bottom surface are different.

[0150] In one embodiment, the light emitting element LE may have a reverse tapered cross-section, for example, an inverted trapezoidal cross-section in which the width of the top surface is wider than the width of the bottom surface.

[0151] In one embodiment, the light emitting element LE may be disposed on the backplane substrate 110 such that the first semiconductor layer SEM1 is located below the active layer MQW and the second semiconductor layer SEM2 is located above the active layer MQW. Figure 7 For example, the light emitting element LE may be provided in each light emitting area EA so that the contact electrode CTE (or the first semiconductor layer SEM1) is in contact with the light emitting area EA. Figure 3 The upper bonding electrode UBE in the second semiconductor layer SEM2 contacts the second semiconductor layer SEM2 (or other contact electrodes provided on the second semiconductor layer SEM2 ) and contacts the common electrode CE. In this case, the common electrode CE may be a cathode electrode.

[0152] The structure, material, size and / or shape of the light emitting element LE are not limited to the above embodiments. For example, the structure, material, size and / or shape of the light emitting element LE may vary in different embodiments.

[0153] Figure 8 is a flow chart showing a method for manufacturing a display device according to one embodiment. Figure 8 is a flowchart illustrating a method of manufacturing the display panel 100 of the display device 10 according to one embodiment. Figures 9 to 25 is a schematic diagram for illustrating a method for manufacturing a display panel according to an embodiment. For example, Figures 9 to 25 Specific steps for forming the display panel 100 are each shown in the form of a cross-sectional view.

[0154] Reference Figure 9 , a backplane substrate 110 ( ) including a contact hole CH exposing at least a portion of the pixel electrode PXE in the interlayer insulating layers INS2 and INS3 may be provided. Figure 8 S110 in the ). Figure 9 is a cross-sectional view showing a schematic shape of the back plate substrate 110 .

[0155] The backplane substrate 110 may include pixel electrodes PXE and interlayer insulating layers INS2 and INS3. For example, the backplane substrate 110 may include pixel electrodes PXE spaced apart from each other and interlayer insulating layers INS2 and INS3 covering the pixel electrodes PXE. The interlayer insulating layers INS2 and INS3 may have contact holes CH that penetrate the interlayer insulating layers INS2 and INS3 on each of the pixel electrodes PXE and expose at least a portion of the pixel electrodes PXE.

[0156] Reference Figure 10 , a through electrode TRE can be formed in the contact hole CH ( Figure 8 S120 in the .

[0157] The contact hole CH may be formed by an etching method such as laser or ion etching.

[0158] Reference Figure 11 , the top surface of the through electrode TRE can be flattened ( Figure 8 In one embodiment, the planarization process may be performed by a polishing process such as a chemical mechanical polishing (CMP) process.

[0159] In a chemical mechanical polishing (CMP) process, the through electrodes TRE protruding onto the interlayer insulating layers INS2 and INS3 may be planarized by contacting the through electrodes TRE with a polishing pad and moving the polishing pad in an orbital motion that is a combination of rotation and linear motion using a slurry composition including an abrasive.

[0160] The slurry composition used in the CMP process can be mainly composed of compounds such as abrasive particles for physical action and an etchant for chemical action. Therefore, by selectively etching the exposed portion of the wafer surface through physical and chemical actions, the slurry composition can perform a more optimized and extensive planarization process. In one embodiment, the slurry composition is used to planarize the through-electrodes TRE protruding outward from the interlayer insulating layers INS2 and INS3, and includes a material that softens the through-electrodes TRE faster than the interlayer insulating layers INS2 and INS3. Therefore, when the interlayer insulating layers INS2 and INS3 and the surface of the through-electrode TRE exposed to the outside are polished by the slurry composition, dishing TRE_D may occur on the through-electrode TRE formed with a material having a faster polishing rate.

[0161] Reference Figure 12 , a first bottom junction electrode material may be applied ( Figure 8 S140 in the ).

[0162] For example, the conductive first bottom bonding electrode layer BBE1_1 may be formed by entirely coating a conductive bonding material (eg, first bottom bonding electrode material) on top surfaces of the through electrode TRE and the interlayer insulating layers INS2 and INS3 where the recess TRE_D occurs.

[0163] The first bottom bonding electrode layer BBE1_1 may follow the surface contour of the lower structure (the second interlayer insulating layer INS3 and the through electrode TRE). Therefore, the first bottom bonding electrode layer BBE1_1 may include a groove BBE_H on both the lower and upper surfaces corresponding to the location where the through electrode TRE is recessed.

[0164] Reference Figure 13 , the first bottom bonding electrode layer BBE1_1 may be planarized, and the first bottom bonding electrode material ( Figure 8 S150 in the ).

[0165] In one embodiment, a planarization process may be performed using a polishing process such as a chemical mechanical polishing (CMP) process. The planarization process may planarize the upper surface of the first bottom bonding electrode layer BBE1_1 so that the grooves BBE_H on the upper surface are removed. Furthermore, the planarization process may form an oxide layer on the upper surface of the first bottom bonding electrode layer BBE1_1.

[0166] A conductive bonding material (e.g., a first bottom bonding electrode material) may be entirely coated on the upper surface of the first bottom bonding electrode layer BBE1_1 on which the oxide layer is formed, to form a conductive second bottom bonding electrode layer BBE1_2. As a result, a conductive first bottom bonding electrode BBE1 may be formed (in describing the method, BBE1 may refer to a first bottom bonding electrode to be formed; similarly, BBE1_1, BBE1_2, BBE2, BBE, UBE1, UBE2, and UBE may refer to a first bottom bonding electrode layer, a second bottom bonding electrode layer, a second bottom bonding electrode, a bottom bonding electrode, a first upper bonding electrode, a second upper bonding electrode, and an upper bonding electrode to be formed, respectively).

[0167] Reference Figure 14 , a second bottom bonding electrode BBE2 ( Figure 8 S160 in the ).

[0168] For example, the conductive second bottom bonding electrode BBE2 can be formed by coating the entire upper surface of the first bottom bonding electrode BBE1 with a conductive bonding material (e.g., a second bottom bonding electrode material). The conductive bonding material used to form the second bottom bonding electrode BBE2 can be different from the conductive bonding material used to form the first bottom bonding electrode BBE1. For example, the first bottom bonding electrode BBE1 can be made of titanium (Ti), and the second bottom bonding electrode BBE2 can be made of gold (Au), but embodiments are not limited thereto.

[0169] Reference Figure 15 , preparing a base substrate BSUB on which a semiconductor material layer LEML is stacked, and forming an upper bonding electrode UBE ( Figure 8 S170 in the ).

[0170] The base substrate BSUB may be a semiconductor substrate suitable for epitaxial growth of a semiconductor. For example, the base substrate BSUB may be a substrate containing a material such as silicon (Si), sapphire, SiC, GaN, GaAs, or ZnO. The type, material, and shape of the base substrate BSUB are not particularly limited as long as epitaxial growth for manufacturing the light-emitting element LE can be successfully performed.

[0171] The semiconductor material layer LEML may include a third semiconductor layer, a second semiconductor layer SEM2 , an active layer MQW, and a first semiconductor layer SEM1 that are sequentially disposed on the base substrate BSUB.

[0172] For example, Figure 7 As shown in , on the base substrate BSUB, a third semiconductor layer, a second semiconductor layer SEM2, an active layer MQW, and a first semiconductor layer SEM1 can be sequentially formed by epitaxial growth. In one embodiment, the third semiconductor layer, the second semiconductor layer SEM2, the active layer MQW, and the first semiconductor layer SEM1 can be formed by epitaxial growth using a process technology such as metal organic chemical vapor deposition (MOCVD), metal organic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or vapor phase epitaxy (VPE).

[0173] The third semiconductor layer may be provided to reduce the difference in lattice constant between the second semiconductor layer SEM2 and the base substrate BSUB. As an example, the third semiconductor layer may include an undoped semiconductor, and may be a material that is not doped to n-type or p-type. In one embodiment, the third semiconductor layer may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto.

[0174] The second semiconductor layer SEM2 may be formed from the materials of the second semiconductor layer SEM2 previously exemplified. For example, the second semiconductor layer SEM2 may be formed from at least one nitride-based semiconductor material or a phosphide-based semiconductor material and may be formed as a single layer or multiple layers. The second semiconductor layer SEM2 may be doped to include a second conductivity-type dopant (e.g., an n-type dopant).

[0175] The active layer MQW can be formed from the materials of the active layer MQW previously exemplified. For example, the active layer MQW can be formed from at least one nitride-based semiconductor material or a phosphide-based semiconductor material. In one embodiment, barrier layers and quantum well layers can be alternately and / or repeatedly formed on the second semiconductor layer SEM2 to form the active layer MQW having a multi-quantum well structure.

[0176] The first semiconductor layer SEM1 may be formed of the material of the first semiconductor layer SEM1 previously exemplified. For example, the first semiconductor layer SEM1 may be formed of a single nitride-based semiconductor material or a phosphide-based semiconductor material, or may be formed as a single layer or multiple layers. The first semiconductor layer SEM1 may be doped to include a first conductivity-type dopant (e.g., a p-type dopant).

[0177] In one embodiment, the manufacturing process includes Figure 7 In the case of the light emitting element LE including the contact electrode CTE in the embodiment, a process for forming the contact electrode CTE (or a conductive layer for forming the contact electrode CTE) on the semiconductor material layer LEML may be further performed. For example, the light emitting element LE may further include the contact electrode CTE formed on the first semiconductor layer SEM1.

[0178] The contact electrode CTE may be formed of the materials previously described. The contact electrode CTE may be formed by a process such as coating (eg, depositing) a conductive material on the semiconductor material layer LEML, and the method of forming the contact electrode CTE is not particularly limited.

[0179] One or more layers of upper bonding electrode material ( Figure 8 S170 in the ).

[0180] For example, the second upper bonding electrode UBE2 can be formed by applying the second bonding electrode material entirely to the top surface of the first semiconductor layer SEM1. Thereafter, the first upper bonding electrode UBE1 can be formed by applying the first bonding electrode material entirely to the second upper bonding electrode UBE2. In one embodiment, the second upper bonding electrode UBE2 can be made of titanium (Ti), and the first upper bonding electrode UBE1 can be made of gold (Au), but the embodiment is not limited thereto.

[0181] Reference Figure 15 and Figure 16 , the base substrate BSUB and the backplane substrate 110 may be bonded, and the base substrate BSUB may be removed ( Figure 8 S180 in the ).

[0182] For example, refer to Figure 15 and Figure 16 , the upper bonding electrode UBE on the base substrate BSUB can be positioned to face the bottom bonding electrode BBE on the backplane substrate 110. Thereafter, the base substrate BSUB can be placed on the backplane substrate 110 for bonding, such that the upper bonding electrode UBE and the bottom bonding electrode BBE contact each other. Thus, the semiconductor layer on the base substrate BSUB can be bonded to the backplane substrate 110.

[0183] In one embodiment, the bottom bonding electrode BBE on the backplane substrate 110 and the upper bonding electrode UBE on the base substrate BSUB may be bonded by a process of bonding the base substrate BSUB to the backplane substrate 110 using a thermocompression (TC) bonding method. The method of bonding (or adhering) the base substrate BSUB to the backplane substrate 110 is not limited thereto, and the backplane substrate 110 and the base substrate BSUB may be bonded in other ways.

[0184] The base body substrate BSUB may be removed.

[0185] For example, a laser device may be used to irradiate a laser beam to the base substrate BSUB to separate the semiconductor material layer LEML from the base substrate BSUB. The base substrate BSUB may be separated from the third semiconductor layer of the semiconductor material layer LEML.

[0186] The process of separating the base substrate BSUB may be performed using a laser lift-off (LLO) process or a polishing process such as a chemical mechanical polishing (CMP) process. The laser lift-off process utilizes laser light, and a KrF excimer laser (approximately 248 nm wavelength) may be used as a laser source, but the embodiment is not limited thereto. By irradiating the base substrate BSUB with laser light, the base substrate BSUB may be separated from the semiconductor material layer LEML.

[0187] In some cases, the third semiconductor layer may be removed, for example by gluing.

[0188] Reference Figures 17 to 25 , the light emitting element LE may be formed, and subsequent processes including processes for forming element insulating layers INS4 and INS5, a reflective layer RF, and a common electrode CE may be performed ( Figure 8 S190 in the ).

[0189] For example, refer to Figure 17 , the semiconductor material layer LEML may be etched using a mask to form a light emitting element LE.

[0190] The semiconductor material layer LEML may be etched using a suitable method. For example, the process for etching the semiconductor material layer LEML may be dry etching, wet etching, reactive ion etching (RIE), deep reactive ion etching (DRIE), inductively coupled plasma reactive ion etching (ICP-RIE), or the like. In the case of a dry etching method, anisotropic etching may be possible and may be suitable for vertical etching. In the case of the above-mentioned etching methods, the etchant may be Cl2 or O2. However, embodiments are not limited thereto.

[0191] For example, the semiconductor material layer LEML overlapping the mask may not be etched and the semiconductor material layer LEML not overlapping the mask may be etched to form the light emitting element LE. Therefore, the light emitting element LE may be formed to include the third semiconductor layer, the second semiconductor layer SEM2, the superlattice layer, the active layer MQW, the electron barrier layer, and the first semiconductor layer SEM1.

[0192] Reference Figure 18 , the upper bonding electrode UBE and the bottom bonding electrode BBE may be etched.

[0193] For example, the upper bonding electrode UBE and the bottom bonding electrode BBE may be etched using the etched light-emitting element LE as a mask. Thus, the upper bonding electrode UBE and the bottom bonding electrode BBE may protrude outward from the light-emitting element LE, but the embodiment is not limited thereto. The process of etching the upper bonding electrode UBE and the bottom bonding electrode BBE may be similar to the process of etching the semiconductor material layer LEML.

[0194] Reference Figure 19 , an insulating material may be entirely applied to the backplane substrate 110 on which the light emitting element LE is formed, thereby forming a first element insulating material layer INSL4.

[0195] Reference Figure 20 , a reflective layer RF may be formed on the first element insulating material layer INSL4 surrounding the side surfaces of the light emitting element LE and the side surfaces of the bonding electrodes UBE and BBE.

[0196] For example, a reflective material may be deposited to cover the first element insulating material layer INSL4. A large voltage difference may be formed in the third direction DR3 without a separate mask, and the reflective layer RF may be etched using an etching material. In this case, the etching material moves in the third direction DR3 (ie, from top to bottom), and the reflective layer RF may be etched. As a result, Figure 20 As shown in FIG, the reflective layer RF disposed on the horizontal plane defined by the first direction DR1 and the second direction DR2 may be removed, while the reflective layer RF disposed on the vertical plane defined by the third direction DR3 may not be removed. Therefore, the reflective layer RF disposed on the top surface of the first element insulating material layer INSL4 may be removed. The reflective layer RF disposed on the side surfaces of the light emitting element LE and the side surfaces of the bonding electrodes UBE and BBE may not be removed.

[0197] Reference Figure 21 , the second element insulating material layer INSL5 may be formed by entirely coating an insulating material on the first element insulating material layer INSL4 and the reflective layer RF.

[0198] Reference Figure 22 , an opening OP may be formed in the first and second element insulating material layers INSL4 and INSL5 on the light emitting element LE to expose the top surface of the light emitting element LE, and the first and second element insulating layers INS4 and INS5 may be formed.

[0199] Reference Figure 23 , an organic film ORL can be formed between the light emitting elements LE.

[0200] For example, a filler may be applied between the light emitting elements LE to fill the organic film ORL between the light emitting elements LE.

[0201] Reference Figure 24 and Figure 25 , subsequent processes for forming the light emitting element layer 120 (including a process for forming the common electrode CE) may be performed.

[0202] In one embodiment, when manufacturing a display panel 100 including a light conversion layer and / or a color filter layer, a process for forming a light conversion layer and / or a color filter layer on top of the light emitting element layer 120 or inside the light emitting element layer 120 may be further performed.

[0203] In one embodiment, the manufacturing process includes Figure 3 In the case of the display panel 100 having the lens type optical structure LS shown in , the process may further include the steps of adhering and / or forming the lens type optical structure LS and the protective layer PRL on the light emitting element layer 120 .

[0204] Figure 26 is a cross-sectional view for illustrating voids that may occur if a planarization process is not performed on the bottom bonding electrode. Figure 26 It is a reference Figures 12 to 16 Schematic cross-sectional view of a comparative example of the described method.

[0205] In the case of Figure 11 After the interlayer insulating layers INS2 and INS3 having different etching rates and the top surfaces of the through electrode TRE are planarized to form a recess TRE_D on the top surface of the through electrode TRE as shown in FIG. Figures 12 to 14 As shown in FIG, first and second bottom bonding electrodes BBE1 and BBE2 are sequentially formed on the interlayer insulating layers INS2 and INS3 and the through electrode TRE. The first and second bottom bonding electrodes BBE1 and BBE2 may have grooves (concavo-convex portions) corresponding to the grooves on the top surface of the through electrode TRE.

[0206] The base substrate BSUB, on which the upper bonding electrode UBE and the semiconductor material layer LEML are disposed, can be bonded to the bottom bonding electrode BBE. Consequently, gaps VD may form between the bottom bonding electrode BBE and the upper bonding electrode UBE, corresponding to the grooves (concave and convex portions) of the first and second bottom bonding electrodes BBE1 and BBE2, resulting in a missing junction. If a missing junction occurs between the bottom bonding electrode BBE and the upper bonding electrode UBE, vertical resistance may increase, potentially leading to a disconnection between the light-emitting element LE and the pixel circuit PXC. This disconnection risk is particularly pronounced in display devices with higher resolutions.

[0207] On the other hand, according to one embodiment, since the upper surface of the bottom bonding electrode BBE can be completely polished, even if a concave-convex portion is formed on the lower surface of the bottom bonding electrode BBE, the upper surface can be formed to be flat, thereby preventing or minimizing the generation of a gap VD between the bottom bonding electrode BBE and the upper bonding electrode UBE. Therefore, the risk of disconnection between the light emitting element LE and the pixel circuit PXC can be minimized.

[0208] Figure 27 is a schematic diagram illustrating a virtual reality device including a display device according to an embodiment. Figure 27 A virtual reality device 1 is shown in which a display device 10_1 according to an embodiment can be provided.

[0209] Reference Figure 27The virtual reality device 1 according to the embodiment may be a device in the form of glasses. The virtual reality device 1 according to the embodiment may include a display device 10_1, a left-eye lens 10a, a right-eye lens 10b, a support frame 20, left legs 30a and right legs 30b, a reflective member 40, and a display device housing 50.

[0210] Figure 27 The virtual reality device 1 includes two legs 30a and 30b. However, the disclosure is not limited thereto. The virtual reality device 1 according to the embodiment may be used in a head-mounted display including a headband that can be mounted on the head instead of the legs 30a and 30b. For example, the virtual reality device 1 according to the embodiment may not be limited to Figure 27 The examples shown in and can be applied in various forms and in various electronic devices.

[0211] The display device housing 50 can accommodate the display device 10_1 and the reflective member 40. The image displayed on the display device 10_1 can be reflected from the reflective member 40 and provided to the user's right eye through the right-eye lens 10b. Therefore, the user can view the virtual reality image displayed on the display device 10_1 through the right eye.

[0212] Figure 27 The display device housing 50 is shown as being disposed at the right end of the support frame 20. However, the disclosed embodiments are not limited thereto. For example, the display device housing 50 may be disposed at the left end of the support frame 20. In this case, the image displayed on the display device 10_1 can be reflected from the reflective member 40 and provided to the user's left eye via the left-eye lens 10a. Thus, the user can view the virtual reality image displayed on the display device 10_1 through the left eye. As another example, the display device housing 50 may be disposed at each of the left and right ends of the support frame 20. In this case, the user can view the virtual reality image displayed on the display device 10_1 through both the left eye and the right eye.

[0213] Figure 28 is a schematic diagram illustrating a smart device including a display device according to an embodiment.

[0214] Reference Figure 28 The display device 10_2 according to the embodiment can be applied to a smart watch 2 which is one of smart devices.

[0215] Figure 29 is a schematic diagram illustrating a vehicle including a display device according to an embodiment. Figure 29 A vehicle provided with the display device according to the embodiment is shown.

[0216] Reference Figure 29The display devices 10_a, 10_b, and 10_c according to the embodiments can be applied to a vehicle dashboard, a vehicle center instrument panel, or a CID (Central Information Display) provided on the vehicle dashboard. Furthermore, each of the display devices 10_d and 10_e according to the embodiments can be applied to a respective interior mirror display that replaces each of the vehicle's side mirrors.

[0217] Figure 30 is a schematic diagram illustrating a transparent display device including a display device according to an embodiment.

[0218] Reference Figure 30 The display device 10_3 according to the embodiment can be applied to a transparent display device. The transparent display device can transmit light while displaying an image IM thereon. Therefore, a user located in front of the transparent display device can not only view the image IM displayed on the display device 10_3, but also view an object RS or background located behind the transparent display device. In the case where the display device 10_3 is applied to a transparent display device, the display device 10_3 Figure 3 The backplane substrate 110 shown in FIG. 1 may include a light-transmitting portion that can transmit light, or may be made of a material that can transmit light.

[0219] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the embodiments without departing substantially from the principles of the disclosure. Therefore, the disclosed embodiments disclosed are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, comprising: a substrate including a pixel circuit; a pixel electrode connected to the pixel circuit; an insulating layer, disposed on the pixel electrode; a through electrode, penetrating the insulating layer and connected to the pixel electrode; a bottom bonding electrode and an upper bonding electrode, sequentially disposed on the through electrode and the insulating layer; as well as A light emitting element is provided on the upper bonding electrode, wherein The through electrode has a groove whose upper surface is concave downwards, The lower surface of the bottom bonding electrode follows the surface contours of the insulating layer and the through electrode disposed thereunder, and the upper surface of the bottom bonding electrode is flat, and The bottom junction electrode includes an oxide layer.

2. The display device according to claim 1, wherein The lower surface of the bottom bonding electrode has a downwardly projecting protrusion corresponding to the recessed groove of the through electrode.

3. The display device according to claim 1, wherein The bottom bonding electrode includes a first bottom bonding electrode and a second bottom bonding electrode formed of different materials, the second bottom bonding electrode being disposed on the first bottom bonding electrode, and The oxide layer is disposed between multiple layers of the first bottom junction electrode.

4. The display device according to claim 3, wherein: The first bottom bonding electrode and the second bottom bonding electrode are made of a material selected from the group consisting of titanium, nickel, platinum, tin, gold, aluminum, and tungsten.

5. The display device according to claim 2, wherein: The upper surface and the lower surface of the upper bonding electrode are flat.

6. The display device according to claim 5, wherein: The upper bonding electrode is formed of one or more layers. 7 . The display device according to claim 1 , further comprising a barrier film surrounding a side surface of the through electrode.

8. The display device according to claim 7, wherein: The barrier film includes a material that prevents movement of metal ions forming the through-electrode.

9. The display device according to claim 1, wherein: The upper bonding electrode and the bottom bonding electrode protrude outward from the light emitting element.

10. The display device according to claim 1, further comprising: a first insulating layer surrounding the light emitting element and side surfaces of the bottom bonding electrode and the upper bonding electrode; a reflective layer, disposed on the side surface of the light-emitting element; a second insulating layer surrounding the light emitting element and the side surfaces of the bottom bonding electrode and the upper bonding electrode on the reflective layer and the first insulating layer; as well as A common electrode is provided on an upper portion of the light emitting element.

11. The display device according to claim 10, further comprising: A lens-type optical structure is on the light-emitting element layer including the light-emitting element and the common electrode.

12. A method for manufacturing a display device, the method comprising the following steps: Providing a backplane substrate, the backplane substrate comprising a pixel electrode connected to the pixel circuit and an insulating layer disposed on the pixel electrode; forming a through electrode, wherein the through electrode penetrates the insulating layer and is connected to the pixel electrode; planarizing top surfaces of the insulating layer and the through-electrodes; applying a first conductive bonding material to the top surface of the through electrode; planarizing the first conductive bonding material to form an oxide layer on the top surface of the through electrode; forming a bottom bonding electrode layer by additionally coating a second conductive bonding material on the first conductive bonding material having the oxide layer formed thereon; providing a base substrate having an upper bonding electrode layer and a plurality of semiconductor layers; bonding the base substrate and the backplane substrate and removing the base substrate; as well as A plurality of light emitting elements are formed by etching the plurality of semiconductor layers.

13. The method of claim 12, wherein: The steps of planarizing the insulating layer and the top surfaces of the through-electrodes, planarizing the first conductive bonding material to form the oxide layer on the top surfaces of the through-electrodes, and removing the base substrate include a chemical mechanical polishing process.

14. The method of claim 12, wherein: The step of planarizing the top surfaces of the insulating layer and the through-electrode includes forming a groove recessed downward on the through-electrode.

15. The method of claim 14, wherein: The bottom surface of the bottom bonding electrode layer has a downwardly protruding protrusion corresponding to the recessed groove of the through electrode, and The upper surface of the bottom bonding electrode layer is flat.

16. The method of claim 12, further comprising: A bonding electrode is formed by etching the bottom bonding electrode layer and the upper bonding electrode layer.

17. The method of claim 16, wherein: The step of forming the bottom bonding electrode layer by additionally coating the second conductive bonding material on the first conductive bonding material having the oxide layer formed thereon includes: forming a first bottom bonding electrode layer by additionally coating the first conductive bonding material on the first conductive bonding material having the oxide layer formed thereon; and A second bottom bonding electrode layer is formed on the first bottom bonding electrode layer by coating the second conductive bonding material different from the first conductive bonding material.

18. The method of claim 12, further comprising: An insulating layer and a reflective layer are formed around side surfaces of the light emitting element.

19. The method of claim 17, further comprising: A common electrode is formed on the light emitting element.

20. The method of claim 19, further comprising: A lens-type optical structure is formed on the light emitting element layer including the light emitting element and the common electrode.

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