Display device

Abstract

The present disclosure relates to a display device, and more particularly, to a display device capable of expanding an area of a display region. According to an embodiment disclosed, a display device includes: a substrate; a pixel circuit on the substrate; a light emitting element connected to the pixel circuit; and a driving circuit connected to the pixel circuit, in which the light emitting element overlaps the driving circuit.

Description

[0001] This application claims priority from and all benefits derived from Korean Patent Application No. 10-2024-0030530 filed on March 4, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display device, and more particularly, to a display device capable of expanding the area of ​​a display region. Background Art

[0003] A head-mounted display (HMD) is a device worn on the user's head in the form of glasses or a helmet, displaying images focused close to the user's eyes. HMDs can enable virtual reality (VR) or augmented reality (AR).

[0004] Head-mounted displays (HMDs) magnify images displayed on a small display device using multiple lenses and display the magnified image. Therefore, HMD display devices must provide high-resolution images, for example, images with a resolution of 3000 PPI (pixels per inch) or higher. To this end, organic light-emitting diodes on silicon (OLEDoS), which are compact, high-resolution organic light-emitting display devices, are used as HMD display devices. OLEDoS is an image display device in which organic light-emitting diodes (OLEDs) are provided on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is provided. Summary of the Invention

[0005] Aspects of the present disclosure provide a display device capable of expanding the area of ​​a display region.

[0006] According to a disclosed embodiment, a display device includes: a substrate; a pixel circuit on the substrate; a light emitting element connected to the pixel circuit; and a driving circuit connected to the pixel circuit, wherein the light emitting element and the driving circuit are overlapped.

[0007] In an embodiment, a light emitting element includes: a first electrode on a substrate; a light emitting layer on the first electrode; and a second electrode on the light emitting layer.

[0008] In an embodiment, the first electrode overlaps the driving circuit.

[0009] In an embodiment, the display device further includes a pixel defining layer disposed on the first electrode and defining an emission area of ​​the light emitting element.

[0010] In an embodiment, the emission region overlaps the driving circuit.

[0011] In an embodiment, the light emitting element is stacked with a non-pixel transistor of the driving circuit.

[0012] In an embodiment, the pixel circuits and the driving circuits are alternately arranged.

[0013] In an embodiment, the pixel circuit is surrounded by the driving circuit.

[0014] In an embodiment, the driving circuit includes at least one of: a scan driver connected to the pixel circuit through a scan line; an emission driver connected to the pixel circuit through an emission control line; a data driver connected to the pixel circuit through a data line; and a timing control circuit connected to the scan driver, the emission driver and the data driver.

[0015] In an embodiment, the display device further includes a reflective electrode layer connected to the light emitting element.

[0016] In an embodiment, the reflective electrode layer overlaps the driving circuit.

[0017] According to a disclosed embodiment, a display device includes: a substrate; a plurality of pixel circuits on the substrate; a plurality of light-emitting elements respectively connected to the plurality of pixel circuits; and a driving circuit connected to at least one pixel circuit, wherein the plurality of light-emitting elements include: a first light-emitting element overlapping with the driving circuit; and a second light-emitting element not overlapping with the driving circuit.

[0018] In an embodiment, the first light-emitting element includes: a first electrode on a substrate; a light-emitting layer on the first electrode; and a second electrode on the light-emitting layer.

[0019] In an embodiment, the first electrode overlaps the driving circuit.

[0020] In an embodiment, the display device further includes a pixel defining layer disposed on the first electrode and defining an emission area of ​​the first light emitting element.

[0021] In an embodiment, the emission region overlaps the driving circuit.

[0022] In an embodiment, the first light emitting element is overlapped with a non-pixel transistor of the driving circuit.

[0023] In an embodiment, the driving circuits and the pixel circuits connected to the first light emitting elements are alternately provided.

[0024] In an embodiment, the pixel circuit connected to the first light emitting element is surrounded by the driving circuit.

[0025] In an embodiment, the driving circuit includes at least one of: a scan driver connected to the pixel circuit through a scan line; an emission driver connected to the pixel circuit through an emission control line; a data driver connected to the pixel circuit through a data line; and a timing control circuit connected to the scan driver, the emission driver and the data driver.

[0026] According to the display device according to one embodiment, the display area can be expanded, and thus the number of dies of a wafer on which a display panel is manufactured increases, so that the manufacturing cost of the display device can be reduced.

[0027] However, the effects according to the embodiments of the present disclosure are not limited to the effects exemplified above, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 is an exploded perspective view showing a display device according to one embodiment; Figure 2 is a block diagram showing a display device according to one embodiment; Figure 3 is an equivalent circuit diagram of a sub-pixel according to one embodiment; Figure 4 is a layout diagram showing an example of a display panel according to one embodiment; Figure 5 and Figure 6 It shows Figure 4 A layout diagram of an embodiment of a display area; Figure 7 It is shown along Figure 5 A cross-sectional view of an example of a display panel taken along line I1-I1'; Figure 8 is a layout diagram showing a portion of a display panel according to one embodiment; Figure 9 It is along Figure 8 A sectional view taken along line III-III'; Figure 10 is a layout diagram of a display panel according to one embodiment; Figure 11 is a layout diagram of a display panel according to one embodiment; Figure 12 is a layout diagram of a display panel according to one embodiment; Figure 13 is a diagram showing a portion of a display area of ​​a display panel according to one embodiment; Figure 14is a diagram showing a portion of a display area of ​​a display panel according to one embodiment; Figure 15 is a diagram showing a portion of a display area of ​​a display panel according to one embodiment; Figure 16 is a perspective view showing a head-mounted display according to one embodiment; Figure 17 It shows Figure 16 an exploded perspective view of an example of a head-mounted display; and Figure 18 is a perspective view showing a head-mounted display according to one embodiment. DETAILED DESCRIPTION

[0029] The advantages and features of the present disclosure and methods for achieving them will become apparent from the following description of exemplary embodiments with reference to the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in a variety of different ways. The exemplary embodiments are provided to make the disclosure of the present disclosure thorough and to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that the scope of the present disclosure is limited only by the claims.

[0030] As used herein, the phrase "element A on element B" means that element A may be directly disposed on element B and / or element A may be indirectly disposed on element B via another element C. Like reference numerals denote like elements throughout the description. The drawings, dimensions, ratios, angles, and quantities of elements given in the drawings are illustrative only and not limiting.

[0031] Although terms such as first, second, etc. are used to arbitrarily distinguish the elements described by such terms, these terms are not necessarily intended to indicate the order or other priority of such elements. These terms are only used to distinguish one element from another. Therefore, as used herein, within the technical scope of the present disclosure, a first element may be a second element.

[0032] The features of the various exemplary embodiments of the present disclosure may be combined in part or in whole. As will be clearly understood by those skilled in the art, various interactions and operations are technically feasible. The various exemplary embodiments may be practiced individually or in combination.

[0033] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0034] Figure 1 is an exploded perspective view showing a display device 10 according to one embodiment. Figure 2 is a block diagram illustrating a display device 10 according to one embodiment.

[0035] Reference Figure 1 and Figure 2 The display device 10 according to one embodiment is a device that displays moving images or still images. The display device 10 according to one embodiment can be applied to portable electronic devices such as mobile phones, smartphones, tablet personal computers, mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile personal computers (UMPCs). For example, the display device 10 according to one embodiment can be applied as a display unit for televisions, laptop computers, monitors, billboards, or Internet of Things (IoT) terminals. Alternatively, the display device 10 according to one embodiment can be applied to smart watches, watch phones, head-mounted displays (HMDs) for implementing virtual reality and augmented reality, and the like.

[0036] A display device 10 according to one embodiment includes a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , a timing control circuit 400 , and a power supply circuit 500 .

[0037] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be a right angle or a rounded (or rounded) corner with a predetermined curvature. The planar shape of the display panel 100 is not limited to a quadrilateral and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may conform to the planar shape of the display panel 100, but the embodiments of the present specification are not limited thereto.

[0038] The display panel 100 includes Figure 2 , there is a display area DAA for displaying an image and a non-display area NDA for not displaying an image.

[0039] The display area DAA includes a plurality of pixels, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0040] A plurality of pixels may be arranged in a matrix in a first direction DR1 and a second direction DR2. A plurality of scan lines SL and a plurality of emission control lines EL may extend in the first direction DR1 and be arranged in the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 and be arranged in the first direction DR1.

[0041] The plurality of scan lines SL include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines EBL. The plurality of emission control lines EL include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0042] Each of the plurality of unit pixels UPX includes a plurality of pixels PX1, PX2, and PX3. The plurality of pixels PX1, PX2, and PX3 may include: Figure 3 The plurality of pixel transistors shown in FIG. 1 and FIG. 2 are formed by a semiconductor process and can be disposed on a semiconductor substrate SSUB (see FIG. 2 ). Figure 7 For example, a plurality of pixel transistors of the data driver 700 may be formed of a complementary metal oxide semiconductor (CMOS).

[0043] Each of the plurality of pixels PX1, PX2, and PX3 can be connected to any one of a plurality of write scan lines GWL, any one of a plurality of control scan lines GCL, any one of a plurality of bias scan lines EBL, any one of a plurality of first emission control lines EL1, any one of a plurality of second emission control lines EL2, and any one of a plurality of data lines DL. Each of the plurality of pixels PX1, PX2, and PX3 can receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL and emit light from the light emitting element according to the data voltage.

[0044] The non-display area NDA includes a scan driver 610 , an emission driver 620 , and a data driver 700 .

[0045] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors may be formed on a semiconductor substrate SSUB (see FIG. Figure 7 ). For example, a plurality of scanning transistors and a plurality of light emitting transistors can be formed by CMOS. Although Figure 2 , the scan driver 610 is provided on the left side of the display area DAA and the emission driver 620 is provided on the right side of the display area DAA, but the embodiments of the present specification are not limited thereto. For example, the scan driver 610 and the emission driver 620 may be provided on both the left and right sides of the display area DAA.

[0046] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate write scan signals based on the scan timing control signal SCS from the timing control circuit 400 and sequentially output them to the write scan lines GWL. The control scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS and sequentially output them to the control scan lines GCL. The bias scan signal output unit 613 may generate bias scan signals based on the scan timing control signal SCS and sequentially output them to the bias scan lines EBL.

[0047] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 can receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 can generate first emission control signals based on the emission timing control signal ECS and sequentially output them to the first emission control line EL1. The second emission control driver 622 can generate second emission control signals based on the emission timing control signal ECS and sequentially output them to the second emission control line EL2.

[0048] The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed on a semiconductor substrate SSUB (see FIG. Figure 7 For example, the plurality of data transistors may be formed of CMOS.

[0049] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, the pixels PX1, PX2, and PX3 are selected by the write scan signal of the scan driver 610, and the data voltage may be supplied to the selected pixels PX1, PX2, and PX3.

[0050] The heat dissipation layer 200 may overlap the display panel 100 in the third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be provided on one surface of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a metal layer having high thermal conductivity, such as graphite, silver (Ag), copper (Cu), or aluminum (Al).

[0051] The circuit board 300 may be electrically connected to the first pad portion PDA1 (see FIG. 1 ) of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film. Figure 4 ) of the multiple first pad PD1 (see Figure 4 ). The circuit board 300 may be a flexible printed circuit board having a flexible material or a flexible film. Figure 1 100, but the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. One end of the circuit board 300 may be the first pad portion PDA1 of the circuit board 300 connected to the display panel 100 by using a conductive adhesive member (see FIG. Figure 4 ) of the multiple first pad PD1 (see Figure 4 ) at the opposite end of the other end.

[0052] The timing control circuit 400 can receive digital video data DATA and timing signals input from the outside. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 can output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0053] The power supply circuit 500 can generate a plurality of panel driving voltages according to the power voltage from the outside. For example, the power supply circuit 500 can generate a common voltage VSS, a driving voltage VDD and an initialization voltage VINT and supply them to the display panel 100. Figure 3 The common voltage VSS, the driving voltage VDD, and the initialization voltage VINT are described.

[0054] Each of the timing control circuit 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) and attached to one surface of the circuit board 300. In this case, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 may be supplied to the display panel 100 through the circuit board 300. In addition, the common voltage VSS, the driving voltage VDD, and the initialization voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 through the circuit board 300.

[0055] Alternatively, similar to the scan driver 610, the emission driver 620, and the data driver 700, each of the timing control circuit 400 and the power supply circuit 500 may be provided in the non-display area NDA of the display panel 100. In this case, the timing control circuit 400 may include a plurality of timing transistors, and each power supply circuit 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed on the semiconductor substrate SSUB (see FIG. 1 ) by a semiconductor process. Figure 7 ). For example, a plurality of timing transistors and a plurality of power transistors may be formed of CMOS. Each of the timing control circuit 400 and the power supply circuit 500 may be provided between the data driver 700 and the first pad portion PDA1 (see Figure 4 )between.

[0056] The scanning transistor, light emitting transistor, data transistor, timing transistor and power transistor mentioned above can be defined as non-pixel transistors. In other words, the non-pixel transistors can include the scanning transistor, light emitting transistor, data transistor, timing transistor and power transistor mentioned above.

[0057] Figure 3 is an equivalent circuit diagram of a sub-pixel according to one embodiment.

[0058] Reference Figure 3 , the first pixel PX1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. Furthermore, the first pixel PX1 can be connected to a common voltage line VSL to which a common voltage VSS corresponding to a low potential voltage is applied, a drive voltage line VDL to which a drive voltage VDD corresponding to a high potential voltage is applied, and an initialization voltage line VIL to which an initialization voltage VINT is applied. That is, the common voltage line VSL can be a low potential voltage line, the drive voltage line VDL can be a high potential voltage line, and the initialization voltage line VIL can be an initialization voltage line. In this case, the common voltage VSS can be lower than the initialization voltage VINT. The drive voltage VDD can be higher than the initialization voltage VINT.

[0059] The first pixel PX1 may include a pixel circuit PC and a light emitting element LE connected to the pixel circuit PC.

[0060] The pixel circuit PC may include a plurality of transistors T1 to T6 , a first capacitor CP1 , and a second capacitor CP2 .

[0061] The light-emitting element LE emits light in response to the driving current Ids flowing through the channel of the first transistor T1. The emission amount of the light-emitting element LE may be proportional to the driving current Ids. The light-emitting element LE may be disposed between the fourth transistor T4 and the common voltage line VSL. The first electrode of the light-emitting element LE may be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE may be connected to the common voltage line VSL. The first electrode of the light-emitting element LE may be an anode electrode, and the second electrode of the light-emitting element LE may be a cathode electrode. The light-emitting element LE may be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but the embodiments of the present specification are not limited thereto. For example, the light-emitting element LE may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. In this case, the light-emitting element LE may be a micro light-emitting diode.

[0062] The first transistor T1 may be a driving transistor that controls a source-drain current Ids (hereinafter referred to as a "driving current") flowing between a source electrode and a drain electrode thereof according to a voltage applied to a gate electrode thereof. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to a drain electrode of the sixth transistor T6, and a drain electrode connected to a second node N2.

[0063] The second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal from the write scan line GWL to connect one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor CP1.

[0064] The third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal from the control scan line GCL to connect the first node N1 to the second node N2. To this end, since the gate electrode and drain electrode of the first transistor T1 are connected, the first transistor T1 can operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0065] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Therefore, the driving current Ids of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0066] The fifth transistor T5 may be disposed between the third node N3 and the initialization voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal from the bias scan line EBL to connect the third node N3 to the initialization voltage line VIL. Therefore, the initialization voltage VINT of the initialization voltage line VIL may be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the initialization voltage line VIL.

[0067] The sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the drive voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the drive voltage line VDL. Therefore, the drive voltage VDD of the drive voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0068] The first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0069] The second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the driving voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and the other electrode connected to the driving voltage line VDL.

[0070] The first node N1 is a junction of the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is a junction of the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a junction of the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0071] Each of the first to sixth transistors T1 to T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first to sixth transistors T1 to T6 may be a P-type MOSFET, but the embodiments of the present specification are not limited thereto. Each of the first to sixth transistors T1 to T6 may be an N-type MOSFET. Alternatively, some of the first to sixth transistors T1 to T6 may be P-type MOSFETs, and each of the remaining transistors may be an N-type MOSFET.

[0072] Despite Figure 3 FIG. 4 shows that the first pixel PX1 includes six transistors T1 to T6 and two capacitors CP1 and CP2 , but the equivalent circuit diagram of the first pixel PX1 is not limited to FIG. Figure 3 For example, the number of transistors and the number of capacitors of the first pixel PX1 are not limited to Figure 3 The example shown in .

[0073] In addition, the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 can be combined with Figure 3 The equivalent circuit diagram of the first pixel PX1 is substantially the same as that described above. Therefore, in this specification, descriptions of the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 will be omitted.

[0074] Figure 4 is a layout diagram illustrating an example of a display panel 100 according to one embodiment.

[0075] Reference Figure 4 The display area DAA of the display panel 100 according to one embodiment includes a plurality of pixels arranged in a matrix form. The non-display area NDA of the display panel 100 according to one embodiment includes a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0076] The scan driver 610 may be provided on a first side of the display area DAA, and the emission driver 620 may be provided on a second side of the display area DAA. For example, the scan driver 610 may be provided on one side of the display area DAA in the first direction DR1, and the emission driver 620 may be provided on the other side of the display area DAA in the first direction DR1. In other words, the scan driver 610 may be provided on the left side of the display area DAA, and the emission driver 620 may be provided on the right side of the display area DAA. However, the embodiments of the present specification are not limited thereto, and the scan driver 610 and the emission driver 620 may be provided on both the first side and the second side of the display area DAA.

[0077] The first pad portion PDA1 may include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 through a conductive adhesive member. The first pad portion PDA1 may be disposed on a third side of the display area DAA. For example, the first pad portion PDA1 may be disposed on one side of the display area DAA in the second direction DR2.

[0078] The first pad portion PDA1 may be disposed outside the data driver 700 in the second direction DR2. That is, the first pad portion PDA1 may be disposed closer to the edge of the display panel 100 than the data driver 700.

[0079] The second pad portion PDA2 may include a plurality of second pads PD2 corresponding to inspection pads for testing whether the display panel 100 is operating normally. The plurality of second pads PD2 may be connected to a jig or probe during an inspection process, or may be connected to the circuit board 300 for inspection. The circuit board 300 for inspection may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0080] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to the plurality of data lines DL. For example, the first distribution circuit 710 can distribute the data voltage applied through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or greater) data lines DL, thereby reducing the number of first pads PD1. The first distribution circuit 710 can be disposed on a third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed on one side of the display area DAA in the second direction DR2. In other words, the first distribution circuit 710 can be disposed on the lower side of the display area DAA.

[0081] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the emission driver 620, and the data lines DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each pixel in the display area DAA. The second distribution circuit 720 can be disposed on a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed on the other side of the display area DAA in the second direction DR2. In other words, the second distribution circuit 720 can be disposed on the upper side of the display area DAA.

[0082] Figure 5 and Figure 6 It shows Figure 4 Layout diagram of an embodiment of the display area DAA.

[0083] Reference Figure 5 and Figure 6 Each of the plurality of unit pixels UPX includes a first emission area EA1 serving as an emission area for a first pixel PX1, a second emission area EA2 serving as an emission area for a second pixel PX2, and a third emission area EA3 serving as an emission area for a third pixel PX3. In other words, the unit pixel UPX may include a unit emission area UEA, and the unit emission area UEA includes the first emission area EA1, the second emission area EA2, and the third emission area EA3 described above.

[0084] Reference Figure 5 and Figure 6 , each of the plurality of pixels includes a first emission area EA1 as an emission area of ​​a first pixel PX1, a second emission area EA2 as an emission area of ​​a second pixel PX2, and a third emission area EA3 as an emission area of ​​a third pixel PX3.

[0085] Each of the first, second, and third emission regions EA1, EA2, and EA3 may have a polygonal shape, a circular shape, an elliptical shape, or an atypical shape in a plan view.

[0086] The maximum length of the third emission area EA3 in the first direction DR1 may be less than the maximum length of the second emission area EA2 in the first direction DR1 and the maximum length of the first emission area EA1 in the first direction DR1. The maximum length of the second emission area EA2 in the first direction DR1 and the maximum length of the first emission area EA1 in the first direction DR1 may be substantially the same.

[0087] The maximum length of the third emission area EA3 in the second direction DR2 may be greater than the maximum length of the second emission area EA2 in the second direction DR2 and the maximum length of the first emission area EA1 in the second direction DR2. The maximum length of the first emission area EA1 in the second direction DR2 may be greater than the maximum length of the second emission area EA2 in the second direction DR2.

[0088] The first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a shape as shown in a plan view. Figure 5 and Figure 6 The first, second, and third emission areas EA1, EA2, and EA3 may have polygonal, circular, elliptical, or atypical shapes other than hexagonal shapes in a plan view.

[0089] like Figure 5 As shown in FIG, in each of the plurality of pixels, the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the second direction DR2. In addition, the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the first direction DR1. In addition, the second emission area EA2 and the third emission area EA3 may be adjacent to each other in the first direction DR1. The area of ​​the first emission area EA1, the area of ​​the second emission area EA2, and the area of ​​the third emission area EA3 may be different.

[0090] Alternatively, if Figure 6 As shown in , the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the first direction DR1, but the second emission area EA2 and the third emission area EA3 may be adjacent to each other in the first oblique direction DD1, and the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the second oblique direction DD2. The first oblique direction DD1 may be a direction between the first direction DR1 and the second direction DR2 and may refer to a direction inclined 45 degrees relative to the first direction DR1 and the second direction DR2, and the second oblique direction DD2 may be a direction perpendicular to the first oblique direction DD1.

[0091] The first emission area EA1 may emit light of a first color, the second emission area EA2 may emit light of a second color, and the third emission area EA3 may emit light of a third color. Here, the first color light may be light in a blue wavelength band, the second color light may be light in a green wavelength band, and the third color light may be light in a red wavelength band. For example, the blue wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 370 nm to approximately 460 nm, the green wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 480 nm to approximately 560 nm, and the red wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 600 nm to approximately 750 nm.

[0092] exist Figure 5 and Figure 6 , each of the plurality of pixels includes three emission areas EA1, EA2, and EA3, but the embodiments of the present specification are not limited thereto. That is, each of the plurality of pixels may include four emission areas.

[0093] Furthermore, the layout of the emission areas of the plurality of pixels is not limited to Figure 5 and Figure 6 For example, the emission regions of the plurality of pixels may be arranged in a stripe structure in which the emission regions are arranged in a first direction DR1, a PenTile structure in which the emission regions are arranged in a diamond shape, or a PenTile structure in which the emission regions are arranged in a diamond shape. ® Structure or Figure 6 The hexagonal structure shown in FIG is arranged in which emission areas having a hexagonal shape in plan view are arranged side by side.

[0094] Figure 7 It is shown along Figure 5 FIG. 1 is a cross-sectional view of an example of the display panel 100 taken along line I1 - I1 ′.

[0095] Reference Figure 7 The display panel 100 includes a semiconductor backplane SBP, a light emitting element backplane EBP, a display element layer EML, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL and a polarizing plate POL.

[0096] The semiconductor backplane SBP may include a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating layers covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR. Figure 3 The first transistor T1 to the sixth transistor T6 are described.

[0097] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with first-type impurities. A plurality of well regions WA may be provided on the top surface of the semiconductor substrate SSUB. The plurality of well regions WA may be regions doped with second-type impurities. The second-type impurities may be different from the aforementioned first-type impurities. For example, when the first-type impurities are p-type impurities, the second-type impurities may be n-type impurities. Alternatively, when the first-type impurities are n-type impurities, the second-type impurities may be p-type impurities.

[0098] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0099] The lower insulating layer BINS may be disposed between the gate electrode GE and the well area WA. The side insulating layer SINS may be disposed on a side surface of the gate electrode GE. The side insulating layer SINS may be disposed on the lower insulating layer BINS.

[0100] Each of the source region SA and the drain region DA may be a region doped with first-type impurities. The gate electrode GE of the pixel transistor PTR may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be provided on one side of the gate electrode GE, and the drain region DA may be provided on the other side of the gate electrode GE.

[0101] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having an impurity concentration lower than that of the source region SA due to the lower insulating layer BINS. The second low-concentration impurity region LDD2 may be a region having an impurity concentration lower than that of the drain region DA due to the lower insulating layer BINS. The distance between the source region SA and the drain region DA may be increased due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH of each of the pixel transistors PTR may be increased, thereby preventing punch-through and hot carrier phenomena that may be caused by a short channel.

[0102] The first semiconductor insulating layer SINS1 may be provided on the semiconductor substrate SSUB. The first semiconductor insulating layer SINS1 may be made of silicon carbonitride (SiCN) or silicon oxide (SiO x )-based inorganic layer is formed, but the embodiments of this specification are not limited thereto.

[0103] The second semiconductor insulating layer SINS2 may be provided on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but the embodiments of this specification are not limited thereto.

[0104] A plurality of contact terminals CTE may be provided on the second semiconductor insulating layer SINS2. Each of the plurality of contact terminals CTE may be connected to any one of the gate electrode GE, source area SA, and drain area DA of each of the pixel transistors PTR via a hole penetrating the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The plurality of contact terminals CTE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of these.

[0105] The third semiconductor insulating layer SINS3 may be provided on the side surface of each of the plurality of contact terminals CTE. The top surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor insulating layer SINS3. The third semiconductor insulating layer SINS3 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but the embodiments of this specification are not limited thereto.

[0106] The semiconductor substrate SSUB can be replaced with a glass substrate or a polymer resin substrate such as polyimide. In this case, the thin film transistor can be provided on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that does not bend, and the polymer resin substrate can be a flexible substrate that can be bent or folded.

[0107] The light emitting element back plate EBP includes a plurality of conductive layers ML1 to ML8 , a plurality of vias VA1 to VA9 , and a plurality of insulating layers INS1 to INS9 disposed between the first to eighth conductive layers ML1 to ML8 .

[0108] The first conductive layer ML1 to the eighth conductive layer ML8 are used to connect a plurality of contact terminals CTE exposed from the semiconductor backplane SBP, thereby realizing Figure 3 . For example, the first to sixth transistors T1 to T6 are formed only on the semiconductor backplane SBP, and the first to sixth transistors T1 to T6 are connected to the first and second capacitors CP1 and CP2 via the first to eighth conductive layers ML1 to ML8. Furthermore, the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE are also connected via the first to eighth conductive layers ML1 to ML8.

[0109] The first insulating layer INS1 may be disposed on the semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first insulating layer INS1 to connect to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first conductive layers ML1 may be disposed on the first insulating layer INS1 and may be connected to the first vias VA1.

[0110] The second insulating layer INS2 may be disposed on the first insulating layer INS1 and the first conductive layer ML1. Each of the second via holes VA2 may penetrate the second insulating layer INS2 and be connected to the exposed first conductive layer ML1. Each of the second conductive layers ML2 may be disposed on the second insulating layer INS2 and may be connected to the second via holes VA2.

[0111] The third insulating layer INS3 may be disposed on the second insulating layer INS2 and the second conductive layer ML2. Each of the third via holes VA3 may penetrate the third insulating layer INS3 and be connected to the exposed second conductive layer ML2. Each of the third conductive layers ML3 may be disposed on the third insulating layer INS3 and may be connected to the third via holes VA3.

[0112] The fourth insulating layer INS4 may be disposed on the third insulating layer INS3 and the third conductive layer ML3. Each of the fourth via holes VA4 may penetrate the fourth insulating layer INS4 and be connected to the exposed third conductive layer ML3. Each of the fourth conductive layers ML4 may be disposed on the fourth insulating layer INS4 and may be connected to the fourth via holes VA4.

[0113] The fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 and the fourth conductive layer ML4. Each of the fifth via holes VA5 may penetrate the fifth insulating layer INS5 and be connected to the exposed fourth conductive layer ML4. Each of the fifth conductive layers ML5 may be disposed on the fifth insulating layer INS5 and may be connected to the fifth via holes VA5.

[0114] The sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 and the fifth conductive layer ML5. Each of the sixth via holes VA6 may penetrate the sixth insulating layer INS6 and be connected to the exposed fifth conductive layer ML5. Each of the sixth conductive layers ML6 may be disposed on the sixth insulating layer INS6 and may be connected to the sixth via hole VA6.

[0115] The seventh insulating layer INS7 may be disposed on the sixth insulating layer INS6 and the sixth conductive layer ML6. Each of the seventh via holes VA7 may penetrate the seventh insulating layer INS7 and be connected to the exposed sixth conductive layer ML6. Each of the seventh conductive layers ML7 may be disposed on the seventh insulating layer INS7 and be connected to the seventh via hole VA7.

[0116] The eighth insulating layer INS8 may be disposed on the seventh insulating layer INS7 and the seventh conductive layer ML7. Each of the eighth via holes VA8 may penetrate the eighth insulating layer INS8 and be connected to the exposed seventh conductive layer ML7. Each of the eighth conductive layers ML8 may be disposed on the eighth insulating layer INS8 and be connected to the eighth via hole VA8.

[0117] The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may be formed of substantially the same material. The first conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The first to eighth vias VA1 to VA8 may be made of substantially the same material. The first to eighth insulating layers INS1 to INS8 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but the embodiments of this specification are not limited thereto.

[0118] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be respectively greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be substantially the same. For example, the thickness of the first conductive layer ML1 may be approximately 1360Å; the thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be approximately 1440Å; and the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 may be approximately 1150Å.

[0119] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 may be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be approximately 9000 Å. The thickness of each of the seventh via VA7 and the eighth via VA8 may be approximately 6000 Å.

[0120] The ninth insulating layer INS9 may be disposed on the eighth insulating layer INS8 and the eighth conductive layer ML8. The ninth insulating layer INS9 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but the embodiments of this specification are not limited thereto.

[0121] Each of the ninth vias VA9 may penetrate the ninth insulating layer INS9 and connect to the exposed eighth conductive layer ML8. The ninth via VA9 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. The thickness of the ninth via VA9 may be approximately 16,500 Å.

[0122] The display element layer EML may be disposed on the light emitting element backplane EBP. The display element layer EML may include a reflective electrode layer RL, tenth and eleventh insulating layers INS10 and INS11, tenth via holes VA10, light emitting elements LE each including a first electrode AND, a light emitting stack ES, and a second electrode CAT, a pixel defining layer PDL, and a plurality of trenches TRC.

[0123] The reflective electrode layer RL may be disposed on the ninth insulating layer INS9. The reflective electrode layer RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, the reflective electrode layer RL may include: Figure 7 , the first reflective electrode RL1 , the second reflective electrode RL2 , the third reflective electrode RL3 and the fourth reflective electrode RL4 shown in FIG.

[0124] Each of the first reflective electrodes RL1 may be disposed on the ninth insulating layer INS9 and may be connected to the ninth via hole VA9. The first reflective electrode RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of these. For example, the first reflective electrode RL1 may include titanium nitride (TiN).

[0125] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of these. For example, the second reflective electrode RL2 may include aluminum (Al).

[0126] Each of the third reflective electrodes RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of these. For example, the third reflective electrode RL3 may include titanium nitride (TiN).

[0127] The fourth reflective electrode RL4 may be disposed on each of the third reflective electrodes RL3. The fourth reflective electrode RL4 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0128] Since the second reflective electrode RL2 is an electrode that substantially reflects light from the light emitting element LE, the thickness of the second reflective electrode RL2 may be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 may be approximately 100 Å, and the thickness of the second reflective electrode RL2 may be 850 Å.

[0129] The tenth insulating layer INS10 may be disposed on the ninth insulating layer INS9. The tenth insulating layer INS10 may be disposed between the reflective electrode layers RL adjacent to each other in the horizontal direction. The tenth insulating layer INS10 may be disposed on the reflective electrode layer RL in the third pixel PX3. The tenth insulating layer INS10 may be made of silicon oxide (SiO x)-based inorganic layer is formed, but the embodiments of this specification are not limited thereto.

[0130] The eleventh insulating layer INS11 may be disposed on the tenth insulating layer INS10 and the reflective electrode layer RL. The eleventh insulating layer INS11 may be made of silicon oxide (SiO x The tenth insulating layer INS10 and the eleventh insulating layer INS11 may be optical auxiliary layers through which light reflected by the reflective electrode layer RL among light emitted from the light emitting element LE passes.

[0131] In order to match the resonance distance of light emitted from the light emitting element LE in at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3, the tenth insulating layer INS10 and the eleventh insulating layer INS11 may not be disposed under the first electrode AND of the first pixel PX1. The first electrode AND of the first pixel PX1 may be disposed directly on the reflective electrode layer RL. The eleventh insulating layer INS11 may be disposed under the first electrode AND of the second pixel PX2. The tenth insulating layer INS10 and the eleventh insulating layer INS11 may be disposed under the first electrode AND of the third pixel PX3.

[0132] In summary, the distance between the first electrode AND and the reflective electrode layer RL may be different in the first pixel PX1, the second pixel PX2, and the third pixel PX3. In order to adjust the distance from the reflective electrode layer RL to the second electrode CAT according to the main wavelength of light emitted from each of the first pixel PX1, the second pixel PX2, and the third pixel PX3, the presence or absence of the tenth insulating layer INS10 and the eleventh insulating layer INS11 may be set in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. For example, Figure 7 ] It is shown that the distance between the first electrode AND and the reflective electrode layer RL in the third pixel PX3 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the second pixel PX2 and the distance between the first electrode AND and the reflective electrode layer RL in the first pixel PX1, and the distance between the first electrode AND and the reflective electrode layer RL in the second pixel PX2 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the first pixel PX1, but the description of the present disclosure is not limited thereto.

[0133] In addition, although the tenth insulating layer INS10 and the eleventh insulating layer INS11 are shown in the embodiment of the present specification, a twelfth insulating layer disposed under the first electrode AND of the first pixel PX1 may be added. In this case, the eleventh insulating layer INS11 and the twelfth insulating layer may be disposed under the first electrode AND of the second pixel PX2, and the tenth insulating layer INS10, the eleventh insulating layer INS11, and the twelfth insulating layer may be disposed under the first electrode AND of the third pixel PX3.

[0134] Each of the tenth via holes VA10 may penetrate the tenth insulating layer INS10 and / or the eleventh insulating layer INS11 in the second pixel PX2 and the third pixel PX3 and may be connected to the exposed reflective electrode layer RL. The tenth via hole VA10 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of these. The thickness of the tenth via hole VA10 in the second pixel PX2 may be smaller than the thickness of the tenth via hole VA10 in the third pixel PX3.

[0135] The first electrode AND of each light-emitting element LE may be disposed on the eleventh insulating layer INS11 and connected to the tenth via VA10. The first electrode AND of each light-emitting element LE may be connected to the drain region DA or the source region SA of the pixel transistor PTR through the tenth via VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth vias VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each light-emitting element LE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of these. For example, the first electrode AND of each light-emitting element LE may be titanium nitride (TiN).

[0136] The pixel defining layer PDL may be disposed on a portion of the first electrode AND of each light emitting element LE. The pixel defining layer PDL may cover the edge of the first electrode AND of each light emitting element LE. The pixel defining layer PDL may be used to separate the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0137] The first emission area EA1 may be defined as an area where the first electrode AND, the light emitting stack ES, and the second electrode CAT are sequentially stacked in the first pixel PX1 to emit light. The second emission area EA2 may be defined as an area where the first electrode AND, the light emitting stack ES, and the second electrode CAT are sequentially stacked in the second pixel PX2 to emit light. The third emission area EA3 may be defined as an area where the first electrode AND, the light emitting stack ES, and the second electrode CAT are sequentially stacked in the third pixel PX3 to emit light.

[0138] The pixel defining layer PDL may include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3. The first pixel defining layer PDL1 may be disposed on the edge of the first electrode AND of each of the light emitting elements LE, the second pixel defining layer PDL2 may be disposed on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 may be disposed on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be made of silicon oxide (SiO x ) is formed as a base inorganic layer, but the embodiments of the present specification are not limited thereto. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may each have a thickness of about 500 Å.

[0139] When the first pixel defining layer (PDL1), the second pixel defining layer (PDL2), and the third pixel defining layer (PDL3) are formed into one pixel defining layer, the height of the pixel defining layer increases, so that the first encapsulating inorganic layer (TFE1) may be cut due to step coverage. Step coverage refers to the ratio of the extent of the thin film coated on the inclined portion to the extent of the thin film coated on the flat portion. The lower the step coverage, the more likely the thin film will be cut at the inclined portion.

[0140] Therefore, to prevent the first encapsulating inorganic layer TFE1 from being cut due to step coverage, the first, second, and third pixel defining layers (PDL1, PDL2, and PDL3) may have a cross-sectional structure with stepped portions. For example, the width of the first pixel defining layer (PDL1) may be greater than the widths of the second and third pixel defining layers (PDL2, PDL3), and the width of the second pixel defining layer (PDL2, PDL3) may be greater than the width of the third pixel defining layer (PDL3). The width of the first pixel defining layer (PDL1) refers to the horizontal length of the first pixel defining layer (PDL1) defined in the first and second directions (DR1, DR2).

[0141] Each of the plurality of trenches TRC may penetrate the first, second, and third pixel defining layers PDL1, PDL2, and PDL3. In addition, each of the plurality of trenches TRC may penetrate the eleventh insulating layer INS11. The tenth insulating layer INS10 may be partially recessed at each of the plurality of trenches TRC.

[0142] At least one trench TRC may be provided between adjacent pixels PX1, PX2, and PX3. Figure 7 It is shown that two trenches TRC are provided between adjacent pixels PX1 , PX2 , and PX3 , but the embodiments of the present specification are not limited thereto.

[0143] The light emitting stack body ES may include a plurality of stacked layers. Figure 7 The light emitting stack ES is shown to have a three-series structure including the first stack layer IL1, the second stack layer IL2, and the third stack layer IL3, but the embodiments of the present specification are not limited thereto. For example, the light emitting stack ES may have a two-series structure including two intermediate layers.

[0144] In the triple-series structure, the light emitting stack ES may have a series structure including a plurality of stack layers IL1, IL2, and IL3 that emit different lights. For example, the light emitting stack ES may include a first stack layer IL1 that emits light of a first color, a second stack layer IL2 that emits light of a second color, and a third stack layer IL3 that emits light of a third color. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 may be stacked sequentially.

[0145] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a second color, and a second electron transport layer are sequentially stacked. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of a third color, and a third electron transport layer are sequentially stacked.

[0146] A first charge generation layer for supplying charges to the second stack layer IL2 and electrons to the first stack layer IL1 may be provided between the first stack layer IL1 and the second stack layer IL2. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first stack layer IL1 and a P-type charge generation layer for supplying holes to the second stack layer IL2. The N-type charge generation layer may include a metal material as a dopant.

[0147] A second charge generation layer for supplying charges to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be provided between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second stacked layer IL2 and a P-type charge generation layer for supplying holes to the third stacked layer IL3.

[0148] The first stacked layer IL1 can be arranged on the first electrode AND and the pixel defining layer PDL, and can be arranged on the bottom surface of each trench TRC. Due to the trench TRC, the first stacked layer IL1 can be separated between adjacent pixels PX1, PX2 and PX3. The second stacked layer IL2 can be arranged on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 can be separated between adjacent pixels PX1, PX2 and PX3. A cavity ESS or empty space can be provided between the first stacked layer IL1 and the second stacked layer IL2. The third stacked layer IL3 can be provided on the second stacked layer IL2. The third stacked layer IL3 is not cut off by the trench TRC and can be arranged to cover the second stacked layer IL2 in each of the trenches TRC. That is, in the three-series structure, each of the multiple trenches TRC can be a structure for cutting off the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent pixels PX1, PX2 and PX3, the first charge generation layer, and the second charge generation layer. Furthermore, in the two-tandem structure, each of the trenches TRC may be a structure for cutting off the charge generation layer and the lower intermediate layer provided between the lower intermediate layer and the upper intermediate layer.

[0149] In order to stably cut off the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent pixels PX1, PX2, and PX3, the height of each of the plurality of grooves TRC may be greater than the height of the pixel defining layer PDL. The height of each of the plurality of grooves TRC refers to the length of each of the plurality of grooves TRC in the third direction DR3. The height of the pixel defining layer PDL refers to the length of the pixel defining layer PDL in the third direction DR3. In order to cut off the first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 of the display element layer EML between adjacent pixels PX1, PX2, and PX3, another structure may be provided in place of the grooves TRC. For example, an inverted tapered partition wall may be provided on the pixel defining layer PDL in place of the grooves TRC.

[0150] The number of stacked layers IL1, IL2 and IL3 emitting different light is not limited to Figure 7. For example, the light-emitting stack ES may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first stacked layer IL1, and the other may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one intermediate layer and supplying charges to the other intermediate layer may be provided between the two intermediate layers.

[0151] also, Figure 7 It is shown that the first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 are all arranged in the first emission area EA1, the second emission area EA2, and the third emission area EA3, but the embodiments of the present specification are not limited thereto. For example, the first stacked layer IL1 may be arranged in the first emission area EA1, and may not be arranged in the second emission area EA2 and the third emission area EA3. In addition, the second stacked layer IL2 may be arranged in the second emission area EA2, and may not be arranged in the first emission area EA1 and the third emission area EA3. In addition, the third stacked layer IL3 may be arranged in the third emission area EA3, and may not be arranged in the first emission area EA1 and the second emission area EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0152] The second electrode CAT may be disposed on the third stacked layer IL3. The second electrode CAT may be disposed on the third stacked layer IL3 in each of the plurality of trenches TRC. The second electrode CAT may be formed of a light-transmitting transparent conductive material (TCO) such as ITO or IZO, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode CAT is formed of a semi-transmissive conductive material, the microcavity effect may improve the luminous efficiency of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0153] The encapsulation layer TFE may be disposed on the display element layer EML. The encapsulation layer TFE may include at least one encapsulation inorganic layer TFE1 and TFE2 to prevent oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1 and a second encapsulation inorganic layer TFE2.

[0154] The first encapsulation inorganic layer TFE1 may be provided on the second electrode CAT. The first encapsulation inorganic layer TFE1 may be formed of a material selected from silicon nitride (SiN x ), silicon oxynitride (SiON) and silicon oxide (SiO xThe first encapsulation inorganic layer TFE1 may be formed by a chemical vapor deposition (CVD) process.

[0155] The second encapsulating inorganic layer TFE2 may be provided on the first encapsulating inorganic layer TFE1. The second encapsulating inorganic layer TFE2 may be made of titanium oxide (TiO x ) or aluminum oxide (AlO x ), but the embodiments of the present specification are not limited thereto. The second encapsulating inorganic layer TFE2 may be formed by an atomic layer deposition (ALD) process. The thickness of the second encapsulating inorganic layer TFE2 may be less than that of the first encapsulating inorganic layer TFE1.

[0156] The organic layer APL may be a layer for increasing interface adhesion between the encapsulation layer TFE and the optical layer OPL. The organic layer APL may be an organic layer such as acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin.

[0157] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filler layer FIL. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the organic layer APL.

[0158] The first color filter CF1 may overlap the first emission area EA1 of the first pixel PX1. The first color filter CF1 may transmit light of the first color, that is, light in the blue wavelength band. The blue wavelength band may be approximately 370 nm to 460 nm. Therefore, the first color filter CF1 may transmit light of the first color among the light emitted from the first emission area EA1.

[0159] The second color filter CF2 may overlap the second emission area EA2 of the second pixel PX2. The second color filter CF2 may transmit light of the second color, i.e., light in the green wavelength band. The green wavelength band may be approximately 480 nm to 560 nm. Therefore, the second color filter CF2 may transmit light of the second color among the light emitted from the second emission area EA2.

[0160] The third color filter CF3 may overlap the third emission area EA3 of the third pixel PX3. The third color filter CF3 may transmit light of a third color, i.e., light in a red wavelength band. The red wavelength band may be approximately 600 nm to 750 nm. Therefore, the third color filter CF3 may transmit light of the third color among the light emitted from the third emission area EA3.

[0161] A plurality of lenses LNS may be provided on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the plurality of lenses LNS may be a structure for increasing the ratio of light guided to the front of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape that is convex in an upward direction.

[0162] A filling layer FIL may be provided on the plurality of lenses LNS. The filling layer FIL may have a predetermined refractive index such that light travels in the third direction DR3 at the interface between the filling layer FIL and the plurality of lenses LNS. Furthermore, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic layer such as an acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0163] The cover layer CVL can be disposed on the filler layer FIL. The cover layer CVL can be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it can be attached to the filler layer FIL. In this case, the filler layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can serve as an encapsulation substrate. When the cover layer CVL is a polymer resin, it can be applied directly to the filler layer FIL.

[0164] A polarizing plate (POL) may be disposed on one surface of the cover layer (CVL). The polarizing plate (POL) may be a structure used to prevent visibility degradation caused by external light reflection. The polarizing plate (POL) may include a linear polarizing plate and a phase retarder film. For example, the phase retarder film may be a λ / 4 plate (quarter-wave plate), but the embodiments of this specification are not limited thereto. However, if visibility degradation caused by external light reflection is sufficiently mitigated by the first, second, and third color filters (CF1, CF2, and CF3), the polarizing plate (POL) may be omitted.

[0165] Figure 8 is a layout diagram illustrating a portion of the display panel 100 according to one embodiment.

[0166] The display panel 100 may include Figure 8 The plurality of pixels PX1, PX2, and PX3 are shown in FIG. The plurality of pixels may include, for example, a first pixel PX1, a second pixel PX2, and a third pixel PX3 disposed adjacent to each other in a first direction DR1.

[0167] Each of the pixels PX1, PX2, and PX3 may include a pixel circuit PC and a light-emitting element LE. In this case, at least one light-emitting element LE may be overlapped with a driver circuit. Here, the driver circuit may be a circuit that provides various types of signals for driving the pixels PX1, PX2, and PX3 of the display panel 100. For example, the driver circuit may include the aforementioned scan driver 610, emission driver 620, data driver 700, first distribution circuit 710, second distribution circuit 720, timing control circuit 400, and power supply circuit 500.

[0168] At least one light emitting element LE may overlap with, for example, at least one of the scan driver 610 , the emission driver 620 , the data driver 700 , the first distribution circuit 710 , the second distribution circuit 720 , the timing control circuit 400 , and the power supply circuit 500 . Figure 8 An embodiment is shown in which some of the plurality of light emitting elements LE (eg, light emitting elements LE disposed at the edge of the display area DAA) overlap with the scan driver 610 , the emission driver 620 , the first distribution circuit 710 , and the second distribution circuit 720 .

[0169] Since at least one light emitting element LE is overlapped with the driving circuit in this manner, the area of ​​the display region DAA can be expanded. Figure 8 When the display area DAA is overlapped with the scan driver 610, the emission driver 620, the first distribution circuit 710 and the second distribution circuit 720 as shown in FIG, the display area DAA can be expanded to further include the scan driver 610, the emission driver 620, the first distribution circuit 710 and the second distribution circuit 720. In other words, although Figure 4 The display area DAA is defined as an area surrounded by the scan driver 610, the emission driver 620, the first distribution circuit 710 and the second distribution circuit 720, but Figure 8 The display area DAA may be defined as a wider area that further includes the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. Therefore, Figure 8 The display area DAA may have a Figure 4 Therefore, the net die of the wafer on which the display panel 100 is manufactured can be improved. For example, assuming that a 1.3-inch display panel is manufactured on a 12-inch wafer, when manufacturing a 1.3-inch display panel with Figure 4 When manufacturing a display panel with a structure of 74, the bare die of the wafer is 74, and when manufacturing a display panel with a structure of Figure 8 When manufacturing a display panel of the structure of the wafer, the bare die of the wafer can be 82. Therefore, when manufacturing a display panel of the structure of the wafer, the bare die of the wafer can be 82. Figure 8When the display panel 100 having a large display area DAA as shown in FIG, the manufacturing cost of the display device 10 can be reduced.

[0170] Figure 9 It is along Figure 8 A cross-sectional view taken along line III-III'.

[0171] like Figure 9 As shown in , the first electrode may include, for example, a first anode electrode AND1 of the first pixel PX1 and a second anode electrode AND2 of the second pixel PX2.

[0172] The first anode electrode AND1 of the first pixel PX1 can be connected to the pixel circuit PC1 of the first pixel PX1 (hereinafter referred to as the first pixel circuit PC1). For example, since the first pixel PX1 may include the first pixel circuit PC1 and a light-emitting element LE1 connected to the first pixel circuit PC1 (hereinafter referred to as the first light-emitting element LE1), the first anode electrode AND1 of the first light-emitting element LE1 can be connected to the pixel transistor PTR of the first pixel circuit PC1. For example, the first anode electrode AND1 can be connected to the drain region DA of the pixel transistor PTR via the reflective electrode layer RL, a plurality of vias VA1 to VA9, and a plurality of conductive layers ML1 to ML8. The first anode electrode AND1 of the first pixel PX1 and the reflective electrode layer RL of the first pixel PX1 may not overlap with the pixel transistor PTR of the first pixel PX1. Furthermore, since the seventh conductive layer ML7 can further extend in the first direction DR1 or the second direction DR2 to overlap with the first anode electrode AND1, the connection between the first anode electrode AND1 and the pixel transistor PTR can be facilitated even if the first anode electrode AND1 and the pixel transistor PTR do not overlap in the third direction DR3.

[0173] The second anode electrode AND2 of the second pixel PX2 may be connected to the pixel circuit PC2 of the second pixel PX2 (hereinafter, referred to as the second pixel circuit PC2). For example, since the second pixel PX2 may include the second pixel circuit PC2 and the light emitting element LE2 connected to the second pixel circuit PC2 (hereinafter, referred to as the second light emitting element LE2), the second anode electrode AND2 of the second light emitting element LE2 may be connected to the pixel transistor of the second pixel circuit PC2.

[0174] like Figure 8 and Figure 9As shown in FIG, the first light-emitting element LE1 of the first pixel PX1 may overlap with the scan driver 610. For example, the first emission area EA1 and the first anode electrode AND1 of the first light-emitting element LE1 may overlap with the scan transistor STR of the scan driver 610. The scan transistor STR may include a CMOS similar to the pixel transistor described above. For example, the scan transistor STR may include a gate electrode GE, a channel region CH, a source region SA, a drain region DA, a first low-concentration impurity region LDD1, a second low-concentration impurity region LDD2, a lower insulating layer BINS, and a side insulating layer SINS.

[0175] Meanwhile, the second light emitting element LE2 of the second pixel PX2 may not overlap with the driving circuit. Figure 9 As shown in , the second light emitting element LE2 of the second pixel PX2 may overlap with the pixel circuit PC of another pixel (eg, the first pixel circuit PC1 of the first pixel PX1). Figure 9 As shown in FIG, the second anode electrode AND2 of the second light emitting element LE2 may overlap the pixel transistor PTR provided in the first pixel circuit PC1.

[0176] Meanwhile, the third pixel PX3 may include a third pixel circuit PC3 and a third light emitting element LE3 connected thereto. The anode electrode of the third light emitting element LE3 (hereinafter referred to as the third anode electrode) may overlap with the driving circuit. For example, Figure 8 As shown in , the third emission region and the third anode electrode of the third light emitting element LE3 may overlap the second distribution circuit 720 (eg, the non-pixel transistor of the second distribution circuit 720 ) in the third direction DR3 .

[0177] Figure 10 is a layout diagram of a display panel 100 according to one embodiment.

[0178] The scan driver 610 may include a scan shift register 610 a , a scan level shifter 610 b , and a scan buffer 610 c .

[0179] The scan shift register 610 a may receive a scan shift clock and a scan start pulse from the timing control circuit 400 , and sequentially generate a plurality of scan signals while shifting the scan start pulse for each cycle of the scan shift clock.

[0180] The scan level shifter 610 b may convert levels of a plurality of scan signals from the scan shift register 610 a and provide them to the scan buffer 610 c .

[0181] The scan buffer 610 c may buffer and output a plurality of scan signals from the scan level shifter 610 b .

[0182] The transmit driver 620 may include a transmit shift register 620a, a transmit level shifter 620b, and a transmit buffer 620c.

[0183] The transmit shift register 620 a may receive a transmit shift clock and a transmit start pulse from the timing control circuit 400 , and sequentially generate a plurality of transmit control signals while shifting the transmit start pulse for each cycle of the transmit shift clock.

[0184] The transmit level shifter 620b may convert the levels of a plurality of transmit control signals from the transmit shift register 620a and provide them to the transmit buffer 620c.

[0185] The transmit buffer 620c may buffer and output a plurality of transmit control signals from the transmit level shifter 620b.

[0186] The gray voltage circuit 501 can divide the gamma reference voltage to generate a plurality of gray voltages and provide them to the data driver 700. For example, the gray voltage circuit 501 can generate a plurality of red gray voltages for red image data, a plurality of green gray voltages for green image data, and a plurality of blue gray voltages for blue image data.

[0187] The interface circuit 900 may convert serial image data from the outside into parallel image data and provide them to the data driver 700 .

[0188] The data driver 700 may include a data shift register 700a, a data sampling latch 700b, a data holding latch 700c, a data level shifter 700d, a digital-to-analog converter 700e, a data buffer 700f, and a demultiplexer 700g. The demultiplexer 700g may include the aforementioned first distribution circuit 710. In other words, the data driver 700 may further include the first distribution circuit 710.

[0189] The data shift register 700 a may receive a source shift clock and a source start pulse from the timing control circuit 400 , and sequentially generate a plurality of sampling signals while shifting the source start pulse for each cycle of the source shift clock.

[0190] The data sampling latch 700 b may sequentially store a plurality of image data signals in response to a plurality of sampling signals sequentially supplied from the data shift register 700 a .

[0191] In response to the source output control signal, the data holding latch 700c can simultaneously receive and store multiple image data signals from the data sampling latch 700b and simultaneously output multiple sampled image data signals stored in the previous period. The multiple image data signals output from the data holding latch 700c can be simultaneously supplied to the data level shifter 700d.

[0192] The data level shifter 700d may convert the levels of the image data signals from the data holding latch 700c and provide them to the digital-to-analog converter 700e.

[0193] The digital-to-analog converter 700e can generate analog image data signals corresponding to the respective bit values ​​of the plurality of image data signals supplied from the data level shifter 700d. For example, the digital-to-analog converter 700e can select a grayscale voltage corresponding to the bit value of the image data signal from the data holding latch 700c from the grayscale generator and can output the selected grayscale voltage as the analog image data signal.

[0194] The data buffer 700f may receive the analog image data signal from the digital-to-analog converter 700e, amplify the received analog image data signal, and output them. The analog image data signal from the data buffer 700f may be provided to the demultiplexer 700g.

[0195] The timing control circuit 400 may include a first timing controller 400 a and a timing buffer 400 b .

[0196] The first timing controller 400 a may output the above-mentioned source shift clock, source start pulse, source output control signal, scan shift clock, scan start pulse, emission shift clock, and emission start pulse.

[0197] The timing buffer 400 b may buffer the signal from the first timing controller 400 a and provide the buffered signal to the above-mentioned scan driver 610 , emission driver 620 , and data driver 700 .

[0198] The second timing controller 502 may control the input timing of the gray voltage supplied from the gray voltage circuit 501 to the digital-to-analog converter 700 e .

[0199] The sensor circuit 888 may include a circuit for driving the touch sensor of the display panel 100 .

[0200] The regulator 503 may generate various types of power required to drive the display panel 100. The regulator 503 may be included in the power supply circuit 500.

[0201] The light-emitting element LE may be overlapped with the driving circuit of the display device 10. For example, the driving circuit of the display device 10 may include the aforementioned scan shift register 610a, the scan level shifter 610b, the scan buffer 610c, the emission shift register 620a, the emission level shifter 620b, the emission buffer 620c, the grayscale voltage circuit 501, the interface circuit 900, the data shift register 700a, the data sampling latch 700b, the data holding latch 700c, the data level shifter 700d, the digital-to-analog converter 700e, the data buffer 700f, the demultiplexer 700g, the first timing controller 400a, the timing buffer 400b, the second timing controller 502, the sensor circuit 888, the regulator 503, and the like, and at least one light-emitting element LE may be overlapped with at least one of the components of the aforementioned driving circuit.

[0202] Figure 10 1 shows an example in which some of the plurality of light emitting elements LE are overlapped with the scan buffer 610c, the transmit buffer 620c, the demultiplexer 700g and the data buffer 700f. Figure 10 As shown in FIG, the first electrode of each of some of the plurality of light emitting elements LE may overlap with the non-pixel transistors of the scan buffer 610 c, the non-pixel transistors of the emission buffer 620 c, the non-pixel transistors of the demultiplexer 700 g, and the non-pixel transistors of the data buffer 700 f in the third direction DR3. Therefore, the display area DAA may be expanded.

[0203] The light-emitting elements LE may have different sizes. For example, the first electrode (or emission region) of a red light-emitting element LE providing red light, the first electrode (or emission region) of a green light-emitting element LE providing green light, and the first electrode (or emission region) of a blue light-emitting element LE providing blue light may have different sizes.

[0204] Figure 11 is a layout diagram of a display panel 100 according to one embodiment.

[0205] Figure 11 The display panel 100 and the above Figure 10 The display panels 100 of FIG. 1 and FIG. 2 are different in terms of the area of ​​the display area DAA, and the following description will mainly focus on this difference.

[0206] Figure 11 An example is shown in which some of the plurality of light emitting elements LE are overlapped with the data shift register 700a, the data sampling latch 700b, the data holding latch 700c, the data level shifter 700d, the digital-to-analog converter 700e, the data buffer 700f, the demultiplexer 700g, and the interface circuit 900. For example, Figure 11As shown in FIG, the first electrode of each of some of the plurality of light emitting elements LE may overlap in the third direction DR3 with the non-pixel transistors of the data shift register 700a, the non-pixel transistors of the data sampling latch 700b, the non-pixel transistors of the data holding latch 700c, the non-pixel transistors of the data level shifter 700d, the non-pixel transistors of the digital-to-analog converter 700e, the non-pixel transistors of the data buffer 700f, the non-pixel transistors of the demultiplexer 700g, and the non-pixel transistors of the interface circuit 900. Therefore, the display area DAA may be expanded.

[0207] Figure 12 is a layout diagram of a display panel 100 according to one embodiment.

[0208] Figure 12 The display panel 100 and the above Figure 10 The display panels 100 of FIG. 1 and FIG. 2 are different in terms of the area of ​​the display area DAA, and the following description will mainly focus on this difference.

[0209] Figure 12 An example is shown in which some of the plurality of light emitting elements LE are overlapped with the scan shift register 610a, the scan level shifter 610b, the scan buffer 610c, the emission shift register 620a, the emission level shifter 620b, the emission buffer 620c, the grayscale voltage circuit 501, the interface circuit 900, the data shift register 700a, the data sampling latch 700b, the data holding latch 700c, the data level shifter 700d, the digital-to-analog converter 700e, the data buffer 700f, the demultiplexer 700g, the first timing controller 400a, the timing buffer 400b, the second timing controller 502, the sensor circuit 888, and the regulator 503. For example, as Figure 12As shown in , the first electrode of each of some of the multiple light emitting elements LE can be connected in the third direction DR3 to the non-pixel transistor of the scan shift register 610a, the non-pixel transistor of the scan level shifter 610b, the non-pixel transistor of the scan buffer 610c, the non-pixel transistor of the emission shift register 620a, the non-pixel transistor of the emission level shifter 620b, the non-pixel transistor of the emission buffer 620c, the non-pixel transistor of the grayscale voltage circuit 501, the non-pixel transistor of the interface circuit 900, and the non-pixel transistor of the data shift register 700a. The transistors, the non-pixel transistors of the data sampling latch 700b, the non-pixel transistors of the data holding latch 700c, the non-pixel transistors of the data level shifter 700d, the non-pixel transistors of the digital-to-analog converter 700e, the non-pixel transistors of the data buffer 700f, the non-pixel transistors of the demultiplexer 700g, the non-pixel transistors of the first timing controller 400a, the non-pixel transistors of the timing buffer 400b, the non-pixel transistors of the second timing controller 502, the non-pixel transistors of the sensor circuit 888, and the non-pixel transistors of the regulator 503 are stacked. Therefore, the display area DAA can be expanded.

[0210] Figure 13 is a diagram illustrating a portion of a display area DAA of a display panel 100 according to one embodiment.

[0211] like Figure 13 As shown in FIG, a plurality of pixel circuit groups PCG1 and PCG2 and a plurality of driving circuits DRC1 and DRC2 may be alternately arranged along a second direction DR2 in a display area DAA of the display panel 100. For example, a first driving circuit DRC1 may be arranged between the first pixel circuit group PCG1 and the second pixel circuit group PCG2, and the second pixel circuit group PCG2 may be arranged between the first driving circuit DRC1 and the second driving circuit DRC2.

[0212] Each of the pixel circuit groups PCG1 and PCG2 may include a plurality of pixel circuits PC.

[0213] For example, the first pixel circuit group PCG1 may include a plurality of pixel circuits PC connected to a plurality of light-emitting elements LE stacked with the first pixel circuit group PCG1 (e.g., a plurality of pixel circuits PC belonging to the first pixel circuit group PCG1) and a plurality of light-emitting elements LE stacked with the first drive circuit DRC1. In other words, the plurality of pixel circuits PC for driving the plurality of light-emitting elements LE on the first pixel circuit group PCG1 and the plurality of light-emitting elements LE on the first drive circuit DRC1 can be integrated into the first pixel circuit group PCG1 at a high density.

[0214] The second pixel circuit group PCG2 may include a plurality of pixel circuits PC connected to a plurality of light-emitting elements LE overlapping the second pixel circuit group PCG2 (e.g., a plurality of pixel circuits PC belonging to the second pixel circuit group PCG2) and a plurality of light-emitting elements LE overlapping the second drive circuit DRC2. In other words, the plurality of pixel circuits PC for driving the plurality of light-emitting elements LE on the second pixel circuit group PCG2 and the plurality of light-emitting elements LE on the second drive circuit DRC2 may be integrated at a high density in the second pixel circuit group PCG2.

[0215] The first drive circuit DRC1 may include, for example Figure 10 any one of the scan shift register 610a, scan level shifter 610b, scan buffer 610c, emission shift register 620a, emission level shifter 620b, emission buffer 620c, grayscale voltage circuit 501, interface circuit 900, data shift register 700a, data sampling latch 700b, data holding latch 700c, data level shifter 700d, digital-to-analog converter 700e, data buffer 700f, demultiplexer 700g, first timing controller 400a, timing buffer 400b, second timing controller 502, sensor circuit 888 and regulator 503.

[0216] The second drive circuit DRC2 may include, for example Figure 10 88 and the regulator 503. For example, the first driving circuit DRC1 and the second driving circuit DRC2 may be driving circuits including different components.

[0217] according to Figure 13 , multiple pixel circuit groups PCG1 and PCG2 and multiple drive circuits DRC1 and DRC2 are alternately arranged in the second direction DR2. Therefore, although the display area DAA is expanded, the distance between the light-emitting elements LE overlapped with the drive circuits DRC1 and DRC2 and the pixel circuits PC for driving those light-emitting elements LE can be prevented from increasing. Therefore, the electrical connection between the light-emitting elements LE on the drive circuits DRC1 and DRC2 and the pixel circuits PC for driving the light-emitting elements LE can be facilitated.

[0218] Figure 14 is a diagram illustrating a portion of a display area DAA of a display panel 100 according to one embodiment.

[0219] like Figure 14 As shown in FIG, a plurality of driving circuits DRC1 and DRC2 and a plurality of pixel circuit groups PCG1 and PCG2 may be alternately arranged along a first direction DR1 in a display area DAA of the display panel 100. For example, the first pixel circuit group PCG1 may be arranged between the first driving circuit DRC1 and the second driving circuit DRC2, and the second driving circuit DRC2 may be arranged between the first pixel circuit group PCG1 and the second pixel circuit group PCG2.

[0220] The first pixel circuit group PCG1 may include a plurality of pixel circuits PC connected to a plurality of light-emitting elements LE stacked with the first pixel circuit group PCG1 (e.g., a plurality of pixel circuits PC belonging to the first pixel circuit group PCG1) and a plurality of light-emitting elements LE stacked with the first drive circuit DRC1. In other words, the plurality of pixel circuits PC for driving the plurality of light-emitting elements LE on the first pixel circuit group PCG1 and the plurality of light-emitting elements LE on the first drive circuit DRC1 may be integrated at a high density in the first pixel circuit group PCG1.

[0221] The second pixel circuit group PCG2 may include a plurality of pixel circuits PC connected to a plurality of light-emitting elements LE overlapping the second pixel circuit group PCG2 (e.g., a plurality of pixel circuits PC belonging to the second pixel circuit group PCG2) and a plurality of light-emitting elements LE overlapping the second drive circuit DRC2. In other words, the plurality of pixel circuits PC for driving the plurality of light-emitting elements LE on the second pixel circuit group PCG2 and the plurality of light-emitting elements LE on the second drive circuit DRC2 may be integrated at a high density in the second pixel circuit group PCG2.

[0222] according to Figure 14 , multiple drive circuits DRC1 and DRC2 and multiple pixel circuit groups PCG1 and PCG2 are alternately arranged in the first direction DR1. Therefore, even if the display area DAA is expanded, the distance between the light-emitting elements LE overlapped with the drive circuits DRC1 and DRC2 and the pixel circuits PC for driving those light-emitting elements LE can be prevented from increasing. As a result, the electrical connection between the light-emitting elements LE on the drive circuits DRC1 and DRC2 and the pixel circuits PC for driving the light-emitting elements LE can be facilitated.

[0223] Figure 15 is a diagram illustrating a portion of a display area DAA of a display panel 100 according to one embodiment.

[0224] like Figure 15As shown in , the plurality of pixel circuit groups PCG1 and PCG2 may be surrounded by the plurality of drive circuits DRC1 and DRC2. For example, the first pixel circuit group PCG1 may be surrounded by the first drive circuit DRC1, and the second pixel circuit group PCG2 may be surrounded by the second drive circuit DRC2.

[0225] The first pixel circuit group PCG1 may include a plurality of pixel circuits PC connected to a plurality of light-emitting elements LE stacked with the first pixel circuit group PCG1 (e.g., a plurality of pixel circuits PC belonging to the first pixel circuit group PCG1) and a plurality of light-emitting elements LE stacked with the first drive circuit DRC1. In other words, the plurality of pixel circuits PC for driving the plurality of light-emitting elements LE on the first pixel circuit group PCG1 and the plurality of light-emitting elements LE on the first drive circuit DRC1 may be integrated at a high density in the first pixel circuit group PCG1.

[0226] The second pixel circuit group PCG2 may include a plurality of pixel circuits PC connected to a plurality of light-emitting elements LE overlapping the second pixel circuit group PCG2 (e.g., a plurality of pixel circuits PC belonging to the second pixel circuit group PCG2) and a plurality of light-emitting elements LE overlapping the second drive circuit DRC2. In other words, the plurality of pixel circuits PC for driving the plurality of light-emitting elements LE on the second pixel circuit group PCG2 and the plurality of light-emitting elements LE on the second drive circuit DRC2 may be integrated at a high density in the second pixel circuit group PCG2.

[0227] according to Figure 15 , multiple drive circuits DRC1 and DRC2 and multiple pixel circuit groups PCG1 and PCG2 are alternately arranged in the second direction DR2. Therefore, even if the display area DAA is expanded, the distance between the light-emitting elements LE overlapped with the drive circuits DRC1 and DRC2 and the pixel circuits PC for driving those light-emitting elements LE can be prevented from increasing. As a result, the electrical connection between the light-emitting elements LE on the drive circuits DRC1 and DRC2 and the pixel circuits PC for driving the light-emitting elements LE can be facilitated.

[0228] Figure 16 is a perspective view showing a head-mounted display according to one embodiment. Figure 17 It shows Figure 16 An exploded perspective view of an example of a head-mounted display.

[0229] Reference Figure 16 and Figure 17According to one embodiment, a head-mounted display 1000 includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted band 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520 and a control circuit board 1600.

[0230] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Figures 1 to 15 The display devices 10 described are substantially the same, and thus descriptions of the first display device 10_1 and the second display device 10_2 will be omitted.

[0231] The first optical member 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0232] The middle frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0233] The control circuit board 1600 may be disposed between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 via a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 via the connector.

[0234] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0235] The display device housing 1100 is used to accommodate the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 is provided to cover one open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 at which the user's left eye is disposed and a second eyepiece 1220 at which the user's right eye is disposed. Figure 16 and Figure 17 The first eyepiece 1210 and the second eyepiece 1220 are shown as being separately provided, but the embodiments of the present specification are not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one eyepiece.

[0236] The first eyepiece 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Therefore, a user may view an image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and may view an image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0237] The head-mounted strap 1300 is used to fix the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are respectively placed on the user's left eye and right eye. When the housing cover 1200 is implemented to be lightweight and small, the head-mounted display 1000 can be provided with a Figure 18 The eyeglass frame shown in FIG. 1 is not a headband 1300 .

[0238] The head-mounted display 1000 may also include a battery for supplying power, an external memory slot for accommodating an external memory, an external connection port for receiving an image source, and a wireless communication module. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0239] Figure 18 1 is a perspective view showing a head mounted display 1000_1 according to one embodiment.

[0240] Reference Figure 18The head-mounted display 1000_1 according to one embodiment may be a glasses-type display device in which the housing cover 1200_1 is implemented in a lightweight and compact manner. The head-mounted display 1000_1 according to one embodiment may include a display device 10_3, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path changing member 1070, and the housing cover 1200_1.

[0241] The housing cover 1200_1 may include a display device 10_3, an optical member 1060, and an optical path changing member 1070. The image displayed on the display device 10_3 may be magnified by the optical member 1060 and provided to the user's right eye through the right-eye lens 1020 after its optical path is changed by the optical path changing member 1070. As a result, the user can view an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image viewed through the right-eye lens 1020 are combined through the right eye.

[0242] Figure 18 While the housing cover 1200_1 is shown as being disposed at the right end of the support frame 1030, embodiments of the present specification are not limited thereto. For example, the housing cover 1200_1 may be disposed at the left end of the support frame 1030, in which case the image of the display device 10_3 can be provided to the user's left eye. Alternatively, the housing cover 1200_1 may be disposed at both the left and right ends of the support frame 1030, in which case the user can view the image displayed on the display device 10_3 with both the left and right eyes.

[0243] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the preferred embodiments without departing substantially from the principles of the present invention. Therefore, the preferred embodiments of the disclosed invention are intended to be general and descriptive only and not for the purpose of limitation.

Claims

1. A display device, comprising: substrate; a pixel circuit on the substrate; a light-emitting element connected to the pixel circuit; as well as a driving circuit connected to the pixel circuit, Wherein, the light emitting element and the driving circuit are overlapped.

2. The display device according to claim 1, wherein The light emitting element comprises: a first electrode on the substrate; a light-emitting layer on the first electrode; and The second electrode is on the light-emitting layer.

3. The display device according to claim 2, wherein: The first electrode overlaps the driving circuit. 4 . The display device according to claim 2 , further comprising a pixel defining layer disposed on the first electrode and defining an emission area of ​​the light emitting element.

5. The display device according to claim 4, wherein The emission region overlaps the driving circuit. The display device according to claim 1 , wherein: The light emitting element is overlapped with a non-pixel transistor of the driving circuit.

7. The display device according to claim 1, wherein The pixel circuits and the driving circuits are alternately arranged.

8. The display device according to claim 1, wherein The pixel circuit is surrounded by the driving circuit.

9. The display device according to claim 1, wherein The driving circuit includes at least one of the following: a scan driver connected to the pixel circuit via a scan line; an emission driver connected to the pixel circuit via an emission control line; a data driver connected to the pixel circuit via a data line; as well as A timing control circuit is connected to the scan driver, the emission driver and the data driver. 10 . The display device according to claim 1 , further comprising a reflective electrode layer connected to the light emitting element.

11. The display device according to claim 10, wherein: The reflective electrode layer overlaps the driving circuit.

12. A display device, comprising: substrate; a plurality of pixel circuits on the substrate; a plurality of light-emitting elements, connected to the plurality of pixel circuits respectively; as well as a driving circuit connected to at least one pixel circuit, The plurality of light-emitting elements include: a first light-emitting element, which is overlapped with the driving circuit; and a second light-emitting element, which is not overlapped with the driving circuit.

13. The display device according to claim 12, wherein: The first light emitting element comprises: a first electrode on the substrate; a light-emitting layer on the first electrode; and The second electrode is on the light-emitting layer.

14. The display device according to claim 13, wherein: The first electrode overlaps the driving circuit. 15 . The display device according to claim 13 , further comprising a pixel defining layer disposed on the first electrode and defining an emission area of ​​the first light emitting element.

16. The display device according to claim 15, wherein The emission region overlaps the driving circuit.

17. The display device according to claim 12, wherein: The first light emitting element is overlapped with a non-pixel transistor of the driving circuit.

18. The display device according to claim 12, wherein: The driving circuits and pixel circuits connected to the first light emitting elements are alternately provided.

19. The display device according to claim 12, wherein: A pixel circuit connected to the first light emitting element is surrounded by the driving circuit.

20. The display device according to claim 12, wherein The driving circuit includes at least one of the following: a scan driver connected to the pixel circuit via a scan line; an emission driver connected to the pixel circuit via an emission control line; a data driver connected to the pixel circuit via a data line; as well as A timing control circuit is connected to the scan driver, the emission driver and the data driver.

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