Display device and head-mounted display device

Abstract

The invention provides a display device and a head-mounted display device. The display device includes: a first single crystal semiconductor substrate on which a plurality of pixel circuits arranged along a first direction and a second direction crossing the first direction are positioned, the plurality of pixel circuits including a first transistor; a second single crystal semiconductor substrate on the first single crystal semiconductor substrate, the second single crystal semiconductor substrate having positioned thereon a plurality of sub-pixels including a plurality of light emitting elements and arranged along the first direction and the second direction; and a connection line layer between the plurality of light emitting elements and the first single crystal semiconductor substrate and including a plurality of bridging lines, each of the plurality of bridging lines being electrically connected to one of the plurality of pixel circuits and one of the plurality of sub-pixels.

Description

Technical Field

[0001] One or more embodiments of the present disclosure relate to a display device and a head-mounted display device. Background Art

[0002] A head-mounted display (HMD) is a device that is worn on the user's head in the form of glasses or a helmet and displays images focused close to the user's eyes. HMDs can enable virtual reality (VR) or augmented reality (AR).

[0003] Head-mounted display devices use multiple lenses to magnify and display images displayed on a small display device. Therefore, the display device used in head-mounted display devices can provide high-resolution images, for example, images with a resolution of 3,000 pixels per inch (PPI) or higher. To this end, organic light-emitting diodes on silicon (OLEDoS), which are high-resolution, small-sized organic light-emitting display devices, can be used as display devices for head-mounted display devices. OLEDoS is a device that displays images by providing organic light-emitting diodes (OLEDs) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is provided. Summary of the Invention

[0004] Aspects and features of embodiments of the present disclosure provide a microdisplay device including a plurality of different single-crystal semiconductor substrates and a head-mounted display device including the microdisplay device.

[0005] Aspects and features of embodiments of the present disclosure also provide a micro display device implemented by an efficient layout design of connection wiring connecting two different semiconductor substrates.

[0006] However, the present disclosure is not limited to those set forth herein. The above and other embodiments of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

[0007] According to one or more embodiments, a display device includes: a first single-crystalline semiconductor substrate on which a plurality of pixel circuits arranged along a first direction and a second direction intersecting the first direction are positioned, the plurality of pixel circuits including first transistors; a second single-crystalline semiconductor substrate on which a plurality of sub-pixels including a plurality of light-emitting elements and arranged along the first and second directions are positioned; and a connection line layer between the plurality of light-emitting elements and the first single-crystalline semiconductor substrate and including a plurality of bridge lines, each of the plurality of bridge lines being electrically connected to one of the plurality of pixel circuits and one of the plurality of sub-pixels. wherein the second single crystal semiconductor substrate includes a plurality of through holes, a corresponding conductive via among the plurality of conductive vias is positioned in each of the plurality of through holes, the plurality of conductive vias are electrically connected to a light-emitting element among the plurality of light-emitting elements corresponding to each of the plurality of sub-pixels and a corresponding bridge wire among the plurality of bridge wires, respectively; wherein the connecting line layer includes a first conductive layer on which a first bridge wire is positioned, a second conductive layer on which a second bridge wire is positioned, and an interlayer insulating layer between the first conductive layer and the second conductive layer; and wherein at least some of the plurality of sub-pixels are electrically connected to the first bridge wire, and other sub-pixels among the plurality of sub-pixels adjacent to the sub-pixels connected to the first bridge wire are electrically connected to the second bridge wire.

[0008] According to one or more embodiments, an outermost sub-pixel in the first direction and an outermost sub-pixel in the second direction among the plurality of sub-pixels are electrically connected to different first bridge lines.

[0009] According to one or more embodiments, among the plurality of subpixels, inner adjacent subpixels in the first direction and inner adjacent subpixels in the second direction are electrically connected to different second bridge lines based on outermost subpixels in the first and second directions.

[0010] According to one or more embodiments, the sub-pixels of a first pixel row are arranged along a first direction, the sub-pixels in the first pixel row are electrically connected to pixel circuits among a plurality of pixel circuits that are aligned with the sub-pixels of the first pixel row in the first direction, and the sub-pixels of a second pixel row adjacent to the first pixel row in a second direction are electrically connected to pixel circuits among a plurality of pixel circuits that are not aligned with the sub-pixels of the second pixel row in the first direction.

[0011] According to one or more embodiments, the bridge line electrically connected to the sub-pixels of the first pixel row overlaps the sub-pixels of the first pixel row.

[0012] According to one or more embodiments, at least a portion of the bridge line electrically connected to the sub-pixels of the second pixel row overlaps the sub-pixels of the first pixel row.

[0013] According to one or more embodiments, a first sub-pixel positioned at an outermost portion of a first pixel row is connected to a first bridge wire, a second sub-pixel adjacent to the first sub-pixel of the first pixel row is connected to a second bridge wire, and the first bridge wire connected to the first sub-pixel is positioned on a side of the second bridge wire connected to the second sub-pixel in a direction opposite to the second direction in the second direction.

[0014] According to one or more embodiments, the sub-pixels of a first pixel column are arranged along a second direction, the sub-pixels of the first pixel column are electrically connected to pixel circuits among a plurality of pixel circuits that are aligned with the sub-pixels of the first pixel column in the second direction, and the sub-pixels of a second pixel column adjacent to the first pixel column in a direction opposite to the first direction are electrically connected to pixel circuits among a plurality of pixel circuits that are not aligned with the sub-pixels of the second pixel column in the second direction.

[0015] According to one or more embodiments, a first sub-pixel at an outermost portion of a first pixel column is connected to a first bridge line, a second sub-pixel adjacent to the first sub-pixel of the first pixel column is connected to a second bridge line, and the first bridge line connected to the first sub-pixel is positioned in the first direction on one side of the second bridge line connected to the second sub-pixel in the first direction.

[0016] According to one or more embodiments, a first sub-pixel at an outermost portion among a plurality of sub-pixels arranged along an oblique direction in a first single crystal semiconductor substrate is connected to a first bridge wire, a second sub-pixel adjacent to the first sub-pixel in the oblique direction is connected to a second bridge wire, and the second bridge wire is positioned above the first bridge wire.

[0017] According to one or more embodiments, a position of one end of a first bridge line in a subpixel among a plurality of subpixels is different from a position of one end of a second bridge line in a subpixel adjacent to an interior of the subpixel connected to the first bridge line.

[0018] According to one or more embodiments, the plurality of sub-pixels include stacked sub-pixels stacked with pixel circuits and non-stacked sub-pixels not stacked with pixel circuits, and wherein a portion of the bridge lines among the plurality of bridge lines connected to the non-stacked sub-pixels does not stack with the first single crystal semiconductor substrate.

[0019] According to one or more embodiments, a bridge line connected to a non-overlapping sub-pixel among the plurality of bridge lines is longer than a bridge line connected to an overlapping sub-pixel.

[0020] According to one or more embodiments, a bridge line connected to overlapping sub-pixels among the plurality of bridge lines has a zigzag shape.

[0021] According to one or more embodiments, an area of ​​the first single crystalline semiconductor substrate is smaller than an area of ​​the second single crystalline semiconductor substrate.

[0022] According to one or more embodiments, a display device includes: a first single crystalline semiconductor substrate, a plurality of first transistors and a plurality of pixel circuits positioned on the first single crystalline semiconductor substrate, the plurality of pixel circuits including the first transistors; a second single crystalline semiconductor substrate on the first single crystalline semiconductor substrate, wherein a plurality of sub-pixels including a plurality of light-emitting elements are positioned on the second single crystalline semiconductor substrate; and a connection line layer between the plurality of light-emitting elements and the first single crystalline semiconductor substrate, wherein the second single crystalline semiconductor substrate includes a plurality of through holes, wherein a plurality of conductive vias electrically connected to a light-emitting element corresponding to each of the plurality of sub-pixels in the plurality of light-emitting elements are respectively positioned in the plurality of through holes, wherein the connection line layer includes a plurality of conductive layers including a plurality of bridge lines and a plurality of bridge contacts and an interlayer insulating layer between the plurality of conductive layers, and wherein the plurality of sub-pixels include a first sub-pixel and a second sub-pixel, the first sub-pixel being connected to one of the plurality of pixel circuits via a first bridge line at a first conductive layer of the connection line layer, and the second sub-pixel being connected to one of the plurality of pixel circuits via a second bridge line at a second conductive layer on the first conductive layer of the connection line layer.

[0023] According to one or more embodiments, the second bridge line is electrically connected to the first bridge contact at the first conductive layer, and the first bridge line is electrically connected to the second bridge contact at the second conductive layer.

[0024] According to one or more embodiments, each of the second bridge line and the second bridge contact is connected to a corresponding one of the conductive vias.

[0025] According to one or more embodiments, at least a portion of the first bridging line is connected to the second bridging line at the second conductive layer.

[0026] According to one or more embodiments, a head-mounted display device includes: a frame; a plurality of display devices on the frame; and a lens on each of the plurality of display devices, wherein the display device includes: a first single-crystalline semiconductor substrate including a plurality of pixel circuits arranged along a first direction and a second direction intersecting the first direction, the plurality of pixel circuits including first transistors; a second single-crystalline semiconductor substrate including a plurality of sub-pixels including a plurality of light-emitting elements and arranged along the first direction and the second direction on the first single-crystalline semiconductor substrate; and a connecting line layer between the plurality of light-emitting elements and the first single-crystalline semiconductor substrate and including a plurality of bridge lines, each of the plurality of bridge lines being electrically connected to a transistor in the plurality of pixel circuits. A pixel circuit and a sub-pixel among a plurality of sub-pixels, wherein a second single crystal semiconductor substrate includes a plurality of through holes, a corresponding conductive via among a plurality of conductive vias is positioned in each of the plurality of through holes, the plurality of conductive vias are electrically connected to a light-emitting element among a plurality of light-emitting elements corresponding to each of the plurality of sub-pixels and a corresponding bridge line among a plurality of bridge lines, respectively, wherein a connecting line layer includes a first conductive layer in which a first bridge line is positioned, a second conductive layer in which a second bridge line is positioned, and an interlayer insulating layer between the first conductive layer and the second conductive layer, and wherein at least some of the plurality of sub-pixels are electrically connected to the first bridge line, and other sub-pixels among the plurality of sub-pixels adjacent to the sub-pixel connected to the first bridge line are electrically connected to the second bridge line.

[0027] According to another aspect of the present disclosure, a display device is provided.

[0028] According to yet another aspect of the present disclosure, a head-mounted display device is provided.

[0029] A display device according to an embodiment may include two different single crystal semiconductor substrates, and a process of manufacturing the single crystal semiconductor substrate disposed therebelow allows manufacturing a large number of single crystal semiconductor substrates per unit wafer substrate, thereby improving manufacturing yield.

[0030] A display device according to an embodiment may include an efficient layout design in which connection wirings connecting two different single crystal semiconductor substrates do not interfere with each other even on a single crystal semiconductor substrate having a relatively small area. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other embodiments and features of the present disclosure will become more apparent by describing embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 is an exploded perspective view of a display device according to one or more embodiments; Figure 2 It shows Figure 1 A plan view of an example of a drive portion shown in FIG; Figure 3 It shows Figure 1 A plan view of an example of a display portion shown in FIG; Figure 4 is a block diagram illustrating a display device according to one or more embodiments; Figure 5 is an equivalent circuit diagram of a pixel according to one or more embodiments; Figure 6 is a schematic cross-sectional view of a display device according to one or more embodiments; Figure 7 is a schematic diagram illustrating a rear surface of a display device according to one or more embodiments; Figure 8 is a schematic cross-sectional view illustrating a display device according to one or more embodiments; Figure 9 is a schematic cross-sectional view of a driving portion according to one or more embodiments; Figure 10 is a plan view illustrating first electrodes, light emitting regions, and pixel defining films of a plurality of sub-pixels provided in a display region of a display portion according to one or more embodiments; Figure 11 is a plan view illustrating first electrodes, light emitting regions, and pixel defining films of a plurality of sub-pixels provided in a display region of a display portion according to one or more embodiments; Figure 12 is a cross-sectional view showing a portion of a display portion according to one or more embodiments; Figure 13 is a diagram showing a schematic arrangement of connection wirings connecting a pixel circuit portion of a display device and sub-pixels of a display region according to one or more embodiments; Figure 14 is a schematic diagram illustrating connections between sub-pixels and pixel circuits through connection wiring of a display device according to one or more embodiments; Figure 15 is a schematic cross-sectional view illustrating an example of a connection line layer of a display device according to one or more embodiments; Figure 16 is a schematic cross-sectional view illustrating an example of a connection line layer of a display device according to one or more embodiments; Figure 17 and Figure 18 It is shown by Figure 14 A schematic diagram of a connection between a sub-pixel and a pixel circuit by a connection wiring in a first region; Figure 19 and Figure 20 It is shown by Figure 14A schematic diagram of a connection between a sub-pixel and a pixel circuit by a connection wiring in a second region; Figures 21 to 23 It is shown by Figure 14 A schematic diagram of a connection between a sub-pixel and a pixel circuit in a third region of the pixel; Figure 24 is a diagram schematically illustrating an arrangement of via holes through which sub-pixels and connection wirings of a display device according to one or more embodiments are connected; Figure 25 is a view showing an example of the shape of a bridge line according to one or more embodiments; Figure 26 is a view showing an example of a cross-sectional connection structure of a connection wiring according to one or more embodiments; Figure 27 is a diagram showing a schematic arrangement of connection wirings connecting a pixel circuit portion of a display device and sub-pixels of a display region according to one or more embodiments; Figure 28 is a schematic cross-sectional view illustrating an example of a connection line layer of a display device according to one or more embodiments; Figure 29 is a perspective view illustrating a head-mounted display device according to one or more embodiments; Figure 30 It shows Figure 29 an exploded perspective view of an example of a head-mounted display device; and Figure 31 is a perspective view illustrating a head-mounted display device according to one or more embodiments. DETAILED DESCRIPTION

[0032] By referring to the detailed description and drawings of the embodiments, the aspects and features of the embodiments of the present disclosure and the methods for implementing the embodiments can be more easily understood. Hereinafter, the embodiments will be described in more detail with reference to the drawings. However, the described embodiments can be implemented in various different forms and should not be interpreted as being limited to the embodiments shown here. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques that are not necessary for those of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described.

[0033] Unless otherwise specified, the same reference numerals, characters or combinations thereof refer to the same elements throughout the drawings and written description, and therefore, their description will not be repeated. In addition, parts not related to the description of one or more embodiments may not be shown to make the description clear.

[0034] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity. In addition, the use of cross-hatching and / or shading is often provided in the drawings to clarify boundaries between adjacent elements. Therefore, unless otherwise indicated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between illustrated elements, and / or any other characteristics, attributes, properties, etc., of an element.

[0035] Various embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Furthermore, for purposes of describing embodiments according to the present disclosure, the specific structural or functional descriptions disclosed herein are merely exemplary. Therefore, the embodiments disclosed herein should not be construed as limited to the specific illustrated shapes of regions, but rather are intended to include deviations in shape due to, for example, manufacturing techniques.

[0036] For example, an implanted region shown as a rectangle may have rounded and / or curved features and / or a gradient of implant concentration at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may cause some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the accompanying drawings are schematic in nature, their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to be limiting. Additionally, as will be appreciated by those skilled in the art, the described embodiments may be modified in a variety of different ways, all without departing from the scope of this disclosure.

[0037] In the detailed description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding of the various embodiments. However, it is apparent that the various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0038] For ease of explanation, spatially relative terms such as "under," "beneath," "lower," "beneath," "above," and / or "above" may be used herein to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as "under," "beneath," or "below" another element or feature would then be oriented "above" the other element and / or feature. Thus, the example terms "under" and "beneath" can encompass both above and below orientations. The device may be oriented differently (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. Similarly, when a first portion is described as being disposed "above" a second portion, this means that the first portion is disposed above or below the second portion, and is not limited to being disposed at the upper side of the second portion based on gravity.

[0039] Furthermore, in this specification, the phrase “on a plane” or “in a plan view” means viewing a target portion from the top, and the phrase “in section” means viewing a section formed by vertically cutting the target portion from the side.

[0040] It will be understood that when an element, layer, region, or component is referred to as being “formed on,” “on,” “connected to,” or “coupled to” another element, layer, region, or component, the element, layer, region, or component may be directly formed on, directly on, directly connected to, or directly coupled to the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to the other element, layer, region, or component, such that one or more intervening elements, layers, regions, or components may be present. For example, when a layer, region, or component is referred to as being “electrically connected to” or “electrically coupled to” another layer, region, or component, the layer, region, or component may be directly electrically connected or directly electrically coupled to the other layer, region, and / or component, or intervening layers, regions, or components may be present. However, "directly connected / directly coupled" means that one component is directly connected or coupled to another component without intervening components. Meanwhile, other expressions describing the relationship between components (such as "between," "immediately between," or "adjacent to," and "directly adjacent to") should be similarly interpreted. Additionally, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0041] For the purposes of this disclosure, expressions such as “at least one of,” “one of,” and “selected from” when following a list of elements modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as, for example, XYZ, XZ, YZ, and XY), or any variation thereof. Similarly, expressions such as “at least one of A and B” can include A, B, or A and B. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, expressions such as “A and / or B” can include A, B, or A and B. In addition, when describing embodiments of the present disclosure, the use of “may” refers to “one or more embodiments of the present disclosure.”

[0042] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, a first element, component, region, layer, or part described below may be referred to as a second element, component, region, layer, or part without departing from the scope of this disclosure.

[0043] In the examples, the x-axis, y-axis, and / or z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0044] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a" and "an" are intended to include the plural forms. It will also be understood that when the terms "comprises," "comprising," "having," "including," and variations thereof are used in this specification, they indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0045] As used herein, the terms "substantially," "approximately," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that one of ordinary skill in the art would recognize. As used herein, "approximately" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Additionally, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0046] When one or more embodiments can be implemented differently, the specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of the described order.

[0047] In addition, any numerical range disclosed and / or described herein is intended to include all subranges of the same numerical precision contained within the described range. For example, the range of "1.0 to 10.0" is intended to include all subranges between (and including) the described minimum value of 1.0 and the described maximum value of 10.0, for example, a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0 (such as 2.4 to 7.6). Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly describe any subranges contained within the ranges expressly described herein. All such ranges are intended to be inherently described in this specification so that modifications to expressly describe any such subranges will meet the requirements.

[0048] The electronic or electronic devices and / or any other related devices or components according to one or more embodiments of the present disclosure described herein may be implemented using any suitable hardware, firmware (e.g., an application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on a single integrated circuit (IC) chip or on separate IC chips. Furthermore, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate.

[0049] In addition, the various components of these devices can be processes or threads that run on one or more processors, execute computer program instructions in one or more computing devices, and interact with other system components to perform the various functions described herein. The computer program instructions are stored in a memory, which can be implemented in a computing device using a standard memory device (such as, for example, random access memory (RAM)). The computer program instructions can also be stored in other non-transitory computer-readable media (such as, for example, a CD-ROM and / or a flash drive). In addition, those skilled in the art should recognize that without departing from the scope of this disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed throughout one or more other computing devices.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, for example, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0051] It will be understood by those skilled in the art that, in view of the overall content of the present disclosure, each suitable feature of the various embodiments of the present disclosure may be combined in part or in whole or in combination with each other, and may be technically interlocked and operated in various suitable manners, and unless otherwise specified or implied, each embodiment may be implemented independently of each other or in combination with each other in any suitable manner.

[0052] Figure 1 is an exploded perspective view of a display device according to one or more embodiments.

[0053] Reference Figure 1 The display device 10 according to one or more embodiments is a device that displays moving images and / or still images. The display device 10 according to one or more embodiments can be applied to portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigation devices, and / or ultra-mobile personal computers (UMPCs). For example, the display device 10 can be applied to the display portion of a television, laptop computer, monitor, billboard, or Internet of Things (IoT) device. Alternatively, the display device 10 can be applied to smart watches, watch phones, and head-mounted displays (HMDs) for implementing virtual reality and / or augmented reality.

[0054] The display device 10 according to one or more embodiments may include a driving portion 100, a display portion 200, and a circuit board 300. The display device 10 may further include a protective layer 900 disposed around the driving portion 100.

[0055] The driving unit 100 may have a planar shape similar to a quadrilateral. For example, the driving unit 100 may have a planar shape similar to a rectangle having one side in the first direction DR1 and another side in the second direction DR2 intersecting the first direction DR1. The one side of the driving unit 100 in the first direction DR1 and the other side of the driving unit 100 in the second direction DR2 may have different lengths. In the driving unit 100, the corner where the one side in the first direction DR1 and the other side in the second direction DR2 meet may be rounded to have a suitable curvature (e.g., a predetermined curvature) or may be formed at a right angle. The planar shape of the driving unit 100 is not limited to a quadrilateral and may be formed similar to other polygons, circles, and / or ellipses.

[0056] The display unit 200 may be disposed on the drive unit 100. In the display device 10, the drive unit 100 and the display unit 200 may be joined to each other. Unlike the drive unit 100, the display unit 200 may have a shape similar to a square. For example, the drive unit 100 may have a planar shape similar to a square having one side in a first direction DR1 and another side in a second direction DR2 intersecting the first direction DR1. The planar shape of the display unit 200 is not limited to a quadrilateral and may be formed similar to other polygons, a circle, and / or an ellipse. The planar shape of the display device 10 may follow the planar shape of the display unit 200, but is not limited thereto.

[0057] According to one or more embodiments, the planar area of ​​the display portion 200 of the display device 10 may be larger than the planar area of ​​the drive portion 100 thereof. The display device 10 includes a drive portion 100 and a display portion 200 comprising different substrates, and the drive portion 100 and the display portion 200 may have different areas. The elements formed in the drive portion 100 and the elements formed in the display portion 200 may be different from each other, and these elements may be formed separately on different substrates. The display device 10 can be manufactured by forming a plurality of elements having different sizes, line widths, and / or manufacturing processes on different substrates and then bonding these substrates, and has the advantage of improving product performance and manufacturing yield.

[0058] The circuit board 300 can be electrically connected to a plurality of pads in a pad area of ​​the display portion 200 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 can be a flexible printed circuit board (FPCB) or a flexible film made of a flexible material. Figure 1, the circuit board 300 is shown unfolded, but the circuit board 300 can be bent. In this case, one end of the circuit board 300 can be placed on the lower surface of the driving unit 100. The other end of the circuit board 300 can be connected to the plurality of pads in the pad area of ​​the display unit 200 using a conductive adhesive member. In one or more embodiments, the circuit board 300 can also be attached to the lower surface of the driving unit 100.

[0059] The protective layer 900 may be disposed around the driving portion 100 (e.g., surrounding the driving portion 100) and may be provided on the lower surface of the display portion 200. The protective layer 900 may reduce a height difference caused by an area difference between the driving portion 100 and the display portion 200, and may also protect the driving portion 100 and the display portion 200.

[0060] Figure 2 It shows Figure 1 2 is a plan view of an example of a drive portion shown in FIG. Figure 3 It shows Figure 1 A plan view of an example of a display portion shown in FIG.

[0061] Reference Figure 2 and Figure 3 The driving portion 100 of the display device 10 may include driving circuit elements of the display device 10. The driving portion 100 may include a first single crystal semiconductor substrate 110 and a driving circuit portion 400, a gate driver 600, a data driver 700, and a pixel circuit portion 800 formed on the first single crystal semiconductor substrate 110.

[0062] The first single crystal semiconductor substrate 110 may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. A plurality of first transistors are formed on the first single crystal semiconductor substrate 110. The plurality of first transistors may be electrically connected to form the driver circuit portion 400, the gate driver 600, the data driver 700, and the pixel circuit portion 800. The first transistors may be formed using a semiconductor process. For example, the plurality of transistors may be formed as complementary metal oxide semiconductor (CMOS) transistors.

[0063] The drawing illustrates that the pixel circuit portion 800 is positioned on the upper side of the driver unit 100, the data driver 700, the driver circuit portion 400, and the signal terminal area TDA are positioned on the lower side of the driver unit 100, and the gate driver 600 is positioned on the right side, which is one side of the pixel circuit portion 800 in the first direction DR1. However, the present disclosure is not limited thereto. In the driver unit 100, the positions of the driver circuit portion 400, the gate driver 600, the data driver 700, and the pixel circuit portion 800 can be modified in various ways depending on the design structure of the plurality of circuit elements formed on the first single crystal semiconductor substrate 110.

[0064] A plurality of signal terminals STD arranged along the first direction DR1 may be provided in the signal terminal area TDA. The plurality of signal terminals STD may be electrically connected to the display unit 200 and may be electrically connected to the circuit board 300 through the display unit 200. The signal terminals STD may transmit electrical signals applied from the circuit board 300 to the driving circuit portion 400, the gate driver 600, the data driver 700, and the pixel circuit portion 800.

[0065] The display portion 200 may include a second single crystal semiconductor substrate 210 and a plurality of pixels PX formed on the second single crystal semiconductor substrate 210. The display portion 200 may include a display area DAA in which the plurality of pixels PX are provided and a non-display area NA surrounding the display area DAA along an edge or periphery of the display area DAA. A through hole area TSA and a pad area PDA may be provided in the non-display area NA.

[0066] The second single crystal semiconductor substrate 210 may be a silicon substrate, a germanium substrate and / or a silicon germanium substrate. Unlike the first single crystal semiconductor substrate 110, no transistors may be formed in the second single crystal semiconductor substrate 210. A display layer (eg, Figure 6 ” 230 ” in the figure may be disposed on the second single crystal semiconductor substrate 210 , and a plurality of light emitting elements included in the display layer may be electrically connected to the pixel circuit portion 800 formed on the first single crystal semiconductor substrate 110 .

[0067] A plurality of pixels PX including light-emitting elements may be provided in the display area DAA. Each of the plurality of pixels PX may include three sub-pixels, for example, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The three sub-pixels SP1, SP2, and SP3 may form one pixel PX and may display colors. However, the present disclosure is not limited thereto, and one pixel PX may include two sub-pixels or more than three sub-pixels. The plurality of sub-pixels SP1, SP2, and SP3 may be arranged in a matrix form along a first direction DR1 and a second direction DR2. Each of the plurality of sub-pixels SP1, SP2, and SP3 may be electrically connected to a pixel circuit (in a pixel circuit portion 800 formed on the first single crystal semiconductor substrate 110) Figure 5 Each of the sub-pixels SP1, SP2, and SP3 may include a light emitting element that may emit light according to an electrical signal applied from a pixel circuit provided in the display area DAA.

[0068] Some of the sub-pixels SP1, SP2, and SP3 disposed in the display area DAA of the display portion 200 may overlap the driving portion 100 in the thickness direction (e.g., the third direction DR3), and other sub-pixels may not overlap the driving portion 100. The driving portion 100 may have a smaller area than the display portion 200 and may be disposed adjacent to one side of the display portion 200. Therefore, only some of the plurality of sub-pixels SP1, SP2, and SP3 may overlap the driving portion 100 in the thickness direction (e.g., the third direction DR3).

[0069] According to one or more embodiments, the display portion 200 of the display device 10 may include a plurality of first through-holes TSV1 overlapping the display area DAA. The first through-holes TSV1 may be formed to penetrate the second single crystal semiconductor substrate 210 of the display portion 200. The first through-holes TSV1 may form a connection path between the pixel circuit portion 800 of the driving portion 100 and each of the sub-pixels SP1, SP2, and SP3 of the display portion 200. The plurality of first through-holes TSV1 may be formed to correspond to each of the sub-pixels SP1, SP2, and SP3 of the display portion 200. In one or more embodiments, the number of first through-holes TSV1 may be the same as the number of sub-pixels SP1, SP2, and SP3, and the first through-holes TSV1 may be formed to overlap the sub-pixels SP1, SP2, and SP3, respectively. However, the present disclosure is not limited thereto. The plurality of first through-holes TSV1 may each correspond to the sub-pixels SP1, SP2, and SP3, but may not necessarily be formed to overlap the sub-pixels SP1, SP2, and SP3. As will be described later, the plurality of sub-pixels SP1 , SP2 , and SP3 may be electrically connected to the pixel circuit of the pixel circuit portion 800 through a connection wiring provided in the first through-hole TSV1 .

[0070] The non-display area NA may be provided around (eg, surrounding) the display area DAA. The non-display area NA may be an area where light is not emitted because no pixels PX are provided. The through hole area TSA and the pad area PDA may be provided in the non-display area NA.

[0071] The pad area PDA may be provided on the lower side of the display area DAA in the second direction DR2. A plurality of pads PD arranged along the first direction DR1 may be provided in the pad area PDA. The circuit board 300 may be attached to the plurality of pads PD. The pads PD may be electrically connected to the circuit board 300 and may transmit electrical signals applied from the circuit board 300 to the driving unit 100.

[0072] The through-hole area TSA may be provided between the pad area PDA and the display area DAA. A plurality of second through-holes TSV2 may be formed in the through-hole area TSA. The second through-holes TSV2 may be a connection path for electrically connecting the signal terminal STD of the driving unit 100 and the signal connection wiring of the circuit board 300. A plurality of second through-holes TSV2 may be formed to correspond to the signal terminals STD of the driving unit 100, respectively. In one or more embodiments, the number of the second through-holes TSV2 may be the same as the number of the signal terminals STD, and each of the second through-holes TSV2 may be formed to overlap with the signal terminal STD. However, the present disclosure is not limited thereto. The circuit board 300 may be electrically connected to the signal terminal STD of the driving unit 100 through a plurality of pads PD and the signal connection wiring provided in the second through-holes TSV2.

[0073] Figure 4 is a block diagram illustrating a display device according to one or more embodiments.

[0074] Reference Figure 4 The driver circuit portion 400 may include a timing controller 410 (e.g., a timing control circuit). Furthermore, the driver circuit portion 400 may include various circuits involved in driving the display device 10, such as a gamma circuit and a logic circuit. The driver circuit portion 400 may include driver circuit transistors formed on the first single crystal semiconductor substrate 110.

[0075] The timing controller 410 can receive digital video data DATA and timing signals from the outside. The timing controller 410 can generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display unit 200 based on the timing signals. The timing controller 410 can output the scan timing control signal SCS to the scan driver 610 of the gate driver 600 and output the emission timing control signal ECS to the light emitting driver 620 of the gate driver 600. The timing controller 410 can output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0076] The power supply unit PSU (or power supply circuit) can generate multiple panel driving voltages based on the power supply voltage from the outside. For example, the power supply unit PSU can generate a first driving voltage VSS, a second driving voltage VDD, a reference voltage VREF, and an initialization voltage VINT, and supply the voltages to multiple pixels PX.

[0077] The plurality of pixels PX may be supplied with a scan timing control signal SCS, an emission timing control signal ECS, digital video data DATA, and a data timing control signal DCS from the timing controller 410. A first driving voltage VSS, a second driving voltage VDD, a reference voltage VREF, and an initialization voltage (also referred to as a third driving voltage) VINT from a power supply unit PSU may also be supplied to the plurality of pixels PX.

[0078] The gate driver 600 may include a scan driver 610 and a light-emitting driver 620. The scan driver 610 may include a plurality of scan transistors formed on a first single-crystal semiconductor substrate 110, and the light-emitting driver 620 may include a plurality of light-emitting transistors formed on the first single-crystal semiconductor substrate 110. The plurality of scan transistors and the plurality of light-emitting transistors may be formed using a semiconductor process. For example, the plurality of scan transistors and the plurality of light-emitting transistors may be formed using CMOS transistors.

[0079] The scan driver 610 may include a first scan signal output unit 611, a second scan signal output unit 612, and a third scan signal output unit 613. Each of the first scan signal output unit 611, the second scan signal output unit 612, and the third scan signal output unit 613 may receive a scan timing control signal SCS from the timing controller 410. The first scan signal output unit 611 may generate a write scan signal based on the scan timing control signal SCS from the timing controller 410 and sequentially output the write scan signal to the first scan line GWL. The second scan signal output unit 612 may generate a control scan signal based on the scan timing control signal SCS and sequentially output the control scan signal to the second scan line GCL. The third scan signal output unit 613 may generate a bias scan signal based on the scan timing control signal SCS and sequentially output the bias scan signal to the third scan line GBL.

[0080] The light emitting driver 620 may include a first light emitting signal output unit 621 and a second light emitting signal output unit 622. Each of the first light emitting signal output unit 621 and the second light emitting signal output unit 622 may receive an emission timing control signal ECS from the timing controller 410. The light emitting driver 620 may generate an emission control signal based on the emission timing control signal ECS and sequentially output the emission control signal to the first emission control line EL1 and the second emission control line EL2.

[0081] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the timing controller 410. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the converted analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 may be selected by the write scan signal of the scan driver 610, and the data voltage may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0082] The pixel circuit portion 800 includes a plurality of pixel transistors formed on the first single crystal semiconductor substrate 110. The plurality of pixel transistors may be formed by a semiconductor process, for example, by CMOS transistors.

[0083] A plurality of data lines DL, a plurality of scan lines GWL, GCL, and GBL, and a plurality of emission control lines EL1 and EL2 may be provided in the pixel circuit portion 800. The plurality of scan lines GWL, GCL, and GBL, and the plurality of emission control lines EL1 and EL2 may extend in a first direction DR1 and may be spaced apart from each other (e.g., spaced apart) in a second direction DR2. The plurality of data lines DL may extend in a second direction DR2 and may be spaced apart from each other (e.g., spaced apart) in the first direction DR1. The pixel circuit portion 800 may be electrically connected to the pixels PX of the display portion 200 and may transmit electrical signals required for the light-emitting devices to emit light. The plurality of data lines DL, the plurality of scan lines GWL, GCL, and GBL, and the plurality of emission control lines EL1 and EL2 may be connected to the plurality of pixels PX of the display portion 200.

[0084] Figure 5 is an equivalent circuit diagram of a pixel according to one or more embodiments.

[0085] Reference Figure 5 , sub-pixels (e.g., Figure 3The pixel circuit PXC of the subpixel SP1, SP2, and SP3 in the pixel circuit (or any of the subpixels SP1, SP2, and SP3 in the pixel circuit) can be connected to the first scan line GWL, the second scan line GCL, the third scan line GBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. Furthermore, the pixel circuit PXC can be connected to a first drive voltage line VSL to which a first drive voltage VSS corresponding to a low potential voltage is applied, a second drive voltage line VDL to which a second drive voltage VDD corresponding to a high potential voltage is applied, and a third drive voltage line VIL to which a third drive voltage VINT corresponding to an initialization voltage is applied. That is, the first drive voltage line VSL can be a low potential voltage line, the second drive voltage line VDL can be a high potential voltage line, and the third drive voltage line VIL can be an initialization voltage line. In this case, the first drive voltage VSS can be a voltage lower than the third drive voltage VINT. The second drive voltage VDD can be a voltage higher than the third drive voltage VINT.

[0086] The pixel circuit PXC includes a plurality of transistors T1 , T2 , T3 , T4 , T5 , and T6 , a light emitting element LE, a first capacitor C1 , and a second capacitor C2 .

[0087] The light-emitting element LE emits light in response to the drive current Ids flowing through the channel of the first transistor T1. The amount of light emitted by the light-emitting element LE may be proportional to the drive current Ids. The light-emitting element LE may be disposed between the fourth transistor T4 and the first drive voltage line VSL. A first electrode of the light-emitting element LE may be connected to the drain electrode of the fourth transistor T4, and a second electrode of the light-emitting element LE may be connected to the first drive voltage line VSL. The first electrode of the light-emitting element LE may be an anode electrode, and the second electrode of the light-emitting element LE may be a cathode electrode. The light-emitting element LE may be, but is not limited to, an organic light-emitting diode (OLED) including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first and second electrodes. For example, the light-emitting element LE may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first and second electrodes. In this case, the light-emitting element LE may be a micro light-emitting diode.

[0088] The first transistor T1 may be a driving transistor that controls a source-drain current (Ids, hereinafter referred to as a "driving current") flowing between a source electrode and a drain electrode according to a voltage applied to a gate electrode. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to a drain electrode of the sixth transistor T6, and a drain electrode connected to a second node N2.

[0089] The second transistor T2 can be disposed between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on by a write scan signal from the first scan line GWL and connects one electrode of the first capacitor C1 to the data line DL. Therefore, a data voltage of the data line DL can be applied to one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the first scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0090] The third transistor T3 may be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a write control signal from the second scan line GCL and connects the first node N1 to the second node N2. Therefore, because the gate and drain electrodes of the first transistor T1 are connected, the first transistor T1 can operate like a diode (e.g., the first transistor T1 may be diode-connected). The third transistor T3 includes a gate electrode connected to the second scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0091] The fourth transistor T4 may be disposed between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line EL1 and connects the second node N2 to the third node N3. Accordingly, the drive current Ids of the first transistor T1 may be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0092] The fifth transistor T5 may be disposed between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal from the third scan line GBL and connects the third node N3 to the third drive voltage line VIL. Therefore, the third drive voltage VINT of the third drive voltage line VIL may be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the third scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third drive voltage line VIL.

[0093] The sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2 and connects the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0094] The first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0095] The second capacitor C2 is formed between the gate electrode (or first node N1) of the first transistor T1 and the second driving voltage line VDL. The second capacitor C2 includes one electrode connected to the gate electrode (or first node N1) of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0096] The first node N1 is a contact point between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 is a contact point between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a contact point between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0097] Each of the first to sixth transistors T1 to T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first to sixth transistors T1 to T6 may be a P-type MOSFET, but is not limited thereto. Each of the first to sixth transistors T1 to T6 may be an N-type MOSFET. Alternatively, each of some of the first to sixth transistors T1 to T6 may be a P-type MOSFET, and each of the remaining transistors may be an N-type MOSFET.

[0098] exist Figure 5 FIG. 4 shows that the pixel circuit PXC includes six transistors T1 to T6 and two capacitors C1 and C2, but it should be noted that the equivalent circuit diagram of the pixel circuit PXC is not limited to Figure 5 For example, the number of transistors and capacitors in the pixel circuit PXC is not limited to Figure 5 The quantity shown.

[0099] Figure 6 is a schematic cross-sectional view of a display device according to one or more embodiments. Figure 7 is a schematic diagram illustrating a rear surface of a display device according to one or more embodiments. Figure 6 Schematic connection relationship of the routing wirings RM1 and RM2 that electrically connect the display section 200 and the drive section 100 is shown. Figure 7 The arrangement of the through-vias TSV1 and TSV2 and the routing wires RM1 and RM2 viewed from the rear surface of the display device 10 is shown.

[0100] Combine Figure 4 Reference Figure 6 and Figure 7 The display device 10 according to one or more embodiments may include a driving portion 100 and a display portion 200. The driving portion 100 includes a first single crystal semiconductor substrate 110 and a driving circuit layer 120 disposed on the first single crystal semiconductor substrate 110. The display portion 200 includes a second single crystal semiconductor substrate 210 and a display layer 230 disposed on the second single crystal semiconductor substrate 210. The display device 10 may include two different single crystal semiconductor substrates 110 and 210 stacked in a third direction DR3, which is a thickness direction of the display device 10.

[0101] The driving unit 100 may include circuit elements necessary for the light-emitting elements included in the display layer 230 of the display unit 200 to emit light. As described above, the driving circuit layer 120 of the driving unit 100 may include a driving circuit portion 400, a gate driver 600, a data driver 700, and a pixel circuit portion 800. Circuit elements (such as transistors and capacitors) constituting the driving circuit portion 400, the gate driver 600, the data driver 700, and the pixel circuit portion 800 may be formed of CMOS on the first single crystal semiconductor substrate 110.

[0102] The display portion 200 may include a plurality of light emitting elements that emit light to display an image of the display device 10. The light emitting elements may be electrically connected to circuit elements formed in the driving portion 100 and emit light.

[0103] According to one or more embodiments, the planar area of ​​the driving portion 100 or the first single crystal semiconductor substrate 110 of the display device 10 can be smaller than the planar area of ​​the display portion 200 or the second single crystal semiconductor substrate 210 of the display device 10. The plurality of transistors formed in the driving portion 100 can be formed by a semiconductor microprocess and can have very small sizes and / or line widths. In the driving portion 100, a large number of circuit elements can be provided with a high degree of integration, and power consumption is reduced due to the miniaturization of the element sizes.

[0104] In addition, because the driver 100 includes only circuit elements formed by CMOS on the first single crystal semiconductor substrate 110 and does not include light-emitting elements, it is only necessary to ensure just enough space to set up the elements formed by micro-processing. It is sufficient for the first single crystal semiconductor substrate 110 to have an area smaller than the second single crystal semiconductor substrate 210, and because the process of forming the driver circuit layer 120 is performed on a single wafer substrate, a large number of driver units 100 can be manufactured on the single wafer substrate, so the manufacturing yield can be improved. In particular, because a high-cost semiconductor process is performed on the driver 100, cost reduction can be achieved by improving the manufacturing yield of the driver 100. In addition, in the display unit 200, a large number of light-emitting elements can be formed on the second single crystal semiconductor substrate 210 having a relatively large area, thereby making it possible to realize a high-resolution display device.

[0105] The display device 10 may include a connection line layer 500 disposed between the second single crystal semiconductor substrate 210 of the display unit 200 and the driving circuit layer 120 of the driving unit 100. The connection line layer 500 may be disposed on the lower surface of the second single crystal semiconductor substrate 210. A portion of the plurality of routing wires RM1 and RM2 may be disposed in the connection line layer 500, and the routing wires RM1 and RM2 may connect the display layer 230 and the circuit board 300 of the display unit 200 with the driving unit 100. The driving circuit layer 120 of the driving unit 100 may be electrically connected to the display unit 200 and the circuit board 300 through the routing wires RM1 and RM2 and transmit electrical signals for light emission.

[0106] The first routing wiring RM1 may be connected to the sub-pixels SP1, SP2, and SP3 provided on the display layer 230 of the display portion 200 and the pixel circuit portion 800 of the driving portion 100. In one or more embodiments, the display device 10 may include a plurality of first through-holes TSV1 provided to correspond to the sub-pixels SP1, SP2, and SP3 of the display portion 200, and the first routing wiring RM1 may connect each of the first through-holes TSV1 to the pixel circuit portion 800. While the first through-holes TSV1 are provided to extend over the display portion 200 in a large area, the pixel circuit portion 800 may have a relatively small area. The first routing wiring RM1 may include a conductive via (e.g., a conductive via hole) provided to extend over the display portion 200 in a large area. Figure 12 ) and a connection wiring (eg, Figure 12 In a plan view, a gap between a first routing wiring RM1 and another first routing wiring RM1 adjacent thereto may be narrower in a portion overlapping the driving part 100 than in the display area DAA.

[0107] In one or more embodiments, some of the plurality of first through vias TSV1 may overlap with the driving part 100 in the thickness direction (e.g., the third direction DR3), and other portions may not overlap with the driving part 100 in the thickness direction (e.g., the third direction DR3). The connection wiring (e.g., Figure 12 Some of the first through vias TSV1 may not overlap with the driving part 100. However, the arrangement of the first through vias TSV1 may vary depending on the position of the layer where the connection wiring RML of the first routing wiring RM1 is provided.

[0108] According to one or more embodiments, the number of first through holes TSV1 may be the same as the number of sub-pixels SP1, SP2, and SP3 provided in the display area DAA. For example, a plurality of sub-pixels SP1, SP2, and SP3 may be arranged along a first direction DR1 and a second direction DR2 in the display area DAA, and the first through holes TSV1 may also be arranged along the first direction DR1 and the second direction DR2 and may correspond to each of the sub-pixels SP1, SP2, and SP3 in a one-to-one manner. The first through holes TSV1 may be formed to overlap each of the sub-pixels SP1, SP2, and SP3. The number of first routing wires RM1 may also be the same as the number of sub-pixels SP1, SP2, and SP3.

[0109] A plurality of second through holes TSV2 may be provided in the through hole area TSA of the display part 200 and may be formed to overlap with the signal terminal area TDA of the driving part 100. The signal terminals STD (eg, see FIG. 1 ) connected to the driving part 100 may be connected to the signal terminals STD (eg, see FIG. 1 ). Figure 2 ) can be disposed in the second through-hole TSV2. Unlike the first through-hole TSV1, the second through-hole TSV2 can be formed to overlap the corresponding signal terminal STD of the driver 100. Therefore, the second routing wiring RM2 can also be disposed to correspond to and overlap the signal terminal STD. The second routing wiring RM2 can be a wiring that transmits signals applied from the circuit board 300 to the driver 100.

[0110] Figure 8 is a schematic cross-sectional view illustrating a display device according to one or more embodiments.

[0111] Reference Figure 8 In the display device 10 according to one or more embodiments, the connection line layer 500 may be provided between the display layer 230 and the second single crystal semiconductor substrate 210. Figure 6 and Figure 7The embodiment is different in that since the connection line layer 500 is disposed on the upper surface rather than the lower surface of the second single crystal semiconductor substrate 210 , the positions of the connection wiring RML, the conductive via RVA, and the first through via TSV1 are different.

[0112] The connection line layer 500 may be provided on the upper surface of the second single crystal semiconductor substrate 210. The interlayer insulating layer RINS (eg, see Figure 12 ) may be provided on the upper surface of the second single crystal semiconductor substrate 210.

[0113] According to one or more embodiments, a plurality of first through-vias TSV1 may overlap the driving unit 100 in the thickness direction (e.g., the third direction DR3), and a first routing wiring RM1 may be electrically connected to the sub-pixels SP1, SP2, and SP3 arranged throughout the display area DAA and may connect the first through-vias TSV1 with the sub-pixels SP1, SP2, and SP3 overlapping the driving unit 100. For example, a connection wiring RML of the first routing wiring RM1 may be concentrated in the region where the first through-vias TSV1 are provided and may connect a terminal connected to each of the sub-pixels SP1, SP2, and SP3 with a conductive via RVA provided in the first through-vias TSV1. In the display device 10, the plurality of first through-vias TSV1 and the conductive via RVA may each overlap the first single crystalline semiconductor substrate 110 in the thickness direction (e.g., the third direction DR3). On the other hand, at least a portion of the connection wiring RML may not overlap the first single crystalline semiconductor substrate 110 in the thickness direction (e.g., the third direction DR3).

[0114] As described above, the planar area of ​​the first single crystal semiconductor substrate 110 can be smaller than the planar area of ​​the second single crystal semiconductor substrate 210, and only some of the connection wiring RML provided throughout the second single crystal semiconductor substrate 210 can overlap with the first single crystal semiconductor substrate 110 in the thickness direction (e.g., the third direction DR3). Therefore, the connection wiring RML can be provided throughout the second single crystal semiconductor substrate 210, and the ends of the connection wiring RML, which includes multiple layers, can overlap with the first single crystal semiconductor substrate 110 in the thickness direction (e.g., the third direction DR3) and can be connected to the multiple through-holes TSV1 and conductive vias RVA. The connection wiring RML can form a path that electrically connects the light-emitting element provided on the entire surface of the display area DAA having a large area to the pixel circuit portion 800 having a relatively small area.

[0115] Hereinafter, the structures of the driving circuit layer 120 of the driving part 100 and the display layer 230 of the display part 200 will be described in detail with further reference to other drawings.

[0116] Figure 9is a schematic cross-sectional view of a driving portion according to one or more embodiments.

[0117] Reference Figure 9 The driving part 100 may include a first single crystal semiconductor substrate 110 and a driving circuit layer 120 disposed on the first single crystal semiconductor substrate 110 .

[0118] The first single crystal semiconductor substrate 110 may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The first single crystal semiconductor substrate 110 may be a substrate doped with first-type impurities. A plurality of well regions WA may be provided on the upper surface of the first single crystal semiconductor substrate 110. The plurality of well regions WA may be regions doped with second-type impurities. The second-type impurities may be different from the first-type impurities described above. For example, when the first-type impurities are p-type impurities, the second-type impurities may be n-type impurities. Alternatively, when the first-type impurities are n-type impurities, the second-type impurities may be p-type impurities.

[0119] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the first transistor PTR1 , a drain region DA corresponding to a drain electrode of the first transistor PTR1 , and a channel region CH disposed between the source region SA and the drain region DA.

[0120] The lower insulating film BINS may be provided between the gate electrode GE and the well area WA. The side insulating film SINS may be provided on the side surface of the gate electrode GE. The side insulating film SINS may be provided on the lower insulating film BINS.

[0121] Each of the source region SA and the drain region DA may be a region doped with first type impurities. The first transistor PTR1 (eg, Figure 5 The gate electrode GE of any of the transistors T1 to T6 in the transistor 1 may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be provided on one side of the gate electrode GE, and the drain region DA may be provided on the other side of the gate electrode GE.

[0122] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having an impurity concentration lower than that of the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 may be a region having an impurity concentration lower than that of the drain region DA due to the lower insulating film BINS. The first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2 can increase the distance between the source region SA and the drain region DA. Therefore, since the length of the channel region CH of each of the first transistors PTR1 can be increased, punch-through and hot carrier phenomena caused by a short channel can be prevented.

[0123] The first single crystalline semiconductor substrate 110 may include a plurality of first transistors PTR1 constituting a plurality of circuit elements of the driving portion 100. The first transistors PTR1 formed in the first single crystalline semiconductor substrate 110 may constitute the driving circuit portion 400, the gate driver 600, the data driver 700, or the pixel circuit portion 800.

[0124] When forming the driving circuit layer 120 on the silicon wafer substrate, a process may be performed to reduce the thickness of the first single crystal semiconductor substrate 110. The first single crystal semiconductor substrate 110 may have a thickness smaller than that of the wafer substrate on which the semiconductor process for forming the driving circuit layer 120 is performed. In one or more embodiments, the thickness of the first single crystal semiconductor substrate 110 may be 100 μm or less, for example, in the range of 80 μm to 100 μm.

[0125] The driving circuit layer 120 may include a first semiconductor insulating layer SINS1, a second semiconductor insulating layer SINS2, a plurality of contact electrodes CTE, a first interlayer insulating layer INS1, a second interlayer insulating layer INS2, a plurality of conductive layers ML1, ML2, ML3, ML4, ML5, ML6, ML7, and ML8, and a plurality of vias VA1, VA2, VA3, VA4, VA5, VA6, VA7, and VA8. The driving circuit layer 120 may include wiring electrically connected to the plurality of first transistors PTR1 included in the first single crystal semiconductor substrate 110.

[0126] The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may be provided on the first single crystal semiconductor substrate 110. The first semiconductor insulating layer SINS1 may be an insulating layer provided on the gate electrode GE of the first transistor PTR1 and the first single crystal semiconductor substrate 110, and the second semiconductor insulating layer SINS2 may be an insulating layer provided on the gate electrode GE of the first transistor PTR1 and the first semiconductor insulating layer SINS1. The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-based inorganic film, but is not limited thereto. The drawings illustrate that the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 are each formed as a single layer having a suitable thickness (e.g., a predetermined thickness), but the present disclosure is not limited thereto. The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may have a structure in which one or more layers are stacked one on top of the other.

[0127] A plurality of contact electrodes (CTEs) may be disposed on the first single crystalline semiconductor substrate 110. The plurality of contact electrodes (CTEs) may be connected to one of the gate electrode GE, source region SA, and drain region DA of each of the first transistors (PTR1) formed in the first single crystalline semiconductor substrate 110 via vias penetrating the first and second semiconductor insulating layers (SINS1, SINS2). The plurality of contact electrodes (CTEs) may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys including one or more of these. The plurality of contact electrodes (CTEs) may have upper surfaces exposed and uncovered by the first and second semiconductor insulating layers (SINS1, SINS2).

[0128] The first interlayer insulating layer INS1 may be disposed on the plurality of contact electrodes CTE and the first and second semiconductor insulating layers SINS1 and SINS2. The second interlayer insulating layer INS2 may be disposed on the first interlayer insulating layer INS1. The first and second interlayer insulating layers INS1 and INS2 may be made of silicon carbon nitride (SiCN) and / or silicon oxide (SiO x )-based inorganic film, but is not limited thereto. The drawings illustrate that the first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 are each formed as a single layer, but the present disclosure is not limited thereto. The first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 may also have a structure in which one or more layers are stacked on top of each other, and may be disposed between the plurality of first to eighth conductive layers ML1 to ML8, which will be described later.

[0129] The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may be electrically connected to the plurality of contact electrodes CTE and may form the driving circuit portion 400 or the data driver 700 of the driving part 100. The plurality of first transistors PTR1 formed in the first single crystal semiconductor substrate 110 may be electrically connected to each other through the first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 and may form the driving circuit portion 400 and the data driver 700 of the driving part 100.

[0130] The first conductive layer ML1 can be connected to the contact electrode CTE through a first via VA1. The first conductive layer ML1 can be disposed on the contact electrode CTE, and the first via VA1 can be disposed between the first conductive layer ML1 and the contact electrode CTE and can contact the first conductive layer ML1 and the contact electrode CTE, respectively. The second conductive layer ML2 can be connected to the first conductive layer ML1 through a second via VA2. The second conductive layer ML2 can be disposed on the first conductive layer ML1, and the second via VA2 can be disposed between the first conductive layer ML1 and the second conductive layer ML2 and can contact the first conductive layer ML1 and the second conductive layer ML2, respectively.

[0131] The third conductive layer ML3 can be connected to the second conductive layer ML2 via a third via VA3. The fourth conductive layer ML4 can be connected to the third conductive layer ML3 via a fourth via VA4, the fifth conductive layer ML5 can be connected to the fourth conductive layer ML4 via a fifth via VA5, and the sixth conductive layer ML6 can be connected to the fifth conductive layer ML5 via a sixth via VA6. The third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be sequentially disposed on the second conductive layer ML2, and the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 can be disposed between the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The third through sixth vias VA3 through VA6 can contact different metal layers disposed above and below the third through sixth vias VA3 through VA6, respectively. A seventh via VA7 can be disposed on the sixth conductive layer ML6. The seventh via VA7 can contact the seventh conductive layer ML7 and the sixth conductive layer ML6 disposed thereon, respectively.

[0132] The first to sixth conductive layers ML1 to ML6 and the first to seventh vias VA1 to VA7 may be disposed in the first interlayer insulating layer INS1. The first to sixth conductive layers ML1 to ML6 and the first to seventh vias VA1 to VA7 may constitute a first driving circuit layer of the driving circuit layer 120 disposed in the first interlayer insulating layer INS1.

[0133] The seventh conductive layer ML7 may be connected to the sixth conductive layer ML6 via a seventh via VA7. The seventh conductive layer ML7 may be disposed on the first interlayer insulating layer INS1 and the sixth conductive layer ML6. The seventh via VA7 may be disposed between the sixth and seventh conductive layers ML6 and may contact the sixth and seventh conductive layers ML6 and ML7, respectively. The eighth conductive layer ML8 may be connected to the seventh conductive layer ML7 via an eighth via VA8. The eighth conductive layer ML8 may be disposed on the seventh conductive layer ML7. The eighth via VA8 may be disposed between the seventh and eighth conductive layers ML7 and may contact the seventh and eighth conductive layers ML7 and ML8, respectively. The eighth conductive layer ML8 may have an upper surface exposed without being covered by the second interlayer insulating layer INS2 and may be electrically connected to the routing wiring (e.g., RM1, RM2) provided in the display portion 200 described above.

[0134] The seventh conductive layer ML7, the eighth via hole VA8, and the eighth conductive layer ML8 may be disposed in the second interlayer insulating layer INS2. The seventh conductive layer ML7, the eighth via hole VA8, and the eighth conductive layer ML8 may constitute a second driving circuit layer of the driving circuit layer 120 disposed in the second interlayer insulating layer INS2.

[0135] The drawings illustrate that the first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 have a structure in which the first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 are stacked one on top of the other. However, their arrangement and connection may be modified in various ways depending on the circuits of the driver circuit portion 400 and the data driver 700 of the driver unit 100. The connection structure shown in the drawings is merely an example, and the connection of the driver circuit layer 120 provided in the driver unit 100 of the display device 10 is not limited thereto. In addition, the driver circuit layer 120 may not necessarily include the first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8, and some of these layers may be omitted or a larger number of layers may be provided.

[0136] The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may be formed of substantially the same material. For example, the first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy including one or more thereof.

[0137] Each of the thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than each of the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. Each of the thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be substantially the same. For example, the thickness of the first conductive layer ML1 may be approximately 1360Å, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 may each be approximately 1440Å, and the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6 may each be 1150Å.

[0138] Each of the thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than each of the thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. Each of the thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than each of the thicknesses of the seventh via VA7 and the eighth via VA8. Each of the thicknesses of the seventh via VA7 and the eighth via VA8 may be greater than each of the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be substantially the same. For example, each of the thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be approximately 9000 Å. Each of the thicknesses of the seventh via VA7 and the eighth via VA8 may be about 6000 Å.

[0139] Figure 10 is a plan view illustrating first electrodes, light emitting regions, and pixel defining films of a plurality of sub-pixels provided in a display region of a display portion according to one or more embodiments.

[0140] Reference Figure 10Each of the plurality of pixels PX may include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3. The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may include emission areas EA1, EA2, and EA3, respectively. For example, the first subpixel SP1 may include a first emission area EA1, the second subpixel SP2 may include a second emission area EA2, and the third subpixel SP3 may include a third emission area EA3.

[0141] Each of the first, second, and third light-emitting areas EA1, EA2, and EA3 may have a quadrilateral planar shape such as a rectangle, a square, and / or a rhombus. For example, the third light-emitting area EA3 may have a rectangular planar shape having a short side in the first direction DR1 and a long side in the second direction DR2. In addition, each of the second and first light-emitting areas EA2 and EA1 may have a rectangular planar shape having a long side in the first direction DR1 and a short side in the second direction DR2.

[0142] Each of the first, second, and third emission areas EA1, EA2, and EA3 may be an area defined by the pixel definition film PDL. For example, each of the first, second, and third emission areas EA1, EA2, and EA3 may be an area defined by the first pixel definition film PDL1.

[0143] The length of the third light emitting area EA3 in the first direction DR1 may be smaller than that of the first light emitting area EA1 in the first direction DR1 and may be smaller than that of the second light emitting area EA2 in the first direction DR1. The length of the first light emitting area EA1 in the first direction DR1 and the length of the second light emitting area EA2 in the first direction DR1 may be substantially the same.

[0144] In each of the plurality of pixels PX, the first light-emitting area EA1 and the second light-emitting area EA2 may be adjacent to each other in the second direction DR2. Furthermore, the first light-emitting area EA1 and the third light-emitting area EA3 may be adjacent to each other in the first direction DR1. Furthermore, the second light-emitting area EA2 and the third light-emitting area EA3 may be adjacent to each other in the first direction DR1. The areas of the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3 may be different.

[0145] In the drawings, each of the first, second, and third light-emitting areas EA1, EA2, and EA3 is shown to have a quadrilateral planar shape, but the present disclosure is not limited thereto. For example, each of the first, second, and third light-emitting areas EA1, EA2, and EA3 may have a polygonal, circular, and / or elliptical planar shape in addition to a quadrilateral shape.

[0146] The first light-emitting area EA1 emits light of a first color, the second light-emitting area EA2 emits light of a second color, and the third light-emitting area EA3 emits light of a third color. Here, the first color of light may be light in a red wavelength band, the second color of light may be light in a green wavelength band, and the third color of light may be light in a blue wavelength band. For example, the blue wavelength band may indicate that the main peak wavelength of light is included in a wavelength band of approximately 370nm to 460nm, the green wavelength band may indicate that the main peak wavelength of light is included in a wavelength band of approximately 480nm to 560nm, and the red wavelength band may indicate that the main peak wavelength of light is included in a wavelength band of approximately 600nm to 750nm.

[0147] The first electrode AND of the light emitting element (for example, see Figure 12 ) may have a rectangular planar shape. In the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, the planar shapes of the first electrode AND of the light-emitting element may be different. For example, the first electrode AND of the first subpixel SP1 and the first electrode AND of the second subpixel SP2 may have a rectangular planar shape having a long side in the first direction DR1 and a short side in the second direction DR2. The first electrode AND of the third subpixel SP3 may have a rectangular planar shape having a short side in the first direction DR1 and a long side in the second direction DR2. The length of the first electrode AND of the third subpixel SP3 in the first direction DR1 may be shorter than the length of the first electrode AND of each of the first subpixel SP1 and the second subpixel SP2 in the second direction DR2. The length of the first electrode AND of the first subpixel SP1 in the second direction DR2 may be longer than the length of the first electrode AND of the second subpixel SP2 in the second direction DR2.

[0148] The first electrode AND of the light emitting element can be connected to the electrode via hole VAP (for example, see Figure 12 ) is connected to the reflective electrode layer (e.g., Figure 12 The electrode via VAP may overlap the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 in the third direction DR3.

[0149] At least one groove TRC (see, for example, Figure 12) may be a light emitting stack IL for disconnecting the light emitting areas EA1, EA2, and EA3 adjacent to each other (eg, see Figure 12 ) structure of at least one charge generation layer. At least one trench TRC may be provided between the first and second emission areas EA1 and EA2, between the first and third emission areas EA3, and between the second and third emission areas EA2 and EA3. More specifically, at least one trench TRC may be provided between the first electrode AND of the first subpixel SP1 and the first electrode AND of the second subpixel SP2, between the first electrode AND of the first subpixel SP1 and the first electrode AND of the third subpixel SP3, and between the first electrode AND of the second subpixel SP2 and the first electrode AND of the third subpixel SP3.

[0150] Figure 11 is a plan view illustrating first electrodes, light emitting regions, and pixel defining films of a plurality of sub-pixels provided in a display region of a display portion according to one or more embodiments.

[0151] Reference Figure 11 , because except for the plane shapes of the first light emitting area EA1, the second light emitting area EA2 and the third light emitting area EA3 Figure 10 In addition to the different embodiments, Figure 11 An embodiment of Figure 10 The embodiments are basically the same, so the Figure 10 The description of the embodiment is repeated.

[0152] The first, second, and third light-emitting areas EA1, EA2, and EA3 may be arranged in a hexagonal structure having a hexagonal planar shape. In this case, the first and second light-emitting areas EA1 and EA2 are adjacent to each other in the first direction DR1, but the second and third light-emitting areas EA2 and EA3 may be adjacent to each other in the first oblique direction DD1, and the first and third light-emitting areas EA1 and EA3 may be adjacent to each other in the second oblique direction DD2. The first oblique direction DD1, which is a direction between the first and second directions DR1 and DR2, may indicate a direction inclined 45 degrees relative to the first and second directions DR1 and DR2, and the second oblique direction DD2 may be a direction perpendicular to the first oblique direction DD1.

[0153] exist Figure 10 and Figure 11 , each of the plurality of pixels PX includes three emission areas EA1, EA2, and EA3, but the present disclosure is not limited thereto. That is, each of the plurality of pixels PX may also include four emission areas.

[0154] In addition, the arrangement of the light-emitting areas of the plurality of pixels PX is not limited to the arrangement shown in the drawings. For example, the light-emitting areas of the plurality of pixels PX may be arranged in a stripe structure in which the light-emitting areas are arranged along the first direction DR1, a PENTILE® structure in which the light-emitting areas have a diamond arrangement, and / or a hexagonal structure in which light-emitting areas having a hexagonal planar shape are arranged. This PENTILE® arrangement structure may be referred to as an RGBG matrix structure (e.g., a PENTILE® structure, a PENTILE® matrix structure, or an RGBG structure). PENTILE® is a registered trademark of Samsung Display Co., Ltd. of South Korea.

[0155] Figure 12 is a cross-sectional view illustrating a portion of a display portion according to one or more embodiments. Figure 12 A partial cross section of the display area DAA of the display portion 200 is shown.

[0156] Reference Figure 12 The display portion 200 may include a second single crystal semiconductor substrate 210, a display element layer EML, an encapsulation layer TFE, an adhesive layer ADL, a color filter layer CFL, a lens LNS, a filling layer FIL, and a cover layer DCL. The display element layer EML, the encapsulation layer TFE, the adhesive layer ADL, the color filter layer CFL, the lens LNS, the filling layer FIL, and the cover layer DCL of the display portion 200 may constitute a display layer 230. In one or more embodiments, the display portion 200 may further include a polarizing plate disposed on the cover layer DCL. The connecting line layer 500 may be disposed on the second single crystal semiconductor substrate 210 and the first single crystal semiconductor substrate 110 (see FIG. 2 ). Figure 6 Alternatively, the connection line layer 500 may be provided between the display element layer EML and the second single crystal semiconductor substrate 210 (see Figure 8 In one or more other embodiments, the connection line layer 500 may be disposed between the display element layer EML and the first single crystalline semiconductor substrate 110 .

[0157] The second single crystal semiconductor substrate 210 may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The second single crystal semiconductor substrate 210 may be a substrate doped with impurities. Unlike the first single crystal semiconductor substrate 110, transistors may not be formed in the second single crystal semiconductor substrate 210. The second single crystal semiconductor substrate 210 may serve as a lower substrate on which the display element layer EML is disposed, and may form a connection path on which the routing wiring RM1 electrically connects the light-emitting elements of the display element layer EML and the pixel circuit portion 800 of the driver 100.

[0158] As described above, the first single crystal semiconductor substrate 110 of the driver unit 100 can have a smaller planar area than the second single crystal semiconductor substrate 210 of the display unit 200 and can have small-sized components arranged with a high degree of integration, thereby reducing power consumption and improving manufacturing yield. On the other hand, a process having a larger planar area and a relatively large line width than the first single crystal semiconductor substrate 110 can be performed on the second single crystal semiconductor substrate 210 of the display unit 200. Unlike the circuit elements formed on the first single crystal semiconductor substrate 110, the elements of the display layer 230 formed on the second single crystal semiconductor substrate 210 may not require a high degree of integration. Therefore, the semiconductor process performed on the first wafer substrate can be performed as a high-cost process with a small line width, and the semiconductor process performed on the second wafer substrate can be performed as a low-cost process with a relatively large line width.

[0159] The second single crystalline semiconductor substrate 210 may include a plurality of first through-holes TSV1 spaced apart from one another (e.g., spaced apart). The first through-holes TSV1 may penetrate from the upper surface to the lower surface of the second single crystalline semiconductor substrate 210. A conductive via RVA of the first routing wiring RM1 may be disposed in the first through-holes TSV1. The first through-holes TSV1 may form a connection path for electrically connecting the pixel circuit portion 800 of the driving unit 100 and the first routing wiring RM1 of the light-emitting element of the display unit 200.

[0160] In one or more embodiments, the second single crystal semiconductor substrate 210 may include a plurality of second through holes TSV2 formed in the non-display area NA, and the conductive vias of the second routing wiring RM2 may be respectively disposed in the second through holes TSV2. The circuit board 300 and the signal terminal STD of the driving unit 100 may be electrically connected to each other through the second routing wiring RM2.

[0161] In one or more embodiments, the first through-holes TSV1 of the second single-crystalline semiconductor substrate 210 may be formed by a through-silicon via (TSV) process that forms a hole penetrating a wafer substrate. The display layer 230 and the driving unit 100 may be electrically connected to each other through the first through-holes TSV1 and the first routing wiring RM1 formed in the second single-crystalline semiconductor substrate 210 without a separate wire.

[0162] The process of reducing the thickness of the second single crystal semiconductor substrate 210 may be performed after forming the driving portion 100 on the silicon wafer substrate. The second single crystal semiconductor substrate 210 may have a thickness smaller than that of the wafer substrate on which the process for forming the conductive layer is performed. In one or more embodiments, the thickness of the second single crystal semiconductor substrate 210 may be 100 μm or less, for example, in the range of 80 μm to 100 μm.

[0163] The connection line layer 500 may be provided on a lower surface of the second single crystal semiconductor substrate 210. The connection line layer 500 may include an interlayer insulating layer RINS and a plurality of connection wirings RML.

[0164] An interlayer insulating layer RINS may be provided on the lower surface of the second single crystal semiconductor substrate 210. The interlayer insulating layer RINS may be made of silicon carbonitride (SiCN) and / or silicon oxide (SiO x )-based inorganic film, but not limited thereto. The interlayer insulating layers RINS are shown in the drawings as each formed of a single layer, but not limited thereto. The interlayer insulating layers RINS may have a structure in which one or more layers are stacked on top of each other, and these may be provided between the connection wirings RML.

[0165] The connection wiring RML may form routing wirings RM1 and RM2 together with the conductive vias RVA. The connection wiring RML may include one or more conductive layers and one or more vias connecting the conductive layers to each other. The connection and structure of the connection wiring RML may be similar to the description of the plurality of conductive layers ML1 to ML8 and the vias VA1 to VA8 described above (e.g., Figure 9 The connection wiring RML can be connected to the light emitting elements or the circuit board 300 of the sub-pixels SP1, SP2, and SP3 through the conductive vias RVA provided in the through-holes TSV1 and TSV2 of the second single crystal semiconductor substrate 210, and can each electrically connect the light emitting elements or the circuit board 300 to the driving circuit layer 120 of the driving unit 100.

[0166] The conductive via RVA of the first routing wiring RM1 may be provided in the first through-hole TSV1. The conductive via RVA of the first routing wiring RM1 may be provided in the first through-hole TSV1 extending from the lower surface of the reflective electrode layer RL to be described later to the lower surface of the second single crystal semiconductor substrate 210. The conductive via RVA may be electrically connected to the first electrode AND provided in each of the sub-pixels SP1, SP2, and SP3 through the reflective electrode layer RL and / or the electrode via VAP. The conductive via RVA may be connected to the reflective electrode layer RL and the connection wiring RML, respectively, and the connection wiring RML may be connected to the pixel circuit portion 800. The connection wiring RML may be in Figure 7 The first routing wiring RM1 may connect the light emitting element of each of the sub-pixels SP1, SP2, and SP3 to the pixel circuit portion 800 of the driving portion 100.

[0167] The display layer 230 may be disposed on the second single crystal semiconductor substrate 210. The display layer 230 may include a display element layer EML, an encapsulation layer TFE, an adhesive layer ADL, an optical layer OPL (including a color filter layer CFL, a lens LNS, and a filler layer FIL), and a cover layer DCL. The display layer 230 may include a light emitting element electrically connected to the driving unit 100 and emitting light.

[0168] The display element layer EML may be provided on the second single crystalline semiconductor substrate 210. The display element layer EML may include light emitting elements, each of which includes a reflective electrode layer RL, interlayer insulating layers INS3 and INS4, an electrode via VAP, a first electrode AND, a light emitting stack IL and a second electrode CAT, a pixel defining film PDL, and a plurality of trenches TRC.

[0169] The reflective electrode layer RL may be disposed on the second single crystal semiconductor substrate 210. The reflective electrode layer RL may include one or more reflective electrodes RL1, RL2, RL3, and RL4. Figure 12 As shown in , the reflective electrode layer RL may include a first reflective electrode RL1 , a second reflective electrode RL2 , a third reflective electrode RL3 , and a fourth reflective electrode RL4 .

[0170] Each of the first reflective electrodes RL1 may be disposed on the second single crystalline semiconductor substrate 210 and may be connected to a conductive via RVA disposed in the first through-hole TSV1. The first reflective electrodes RL1 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy including one or more thereof. For example, the first reflective electrodes RL1 may include titanium nitride (TiN).

[0171] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrodes RL2 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy including one or more thereof. For example, the second reflective electrodes RL2 may include aluminum (Al).

[0172] Each of the third reflective electrodes RL3 may be disposed on the second reflective electrode RL2. The third reflective electrodes RL3 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy including one or more thereof. For example, the third reflective electrodes RL3 may include titanium nitride (TiN).

[0173] Each of the fourth reflective electrodes RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrodes RL4 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy including one or more thereof. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0174] In one or more embodiments, the second reflective electrode RL2 may be an electrode that substantially reflects light from the light-emitting element. In one or more embodiments, the thickness of the second reflective electrode RL2 may be greater than the thickness of the first reflective electrode RL1, the thickness of the third reflective electrode RL3, and the thickness of the fourth reflective electrode RL4. For example, the thickness of the first reflective electrode RL1, the thickness of the third reflective electrode RL3, and the thickness of the fourth reflective electrode RL4 may be approximately 100 Å, and the thickness of the second reflective electrode RL2 may be approximately 850 Å. However, in one or more other embodiments, the thickness of the second reflective electrode RL2 may be substantially the same as the thickness of the first reflective electrode RL1, the thickness of the third reflective electrode RL3, and the thickness of the fourth reflective electrode RL4.

[0175] The third interlayer insulating layer INS3 may be provided on the second single crystal semiconductor substrate 210. The third interlayer insulating layer INS3 may be provided between adjacent reflective electrode layers RL. The third interlayer insulating layer INS3 may be provided on the reflective electrode layer RL in the first sub-pixel SP1. The third interlayer insulating layer INS3 may be made of silicon oxide (SiO x )-based inorganic film formation, but not limited to this.

[0176] The fourth interlayer insulating layer INS4 may be provided on the third interlayer insulating layer INS3 and the reflective electrode layer RL. The fourth interlayer insulating layer INS4 may be made of silicon oxide (SiO x )-based inorganic film formation, but not limited to this.

[0177] In at least one of the first to third subpixels SP1, SP2, and SP3, the third and fourth interlayer insulating layers INS3 and INS4 may not be disposed under the first electrode AND considering a resonance distance of light emitted from the light emitting element.

[0178] For example, the first electrode AND of the third subpixel SP3 may be directly disposed on the fourth reflective electrode RL4, and the first electrode AND of the third subpixel SP3 may not overlap the third interlayer insulating layer INS3 and the fourth interlayer insulating layer INS4. The first electrode AND of the second subpixel SP2 may be disposed on the fourth interlayer insulating layer INS4, and the fourth interlayer insulating layer INS4 may be directly disposed on the fourth reflective electrode RL4. In other words, the first electrode AND of the second subpixel SP2 may not overlap the third interlayer insulating layer INS3. The first electrode AND of the first subpixel SP1 may be disposed on the fourth interlayer insulating layer INS4 and may overlap the third interlayer insulating layer INS3.

[0179] In one or more embodiments, in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the distance between the first electrode AND and the reflective electrode layer RL may be different. In order to adjust the distance from the reflective electrode layer RL to the first electrode AND according to the main wavelength of light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence or absence of the third interlayer insulating layer INS3 and the fourth interlayer insulating layer INS4 may be set in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, in Figure 12 In the embodiment of the present invention, the distance between the first electrode AND and the reflective electrode layer RL in the first subpixel SP1 may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the third subpixel SP3, and the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the third subpixel SP3. However, the present disclosure is not limited thereto. In each of the subpixels SP1, SP2, and SP3, the distance between the first electrode AND and the reflective electrode layer RL may be modified and designed in various ways.

[0180] Each of the electrode vias VAP may be connected to the fourth reflective electrode RL4 exposed in the first and second sub-pixels SP1 and SP2 by penetrating the third interlayer insulating layer INS3 and / or the fourth interlayer insulating layer INS4. The electrode vias VAP may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy including one or more thereof. The thickness of the electrode vias VAP in the second sub-pixel SP2 may be smaller than that of the electrode vias VAP in the first sub-pixel SP1.

[0181] The first electrode AND of each light-emitting element can be disposed on the fourth interlayer insulating layer INS4 or the reflective electrode layer RL and can be connected to the electrode via VAP. The first electrode AND of each light-emitting element LE can be connected to the pixel circuit portion 800 via the electrode via VAP, the first to fourth reflective electrodes RL1 to RL4, and the first routing wiring RM1 (e.g., the connection via RVA and the connection wiring RML). The first electrode AND of each light-emitting element can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy including one or more of these. For example, the first electrode AND of each light-emitting element can be formed of titanium nitride (TiN).

[0182] The pixel definition film PDL may be provided in a partial region of the first electrode AND of each light emitting element. The pixel definition film PDL may cover the edge of the first electrode AND of each light emitting element. The pixel definition film PDL is used to divide the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3.

[0183] The first light emitting area EA1 may be defined as an area where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second light emitting area EA2 may be defined as an area where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third light emitting area EA3 may be defined as an area where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0184] The pixel definition film PDL may include a first pixel definition film PDL1, a second pixel definition film PDL2, and a third pixel definition film PDL3. The first pixel definition film PDL1 may be disposed at the edge of the first electrode AND of each of the light emitting elements LE, the second pixel definition film PDL2 may be disposed on the first pixel definition film PDL1, and the third pixel definition film PDL3 may be disposed on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 may be made of silicon oxide (SiO x Each of the thicknesses of the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may be approximately 500 Å.

[0185] When the first, second, and third pixel-defining layers (PDL1, PDL2, and PDL3) are formed into a single pixel-defining layer, the increased height of the pixel-defining layer may cause disconnection in the first inorganic encapsulation layer (TFE1) due to step coverage. Step coverage refers to the ratio of the extent (thickness) of film coating on inclined portions relative to the extent (thickness) of film coating on flat portions. As step coverage decreases, the likelihood of film disconnection on inclined portions increases.

[0186] To prevent disconnection of the first inorganic encapsulation layer TFE1 due to step coverage, the first, second, and third pixel-defining layers (PDL1, PDL2, and PDL3) may have a cross-sectional structure with a stepped height difference. For example, the width of the first pixel-defining layer (PDL1) may be greater than the widths of the second and third pixel-defining layers (PDL2 and PDL3), and the width of the second pixel-defining layer (PDL2) may be greater than the width of the third pixel-defining layer (PDL3). The width of the first pixel-defining layer (PDL1) refers to the horizontal length of the first pixel-defining layer (PDL1) defined by the first and second directions (DR1, DR2).

[0187] Each of the plurality of trenches TRC may penetrate the first to third pixel defining films PDL1, PDL2, and PDL3, may dig a portion of the third interlayer insulating layer INS3, and may penetrate the fourth interlayer insulating layer INS4.

[0188] At least one trench TRC may be provided between the sub-pixels SP1, SP2, and SP3 adjacent to each other. Figure 12 , two trenches TRC are shown to be provided between the sub-pixels SP1 , SP2 , and SP3 adjacent to each other, but the present disclosure is not limited thereto.

[0189] The light emitting stack IL may include a plurality of light emitting stacks IL1, IL2, and IL3. The drawings illustrate that the light emitting stack IL has a triple-series structure including a first light emitting stack IL1, a second light emitting stack IL2, and a third light emitting stack IL3, but the present disclosure is not limited thereto. For example, the light emitting stack IL may have a dual-series structure including two stacks.

[0190] In the triple-series structure, the light-emitting stack IL may have a series structure including a plurality of light-emitting stacks IL1, IL2, and IL3 that emit different lights. For example, the light-emitting stack IL may include a first light-emitting stack IL1 that emits light of a first color, a second light-emitting stack IL2 that emits light of a second color, and a third light-emitting stack IL3 that emits light of a third color. The first light-emitting stack IL1, the second light-emitting stack IL2, and the third light-emitting stack IL3 may be stacked sequentially.

[0191] The first light-emitting stack IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second light-emitting stack IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a second color, and a second electron transport layer are sequentially stacked. The third light-emitting stack IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of a third color, and a third electron transport layer are sequentially stacked.

[0192] A first charge generation layer for supplying holes to the second light-emitting stack IL2 and electrons to the first light-emitting stack IL1 may be provided between the first light-emitting stack IL1 and the second light-emitting stack IL2. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first light-emitting stack IL1 and a P-type charge generation layer for supplying holes to the second light-emitting stack IL2. The N-type charge generation layer may include a dopant of a metal material.

[0193] A second charge generation layer for supplying holes to the third light-emitting stack IL3 and electrons to the second light-emitting stack IL2 may be provided between the second light-emitting stack IL2 and the third light-emitting stack IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second light-emitting stack IL2 and a P-type charge generation layer for supplying holes to the third light-emitting stack IL3.

[0194] The first light-emitting stack IL1 may be disposed on the first electrode AND and the pixel-defining film PDL and may be disposed on the bottom surface of each of the trenches TRC. Due to the trenches TRC, the first light-emitting stack IL1 may be disconnected between adjacent sub-pixels SP1, SP2, and SP3. The second light-emitting stack IL2 may be disposed on the first light-emitting stack IL1. Due to the trenches TRC, the second light-emitting stack IL2 may be disconnected between adjacent sub-pixels SP1, SP2, and SP3. A cavity or empty space ESS may be disposed between the first light-emitting stack IL1 and the second light-emitting stack IL2. The third light-emitting stack IL3 may be disposed on the second light-emitting stack IL2. The third light-emitting stack IL3 may not be disconnected by the trenches TRC and may be disposed so as to cover the second light-emitting stack IL2 in each of the trenches TRC. That is, in the three-series structure, each of the plurality of trenches TRC may be a structure for disconnecting the first and second light-emitting stacks IL1 and IL2, and the first and second charge generation layers, of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3. In addition, in the two-series structure, each of the plurality of trenches TRC may be a structure for disconnecting the charge generation layer provided between the lower intermediate layer and the upper intermediate layer from the lower intermediate layer.

[0195] In order to stably disconnect the first light-emitting stack IL1 and the second light-emitting stack IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of grooves TRC may be greater than the height of the pixel-defining film PDL. The height of each of the plurality of grooves TRC represents the length of each of the plurality of grooves TRC in the third direction DR3. The height of the pixel-defining film PDL represents the length of the pixel-defining film PDL in the third direction DR3. In order to disconnect the first light-emitting stack IL1, the second light-emitting stack IL2, and the third light-emitting stack IL3 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, other structures may be used instead of the grooves TRC. For example, instead of the grooves TRC, a partition wall having an inverted tapered shape may be provided on the pixel-defining film PDL.

[0196] The number of light-emitting stacks IL1, IL2, and IL3 that emit different light is not limited to the number shown in the drawings. For example, the light-emitting stack IL may include two intermediate layers. In this case, one of the two intermediate layers may be substantially identical to the first light-emitting stack IL1, and the other may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge generation layer may be provided between the two intermediate layers to supply electrons to one intermediate layer and holes to the other intermediate layer.

[0197] In addition, Figure 12 , the first light-emitting stack IL1, the second light-emitting stack IL2, and the third light-emitting stack IL3 are all disposed in the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3, but the present disclosure is not limited thereto. For example, the first light-emitting stack IL1 may be disposed in the first light-emitting area EA1 and may not be disposed in the second light-emitting area EA2 and the third light-emitting area EA3. In addition, the second light-emitting stack IL2 may be disposed in the second light-emitting area EA2 and may not be disposed in the first light-emitting area EA1 and the third light-emitting area EA3. In addition, the third light-emitting stack IL3 may be disposed in the third light-emitting area EA3 and may not be disposed in the first light-emitting area EA1 and the second light-emitting area EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0198] The second electrode CAT may be disposed on the third light-emitting stack IL3. The second electrode CAT may be disposed on the third light-emitting stack IL3 in each of the plurality of trenches TRC. The second electrode CAT may be formed of a transparent conductive material (TCO) capable of transmitting light, such as ITO and / or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), and / or an alloy of magnesium (Mg) and silver (Ag). When the second electrode CAT is formed of a semi-transmissive conductive material, light emission efficiency can be increased in each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 through the microcavity.

[0199] The encapsulation layer TFE may be disposed on the display element layer EML. The encapsulation layer TFE may include one or more inorganic encapsulation layers TFE1 and TFE3 to prevent oxygen and / or moisture from penetrating into the display element layer EML. In addition, the encapsulation layer TFE may include at least one organic film to protect the display element layer EML from foreign matter such as dust. For example, the encapsulation layer TFE may include a first inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and a second inorganic encapsulation layer TFE3.

[0200] The first inorganic encapsulation layer TFE1 may be disposed on the second electrode CAT, the organic encapsulation layer TFE2 may be disposed on the first inorganic encapsulation layer TFE1, and the second inorganic encapsulation layer TFE3 may be disposed on the organic encapsulation layer TFE2. The first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 may be formed as a silicon nitride layer (SiN x ), silicon oxynitride layer (SiON), silicon oxide layer (SiO x ), titanium oxide layer (TiO x ) and aluminum oxide layer (AlO x ) in a multilayer film alternately stacked with one or more inorganic films. The organic encapsulation layer TFE2 can be a monomer. Alternatively, the organic encapsulation layer TFE2 can be an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin and / or polyimide resin.

[0201] The adhesive layer ADL may be provided on the encapsulation layer TFE. The adhesive layer ADL may be a layer for adhering the encapsulation layer TFE to the layer provided thereon. The adhesive layer ADL may be a double-sided adhesive member. Alternatively, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive and / or a transparent adhesive resin.

[0202] The optical layer OPL may include a color filter layer CFL, a plurality of lenses LNS, and a filling layer FIL. The color filter layer CFL may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the adhesive layer ADL.

[0203] The first color filter CF1 may overlap the first light emitting area EA1. The first color filter CF1 may transmit light of the first color (i.e., light in the red wavelength band). The red wavelength band may be approximately 600 nm to 750 nm. The first color filter CF1 may transmit light of the first color among the light emitted from the first light emitting area EA1.

[0204] The second color filter CF2 may overlap the second light emitting area EA2. The second color filter CF2 may transmit light of the second color (i.e., light in the green wavelength band). The green wavelength band may be approximately 480 nm to 560 nm. The second color filter CF2 may transmit light of the second color among the light emitted from the second light emitting area EA2.

[0205] The third color filter CF3 may overlap the third light emitting area EA3. The third color filter CF3 may transmit light of a third color (i.e., light in a blue wavelength band). The blue wavelength band may be approximately 370 nm to 460 nm. The third color filter CF3 may transmit light of the third color among the light emitted from the third light emitting area EA3.

[0206] Each of the plurality of lenses LNS may be disposed on each of the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS may be a structure for increasing the ratio of light guided to the front of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape that is convex in an upward direction.

[0207] A filling layer FIL may be provided on the plurality of lenses LNS. The filling layer FIL may have a suitable refractive index (e.g., a predetermined refractive index) such that light travels in the third direction DR3 at the interface between the plurality of lenses LNS and the filling layer FIL. Alternatively, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film made of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and / or a polyimide resin.

[0208] The cover layer DCL may be disposed on the filling layer FIL. The cover layer DCL may be a glass substrate and / or a polymer resin such as resin. When the cover layer DCL is a glass substrate, the cover layer DCL may be attached to the filling layer FIL. In this case, the filling layer FIL may be used to bond the cover layer DCL. When the cover layer DCL is a glass substrate, the cover layer DCL may serve as an encapsulation substrate. When the cover layer DCL is a polymer resin such as resin, the cover layer DCL may be applied directly to the filling layer FIL.

[0209] In one or more embodiments, the display portion 200 may further include a polarizing plate disposed on the cover layer DCL. The polarizing plate may be disposed on one surface of the cover layer DCL. The polarizing plate may be a structure for preventing visibility degradation due to reflection of external light. The polarizing plate may include a linear polarizing plate and / or a phase retarder film. For example, the phase retarder film may be a λ / 4 (quarter wavelength) plate, but is not limited thereto. However, if visibility degradation due to reflection of external light is sufficiently improved by the first, second, and third color filters CF1, CF2, and CF3, the polarizing plate may be omitted.

[0210] Figure 13 is a diagram illustrating a schematic arrangement of connection wirings connecting a pixel circuit portion of a display device and sub-pixels of a display region according to one or more embodiments. Figure 13 The relative arrangement of the connection wiring RML connecting the pixel circuit portion 800 included in the drive section 100 of the display device 10 and the display area DAA of the display section 200 is shown.

[0211] Reference Figure 13 In the display device 10 according to one or more embodiments, the driving unit 100 and the display unit 200 may have different areas, and the pixel circuit portion 800 and the display area DAA may also have different areas. However, the plurality of pixel circuits (in Figure 5 The PXC in the display area DAA) can each be connected to multiple sub-pixels in the display area DAA Figure 3 The plurality of pixel circuits and the plurality of sub-pixels may be connected to each other via connection wirings RML, corresponding to the plurality of sub-pixels SP1, SP2, and SP3 in the display unit 200. In one or more embodiments, the number of pixel circuits PXC provided in the driver unit 100 of the display device 10 may be the same as the number of sub-pixels SP1, SP2, and SP3 in the display unit 200. The number of each of the pixel circuits PXC and the number of sub-pixels SP1, SP2, and SP3 may be the same as the number of connection wirings RML and first through-vias TSV1 formed in the second single crystal semiconductor substrate 210.

[0212] The connection wiring RML of the connection line layer 500 can connect the pixel circuit PXC and the sub-pixels SP1, SP2 and SP3 to correspond to each other. The plurality of connection wirings RML can be set so that the pixel circuit PXC provided in the pixel circuit portion 800 having a small area corresponds to the sub-pixels SP1, SP2 and SP3 provided in the display area DAA having a large area. In addition, some of the sub-pixels SP1, SP2 and SP3 of the display area DAA may overlap with the pixel circuit portion 800, and others may not overlap with the pixel circuit portion 800. Therefore, some of the connection wirings RML may be set to extend from the pixel circuit portion 800 to an area of ​​the display area DAA that does not overlap with the pixel circuit portion 800, and other connection wirings RML may be set in an area of ​​the display area DAA that overlaps with the pixel circuit portion 800. In the area of ​​the display area DAA that does not overlap the pixel circuit portion 800, the gaps between the connection wirings RML are wide, but as the connection wirings RML are concentrated in the area of ​​the display area DAA that overlaps the pixel circuit portion 800, the gaps between the connection wirings RML may be narrow. According to one or more embodiments, the connection wirings RML may include a plurality of bridge lines RBL1, RBL2, and RBL3 and bridge contacts RCT1, RCT2, and RCT3 provided at different layers (for example, see Figure 15 ), and even if the bridge lines RBL1, RBL2, and RBL3 are disposed adjacent to each other in a plan view, the bridge lines RBL1, RBL2, and RBL3 may be disposed at different layers, thereby preventing electrical interference.

[0213] Hereinafter, a more detailed structure of the connection wiring RML will be described with reference to other drawings.

[0214] Figure 14 is a schematic diagram illustrating connections between sub-pixels and pixel circuits through connection wiring of a display device according to one or more embodiments. Figure 14 The sub-pixels SP (eg, Figure 3 The relative arrangement of the sub-pixels SP1, SP2, and SP3 in the pixel circuit section 800 and the pixel circuit PXC of the pixel circuit section 800 and the arrangement design of the connection wiring RML corresponding thereto are also described.

[0215] Reference Figure 14The pixel circuit portion 800 may include a plurality of pixel circuits PXC, and the plurality of pixel circuits PXC may be arranged along a first direction DR1 and a second direction DR2. The pixel circuits PXC may include a first circuit column PC1, a second circuit column PC2, a third circuit column PC3, a fourth circuit column PC4, a fifth circuit column PC5, a sixth circuit column PC6, a seventh circuit column PC7, and an eighth circuit column PC8 arranged along the first direction DR1, and a first circuit row PR1, a second circuit row PR2, a third circuit row PR3, a fourth circuit row PR4, a fifth circuit row PR5, a sixth circuit row PR6, a seventh circuit row PR7, and an eighth circuit row PR8 arranged along the second direction DR2. Figure 14 An arrangement of a total of 64 pixel circuits PXC in 8 circuit columns and 8 circuit rows is shown.

[0216] The display portion 200 may include a plurality of sub-pixels SP disposed in a display area DAA, and the plurality of sub-pixels SP may also be arranged along a first direction DR1 and a second direction DR2. The pixel circuit PXC may include a first pixel column EC1, a second pixel column EC2, a third pixel column EC3, a fourth pixel column EC4, a fifth pixel column EC5, a sixth pixel column EC6, a seventh pixel column EC7, and an eighth pixel column EC8 arranged along the first direction DR1, and a first pixel row ER1, a second pixel row ER2, a third pixel row ER3, a fourth pixel row ER4, a fifth pixel row ER5, a sixth pixel row ER6, a seventh pixel row ER7, and an eighth pixel row ER8 arranged along the second direction DR2. Figure 14 8 pixel columns and 8 pixel rows, a total of 64 sub-pixels SP are arranged. Among the plurality of sub-pixels SP, 16 sub-pixels SP belonging to the first pixel row ER1, the second pixel row ER2, the third pixel row ER3, and the fourth pixel row ER4 and belonging to the fifth pixel column EC5, the sixth pixel column EC6, the seventh pixel column EC7, and the eighth pixel column EC8 may overlap with the pixel circuit portion 800. The other sub-pixels SP may not overlap with the pixel circuit portion 800.

[0217] As described above, the 64 pixel circuits PXC of the pixel circuit portion 800 can each correspond to the 64 sub-pixels SP of the display area DAA, and the 64 pixel circuits PXC and the 64 sub-pixels SP can be connected to each other through the connection wiring RML. The sub-pixels SP arranged in the first pixel row ER1 arranged along the first direction DR1 of the pixel circuit portion 800 can be connected to the pixel circuit PXC through the connection wiring RML extending approximately in the first direction DR1. The sub-pixels SP arranged in the eighth pixel column EC8 arranged along the second direction DR2 of the pixel circuit portion 800 can be connected to the pixel circuit PXC through the connection wiring RML extending approximately in the second direction DR2. The sub-pixels SP arranged in the oblique direction between the first direction DR1 and the second direction DR2 of the pixel circuit portion 800 can be connected to the pixel circuit PXC through the connection wiring RML extending approximately in the oblique direction. In one or more embodiments, other sub-pixels SP can also be connected to the pixel circuit PXC through the connection wiring RML.

[0218] Although the drawings show the connection wirings RML connecting some sub-pixels SP and pixel circuits PXC, an equal number of connection wirings RML corresponding to the sub-pixels SP and pixel circuits PXC may be provided. Figure 14 For example, as shown in the portion shown in FIG. Figure 14 As shown in FIG, 64 connection wirings RML may be provided in the corresponding region. In addition to the 12 connection wirings RML shown in the drawing, a total of 52 connection wirings RML may be provided to correspond to each sub-pixel SP and pixel circuit PXC.

[0219] When the connection wirings RML are arranged according to a random rule to connect the sub-pixels SP and the pixel circuits PXC, interference may occur between the adjacent connection wirings RML. However, by separating the connection wirings RML from the bridge wires arranged at different layers and arranging the bridge wires at different layers or arranging the bridge wires sequentially according to distance, the interference between the connection wirings RML can be reduced or minimized.

[0220] Figure 15 is a schematic cross-sectional view illustrating an example of a connection line layer of a display device according to one or more embodiments.

[0221] Reference Figure 15The connection line layer 500 of the display device 10 may include multiple conductive layers and interlayer insulating layers RINS1, RINS2, and RINS3 between the multiple conductive layers. The first interlayer insulating layer RINS1 may be disposed on the driving circuit layer 120, and the second interlayer insulating layer RINS2 and the third interlayer insulating layer RINS3 may be sequentially disposed on the first interlayer insulating layer RINS1. The second single crystal semiconductor substrate 210 may be disposed on the third interlayer insulating layer RINS3. The first conductive layer of the connection line layer 500 may be disposed on the first interlayer insulating layer RINS1, the second conductive layer of the connection line layer 500 may be disposed on the second interlayer insulating layer RINS2, and the third conductive layer of the connection line layer 500 may be disposed on the third interlayer insulating layer RINS3.

[0222] The first conductive layer may include a first bridge line RBL1 and a plurality of first bridge contacts RCT1, the second conductive layer may include a second bridge line RBL2 and a plurality of second bridge contacts RCT2, and the third conductive layer may include a third bridge line RBL3 and a plurality of third bridge contacts RCT3. Since the plurality of bridge lines RBL1, RBL2, and RBL3 include interlayer insulating layers RINS1, RINS2, and RINS3 disposed therebetween, the plurality of bridge lines RBL1, RBL2, and RBL3 may be electrically insulated even though the plurality of bridge lines RBL1, RBL2, and RBL3 are disposed adjacent to each other.

[0223] In the display device 10, the connection wiring RML may include bridge lines RBL1, RBL2, and RBL3, bridge contacts RCT1, RCT2, and RCT3, and bridge vias between the bridge lines RBL1, RBL2, and RBL3 and the bridge contacts RCT1, RCT2, and RCT3. The connection wiring RML may be connected to the reflective electrode layer RL of the display layer 230 through a conductive via RVA provided in the first through hole TSV1 of the second single crystal semiconductor substrate 210.

[0224] For example, a connection wiring RML may include one bridge wire from among a plurality of bridge wires RBL1, RBL2, and RBL3 and two bridge contacts from among a plurality of bridge contacts RCT1, RCT2, and RCT3. The first bridge wire RBL1 may be connected to the conductive via RVA via the second bridge contact RCT2 and the third bridge contact RCT3. In addition, the first bridge wire RBL1 may be connected to the drive circuit layer 120 via the bridge via. The second bridge wire RBL2 may be connected to the drive circuit layer 120 via the first bridge contact RCT1 and may be connected to the conductive via RVA via the third bridge contact RCT3. The third bridge wire RBL3 may be connected to the conductive via RVA and may be connected to the drive circuit layer 120 via the second bridge contact RCT2 and the first bridge contact RCT1.

[0225] One side of each of the plurality of bridge lines RBL1, RBL2, and RBL3 may overlap with a subpixel SP or a reflective electrode layer RL of the display unit 200, and the other side of each of the plurality of bridge lines RBL1, RBL2, and RBL3 may overlap with a pixel circuit PXC of the driving circuit layer 120 of the driving unit 100. A connection wiring RML may include one bridge line from among the plurality of bridge lines RBL1, RBL2, and RBL3 and one or more bridge contacts RCT1, RCT2, and RCT3 at both ends of the bridge lines RBL1, RBL2, and RBL3. One bridge line from among the plurality of bridge lines RBL1, RBL2, and RBL3 may be provided to extend between a pair of connected subpixels SP and pixel circuits PXC, and may be electrically connected to the subpixels SP and pixel circuits PXC via the bridge contacts RCT1, RCT2, and RCT3 at both ends of the corresponding bridge lines RBL1, RBL2, and RBL3.

[0226] Figure 16 is a schematic cross-sectional view illustrating an example of a connection line layer of a display device according to one or more embodiments.

[0227] Reference Figure 16 In one or more embodiments in which the connection line layer 500 is disposed on the second single crystalline semiconductor substrate 210, the first conductive layer of the connection line layer 500 may be disposed on the second single crystalline semiconductor substrate 210. The reflective electrode layer RL of the display element layer EML may be disposed on the third interlayer insulating layer RINS3. The first conductive layer of the connection line layer 500 may be connected to the driving circuit layer 120 or the pixel circuit PXC of the driving unit 100 via a conductive via RVA, and the third conductive layer may be connected to the reflective electrode layer RL via a bridge via.

[0228] Different connection wirings RML in display device 10 can vary the position of the conductive layer on which bridge lines RBL1, RBL2, and RBL3 are provided, and can also vary the length and / or extension direction of bridge lines RBL1, RBL2, and RBL3. Furthermore, different connection wirings RML can also vary the position of bridge contacts RCT1, RCT2, and RCT3, or the bridge vias connected to both ends of bridge lines RBL1, RBL2, and RBL3. Display device 10 can prevent or reduce interference between adjacent connection wirings RML by differently designing the positions of the conductive layers on which bridge lines RBL1, RBL2, and RBL3 of connection wiring RML are provided.

[0229] In addition, the display device 10 can have an arrangement design that secures sufficient space in a plan view so that when the connection wirings RML are concentrated and disposed in the pixel circuit portion 800 having a small area, the connection wirings RML are not disposed too close to each other.

[0230] Figure 17 and Figure 18 It is shown by Figure 14 Schematic diagram of connection between sub-pixels and pixel circuits using connection wiring in the first region. Figure 17 and Figure 18 Arrangement of bridge lines RBL1, RBL2, and RBL3 of a connection wiring RML connecting a first pixel row ER1 and a second pixel row ER2 arranged along a first direction DR1 of the pixel circuit portion 800 among sub-pixels SP provided in the display area DAA to the pixel circuit PXC is shown.

[0231] Reference Figure 17 and Figure 18 , the sub-pixel SP farthest from the pixel circuit portion 800 among the sub-pixels SP or the sub-pixel SP disposed at the outermost portion of the display area DAA can be connected to the pixel circuit PXC disposed at the outermost portion of the pixel circuit portion 800. The sub-pixels SP sequentially disposed inside from the outermost sub-pixel SP can be respectively connected to the pixel circuit PXC sequentially disposed inside from the outermost pixel circuit PXC. For example, the sub-pixel SP disposed in the first pixel column EC1 of the first pixel row ER1 can be connected to the pixel circuit PXC of the first circuit column PC1 of the first circuit row PR1. The other sub-pixels SP of the first pixel row ER1 can be respectively connected to the pixel circuit PXC of the first circuit row PR1. The sub-pixel SP disposed in the first pixel column EC1 of the second pixel row ER2 can be connected to the pixel circuit PXC of the first circuit column PC1 of the second circuit row PR2. The other sub-pixels SP of the second pixel row ER2 can be respectively connected to the pixel circuit PXC of the second circuit row PR2.

[0232] Among the subpixels SP arranged in the first pixel row ER1, the four subpixels SP that do not overlap the pixel circuit portion 800 can be arranged to extend outside the pixel circuit portion 800 via bridge lines RBL1, RBL2, and RBL3 of the connection wiring RML. Specifically, the outermost first subpixel SP#1 in the display area DAA can be connected to the pixel circuit PXC via a connection wiring including a first bridge line RBL1 arranged in the first conductive layer of the connection wiring layer 500. The second subpixel SP#2, adjacent to the first subpixel SP#1 in the first direction DR1, can be connected to the pixel circuit PXC via a connection wiring including a second bridge line RBL2 arranged in the second conductive layer of the connection wiring layer 500. The third subpixel SP#3, adjacent to the second subpixel SP#2 in the first direction DR1, can be connected to the pixel circuit PXC via a connection wiring including a third bridge line RBL3 arranged in the third conductive layer of the connection wiring layer 500. The fourth subpixel SP#4, adjacent to the third subpixel SP#3 in the first direction DR1, can be connected to the pixel circuit PXC via a connection wiring including a first bridge line RBL1 arranged in the first conductive layer of the connection wiring layer 500. The four sub-pixels SP may be respectively connected to the pixel circuit PXC through connection wirings including bridge lines RBL1 , RBL2 , and RBL3 provided at a layer different from other sub-pixels SP adjacent to each other.

[0233] Furthermore, the first bridge line RBL1 connected to the outermost first subpixel SP#1 in the display area DAA can be connected to the pixel circuit PXC of the pixel circuit section 800 via the second subpixel SP#2, the third subpixel SP#3, and the fourth subpixel SP#4. The second bridge line RBL2 connected to the second subpixel SP#2 can also be connected to the pixel circuit PXC of the pixel circuit section 800 via the third subpixel SP#3 and the fourth subpixel SP#4. In other words, it is desirable to ensure space for arranging at least four bridge lines RBL1, RBL2, and RBL3 in the fourth subpixel SP#4. Considering this, the first bridge line RBL1 connected to the outermost first subpixel SP#1 among the multiple bridge lines RBL1, RBL2, and RBL3 can be arranged offset from the center of the first subpixel SP#1 downward, the downward side being the other side in the second direction DR2. The second bridge line RBL2 and the third bridge line RBL3 can be arranged sequentially from the first bridge line RBL1 to the upper side, the upper side being one side in the second direction DR2. That is, compared with the bridge lines RBL1, RBL2, RBL3 connected to the sub-pixels SP arranged inside the above-mentioned sub-pixels SP, the bridge lines RBL1, RBL2, RBL3 connected to the sub-pixels SP arranged on the relatively outer side can be set to deviate to one side from the center of the corresponding sub-pixel SP.

[0234] Therefore, the positions of the ends of the bridge lines RBL1, RBL2, and RBL3, which serve as starting points, within the four sub-pixels SP of the first pixel row ER1, may be different from one another. For example, the position of the end of the first bridge line RBL1 in the outermost first sub-pixel SP#1 may be different from the position of the end of the second bridge line RBL2 in the second sub-pixel SP#2 adjacent to the first sub-pixel SP#1 in the first direction DR1, and the relative positions within each of the corresponding sub-pixels SP may also be different.

[0235] Among the sub-pixels SP arranged in the second pixel row ER2, the four sub-pixels SP that do not overlap with the pixel circuit portion 800 may also be arranged to extend outside the pixel circuit portion 800 through the bridge lines RBL1, RBL2, and RBL3 of the connection wiring RML. The first sub-pixel SP#1, the second sub-pixel SP#2, the third sub-pixel SP#3, and the fourth sub-pixel SP#4 of the second pixel row ER2 may also be connected to the pixel circuit PXC of the second circuit row PR2 through the connection wiring RML including the first bridge line RBL1, the second bridge line RBL2, the third bridge line RBL3, and the first bridge line RBL1, respectively.

[0236] The sub-pixels SP of the first pixel row ER1 can be connected to the first circuit row PR1 parallel to the first direction DR1 (e.g., aligned in the first direction DR1). On the other hand, the sub-pixels SP of the second pixel row ER2 can be connected to the second circuit row PR2, but may not be parallel to each other (e.g., aligned) in the first direction DR1. Therefore, the bridge lines RBL1, RBL2, and RBL3 connected to the second pixel row ER2 can extend in an oblique direction. However, since the bridge lines RBL1, RBL2, and RBL3 connected to the first pixel row ER1 are arranged to be biased toward the bottom side in the sub-pixels SP, sufficient space can be ensured so that the bridge lines RBL1, RBL2, and RBL3 connected to the sub-pixels SP of the second pixel row ER2 extend and are arranged in an oblique direction.

[0237] This can be similarly applied to the sub-pixels SP in the first pixel row ER1 and the second pixel row ER2 that overlap with the pixel circuit portion 800. For example, the sub-pixels SP in the fifth pixel column EC5, the sixth pixel column EC6, the seventh pixel column EC7, and the eighth pixel column EC8 in the first pixel row ER1 and the second pixel row ER2 can be connected to the pixel circuit PXC through the connection wiring RML or the bridge wirings RBL1, RBL2, and RBL3 that overlap with the pixel circuit portion 800. As described above, other sub-pixels SP adjacent to each other can be connected to the pixel circuit PXC through the connection wiring RML including the bridge wirings RBL1, RBL2, and RBL3 of different layers, and the bridge wirings RBL1, RBL2, and RBL3 connected to the sub-pixels SP disposed on the relatively outer portion can be disposed to deviate to one side from the center of the corresponding sub-pixel SP, as compared to the bridge wirings RBL1, RBL2, and RBL3 connected to the sub-pixels SP disposed inside the above-mentioned sub-pixels SP.

[0238] Figure 19 and Figure 20 It is shown by Figure 14 Schematic diagram of connection between sub-pixels and pixel circuits using connection wiring in the second region. Figure 19 and Figure 20 Arrangement of bridge lines RBL1, RBL2, and RBL3 of the connection wiring RML is shown, which connects the seventh pixel column EC7 and the eighth pixel column EC8 arranged along the second direction DR2 of the pixel circuit part 800 among the sub-pixels SP arranged in the display area DAA to the pixel circuit PXC.

[0239] Reference Figure 19 and Figure 20 , the sub-pixels SP arranged in the inner part sequentially from the outermost sub-pixel SP can be respectively connected to the pixel circuits PXC arranged in the inner part sequentially from the outermost pixel circuit PXC. For example, the sub-pixel SP arranged in the eighth pixel row ER8 of the eighth pixel column EC8 can be connected to the pixel circuit PXC of the eighth circuit row PR8 of the eighth circuit column PC8. The other sub-pixels SP of the eighth pixel column EC8 can be respectively connected to the pixel circuit PXC of the eighth circuit column PC8. The sub-pixels SP arranged in the eighth pixel row ER8 of the seventh pixel column EC7 can be connected to the pixel circuit PXC of the eighth circuit row PR8 of the seventh circuit column PC7. The other sub-pixels SP of the seventh pixel column EC7 can be respectively connected to the pixel circuit PXC of the seventh circuit column PC7.

[0240] Among the subpixels SP arranged in the eighth pixel column EC8, the four subpixels SP that do not overlap the pixel circuit portion 800 can be arranged to extend outside the pixel circuit portion 800 via bridge lines RBL1, RBL2, and RBL3 of the connection wiring RML. Specifically, the outermost first subpixel SP#1 in the display area DAA can be connected to the pixel circuit PXC via a connection wiring comprising the first bridge line RBL1 of the connection wiring layer 500. The second subpixel SP#2, which is adjacent to the first subpixel SP#1 in the second direction DR2, can be connected to the pixel circuit PXC via a connection wiring comprising the second bridge line RBL2 of the connection wiring layer 500. The third subpixel SP#3, which is adjacent to the second subpixel SP#2 in the second direction DR2, can be connected to the pixel circuit PXC via a connection wiring comprising the third bridge line RBL3 of the connection wiring layer 500. The fourth subpixel SP#4, which is adjacent to the third subpixel SP#3 in the second direction DR2, can be connected to the pixel circuit PXC via a connection wiring comprising the first bridge line RBL1 of the connection wiring layer 500. The four sub-pixels SP may be respectively connected to the pixel circuit PXC through connection wirings including bridge lines RBL1 , RBL2 , and RBL3 provided at a layer different from other sub-pixels SP adjacent to each other.

[0241] Furthermore, the first bridge line RBL1 connected to the outermost first subpixel SP#1 in the display area DAA can be connected to the pixel circuit PXC of the pixel circuit section 800 via the second subpixel SP#2, the third subpixel SP#3, and the fourth subpixel SP#4. The second bridge line RBL2 connected to the second subpixel SP#2 can also be connected to the pixel circuit PXC of the pixel circuit section 800 via the third subpixel SP#3 and the fourth subpixel SP#4. In other words, it is desirable to ensure space for arranging at least four bridge lines RBL1, RBL2, and RBL3 in the fourth subpixel SP#4. Considering this, the first bridge line RBL1 connected to the outermost first subpixel SP#1 among the multiple bridge lines RBL1, RBL2, and RBL3 can be arranged offset from the center of the first subpixel SP#1 to the right, which is one side in the first direction DR1. The second bridge line RBL2 and the third bridge line RBL3 can be arranged sequentially from the first bridge line RBL1 to the left, which is the other side in the first direction DR1. That is, compared with the bridge lines RBL1, RBL2, RBL3 connected to the sub-pixels SP arranged inside the above-mentioned sub-pixels SP, the bridge lines RBL1, RBL2, RBL3 connected to the sub-pixels SP arranged on the relatively outer side can be set to deviate to one side from the center of the corresponding sub-pixel SP.

[0242] Therefore, the positions of the ends of the bridge lines RBL1, RBL2, and RBL3, which are the starting points, can be different from each other within the four sub-pixels SP of the eighth pixel column EC8. For example, the position of the end of the first bridge line RBL1 in the outermost first sub-pixel SP#1 can be different from the position of the end of the second bridge line RBL2 in the second sub-pixel SP#2 adjacent to the first sub-pixel SP#1 in the second direction DR2, and the relative positions in each of the corresponding sub-pixels SP may also be different.

[0243] Among the sub-pixels SP arranged in the seventh pixel column EC7, four sub-pixels SP that do not overlap with the pixel circuit portion 800 may also be arranged to extend outside the pixel circuit portion 800 through the bridge lines RBL1, RBL2, and RBL3 of the connection wiring RML. The first sub-pixel SP#1, the second sub-pixel SP#2, the third sub-pixel SP#3, and the fourth sub-pixel SP#4 of the seventh pixel column EC7 may also be connected to the pixel circuit PXC of the seventh circuit column PC7 through the connection wiring RML including the first bridge line RBL1, the second bridge line RBL2, the third bridge line RBL3, and the first bridge line RBL1, respectively.

[0244] The sub-pixels SP of the eighth pixel column EC8 can be connected to the eighth circuit column PC8 parallel to the second direction DR2 (e.g., aligned in the second direction DR2). On the other hand, the sub-pixels SP of the seventh pixel column EC7 can be connected to the seventh circuit column PC7, but may not be parallel to each other (e.g., aligned) in the second direction DR2. Therefore, the bridge lines RBL1, RBL2, and RBL3 connected to the seventh pixel column EC7 can extend in an oblique direction. However, since the bridge lines RBL1, RBL2, and RBL3 connected to the eighth pixel column EC8 are arranged to be offset toward the right side in the sub-pixels SP, sufficient space can be ensured so that the bridge lines RBL1, RBL2, and RBL3 connected to the sub-pixels SP of the seventh pixel column EC7 extend and are arranged in an oblique direction.

[0245] This can be similarly applied to the sub-pixels SP in the eighth pixel column EC8 and the seventh pixel column EC7 that overlap with the pixel circuit portion 800. For example, the sub-pixels SP of the first pixel row ER1, the second pixel row ER2, the third pixel row ER3, and the fourth pixel row ER4 in the eighth pixel column EC8 and the seventh pixel column EC7 can be connected to the pixel circuit PXC through the connection wiring RML or the bridge wires RBL1, RBL2, and RBL3 that overlap with the pixel circuit portion 800.

[0246] Figures 21 to 23 It is shown by Figure 14 Schematic diagram of the connection between the sub-pixels and the pixel circuit in the connection wiring in the third region. Figures 21 to 23Arrangement of bridge lines RBL1, RBL2, and RBL3 of a connection wiring RML is shown, which connects subpixels SP arranged in an oblique direction between the first direction DR1 and the second direction DR2 of the pixel circuit portion 800 among subpixels SP arranged in the display area DAA to the pixel circuit PXC.

[0247] Reference Figures 21 to 23 , a plurality of first sub-pixels SP#1, second sub-pixels SP#2, third sub-pixels SP#3, and fourth sub-pixels SP#4 sequentially arranged along an oblique direction from among a plurality of sub-pixels SP in the display area DAA may be sequentially connected to the pixel circuits PXC sequentially arranged along an oblique direction of the pixel circuit portion 800. For example, in Figure 21 , the first subpixel SP#1 disposed in the eighth pixel row ER8 of the first pixel column EC1 is the outermost subpixel in the oblique direction and can be connected to the pixel circuit PXC of the eighth circuit row PR8 of the first circuit column PC1 in the pixel circuit portion 800. Figure 21 The second subpixel SP#2, the third subpixel SP#3 and the fourth subpixel SP#4 arranged along the oblique direction from the first subpixel SP#1 in the image may be respectively connected to the pixel circuit PXC arranged along the oblique direction from the pixel circuit PXC connected to the first subpixel SP#1.

[0248] Figure 21 The first sub-pixel SP# 1 may be connected to the pixel circuit PXC through a connection wiring RML including a first bridge line RBL1 . Figure 21 The second sub-pixel SP#2, the third sub-pixel SP#3 and the fourth sub-pixel SP#4 can be connected to the pixel circuit PXC through the connection wiring RML including the second bridge line RBL2, the third bridge line RBL3 and the first bridge line RBL1. Figure 21 In the fourth subpixel SP#4, it is desirable to ensure space for the four bridge wires RBL1, RBL2, and RBL3, and the first bridge wire RBL1 connected to the first subpixel SP#1 can be arranged offset to one side from the center of the subpixel, for example, offset to the lower left side in the oblique direction. The other bridge wires connected to the second subpixel SP#2, the third subpixel SP#3, and the fourth subpixel SP#4 can be arranged sequentially to the upper right side from the first bridge wire RBL1 connected to the first subpixel SP#1.

[0249] Figure 22 The first sub-pixel SP#1, the second sub-pixel SP#2, the third sub-pixel SP#3 and the fourth sub-pixel SP#4 may be respectively adjacent to each other in the second direction DR2. Figure 21The first sub-pixel SP#1, the second sub-pixel SP#2, the third sub-pixel SP#3 and the fourth sub-pixel SP#4 are adjacent to each other. Figure 22 The pixel circuits PXC of the first sub-pixel SP#1, the second sub-pixel SP#2, the third sub-pixel SP#3 and the fourth sub-pixel SP#4 may also be connected to the pixel circuits PXC in the second direction DR2. Figure 21 The pixel circuits PXC of the first sub-pixel SP#1, the second sub-pixel SP#2, the third sub-pixel SP#3 and the fourth sub-pixel SP#4 are adjacent to the pixel circuits PXC.

[0250] As Figure 22 The first subpixel SP#1, which is the outermost subpixel among the first, second, third, and fourth subpixels SP#1, SP#2, SP#3, and SP#4, may be connected to the pixel circuit PXC through a connection wiring RML including a first bridge line RBL1. Figure 22 The second sub-pixel SP#2, the third sub-pixel SP#3 and the fourth sub-pixel SP#4 can be connected to the pixel circuit PXC through the connection wiring RML including the second bridge line RBL2, the third bridge line RBL3 and the first bridge line RBL1. Figure 22 In the fourth sub-pixel SP#4, it is desirable to ensure a space in which four bridge lines RBL1, RBL2, and RBL3 can be provided. Figure 21 The arrangements of the bridge lines RBL1, RBL2, and RBL3 are different. The first bridge line RBL1 connected to the first subpixel SP#1 can be arranged offset to one side from the center of the subpixel, for example, to the upper right side in the oblique direction. The other bridge lines connected to the second subpixel SP#2, the third subpixel SP#3, and the fourth subpixel SP#4 can be arranged sequentially to the lower left side from the first bridge line RBL1 connected to the first subpixel SP#1.

[0251] Figure 23 The first sub-pixel SP#1, the second sub-pixel SP#2, the third sub-pixel SP#3 and the fourth sub-pixel SP#4 may be respectively aligned with the first direction DR1. Figure 21 The first sub-pixel SP#1, the second sub-pixel SP#2, the third sub-pixel SP#3 and the fourth sub-pixel SP#4 are adjacent to each other. Figure 23 The pixel circuits PXC of the first sub-pixel SP#1, the second sub-pixel SP#2, the third sub-pixel SP#3 and the fourth sub-pixel SP#4 may also be connected to the first direction DR1. Figure 21 The pixel circuits PXC of the first sub-pixel SP#1, the second sub-pixel SP#2, the third sub-pixel SP#3 and the fourth sub-pixel SP#4 are adjacent to the pixel circuits PXC.

[0252] As Figure 23 The first subpixel SP#1, which is the outermost subpixel among the first, second, third, and fourth subpixels SP#1, SP#2, SP#3, and SP#4, may be connected to the pixel circuit PXC through a connection wiring RML including a first bridge line RBL1. Figure 23 The second sub-pixel SP#2, the third sub-pixel SP#3 and the fourth sub-pixel SP#4 can be connected to the pixel circuit PXC through the connection wiring RML including the second bridge line RBL2, the third bridge line RBL3 and the first bridge line RBL1. Figure 23 In the fourth sub-pixel SP#4, it is desirable to ensure a space in which four bridge lines RBL1, RBL2, and RBL3 can be provided. Figure 21 The arrangement of the bridge lines RBL1, RBL2, and RBL3 is similar. The first bridge line RBL1 connected to the first sub-pixel SP#1 can be arranged offset to one side from the center of the sub-pixel, for example, to the lower left side in the oblique direction. The other bridge lines connected to the second sub-pixel SP#2, the third sub-pixel SP#3, and the fourth sub-pixel SP#4 can be arranged sequentially from the first bridge line RBL1 connected to the first sub-pixel SP#1 to the upper right side.

[0253] Connect to Figure 22 The first bridge line RBL1 of the first sub-pixel SP#1 may be configured not to interfere with the connection to Figure 21 The first bridge line RBL1 of the first sub-pixel SP#1 is connected to Figure 23 The first bridge line RBL1 of the first sub-pixel SP#1 may be configured not to interfere with the connection to Figure 21 The first bridge line RBL1 of the fourth sub-pixel SP#4. Figures 17 to 20 As described above, since the bridge lines RBL1, RBL2, and RBL3 arranged in two regions (the first region and the second region) parallel to each other in the first direction DR1 or the second direction DR2 from the pixel circuit portion 800 are arranged offset to one side from the center of the sub-pixel SP, sufficient space can be ensured in which the bridge lines RBL1, RBL2, and RBL3 arranged in the region (the third region) parallel to the pixel circuit portion 800 in an oblique direction can be arranged. In addition, when two adjacent bridge lines RBL1, RBL2, and RBL3 do not have enough space to separate from each other or interfere with each other, the adjacent bridge lines RBL1, RBL2, and RBL3 can be arranged on different conductive layers.

[0254] Figure 24 is a diagram schematically illustrating the arrangement of via holes through which sub-pixels and connection wirings of a display device according to one or more embodiments are connected. Figure 24 It is shown that the bridge lines RBL1 , RBL2 , and RBL3 of the connection wiring RML are connected to the via holes of the sub-pixels SP or a region where one ends of the bridge lines RBL1 , RBL2 , and RBL3 are placed.

[0255] Reference Figure 24 , the outermost sub-pixels SP of the display area DAA may be sub-pixels arranged in the first pixel column EC1 and the eighth pixel row ER8. The sub-pixels arranged in the first pixel column EC1 and the eighth pixel row ER8 may be connected to the pixel circuit PXC through the connection wiring RML including the first bridge line RBL1. The via hole connected to the first bridge line RBL1 (for example, Figure 15 A via between the first bridge line RBL1 and the second bridge contact RCT2 in the eighth pixel column or a conductive via RVA provided in the first through hole TSV1 may overlap the first pixel column EC1 and the eighth pixel row ER8 . Figure 24 The first contact area CNA1 may be an area where a bridge contact connected to the first bridge line RBL1 is provided, or a via or conductive via RVA.

[0256] The sub-pixels arranged in the second pixel column EC2 and the seventh pixel row ER7 may be connected to the pixel circuit PXC through the connection wiring RML including the second bridge line RBL2. The via hole connected to the second bridge line RBL2 (for example, Figure 15 A conductive via RVA provided between the second bridge line RBL2 and the third bridge contact RCT3 in the first through hole TSV1 or a conductive via RVA provided in the first through hole TSV1 may overlap the second pixel column EC2 and the seventh pixel row ER7. Figure 24 The second contact area CNA2 may be an area where a bridge contact or a via connected to the second bridge line RBL2 is provided.

[0257] The sub-pixels arranged in the third pixel column EC3 and the sixth pixel row ER6 may be connected to the pixel circuit PXC through the connection wiring RML including the third bridge line RBL3. The via hole (eg, Figure 15 The conductive via RVA connected to the third bridge line RBL3 may overlap the third pixel column EC3 and the sixth pixel row ER6. Figure 24 The third contact area CNA3 may be a region provided with a conductive via connected to the third bridge line RBL3 .

[0258] Since one end of the bridge wires RBL1, RBL2, and RBL3 is provided in the same conductive layer (for example, at the same conductive layer), the one end connected to the sub-pixel SP can be provided in the same pixel row or the same pixel column. For example, one end of the first bridge wire RBL1 can be provided in the first pixel column EC1 and the eighth pixel row ER8. In one or more embodiments, as the opposite ends of the bridge wires RBL1, RBL2, and RBL3, the ends of the pixel circuits PXC connected to the pixel circuit portion 800 can also be provided in the same circuit row and the same circuit column. For example, the other end of the first bridge wire RBL1 can be provided in the first circuit column PC1 and the eighth circuit row PR8. Although Figures 21 to 24 Only the arrangement of the connection wiring RML connected to the sub-pixel SP set on the upper left side of the pixel circuit part 800 is shown, but the connection wiring RML connected to the sub-pixels SP set on the lower left side, upper right side and lower right side of the pixel circuit part 800 can be arranged with a similar rule.

[0259] Since the display device 10 includes the plurality of bridge lines RBL1, RBL2, and RBL3 provided at different conductive layers (e.g., at different conductive layers) in the connection line layer 500, and the plurality of bridge lines RBL1, RBL2, and RBL3 are provided in the above-described rule, the plurality of connection wirings RML provided in a narrow area may have an arrangement that does not electrically interfere with each other.

[0260] like Figures 17 to 23 As shown in FIG, among the plurality of bridge lines RBL1, RBL2, and RBL3, the bridge lines RBL1, RBL2, and RBL3 connected to the sub-pixels SP overlapping the pixel circuit portion 800 may be shorter than the bridge lines RBL1, RBL2, and RBL3 connected to the sub-pixels SP not overlapping the pixel circuit portion 800. In this case, the length and conductor resistance of the connection wiring RML connected to the pixel circuit portion 800 may vary depending on the position of the sub-pixels SP, and signal deviation may occur between the sub-pixels SP. In view of this, the bridge lines RBL1, RBL2, and RBL3 connected to the sub-pixels SP overlapping the pixel circuit portion 800 may have a different wiring path than the bridge lines RBL1, RBL2, and RBL3 connected to the sub-pixels SP not overlapping the pixel circuit portion 800.

[0261] Figure 25 : are views illustrating examples of the shape of a bridge line according to one or more embodiments. Figure 25 An example of a bridge line RBL connected to a sub-pixel SP overlapping the pixel circuit portion 800 is shown.

[0262] Reference Figure 25, the multiple bridge lines RBL can generally have a straight line shape as described above, but the bridge line RBL connected to the sub-pixel SP overlapping the pixel circuit portion 800 can have a partially curved shape to extend the wiring length. Because the sub-pixel SP overlapping the pixel circuit portion 800 has a short plane distance from the pixel circuit PXC, sufficient space can be ensured in which the bridge line RBL connecting the sub-pixel SP can be partially bent. Therefore, the bridge line RBL connected to the sub-pixel SP overlapping the pixel circuit portion 800 or the bridge line RBL completely overlapping the pixel circuit portion 800 can have a zigzag shape, so that the wiring length can be extended compared to the plane distance. Therefore, regardless of the position of the sub-pixel SP, the wiring resistance of the wiring to which the signal is applied from the driving unit 100 can be designed to be uniform.

[0263] Figure 26 is a view illustrating an example of a cross-sectional connection structure of connection wiring according to one or more embodiments. Figure 26 An example of the bridge lines RBLa, RBLb, and RBLc connected to the sub-pixel SP overlapping the pixel circuit portion 800 is shown.

[0264] Reference Figure 26 The multiple connection wirings RML may include one bridge line RBL and two bridge contacts as described above. However, the bridge line RBL connected to the sub-pixel SP overlapping the pixel circuit portion 800 may include multiple bridge lines RBLa, RBLb, and RBLc to extend the wiring length. Because the sub-pixel SP overlapping the pixel circuit portion 800 has a short planar distance from the pixel circuit PXC, sufficient space can be ensured for the connection wiring connecting the sub-pixel SP to be connected via the multiple bridge lines RBLa, RBLb, and RBLc disposed at different conductive layers (e.g., at different conductive layers). The bridge line RBL connected to the sub-pixel SP overlapping the pixel circuit portion 800, or the bridge line RBL completely overlapping the pixel circuit portion 800, may have a wiring length extended compared to the planar distance. For example, the single connection wiring RML may include a first bridge line RBLa on the first conductive layer, a second bridge line RBLb on the second conductive layer, and a third bridge line RBLc on the third conductive layer. Therefore, regardless of the position of the sub-pixel SP, the wiring resistance of the wiring to which the signal is applied from the driver 100 can be designed to be uniform.

[0265] Hereinafter, various embodiments of the display device 10 will be described with reference to other drawings.

[0266] Figure 27 is a diagram illustrating a schematic arrangement of connection wirings connecting a pixel circuit portion of a display device and sub-pixels of a display region according to one or more embodiments.

[0267] Reference Figure 27 In the display device 10, the driving portion 100 having a small area may include a plurality of first single crystal semiconductor substrates 110a, 110b, 110c, and 110d, and a plurality of pixel circuit portions 800a, 800b, 800c, and 800d provided in each of the plurality of first single crystal semiconductor substrates 110a, 110b, 110c, and 110d may be connected to the sub-pixels SP of the display area DAA. When one pixel circuit portion 800 is connected to the sub-pixels SP provided in the display area DAA having a large area, there may not be sufficient space for providing the connection wiring RML. On the other hand, when the driving portion 100 is made of a plurality of first single crystal semiconductor substrates 110a, 110b, 110c and 110d and includes a plurality of pixel circuit portions 800a, 800b, 800c and 800d, since the plurality of pixel circuit portions 800a, 800b, 800c and 800d partially cover the sub-pixels SP of the display area DAA, it can be expected that a space in which the connection wiring RML is provided can be ensured.

[0268] Figure 28 is a schematic cross-sectional view illustrating an example of a connection line layer of a display device according to one or more embodiments.

[0269] Reference Figure 28 In the display device 10, the first single crystal semiconductor substrate 110 of the driving portion 100 may have an area larger than the second single crystal semiconductor substrate 210 of the display portion 200. Therefore, the protective layer 900 may be around (eg, surround) the second single crystal semiconductor substrate 210.

[0270] Figure 29 is a perspective view illustrating a head-mounted display device according to one or more embodiments. Figure 30 It shows Figure 29 An exploded perspective view of an example of a head-mounted display device.

[0271] Reference Figure 29 and Figure 30 According to one or more embodiments, the head-mounted display device 1000 includes a first display device 11, a second display device 12, a display device accommodating portion 1100, a accommodating portion cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted strap 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, a control circuit board 1600, and a connector.

[0272] The first display device 11 provides an image to the left eye of the user, and the second display device 12 provides an image to the right eye of the user. Figure 1The display devices 10 described are substantially the same, so descriptions of the first display device 11 and the second display device 12 will be omitted.

[0273] The first optical member 1510 may be disposed between the first display device 11 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 12 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0274] The middle frame 1400 may be disposed between the first display device 11 and the control circuit board 1600 and between the second display device 12 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 11, the second display device 12 and the control circuit board 1600.

[0275] The control circuit board 1600 may be disposed between the middle frame 1400 and the display device receiving portion 1100. The control circuit board 1600 may be connected to the first display device 11 and the second display device 12 through a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA and transmit the digital video data DATA to the first display device 11 and the second display device 12 through the connector.

[0276] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 11, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 12. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to both the first display device 11 and the second display device 12.

[0277] The display device housing 1100 is used to accommodate the first display device 11, the second display device 12, the intermediate frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and the connector. The housing cover 1200 is provided to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. The first eyepiece 1210 and the second eyepiece 1220 are shown as being separately provided in the drawings, but the present disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be formed as a single unit.

[0278] The first eyepiece 1210 may be aligned with the first display device 11 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 12 and the second optical member 1520. Therefore, the user can view the image of the first display device 11 magnified into a virtual image by the first optical member 1510 through the first eyepiece 1210, and can view the image of the second display device 12 magnified into a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0279] The headband 1300 is used to secure the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are positioned over the user's left eye and right eye, respectively. If the display device housing 1100 is implemented to be lightweight and small in size, the head-mounted display device 1000 may include an eyeglass frame instead of the headband 1300.

[0280] In addition, the head-mounted display device 1000 may further include a battery for power supply, an external memory slot for accommodating an external memory, an external connection port for receiving an image source, and a wireless communication module. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0281] Figure 31 is a perspective view illustrating a head-mounted display device according to one or more embodiments.

[0282] Reference Figure 31 The head-mounted display device 1000_1 according to one or more embodiments may be a glasses-type display device in which the display device housing 1200_1 is implemented in a lightweight and small size. The head-mounted display device 1000_1 according to one or more embodiments may include a display device 13, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, glasses frame legs 1040 and 1050, an optical member 1060, an optical path conversion member 1070, and a display device housing 1200_1.

[0283] The display device housing portion 1200_1 may include the display device 13, the optical member 1060, and the optical path conversion member 1070. When the image displayed on the display device 13 is magnified by the optical member 1060 and its optical path is converted by the optical path conversion member 1070, the image can be provided to the user's right eye through the right-eye lens 1020. Thus, the user can view an augmented reality image in which the virtual image displayed on the display device 13 and the real image viewed through the right-eye lens 1020 are combined through the right eye.

[0284] The accompanying drawings illustrate that the display device housing 1200_1 is located at the far right end of the support frame 1030, but the present disclosure is not limited thereto. For example, the display device housing 1200_1 may be located at the far left end of the support frame 1030. In this case, the image of the display device 13 may be provided to the user's left eye. Alternatively, the display device housing 1200_1 may be located at both the far left and far right ends of the support frame 1030. In this case, the user may view the image displayed on the display device 13 through both the user's left eye and the right eye.

[0285] However, it should be understood that the aspects and features of the embodiments of the present disclosure are not limited to the aspects and features set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art by referring to the claims and their equivalents included in the claims.

Claims

1. A display device, comprising: a first single crystal semiconductor substrate on which a plurality of pixel circuits arranged along a first direction and a second direction intersecting the first direction are positioned, the plurality of pixel circuits including first transistors; a second single crystal semiconductor substrate on the first single crystal semiconductor substrate, wherein a plurality of sub-pixels including a plurality of light emitting elements and arranged along the first direction and the second direction are positioned on the second single crystal semiconductor substrate; and a connecting line layer between the plurality of light emitting elements and the first single crystal semiconductor substrate and including a plurality of bridge lines, each of the plurality of bridge lines being electrically connected to one pixel circuit among the plurality of pixel circuits and one sub-pixel among the plurality of sub-pixels, The second single crystal semiconductor substrate includes a plurality of through holes, a corresponding conductive via among the plurality of conductive vias is positioned in each of the plurality of through holes, and the plurality of conductive vias are electrically connected to a light emitting element among the plurality of light emitting elements corresponding to each of the plurality of sub-pixels and a corresponding bridge wire among the plurality of bridge wires, respectively. The connecting line layer includes a first conductive layer on which a first bridge line is located, a second conductive layer on which a second bridge line is located, and an interlayer insulating layer between the first conductive layer and the second conductive layer. At least some of the plurality of sub-pixels are electrically connected to the first bridge line, and other sub-pixels adjacent to the sub-pixels connected to the first bridge line are electrically connected to the second bridge line.

2. The display device according to claim 1, wherein An outermost sub-pixel in the first direction and an outermost sub-pixel in the second direction among the plurality of sub-pixels are electrically connected to different first bridge lines.

3. The display device according to claim 2, wherein: Among the plurality of sub-pixels, sub-pixels that are internally adjacent in the first direction and sub-pixels that are internally adjacent in the second direction are electrically connected to different second bridge lines based on outermost sub-pixels in the first and second directions.

4. The display device according to claim 1, wherein The sub-pixels of a first pixel row are arranged along the first direction, the sub-pixels in the first pixel row are electrically connected to pixel circuits among the multiple pixel circuits that are aligned with the sub-pixels of the first pixel row in the first direction, and the sub-pixels of a second pixel row adjacent to the first pixel row in the second direction are electrically connected to pixel circuits among the multiple pixel circuits that are not aligned with the sub-pixels of the second pixel row in the first direction.

5. The display device according to claim 4, wherein A bridge line electrically connected to the sub-pixels of the first pixel row overlaps the sub-pixels of the first pixel row. The display device according to claim 4 , wherein: At least a portion of the bridge line electrically connected to the sub-pixels of the second pixel row overlaps the sub-pixels of the first pixel row.

7. The display device according to claim 4, wherein A first sub-pixel positioned at the outermost portion of the first pixel row is connected to the first bridge wire, a second sub-pixel adjacent to the first sub-pixel of the first pixel row is connected to the second bridge wire, and the first bridge wire connected to the first sub-pixel is positioned on a side of the second bridge wire connected to the second sub-pixel in a direction opposite to the second direction in the second direction.

8. The display device according to claim 4, wherein The sub-pixels of the first pixel column are arranged along the second direction, the sub-pixels of the first pixel column are electrically connected to pixel circuits among the multiple pixel circuits that are aligned with the sub-pixels of the first pixel column in the second direction, and the sub-pixels of the second pixel column adjacent to the first pixel column in a direction opposite to the first direction are electrically connected to pixel circuits among the multiple pixel circuits that are not aligned with the sub-pixels of the second pixel column in the second direction.

9. The display device according to claim 8, wherein A first sub-pixel at the outermost part of the first pixel column is connected to the first bridge wire, a second sub-pixel adjacent to the first sub-pixel of the first pixel column is connected to the second bridge wire, and the first bridge wire connected to the first sub-pixel is positioned on one side of the second bridge wire connected to the second sub-pixel in the first direction.

10. The display device according to claim 1, wherein A first sub-pixel at an outermost portion among the plurality of sub-pixels arranged along an oblique direction in the first single crystal semiconductor substrate is connected to the first bridge wiring, a second sub-pixel adjacent to the first sub-pixel in the oblique direction is connected to the second bridge wiring, and the second bridge wiring is positioned above the first bridge wiring.

11. The display device according to claim 1, wherein A position of one end of the first bridge line in a subpixel among the plurality of subpixels is different from a position of one end of the second bridge line in a subpixel adjacent to an interior of the subpixel connected to the first bridge line.

12. The display device according to claim 1, wherein The plurality of sub-pixels include overlapping sub-pixels overlapping the pixel circuit and non-overlapping sub-pixels not overlapping the pixel circuit, and Part of the bridge line connected to the non-overlapping sub-pixel among the plurality of bridge lines does not overlap with the first single crystal semiconductor substrate.

13. The display device according to claim 12, wherein: The bridge line connected to the non-overlapping sub-pixel among the plurality of bridge lines is longer than the bridge line connected to the overlapping sub-pixel.

14. The display device according to claim 12, wherein: A bridge line connected to the overlapping sub-pixel among the plurality of bridge lines has a zigzag shape.

15. The display device according to claim 1, wherein An area of ​​the first single crystal semiconductor substrate is smaller than an area of ​​the second single crystal semiconductor substrate.

16. A display device, comprising: a first single crystal semiconductor substrate, a plurality of first transistors and a plurality of pixel circuits positioned on the first single crystal semiconductor substrate, the plurality of pixel circuits including the first transistors; a second single crystal semiconductor substrate on the first single crystal semiconductor substrate, wherein a plurality of sub-pixels including a plurality of light emitting elements are positioned on the second single crystal semiconductor substrate; and A connecting line layer is provided between the plurality of light emitting elements and the first single crystal semiconductor substrate. The second single crystal semiconductor substrate includes a plurality of through holes, wherein a plurality of conductive vias electrically connected to a light emitting element corresponding to each of the plurality of sub-pixels in the plurality of light emitting elements are respectively located in the plurality of through holes. The connecting line layer includes a plurality of conductive layers including a plurality of bridge lines and a plurality of bridge contacts and an interlayer insulating layer between the plurality of conductive layers, and Among them, the multiple sub-pixels include a first sub-pixel and a second sub-pixel, the first sub-pixel is connected to one of the multiple pixel circuits through a first bridge line at the first conductive layer of the connecting line layer, and the second sub-pixel is connected to one of the multiple pixel circuits through a second bridge line at the second conductive layer on the first conductive layer of the connecting line layer.

17. The display device according to claim 16, wherein: The second bridge line is electrically connected to a first bridge contact at the first conductive layer, and the first bridge line is electrically connected to a second bridge contact at the second conductive layer.

18. The display device according to claim 17, wherein: Each of the second bridge line and the second bridge contact is connected to a corresponding conductive via of the plurality of conductive vias.

19. The display device according to claim 16, wherein: At least a portion of the first bridging line is connected to the second bridging line at the second conductive layer.

20. A head-mounted display device, comprising: frame; a plurality of display devices on the frame; as well as a lens on each of the plurality of display devices; Wherein, the display device includes: A first single crystal semiconductor substrate including a plurality of pixel circuits arranged along a first direction and a second direction intersecting the first direction, the plurality of pixel circuits including first transistors; a second single crystal semiconductor substrate including, on the first single crystal semiconductor substrate, a plurality of sub-pixels including a plurality of light emitting elements and arranged along the first direction and the second direction; and a connecting line layer between the plurality of light emitting elements and the first single crystal semiconductor substrate and including a plurality of bridge lines, each of the plurality of bridge lines being electrically connected to one pixel circuit among the plurality of pixel circuits and one sub-pixel among the plurality of sub-pixels, The second single crystal semiconductor substrate includes a plurality of through holes, each of the plurality of through holes having a corresponding conductive via located therein, the plurality of conductive vias being electrically connected to a light emitting element corresponding to each sub-pixel in the plurality of sub-pixels and a corresponding bridge wire in the plurality of bridge wires, respectively. The connecting line layer includes a first conductive layer on which a first bridge line is located, a second conductive layer on which a second bridge line is located, and an interlayer insulating layer between the first conductive layer and the second conductive layer. At least some of the plurality of sub-pixels are electrically connected to the first bridge line, and other sub-pixels adjacent to the sub-pixels connected to the first bridge line are electrically connected to the second bridge line.

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