Metal-insulator-metal capacitor structure and manufacturing method thereof

Abstract

The invention provides a metal-insulator-metal capacitor structure and a manufacturing method thereof, and the manufacturing method comprises the steps: providing a substrate which is provided with a stack; forming a covering material layer; executing first photoetching and a corresponding etching process to form N first openings and (N + 1) th openings; performing second to Mth photoetching and corresponding etching processes to form second to Nth openings, and etching the (N + 1) th opening to expose the surface of the substrate, and in the second to Mth photoetching and corresponding etching processes, etching the (N + 1) th opening to expose the surface of the substrate, part of the first openings in the second lead-out region to the Nth lead-out region are selected in each time of photoetching, at most A layers of electrode material layers and at most A layers are removed through etching in each time of etching process, and A is an integer ranging from 2 to N-1; and forming a side wall, and filling conductive material layers in the first to Nth openings to form a lead-out structure. According to the invention, the number of the mask plates can be optimized and the etching difficulty can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a metal-insulator-metal capacitor structure and a manufacturing method thereof. Background Art

[0002] With the continuous development of semiconductor technology, the application of metal-insulator-metal (MIM) capacitors has become increasingly widespread. The application of MIM capacitor structures can reduce the size of semiconductor devices, making them more functional. However, the preparation process of semiconductor devices with MIM capacitor structures is cumbersome, resulting in low production efficiency of semiconductor devices with MIM capacitor structures.

[0003] In related technologies, such as Figure 1 As shown, a substrate 10' includes multiple layers of electrode material layers 11' and dielectric material layers 12' alternately stacked in sequence to form a multilayer trench capacitor. The edges of the multilayer trench capacitor are stepped, that is, each electrode material layer 11' extends outward at one end from top to bottom to form an exposed step surface 13'. Then, a lead structure is formed on each step surface 13' to lead each electrode material layer 11' upward. However, forming the multilayer capacitor with the step surface 13' requires patterning each electrode material layer 11' separately. When forming the lead structure on each step surface 13', multiple masks are used to form multiple openings (contact holes) aligned with each electrode material layer 11', and etching stops on the step surface 13' of each electrode material layer. As can be seen from the above process, manufacturing multi-layer capacitors requires a large number of masks (greater than the number of electrode material layers) and photolithography times, which wastes photolithography resources. Moreover, when etching to form openings to expose the stepped surfaces of the electrode material layers, each opening must be etched through materials of different thicknesses and structures, and the etching process must stop precisely on the stepped surface, making it very challenging. Summary of the Invention

[0004] The object of the present invention is to provide a metal-insulator-metal capacitor and a manufacturing method thereof, so as to optimize the number of masks and reduce the difficulty of etching.

[0005] To solve the above technical problems, the present invention provides a method for manufacturing a metal-insulator-metal capacitor, comprising:

[0006] Providing a substrate having a stack formed by alternating electrode material layers and dielectric material layers, the stack including first to Nth electrode material layers and first to Nth lead-out regions corresponding to the first to Nth electrode material layers, respectively, where N is an integer greater than or equal to 4;

[0007] forming a covering material layer to cover the surface of the stack;

[0008] Performing a first photolithography and corresponding etching process on the cover material layer and the stack to form N first openings to expose the surface of the first electrode material layer of the first to Nth lead-out regions and forming an N+1th opening for defining a boundary of the capacitor;

[0009] performing second to Mth photolithography and corresponding etching processes on the cover material layer and the stack, respectively, to form second to Nth openings, each exposing a surface of the electrode material layer corresponding to the second to Nth lead-out regions, and etching the N+1th opening to expose the surface of the substrate, wherein in the second to Mth photolithography and corresponding etching processes, each photolithography selects a portion of the first opening in the second to Nth lead-out regions, and each photolithography and corresponding etching process etches away at most A layers of the electrode material layer and at most A layers of the dielectric material layer, where A is an integer of 2ˉN-1, and M is N / A rounded up plus A-1;

[0010] A sidewall spacer is formed to cover the sidewalls of the first to N+1th openings, and a conductive material layer is filled in the first to Nth openings to form a lead-out structure for leading out each electrode material layer.

[0011] Optionally, the stack includes a multilayer flat plate capacitor and / or trench capacitor formed by the electrode material layer and the dielectric material layer, and the first to Nth lead-out regions are located in non-trench areas of the flat plate capacitor and / or trench capacitor.

[0012] Optionally, the width of the (N+1)th opening is greater than or equal to twice the width of the first opening.

[0013] Optionally, the first to Nth openings have the same opening width.

[0014] Optionally, B*B is the square number closest to N, B is a positive integer, and A is one of B-1, B or B+1.

[0015] Optionally, A=2, the etching processes corresponding to the second to Mth photolithography include M-2 first etching processes and 1 second etching process, the first etching process removes two layers of electrode material and two layers of dielectric material on part of the lead-out area, and the second etching process removes one layer of electrode material and one layer of dielectric material on part of the lead-out area.

[0016] Optionally, when performing the etching processes corresponding to the second to M-th photolithography, the first etching process is performed continuously for M-2 times and then the second etching process is performed, or the second etching process is performed and then the first etching process is performed continuously for M-2 times.

[0017] Optionally, in the M-2 first etching processes, the number of the second to Nth openings exposed by each photolithography process decreases successively.

[0018] According to another aspect of the present invention, there is also provided a metal-insulator-metal capacitor structure, comprising:

[0019] substrate;

[0020] a stacked body disposed on the substrate and formed by alternately stacking dielectric material layers and first to Nth electrode material layers, wherein the sidewalls of the stacked body are vertically planar;

[0021] First to Nth openings are provided in the stack body and respectively expose surfaces of the first to Nth electrode material layers;

[0022] Side walls, provided on side walls of the first to Nth openings;

[0023] The lead-out structures filled in the first to N-th openings electrically lead out the first to N-th electrode material layers respectively.

[0024] Optionally, at least some of the first to Nth openings are centrally symmetrically distributed on the surface of the stack.

[0025] In summary, the present invention alternately stacks electrode material layers and dielectric material layers on a substrate to form a stack, which includes first to N electrode material layers and first to N lead-out regions corresponding to the first to N electrode material layers, respectively. Then, a covering material layer is formed to cover the surface of the stack, and then, a first photolithography and corresponding etching process are performed on the covering material layer and the stack to form N first openings exposing the surface of the first electrode material layer of the first to N lead-out regions and forming an N+1th opening for defining the boundary of the capacitor, and then, a second to Mth photolithography and corresponding etching process are performed on the covering material layer and the stack to form the second to Nth lead-out regions. The Nth openings each expose the surface of the electrode material layer corresponding to the second to Nth extraction regions, and the N+1th opening is etched to expose the surface of the substrate. In the second to Mth photolithography and corresponding etching processes, each photolithography step selects a portion of the first opening in the second to Nth extraction regions, and each photolithography step corresponding to the etching process removes at most A layers of the electrode material layer and at most A layers of the dielectric material layer, where A is an integer of 2ˉN-1 and M is N / A rounded up plus A-1. Next, sidewalls are formed to cover the sidewalls of the first to N+1th openings, and a conductive material layer is filled within the first to Nth openings to form extraction structures for extracting each electrode material layer. As can be seen from the above process, in the present invention, only M photolithography steps (including the first photolithography step) and corresponding etching processes are required to complete the independent extraction of each electrode material layer of the capacitor structure and the patterning of the capacitor structure. In particular, when the number of electrode material layers is large, only less than half the number of photolithography and etching processes are required, which helps save the number of masks, the number of photolithography steps, and the corresponding etching times. Moreover, compared to the etching process of the related art (capacitor structure with stepped sidewalls) in which different layers of film are etched multiple times (multiple etching recipes), in the etching process corresponding to the second to Mth photolithography of the present invention, fewer layers of electrode material layer and dielectric material layer are removed each time, making the etching process simpler and easier to achieve better etching effects, including improving etching uniformity and consistency of etching stop, and easily stopping on the surface of the ultra-thin electrode material layer. In addition, compared to the stepped sidewalls, the sidewalls of the capacitor structure of the present invention are vertically planar, which can also give it a larger capacitor area. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0027] Figure 1 Schematic diagram of the lead-out structure of a multilayer capacitor structure in the related art;

[0028] Figure 2 is a flow chart of a method for manufacturing a metal-insulator-metal capacitor provided in Example 1;

[0029] Figure 3a-Figure 3iA schematic structural diagram corresponding to the corresponding steps of the method for manufacturing a metal-insulator-metal capacitor provided in Example 1;

[0030] Figure 4a and Figure 4b This is a schematic diagram of the lead-out area layout of the capacitor structure provided in the second embodiment.

[0031] Figure 1 Middle: 10'-substrate; 11'-electrode material layer; 12'-dielectric material layer; 13'-step surface; 15'-lead structure.

[0032] Figures 3a to 4b In the figure: 10-substrate; 11a-first electrode material layer; 11b-second electrode material layer; 11c-third electrode material layer; 11d-fourth electrode material layer; 11e-fifth electrode material layer; 12a-first dielectric material layer; 12b-second dielectric material layer; 12c-third dielectric material layer; 12d-fourth dielectric material layer; 13a-first lead-out area; 13b-second lead-out area; 13c-third lead-out area; 13d-fourth lead-out area; 13e-fifth lead-out area; 14-groove; 21-covering material layer; 22a-first opening; 22b-second opening; 22c-third opening; 22d-fourth opening; 22e-fifth opening; 23-sixth opening; 24a-sidewall material layer; 24b-sidewall; 25-conductive material layer. DETAILED DESCRIPTION

[0033] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0034] As used in the present invention, the singular forms "a", "an", and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features specified as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0035] Example 1

[0036] Embodiment 1 provides a method for manufacturing a metal-insulator-metal capacitor.

[0037] Figure 2 This is a flow chart of a method for manufacturing a metal-insulator-metal capacitor provided in Example 1.

[0038] like Figure 2 As shown, the manufacturing method of the metal-insulator-metal capacitor provided in this embodiment includes:

[0039] S01: Providing a substrate having a stack formed by alternating electrode material layers and dielectric material layers, the stack comprising first to Nth electrode material layers and first to Nth lead-out regions corresponding to the first to Nth electrode material layers, respectively, where N is an integer greater than or equal to 4;

[0040] S02: forming a covering material layer to cover the surface of the stack;

[0041] S03: performing a first photolithography and corresponding etching process on the cover material layer and the stack to form N first openings to expose the surface of the first electrode material layer of the first to Nth lead-out regions and forming an N+1th opening for defining a boundary of the capacitor;

[0042] S04: performing second to Mth photolithography and corresponding etching processes on the cover material layer and the stack, respectively, to form second to Nth openings, each exposing a surface of the electrode material layer corresponding to the second to Nth lead-out regions, and etching the N+1th opening to expose the surface of the substrate, wherein in the second to Mth photolithography and corresponding etching processes, each photolithography selects a portion of the first opening in the second to Nth lead-out regions, and each photolithography corresponding etching process etches away at most A layers of the electrode material layer and at most A layers of the dielectric material layer, where A is an integer of 2ˉN-1, and M is N / A rounded up plus A-1;

[0043] S05: forming sidewalls to cover the sidewalls of the first to N+1th openings, and filling the first to Nth openings with a conductive material layer to form a lead-out structure for leading out each electrode material layer.

[0044] Figure 3a ˉ Figure 3i The structural diagram corresponding to the corresponding steps of the manufacturing method of the metal-insulator-metal capacitor provided in this embodiment is shown in FIG. Figure 3a ˉ Figure 3i A method for manufacturing the metal-insulator-metal capacitor will be described in detail.

[0045] First, please refer to Figure 3a, perform step S01, provide a substrate 10, which has a stack formed by alternating electrode material layers and dielectric material layers, the stack including first to N electrode material layers and first to N lead-out regions corresponding to the first to N electrode material layers, respectively, where N is an integer greater than or equal to 4.

[0046] The substrate 10 may be any suitable base material known to those skilled in the art, for example, at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SiOI), silicon-germanium-on-insulator (SiGe-on-insulator (SiGe-on-insulator (SiGe-on-insulator (SiIG)), and germanium-on-insulator (GeOI). In this embodiment, the material of the substrate 10 is described using silicon (silicon substrate 10) as an example.

[0047] The electrode material layer comprises any suitable conductive material that can be etched, such as platinum, aluminum copper, titanium nitride, gold, titanium, tantalum nitride, tungsten, or tungsten nitride. The dielectric material layer can be an insulating material and preferably has a high dielectric constant. It can be one or more of the following: aluminum oxide, hafnium oxide, tantalum oxide, titanium oxide, tantalum oxide, zinc oxide, tungsten oxide, nickel oxide, molybdenum oxide, or silicon dioxide. In the stack of this embodiment, the material and thickness of all electrode material layers can be the same, and the material and thickness of all dielectric material layers can be the same to simplify the subsequent etching process. The number of electrode material layers can preferably be greater than or equal to 4 (i.e., N is greater than or equal to 4). The number of dielectric material layers can be one less than the number of electrode material layers, i.e., N-1 layers. The N electrode material layers in the stack can be, from top to bottom, the first to Nth electrode material layers, and the N-1 dielectric material layers can be, from top to bottom, the first to N-1th dielectric material layers. Of course, an isolation dielectric layer (not shown) may be provided between the substrate 10 and the stack.

[0048] The stack includes first to Nth lead-out regions for electrically leading out the corresponding electrode material layers. For example, the first lead-out region 13a is used to electrically lead out the first electrode material layer 11a, and the second lead-out region 13b is used to electrically lead out the second electrode material layer 11b. Of course, each electrode material layer may also have at least two lead-out regions, and the at least two lead-out regions are dispersed and disposed in different regions.

[0049] In this embodiment, a plurality of trenches 14 are provided on the surface of the substrate 10. A stack of layers covering the trenches 14 and their surrounding areas sequentially forms a multi-layer trench capacitor. The stack may include a total of five electrode material layers and four dielectric material layers, namely, a first electrode material layer 11a, a first dielectric material layer 12a, a second electrode material layer 11b, a second dielectric material layer 12b, a third electrode material layer 11c, a third dielectric material layer 12c, a fourth electrode material layer 11d, a fourth dielectric material layer 12d, and a fifth electrode material layer 11e. Furthermore, for ease of description and illustration, this embodiment intentionally places the five lead-out regions (first to fifth lead-out regions 13a-13e) of the stack in the same cross-sectional view for ease of description and illustration.

[0050] Next, please refer to Figure 3b , executing step S02 to form a covering material layer 21 to cover the surface of the stacked body.

[0051] The cover material layer 21 can be an insulating material and can be a single thin film or a composite structure consisting of at least two thin films. For example, it can include one or more of silicon oxide, silicon nitride, silicon carbide nitride, or silicon oxynitride. The cover material layer 21 covers the surface of the stack and fills the grooves and gaps therein to form a flat surface suitable for photolithography.

[0052] Next, please refer to Figure 3c , execute step S03, perform a first photolithography and corresponding etching process on the covering material layer 21 and the stack, form N first openings 22a to expose the surface of the first electrode material layer 11a of the first to Nth lead-out areas and form the N+1th opening for defining the boundary of the capacitor (capacitor structure).

[0053] Specifically, for example, a first photolithography and corresponding etching process can be performed using a first mask to form at least one first opening 22a in each lead-out region (the first to Nth lead-out regions) for subsequently leading out the first to Nth electrode material layers. The first openings 22a all open the cover material layer 21 and expose the surface of the first electrode material layer 11a. The number and / or cross-sectional shape of the first openings 22a in different lead-out regions can vary. Specifically, the first opening 22a in the first lead-out region 13a can be used directly to lead out the first electrode material layer 11a, while the first openings 22a in other lead-out regions require subsequent photolithography and etching processes to open the corresponding electrode material layers. In one example, some lead-out regions may include at least two first openings 22a, each of which may be in the form of a circular hole or a square hole, while other lead-out regions may include only one first opening 22a, and this first opening 22a may be in the form of an elongated strip (e.g., a trench). Of course, the openings with different cross-sectional shapes preferably have the same or similar opening widths to facilitate improved etching uniformity.

[0054] In particular, while forming the above-mentioned first opening 22a, an N+1 opening (e.g., a sixth opening 23) is also formed. The sixth opening 23 is in the shape of a groove 14 and surrounds all the above-mentioned first openings 22a, and is used to define the boundary outline of the metal-insulator-metal capacitor. Among them, the opening width of the N+1 opening (sixth opening 23) can be greater than or equal to twice the width of the first opening 22a, so as to achieve the patterning of the capacitor structure while forming the lead-out structure in each lead-out area. It should be understood that due to the load effect of the etching process, the etching rate of the electrode material layer and the dielectric material layer under the N+1 opening with a wider opening is greater than that of the first opening 22a with a smaller opening. Therefore, after the first photolithography and the corresponding etching process, the etching stop depth (etching removal depth) of the N+1 opening (sixth opening 23) is greater than the etching stop depth of the first opening 22a.

[0055] Next, step S04 is executed, and the second to Mth photolithography and corresponding etching processes are performed on the covering material layer 21 and the stack, respectively, to form second to Nth openings to expose the surface of the electrode material layer corresponding to the second to Nth lead-out areas, and the N+1th opening is etched to expose the surface of the substrate 10, wherein, in the second to Mth photolithography and corresponding etching processes, each photolithography selects part of the first openings in the second to Nth lead-out areas and each photolithography corresponding etching process etches away at most A layers of electrode material layers and at most A layers of dielectric material layers, where A is an integer of 2ˉN-1, and M is N / A rounded up plus A-1.

[0056] As described above, in this embodiment, A=2, that is, M is N / 2 rounded up plus 1. In the second to M-th photolithography and corresponding etching processes, each photolithography selects part of the first openings 22a in the second to N-th lead-out areas and each photolithography corresponding etching process etches away one electrode material layer and one dielectric material layer or removes two electrode material layers and two dielectric material layers.

[0057] In an example of this embodiment, please refer to Figure 3d ˉ Figure 3f , the number of electrode material layers N is 5, and the second to fourth photolithography and corresponding etching processes can be performed respectively ( Figure 3d Corresponding to the second lithography, Figure 3e Corresponding to the third lithography, Figure 3f Corresponding to the fourth photolithography), which may include two first etching processes and one second etching process, the first etching process removes two electrode material layers and two dielectric material layers on part of the lead-out area, and the second etching process removes one electrode material layer and one dielectric material layer on part of the lead-out area.

[0058] Table 1 shows one of the photolithography and etching schemes

[0059]

[0060] For details, please refer to Figure 3d , perform a second photolithography and corresponding etching process, that is, perform a first etching on the first opening 22a of the third to fifth lead-out regions 13cˉ13e to remove the first to second electrode layers 11aˉ11b and the first to second dielectric material layers 12aˉ12b; then, refer to Figure 3e , perform a third photolithography and corresponding etching process, that is, perform a first etching on the first opening 22a of the fifth lead-out 13e to remove the third to fourth electrode layers 11cˉ11d and the third to fourth dielectric material layers 12cˉ12d; then, refer to Figure 3f , perform a fourth photolithography and corresponding etching process, that is, perform a second etching on the first opening 22a of the second lead-out area 13b to remove the first electrode material layer 11a and the first dielectric material layer 12a, and perform a second etching on the first opening 22a of the fourth lead-out area 13d to remove the third electrode layer 11c and the third dielectric layer 12c. As a result, the first opening 22a of the second lead-out area 13b is subjected to one of the second etching processes to remove a layer of electrode material layer and dielectric material layer to expose the surface of the second electrode material layer 11b, and the first opening 22a of the second lead-out area 13b is used as the second opening 22b for subsequently leading out the second electrode material layer 11b; the first opening 22a of the third lead-out area 13c is subjected to one of the first etching processes to expose the surface of the third electrode material layer 11c, and the first opening 22a of the third lead-out area 13c is used as the third opening 22c for subsequently leading out the third electrode material The first opening 22a of the fourth lead-out area 13d is subjected to a first etching process and a second etching process to expose the surface of the fourth electrode material layer 11d, and the first opening 22a of the fourth lead-out area 13d is used as the fourth opening 22d for subsequently leading out the fourth electrode material layer 11d; the first opening 22a of the fifth lead-out area 13e is subjected to two first etching processes to expose the surface of the fifth electrode material layer 11e, and the first opening 22a of the fifth lead-out area 13e is used as the fifth opening 22e for subsequently leading out the fifth electrode material layer 11e. In addition, the order of the above process steps does not necessarily have to follow the order of Table 1 and the accompanying drawings. For example, step 2 (first etching) of the third lead-out area can also be etched after the third photolithography, as long as the number of layers etched in each lead-out area meets the requirements.

[0061] In another example of this embodiment, the number N of electrode material layers is 8, and the second to fifth photolithography processes and corresponding etching processes may be performed respectively, which may include three first etching processes and one second etching process in total.

[0062] Table 2 shows one of the photolithography and etching schemes.

[0063]

[0064]

[0065] Specifically, as shown in Table 2, in the second photolithography and corresponding etching process, the first etching is performed on the first openings of the third to eighth lead-out areas to remove two electrode material layers and two dielectric material layers; then, in the third photolithography and corresponding etching process, the first etching is performed on the first openings of the fifth to eighth lead-out areas to remove two electrode material layers and two dielectric material layers; then, in the fourth photolithography and corresponding etching process, the first etching is performed on the first openings of the seventh to eighth lead-out areas to remove two electrode material layers and two dielectric material layers; then, in the fifth photolithography and corresponding etching process, the second etching is performed on the first openings of the second lead-out area, the fourth lead-out area, the sixth lead-out area, and the eighth lead-out area to remove one electrode material layer and one dielectric material layer. Thus, the first opening of the second lead-out area is subjected to one of the second etching processes to remove a layer of electrode material layer and a dielectric material layer to expose the surface of the second electrode material layer, and the first opening of the second lead-out area is used as the second opening for subsequently leading out the second electrode material layer; the first opening of the third lead-out area is subjected to one of the first etching processes to expose the surface of the third electrode material layer, and the first opening of the third lead-out area is used as the third opening for subsequently leading out the third electrode material layer; the first opening of the fourth lead-out area is subjected to one of the first etching processes and one of the second etching processes to expose the surface of the fourth electrode material layer, and the first opening of the fourth lead-out area is used as the fourth opening for subsequently leading out the fourth electrode material layer; the first opening of the fifth lead-out area is subjected to one of the first etching processes and one of the second etching processes Two first etching processes expose the surface of the fifth electrode material layer, and the first opening of the fifth lead-out area is used as the fifth opening for subsequently leading out the fifth electrode material layer; the first opening of the sixth lead-out area exposes the sixth electrode material layer in the sixth lead-out area through two first etching processes and one second etching process; the first opening of the seventh lead-out area exposes the surface of the seventh electrode material layer through three first etching processes, and the first opening of the seventh lead-out area is used as the seventh opening for subsequently leading out the seventh electrode material layer; the first opening of the eighth lead-out area exposes the surface of the eighth electrode material layer through three first etching processes and one second etching process, and the first opening of the eighth lead-out area is used as the eighth opening for subsequently leading out the eighth electrode material layer.

[0066] In the above two examples, in order to independently lead out the N electrode material layers of the capacitor structure, a total of M photolithography processes (including the first photolithography) and corresponding etching processes are required, where M is N / 2 rounded up plus 1. Therefore, M is less than N, and when the number of electrode material layers is large, only about half of the number of layers of photolithography and etching processes are required, which is beneficial to saving the number of masks, the number of photolithography times and the corresponding etching times. Moreover, in the etching processes corresponding to the above-mentioned second to M-th photolithography, each time is one of the first etching process or the second etching process, that is, each time etching removes one electrode material layer and one dielectric material layer, or removes two electrode material layers and two dielectric material layers. Compared with the etching process in the related art (capacitor structure with stepped side walls) that etches different number of film layers (multiple etching recipes) multiple times, this embodiment actually only includes the first etching process and the second etching process, that is, two etching recipes. Moreover, the aspect ratio of the first etching process and the second etching process is relatively small, which makes the etching process simpler and easier to achieve better etching effects, such as improving etching uniformity and consistency of etching stop, and easily stopping on the surface of the ultra-thin electrode material layer.

[0067] In fact, the etching process corresponding to the second to M-th photolithography includes a total of M-2 first etching processes and 1 second etching process. As shown in the preferred embodiments of Table 1 and Table 2, the second etching process is performed after the first etching process is performed continuously for M-2 times, and the number of the second to N-th openings exposed by each photolithography in the M-2 first etching processes decreases successively. In addition, it is also feasible to perform the first etching process continuously for M-2 times after performing the second etching process. Of course, in other examples of this embodiment, the order of the second to M-th photolithography and the corresponding etching process may not be limited. For example, the second to M-th photolithography and the corresponding etching process shown in Table 1 or Table 2 may be replaced by

[0068] In addition, it should be noted that in the etching processes corresponding to the second to Mth photolithography, the N+1 opening (e.g., the sixth opening 23) is exposed each time and the corresponding etching process is performed to expose the surface of the substrate 10, thereby realizing the patterning of the capacitor structure and making the capacitor structure (stack) have a vertical plane-shaped sidewall. Compared with the step-shaped sidewall, the capacitor structure of this embodiment can have a larger capacitor area. In the scheme where the number of electrode material layers N is an even number, as shown in Table 2, the number of electrode material layers and dielectric material layers corresponding to the M-2 first etching processes and the 1 second etching process are each one less than the number of electrode material layers and dielectric material layers under the N+1 opening before etching. However, as shown above, since the opening width of the N+1 opening can be greater than or equal to twice the width of the first opening 22a, the etching rate of the electrode material layer and the dielectric material layer under the N+1 opening is greater than the etching rate of the lead-out region, thereby electrically cutting off the region to realize the patterning of the capacitor structure. Of course, in the case where the number of electrode material layers N is an odd number, as shown in Table 1, the number of electrode material layers and dielectric material layers corresponding to M-2 first etching processes and 1 second etching process is the same as the number of electrode material layers and dielectric material layers below the N+1th opening before etching. Therefore, it is easier to achieve patterning of the capacitor structure. In some examples, when the number of electrode material layers N is an odd number, the opening width of the N+1th opening can also be the same as the opening width of the lead-out region.

[0069] It is understood that in each of the second to Mth photolithography passes, the opening width of the same lead-out region can be slightly larger than the opening width of the previous photolithography pass to prevent the influence of overlay deviation. Next, step S05 is performed to form sidewall spacers 24b covering the sidewalls of the first to N+1th openings, and fill the first to Nth openings with a conductive material layer 25 to form a lead-out structure for leading out each electrode material layer.

[0070] For details, please refer to Figure 3g , forming a sidewall material layer 24a to conformally cover the surface of the cover material layer 21 and the inner walls of the first to Nth openings. Figure 3h , an etching process is then performed to remove the spacer material layer 24a at the bottom of the first through Nth openings, exposing the surface of the corresponding electrode material layer. The spacer material layer 24a covering the sidewalls of the first through Nth openings serves as the spacer 24b. Of course, the spacer material layer 24a also conformally covers the inner wall of the N+1th opening and forms the spacer 24b covering the sidewall of the N+1th opening. Whether the bottom of the N+1th opening exposes the surface of the substrate 10 is not feasible. Furthermore, the spacer material layer 24a may be retained, not retained, or partially retained on the surface of the covering material layer 21.

[0071] Please refer to Figure 3i, forming a conductive material layer 25 to cover the surface of the covering material layer 21, and filling the first to Nth openings to the top of the covering material layer 21, then removing the conductive material layer 25 on the covering material layer 21, and using the conductive material layer 25 in the first to Nth openings as a lead-out structure to electrically lead out the electrode material layers of the capacitor structure. Of course, it is feasible that the conductive material layer 25 also fills the N+1th opening or partially fills the N+1th opening. The conductive material layer 25 can be any suitable conductive material, such as titanium, titanium nitride, tantalum, tantalum nitride, tungsten or copper.

[0072] Example 2

[0073] Embodiment 2 provides a method for manufacturing a metal-insulator-metal capacitor.

[0074] Figure 2 This is a flow chart of a method for manufacturing a metal-insulator-metal capacitor provided in Example 2.

[0075] like Figure 2 As shown, the manufacturing method of the metal-insulator-metal capacitor provided in this embodiment includes:

[0076] S01: Providing a substrate having a stack formed by alternating electrode material layers and dielectric material layers, the stack comprising first to Nth electrode material layers and first to Nth lead-out regions corresponding to the first to Nth electrode material layers, respectively, where N is an integer greater than or equal to 4;

[0077] S02: forming a covering material layer to cover the surface of the stack;

[0078] S03: performing a first photolithography and corresponding etching process on the cover material layer and the stack to form N first openings to expose the surface of the first electrode material layer of the first to Nth lead-out regions and forming an N+1th opening for defining a boundary of the capacitor;

[0079] S04: performing second to Mth photolithography and corresponding etching processes on the cover material layer and the stack, respectively, to form second to Nth openings, each exposing a surface of the electrode material layer corresponding to the second to Nth lead-out regions, and etching the N+1th opening to expose the surface of the substrate, wherein in the second to Mth photolithography and corresponding etching processes, each photolithography selects a portion of the first opening in the second to Nth lead-out regions, and each photolithography corresponding etching process etches away at most A layers of the electrode material layer and at most A layers of the dielectric material layer, where A is an integer of 2ˉN-1, and M is N / A rounded up plus A-1;

[0080] S05: forming sidewalls to cover the sidewalls of the first to N+1th openings, and filling the first to Nth openings with a conductive material layer to form a lead-out structure for leading out each electrode material layer.

[0081] The manufacturing method of the metal-insulator-metal capacitor provided in Example 2 is consistent with the manufacturing method of Example 1 in basic principles and basic steps. The only difference is that in step S04, A in Example 2 can also be an integer of 3ˉN-1 (other than 2). For example, N=9, A can be other than 2, and can also be 3 or 4, etc., so as to minimize the number of photolithography times (or masks).

[0082] In one example, the number of electrode material layers N is 9, A=3, and according to the different numbers of etched electrode material layers and dielectric material layers, the etching processes corresponding to the second to Mth photolithography can be divided into first to third etching processes. The first etching process removes three electrode material layers and three dielectric material layers on part of the lead-out area, the second etching process removes two electrode material layers and two dielectric material layers on part of the lead-out area, and the third etching process removes one electrode material layer and one dielectric material layer on part of the lead-out area.

[0083] Table 3 shows one of the photolithography and etching schemes

[0084]

[0085]

[0086] In the photolithography and etching scheme shown in Table 3, in the second photolithography and corresponding etching process, the first etching is performed on the first openings of the fourth to ninth lead-out areas to remove three electrode material layers and three dielectric material layers; then, in the third photolithography and corresponding etching process, the first etching is performed on the first openings of the seventh to ninth lead-out areas to remove three electrode material layers and three dielectric material layers; then, in the fourth photolithography and corresponding etching process, the second etching is performed on the first openings of the third, sixth and ninth lead-out areas to remove two electrode material layers and two dielectric material layers; then, in the fifth photolithography and corresponding etching process, the third etching is performed on the first openings of the second, fifth and eighth lead-out areas to remove one electrode material layer and one dielectric material layer. Thus, the first opening of the second lead-out area is subjected to one of the third etching processes to remove a layer of electrode material layer and a dielectric material layer to expose the surface of the second electrode material layer, and the first opening of the second lead-out area is used as the second opening for subsequently leading out the second electrode material layer; the first opening of the third lead-out area is subjected to one of the second etching processes to expose the surface of the third electrode material layer, and the first opening of the third lead-out area is used as the third opening for subsequently leading out the third electrode material layer; the first opening of the fourth lead-out area is subjected to one of the first etching processes to expose the surface of the fourth electrode material layer, and the first opening of the fourth lead-out area is used as the fourth opening for subsequently leading out the fourth electrode material layer; the first opening of the fifth lead-out area is subjected to one of the first etching processes and one of the third etching processes to expose the surface of the fifth electrode material layer, and the first opening of the fifth lead-out area is used as the fifth The opening is used for the subsequent lead-out of the fifth electrode material layer; the first opening of the sixth lead-out area exposes the sixth electrode material layer of the sixth lead-out area through a first etching process and a second etching process; the first opening of the seventh lead-out area exposes the surface of the seventh electrode material layer through two first etching processes, and the first opening of the seventh lead-out area is used as the seventh opening for the subsequent lead-out of the seventh electrode material layer; the first opening of the eighth lead-out area exposes the surface of the eighth electrode material layer through two first etching processes and a third etching process, and the first opening of the eighth lead-out area is used as the eighth opening for the subsequent lead-out of the eighth electrode material layer; the first opening of the ninth lead-out area exposes the surface of the eighth electrode material layer through two first etching processes and a second etching process, and the first opening of the eighth lead-out area is used as the eighth opening for the subsequent lead-out of the eighth electrode material layer.

[0087] In another example, the number of electrode material layers N is 9, A=4, and according to the different numbers of etched electrode material layers and dielectric material layers, the etching processes corresponding to the second to Mth photolithography can be divided into first to fourth etching processes. The first etching process removes four electrode material layers and four dielectric material layers on the partial lead-out area, the second etching process removes three electrode material layers and three dielectric material layers on the partial lead-out area, the third etching process removes two electrode material layers and two dielectric material layers on the partial lead-out area, and the fourth etching process removes one electrode material layer and one dielectric material layer on the partial lead-out area.

[0088] Table 4 shows one of the photolithography and etching solutions

[0089]

[0090] In this example, the photolithography and etching schemes are shown in Table 4. The photolithography and etching processes are similar to those in Tables 1, 2, and 3, and are not described in detail here.

[0091] It's worth noting that for the number of electrode material layers N, A can be an integer of 2ˉN-1. In a preferred example, B*B is the number closest to the square of N, B is a positive integer, and A is one of B-1, B, or B+1, which can optimize the overall number of photolithography times (or the number of masks). However, conversely, the larger A is, the larger the aspect ratio of the etching process corresponding to A, the greater the difficulty of the etching process, and the more difficult it is to ensure the etching effect. Therefore, it is necessary to balance the difficulty of the etching process and the number of photolithography times. Taking N as 9 as an example, B is 3, and A can be one of 2, 3, or 4. When A is 3, the number of photolithography times is the smallest, and when A is 2, the etching difficulty is the lowest. Taking N as 15 as an example, B is 4, and A can be one of 3, 4, or 5. The number of photolithography times 3, 4, and 5 are the same, and when A is 3, the etching difficulty is the lowest.

[0092] Example 3

[0093] Embodiment 3 provides a metal-insulator-metal capacitor structure.

[0094] Figure 3i This is a schematic cross-sectional view of the metal-insulator-metal capacitor structure provided in Example 3.

[0095] like Figure 3iAs shown, the metal-insulator-metal capacitor provided in this embodiment includes a substrate 10, a stack, first to Nth openings, sidewalls 24b and a lead-out structure. The stack is provided on the substrate 10 and is formed by alternating dielectric material layers and N electrode material layers, and the sidewalls of the stack are vertically planar. The stack is provided with first to Nth openings, each of which exposes the surface of each electrode material layer. The sidewalls of the first to Nth openings are provided with sidewalls 24b. The first to Nth openings are filled with a conductive material layer 25 to form a lead-out structure, which electrically leads out each electrode material layer.

[0096] The stack includes N electrode material layers and N-1 dielectric material layers, and the above-mentioned electrode material layers and dielectric material layers are alternately stacked in sequence to form a multi-layer flat capacitor and / or a multi-layer trench capacitor. Among them, the N electrode material layers can be the first to the Nth electrode material layers from top to bottom, and the N-1 dielectric material layers can be the first to the N-1th dielectric material layers from top to bottom. It should be noted that the above-mentioned stack (capacitor structure) has a side wall in the shape of a vertical plane, that is, each layer of electrode material layer has a similar area. Compared with the side wall in the shape of a step, the vertical planar side wall can maximize the capacitance area of ​​the capacitor structure.

[0097] The stack is distributed with first to Nth lead-out regions, which are arranged in the planar area (non-trench area) of the above-mentioned flat plate capacitor and / or trench capacitor, and are used to electrically lead out the corresponding first to Nth electrode material layers. For example, the first lead-out region 13a is used to electrically lead out the first electrode material layer 11a, and the second lead-out region 13b is used to electrically lead out the second electrode material layer 11b. Each of the first to Nth lead-out regions is provided with an opening. The opening penetrates the covering material layer 21 on the surface of the stack, exposing the surface of the corresponding layer of the first to Nth electrode material layers. For example, the opening in the first lead-out region 13a penetrates the covering material layer 21 to expose the surface of the first electrode material layer 11a, which may be a first opening 22a. The opening in the second lead-out region 13b penetrates the covering material layer 21, one electrode material layer, and one dielectric material layer to expose the surface of the second electrode material layer 11b, which may be a second opening 22b. The opening in the third lead-out region 13c penetrates the covering material layer 21, two electrode material layers, and two dielectric material layers to expose the surface of the third electrode material layer 11c, which may be a third opening 22c. The number and / or cross-sectional shape of the openings (first to Nth openings) in different lead-out regions may vary. Some lead-out regions may include at least two openings, each of which may be circular or square, and / or another lead-out region may include only one opening, which may be an elongated strip (groove 14). In a preferred example, the openings with different opening cross-sectional shapes may also have the same or similar opening widths.

[0098] In addition, at least part of the electrode material layer may also have at least two lead-out areas, and the at least two lead-out areas are dispersed and arranged in different areas. In a preferred embodiment, the at least two lead-out areas and / or at least two openings are centrally symmetrically distributed on the surface of the stack, so that the lead-out structure in each opening can electrically lead each electrode material layer from the stack. Figure 4a In the top view shown, four groups of trenches 14 are provided on the surface of the substrate 10. Adjacent groups of trenches 14 are arranged orthogonally. The stack covers the trenches 14 and the surrounding areas to form a multi-layer trench capacitor. The stack has seven electrode material layers and corresponding first to seventh lead-out regions ( Figure 4a In ①ˉ⑦), the number of lead-out regions of each electrode material layer is two, and they are all centrally symmetrically distributed on the surface of the stack, and each lead-out region is provided with four openings and a conductive material layer 25 in the openings. Figure 4b In the top view shown, the stack has eight electrode material layers and corresponding first to eighth lead-out regions ( Figure 4b ①ˉ⑧) in the figure, wherein the first to seventh lead-out areas (①ˉ⑦) can be set as reference. Figure 4a The number of the eighth lead-out region (⑧) can be one and located at the center of the stack surface. In addition, in other examples of this embodiment, the number of trench groups of the trench capacitor can be other suitable numbers, and the trenches 14 can be arranged in any other suitable manner.

[0099] In summary, the present invention alternately stacks electrode material layers and dielectric material layers on a substrate to form a stack, which includes first to N electrode material layers and first to N lead-out regions corresponding to the first to N electrode material layers, respectively. Then, a covering material layer is formed to cover the surface of the stack, and then, a first photolithography and corresponding etching process are performed on the covering material layer and the stack to form N first openings exposing the surface of the first electrode material layer of the first to N lead-out regions and forming an N+1th opening for defining the boundary of the capacitor, and then, a second to Mth photolithography and corresponding etching process are performed on the covering material layer and the stack to form the second to Nth lead-out regions. The Nth openings each expose the surface of the electrode material layer corresponding to the second to Nth extraction regions, and the N+1th opening is etched to expose the surface of the substrate. In the second to Mth photolithography and corresponding etching processes, each photolithography step selects a portion of the first opening in the second to Nth extraction regions, and each photolithography step corresponding to the etching process removes at most A layers of the electrode material layer and at most A layers of the dielectric material layer, where A is an integer of 2ˉN-1 and M is N / A rounded up plus A-1. Next, sidewalls are formed to cover the sidewalls of the first to N+1th openings, and a conductive material layer is filled within the first to Nth openings to form extraction structures for extracting each electrode material layer. As can be seen from the above process, in the present invention, only M photolithography steps (including the first photolithography step) and corresponding etching processes are required to complete the independent extraction of each electrode material layer of the capacitor structure and the patterning of the capacitor structure. In particular, when the number of electrode material layers is large, only less than half the number of photolithography and etching processes are required, which helps save the number of masks, the number of photolithography steps, and the corresponding etching times. Moreover, compared to the etching process of the related art (capacitor structure with stepped sidewalls) in which different layers of film are etched multiple times (multiple etching recipes), in the etching process corresponding to the second to Mth photolithography of the present invention, fewer layers of electrode material layer and dielectric material layer are removed each time, making the etching process simpler and easier to achieve better etching effects, including improving etching uniformity and consistency of etching stop, and easily stopping on the surface of the ultra-thin electrode material layer. In addition, compared to the stepped sidewalls, the sidewalls of the capacitor structure of the present invention are vertically planar, which can also give it a larger capacitor area.

[0100] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a metal-insulator-metal capacitor, characterized in that: include: Providing a substrate having a stack formed by alternating electrode material layers and dielectric material layers, the stack including first to Nth electrode material layers and first to Nth lead-out regions corresponding to the first to Nth electrode material layers, respectively, where N is an integer greater than or equal to 4; forming a covering material layer to cover the surface of the stack; Performing a first photolithography and corresponding etching process on the cover material layer and the stack to form N first openings to expose the surface of the first electrode material layer of the first to Nth lead-out regions and forming an N+1th opening for defining a boundary of the capacitor; performing second to Mth photolithography and corresponding etching processes on the cover material layer and the stack, respectively, to form second to Nth openings, each exposing a surface of the electrode material layer corresponding to the second to Nth lead-out regions, and etching the N+1th opening to expose the surface of the substrate, wherein in the second to Mth photolithography and corresponding etching processes, each photolithography selects a portion of the first opening in the second to Nth lead-out regions, and each photolithography and corresponding etching process etches away at most A layers of the electrode material layer and at most A layers of the dielectric material layer, where A is an integer of 2ˉN-1, and M is N / A rounded up plus A-1; A sidewall spacer is formed to cover the sidewalls of the first to N+1th openings, and a conductive material layer is filled in the first to Nth openings to form a lead-out structure for leading out each electrode material layer.

2. The method for manufacturing a metal-insulator-metal capacitor according to claim 1, wherein: The stack includes a multilayer flat plate capacitor and / or trench capacitor formed by the electrode material layer and the dielectric material layer, and the first to Nth lead-out regions are located in non-trench areas of the flat plate capacitor and / or trench capacitor.

3. The method for manufacturing a metal-insulator-metal capacitor according to claim 1, wherein: A width of the (N+1)th opening is greater than or equal to twice a width of the first opening.

4. The method for manufacturing a metal-insulator-metal capacitor according to claim 1 or 3, wherein: The first to Nth openings have the same opening width.

5. The method for manufacturing a metal-insulator-metal capacitor according to claim 1, wherein: B*B is the square number closest to N, B is a positive integer, and A is one of B-1, B or B+1.

6. The method for manufacturing a metal-insulator-metal capacitor according to claim 1, wherein: A=2, the etching processes corresponding to the second to Mth photolithography include M-2 first etching processes and 1 second etching process, the first etching process removes two layers of electrode material and two layers of dielectric material on part of the lead-out area, and the second etching process removes one layer of electrode material and one layer of dielectric material on part of the lead-out area.

7. The method for manufacturing a metal-insulator-metal capacitor according to claim 6, wherein: When performing the etching processes corresponding to the second to M-th photolithography, the first etching process is continuously performed M-2 times and then the second etching process is performed, or the second etching process is continuously performed M-2 times and then the first etching process is performed.

8. The method for manufacturing a metal-insulator-metal capacitor according to claim 6 or 7, wherein: The numbers of the second to Nth openings exposed by each photolithography process in M-2 times of the first etching process decrease in sequence.

9. A metal-insulator-metal capacitor structure, characterized in that: include: substrate; a stacked body disposed on the substrate and formed by alternately stacking dielectric material layers and first to Nth electrode material layers, wherein the sidewalls of the stacked body are vertically planar; First to Nth openings are provided in the stack body and respectively expose surfaces of the first to Nth electrode material layers; Side walls, provided on side walls of the first to Nth openings; The lead-out structures filled in the first to N-th openings electrically lead out the first to N-th electrode material layers respectively.

10. The metal-insulator-metal capacitor structure according to claim 9, wherein: At least some of the first to Nth openings are centrally symmetrically distributed on the surface of the stack.

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