Modeling method and device of semiconductor device and electronic equipment

Abstract

The invention provides a modeling method and device of a semiconductor device and electronic equipment. A semiconductor device model comprises a parasitic part and an intrinsic part, and the modeling method comprises the steps that parasitic parameters and intrinsic parameters of a semiconductor device are acquired, the parasitic parameters are used for forming the parasitic part, and the intrinsic parameters are used for forming the intrinsic part; according to a preset algorithm and the intrinsic parameters, electrical characteristic parameters of the intrinsic part are obtained, and the electrical characteristic parameters at least comprise a current source model and a charge source model; and generating a semiconductor device model according to the electrical characteristic parameters and the parasitic parameters. Therefore, parameters of the model can be adjusted, and the model is obviously superior to an existing model in terms of convergence, precision, simulation speed and model development difficulty.

Description

Semiconductor device modeling method, device and electronic equipment Technical Field

[0001] The present application relates to the field of device modeling technology, and in particular to a semiconductor device modeling method, a semiconductor device modeling apparatus, an electronic device, and a computer-readable storage medium. Background Art

[0002] Semiconductor device models are the link between device physics and circuit design, and are the raw materials for circuit simulation using EDA software. Usually, accurate circuit simulation results can only be guaranteed if an accurate semiconductor device model is obtained.

[0003] In the prior art, semiconductor device models are mainly divided into physical models, empirical models, behavioral models, and table-based models. Among them, the physical model has a clear physical meaning, is easy to scale, and has adjustable parameters, but is difficult to develop, time-consuming to calculate, and has poor convergence; the empirical model has high accuracy, good convergence, and fast simulation speed, but has unclear physical meaning and difficult parameter extraction; the behavioral model has high accuracy, is difficult to scale, has non-adjustable parameters, high testing cost, and a large amount of test data; the table-based model has high accuracy, is easy to model, has a fast simulation speed, and good convergence, but is difficult to extrapolate, has non-adjustable parameters, and has unclear physical meaning. Therefore, due to the uncontrollability of the device research and development process, the semiconductor device model has certain limitations. Moreover, since the formation of a good semiconductor device model is inextricably linked to the convergence, accuracy, simulation speed, and difficulty of model development, it is urgent to develop a new modeling method that can improve the controllability and accuracy of the semiconductor device model so that the formed semiconductor device model can be significantly better than the existing model.

[0004] Summary of the Invention

[0005] The main purpose of this application is to provide a semiconductor device modeling method, a semiconductor device modeling device, an electronic device and a computer-readable storage medium to solve the problem in the prior art of difficulties in semiconductor device research and development due to the limitations of semiconductor device models.

[0006] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a modeling method for a semiconductor device is provided, wherein the semiconductor device model includes a parasitic part and an intrinsic part, and the modeling method includes: obtaining parasitic parameters of the semiconductor device and intrinsic parameters of the semiconductor device, wherein the parasitic parameters are used to form the parasitic part, and the intrinsic parameters are used to form the intrinsic part; according to a preset algorithm and the intrinsic parameters, obtaining electrical characteristic parameters of the intrinsic part, the electrical characteristic parameters include at least a current source model and a charge source model; and generating a semiconductor device model according to the electrical characteristic parameters and the parasitic parameters.

[0007] Optionally, obtaining the electrical characteristic parameters according to a preset algorithm and the intrinsic parameters includes: preprocessing the intrinsic parameters to obtain equivalent parameters corresponding to the intrinsic parameters; and obtaining the electrical characteristic parameters according to the preset algorithm and the equivalent parameters.

[0008] Optionally, the intrinsic parameters are preprocessed to obtain equivalent parameters corresponding to the intrinsic parameters, including: obtaining preset parameters of the semiconductor device, the preset parameters including at least delay parameters, threshold voltage, subthreshold parameters, leakage voltage coefficient, trap effect parameters, mobility parameters, preprocessing adjustable parameters and temperature; preprocessing is performed according to the preset parameters and the intrinsic parameters to obtain equivalent parameters corresponding to the intrinsic parameters.

[0009] Optionally, the intrinsic parameters include at least a gate-source bias voltage of the semiconductor device and a source-drain bias voltage of the semiconductor device, and the intrinsic parameters are preprocessed to obtain equivalent parameters corresponding to the intrinsic parameters, including: performing a first preprocessing on the gate-source bias voltage to obtain an equivalent gate-source bias voltage; performing a second preprocessing on the source-drain bias voltage to obtain an equivalent source-drain bias voltage.

[0010] Optionally, electrical characteristic parameters are obtained according to a preset algorithm and equivalent parameters, including: obtaining test data of the semiconductor device, the test data including at least a bias voltage value of the semiconductor device and a current value corresponding to the bias voltage value, the test data being used to characterize the electrical characteristics of the semiconductor device according to the bias voltage value and the current value; and obtaining electrical characteristic parameters according to the test data, equivalent parameters and the preset algorithm.

[0011] Optionally, the bias voltage interval of the semiconductor device includes a gate-source bias voltage interval and a source-drain bias voltage interval, different bias voltage intervals of the gate-source bias voltage interval include a low gate-source bias voltage interval and a high gate-source bias voltage interval, and different bias voltage intervals of the source-drain bias voltage interval include a low source-drain bias voltage interval and a high source-drain bias voltage interval. Obtaining test data of the semiconductor device includes: obtaining first test data corresponding to a first test point, wherein the first test point is a test point in a low gate-source bias voltage region and a low source-drain bias voltage region; obtaining second test data corresponding to a second test point, wherein the second test point is a test point in a high gate-source bias voltage region and a high source-drain bias voltage region, and a step size of bias voltage values ​​between adjacent first test points is smaller than a step size of bias voltage values ​​between adjacent second test points.

[0012] Optionally, it also includes: obtaining post-processing adjustable parameters of the semiconductor device, the post-processing adjustable parameters including at least thermal effect parameters and breakdown voltage parameters; performing post-processing according to the current source model and the post-processing adjustable parameters to obtain a target current source model; and generating a semiconductor device model according to the target current source model, the charge source model and the parasitic parameters.

[0013] According to another aspect of the present application, a modeling device for a semiconductor device is provided, wherein the semiconductor device model includes a parasitic part and an intrinsic part, and the device includes: an acquisition module for acquiring parasitic parameters and intrinsic parameters of the semiconductor device, the parasitic parameters are used to form the parasitic part, and the intrinsic parameters are used to form the intrinsic part; an acquisition module for obtaining electrical characteristic parameters of the intrinsic part according to a preset algorithm and the intrinsic parameters, the electrical characteristic parameters including at least a current source model and a charge source model; and a generation module for generating a semiconductor device model according to the electrical characteristic parameters and the parasitic parameters.

[0014] According to another aspect of the present application, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement the semiconductor device modeling method as described above.

[0015] According to another aspect of the present application, a computer-readable storage medium is provided. When instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device can execute the semiconductor device modeling method as described above.

[0016] By applying the technical solution of the present application, a modeling method for semiconductor devices is provided, in which the acquired intrinsic parameters of the semiconductor device are first processed using a preset algorithm, so that the electrical characteristic parameters of the intrinsic part can be obtained according to the intrinsic parameters and the preset algorithm, and then a semiconductor device model is formed according to the electrical characteristic parameters and the parasitic parameters obtained above. Since the mapping relationship between the intrinsic parameters and the electrical characteristic parameters includes adjustable parameters, the parameters of the model can be adjusted after training between the above intrinsic parameters and the electrical characteristic parameters through the preset algorithm, so that the model is significantly superior to the existing model in terms of model convergence, accuracy, simulation speed and difficulty of model development. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings that constitute part of this application are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0018] FIG1 is a hardware structure block diagram of a computer terminal for a modeling method of a semiconductor device according to an exemplary embodiment;

[0019] FIG2 is a flowchart illustrating a modeling method for a semiconductor device according to an exemplary embodiment;

[0020] 3 is a structural block diagram of a semiconductor device modeling apparatus according to Embodiment 2 of the present application;

[0021] FIG4 is a device block diagram of a terminal according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0023] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0025] Example 1

[0026] According to an embodiment of the present application, an embodiment of a modeling method for a semiconductor device is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0027] The method embodiment provided in Example 1 of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Figure 1 shows a hardware structure block diagram of a computer terminal (or mobile device) for implementing a modeling method for a semiconductor device. As shown in Figure 1, the computer terminal 10 (or mobile device) may include one or more (102a, 102b, ..., 102n are used in the figure to illustrate) processors 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory 104 for storing data, and a transmission device for communication functions. In addition, it may also include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of the BUS bus), a network interface, a power supply and / or a camera. It will be understood by those skilled in the art that the structure shown in Figure 1 is only for illustration and does not limit the structure of the above-mentioned electronic device. For example, the computer terminal 10 may also include more or fewer components than those shown in Figure 1, or have a configuration different from that shown in Figure 1.

[0028] It should be noted that the one or more processors 102 and / or other data processing circuits described above may generally be referred to herein as "data processing circuitry". The data processing circuitry may be embodied in whole or in part as software, hardware, firmware, or any other combination thereof. In addition, the data processing circuitry may be a single independent processing module, or may be incorporated in whole or in part into any of the other components of the computer terminal 10 (or mobile device). As described in the embodiments of the present application, the data processing circuitry serves as a processor control (e.g., selection of a variable resistor terminal path connected to an interface).

[0029] The memory 104 can be used to store software programs and modules of application software, such as the program instructions / data storage device corresponding to the semiconductor device modeling method in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, the semiconductor device modeling method of the above-mentioned application is realized. The memory 104 may include a high-speed random access memory and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories may be connected to the computer terminal 10 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0030] The transmission device is used to receive or send data via a network. Specific examples of the aforementioned network may include a wireless network provided by the communications provider of the computer terminal 10. In one embodiment, the transmission device includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0031] The display may be, for example, a touch screen liquid crystal display (LCD) that enables a user to interact with a user interface of the computer terminal 10 (or mobile device).

[0032] In the above operating environment, the present application provides a modeling method for a semiconductor device as shown in FIG2 . FIG2 is a flow chart of the modeling method for a semiconductor device according to Embodiment 1 of the present application. As shown in FIG2 , the semiconductor device model includes a parasitic part and an intrinsic part. The modeling method includes:

[0033] Step S202, obtaining parasitic parameters and intrinsic parameters of the semiconductor device, wherein the parasitic parameters are used to form a parasitic part, and the intrinsic parameters are used to form an intrinsic part;

[0034] Step S204, obtaining electrical characteristic parameters of the intrinsic part according to a preset algorithm and the intrinsic parameters, where the electrical characteristic parameters at least include a current source model and a charge source model;

[0035] Step S206 : generating a semiconductor device model according to the electrical characteristic parameters and parasitic parameters.

[0036] The above-mentioned semiconductor device modeling method is adopted. By first processing the obtained intrinsic parameters of the semiconductor device using a preset algorithm, the electrical characteristic parameters of the intrinsic part can be obtained according to the intrinsic parameters and the preset algorithm, and then a semiconductor device model is formed according to the electrical characteristic parameters and the parasitic parameters obtained above. Since the mapping relationship formed between the intrinsic parameters and the electrical characteristic parameters includes adjustable parameters, the parameters of the model can be adjusted after training between the above-mentioned intrinsic parameters and the electrical characteristic parameters through a preset algorithm, so that the model is significantly superior to the existing model in terms of convergence, accuracy, simulation speed and difficulty of model development.

[0037] In some optional embodiments, electrical characteristic parameters are obtained according to a preset algorithm and intrinsic parameters, including: preprocessing the intrinsic parameters to obtain equivalent parameters corresponding to the intrinsic parameters; and obtaining electrical characteristic parameters according to the preset algorithm and the equivalent parameters.

[0038] In the above embodiment, in order to obtain the electrical characteristic parameters through the above preset algorithm and intrinsic parameters, the mapping relationship between the intrinsic parameters and the electrical characteristic parameters includes adjustable parameters, and the intrinsic parameters are preprocessed to obtain equivalent parameters corresponding to the intrinsic parameters. Since the parameters involved in the preprocessing include adjustable parameters, the parameters of the equivalent parameters are adjustable, and then after the optimization operation is performed according to the equivalent parameters and the preset algorithm, the electrical characteristic parameters obtained can be made more consistent with the actual device characteristics by adjusting the above adjustable parameters.

[0039] In some optional embodiments, the intrinsic parameters are preprocessed to obtain equivalent parameters corresponding to the intrinsic parameters, including: obtaining preset parameters of the semiconductor device, the preset parameters including at least a delay parameter, a threshold voltage, a subthreshold parameter, a leakage voltage coefficient, a trap effect parameter, a mobility parameter, a preprocessing adjustable parameter, and a temperature; and performing preprocessing according to the preset parameters and the intrinsic parameters to obtain equivalent parameters corresponding to the intrinsic parameters.

[0040] Since the model parameters of the semiconductor device model are closely related to the physical mechanism, in order to make the semiconductor device model satisfy the physical mechanism, in the above embodiment, the above intrinsic parameters are preprocessed so that the obtained equivalent parameters are more in line with the actual device characteristics, thereby satisfying the physical mechanism of the device. Moreover, since adjustable parameters are involved in the above preprocessing process, the parameter adaptation range of the model parameters is larger, thereby being able to form a semiconductor device model that is better than the existing model.

[0041] Among them, in order to enable the threshold voltage offset, drain-induced barrier lowering effect (DIBL) and channel length modulation effect (CLM), trap effect, thermal effect, etc. of the semiconductor device model to be adjusted through adjustable parameters, delay parameters, threshold voltage, subthreshold parameters, leakage voltage coefficient, trap effect, mobility parameters, pretreatment adjustable parameters and temperature are also added in the pretreatment process to introduce device physical effects, thereby achieving the purpose of adjusting the channel length modulation effect (CLM), the threshold voltage offset, mobility reduction, saturation velocity, hot carrier effect, drain-induced barrier lowering effect (DIBL) and output impedance change caused by leakage voltage of the semiconductor device model by adjusting the above-mentioned adjustable parameters.

[0042] In some optional embodiments, the intrinsic parameters include at least a gate-source bias voltage and a source-drain bias voltage of the semiconductor device, and preprocessing the intrinsic parameters to obtain equivalent parameters corresponding to the intrinsic parameters includes: performing a first preprocessing on the gate-source bias voltage to obtain an equivalent gate-source bias voltage; and performing a second preprocessing on the source-drain bias voltage to obtain an equivalent source-drain bias voltage. In the above embodiment, since the intrinsic portion of the semiconductor device model is related to the bias voltage, the intrinsic parameters include at least the gate-source bias voltage and the source-drain bias voltage of the semiconductor device. By preprocessing the gate-source bias voltage and the source-drain bias voltage, the equivalent gate-source bias voltage and the equivalent source-drain bias voltage can be obtained, wherein the equivalent gate-source bias voltage is obtained by performing the first preprocessing on the gate-source bias voltage, and the equivalent source-drain bias voltage is obtained by performing the second preprocessing on the source-drain bias voltage.

[0043] Exemplarily, firstly, the first preset parameters involved in the first preprocessing are obtained, and the first preset parameters may include the above-mentioned delay parameters, the above-mentioned threshold voltage, the above-mentioned subthreshold parameters, the above-mentioned leakage voltage coefficient, and the first preprocessing adjustable parameters and the second preprocessing adjustable parameters. Then, the first preprocessing is performed according to the above-mentioned first preset parameters and the gate-source bias voltage, so as to obtain an equivalent gate-source bias voltage corresponding to the gate-source bias voltage. Thus, by adjusting the above-mentioned first preprocessing adjustable parameters and the second preprocessing adjustable parameters, the equivalent gate-source bias voltage under different parameters can be obtained, so that the model parameter adaptation range of the semiconductor device model is larger.

[0044] Exemplarily, the first preprocessing may include:

[0045] V gs_delayed (t) = V gs (t-TAU),

[0046] V gst2 =V gs_delayed -(V to_f +(GAMMA×V ds )),

[0047]

[0048]

[0049] Among them, V gs is the gate-source bias voltage, V ds is the source-drain bias voltage, t is the time variable, TAU is the delay parameter, V gs_delayed (t) is the delayed gate-source bias voltage, V to_f is the threshold voltage, GAMMA is the leakage voltage coefficient, VK is the first pre-processing adjustable parameter, DELTA is the second pre-processing adjustable parameter, VST is the sub-threshold parameter, Vgst1 and V gst2 is the intermediate parameter of the equivalent gate-source bias voltage, V gst is the final equivalent gate-source bias voltage.

[0050] Exemplarily, first obtain the second preset parameters involved in the second preprocessing, which may include the above-mentioned breakdown voltage, the third preprocessing adjustable parameter, the fourth preprocessing adjustable parameter, the fifth preprocessing adjustable parameter and the sixth preprocessing adjustable parameter, and then perform the second preprocessing by the second preprocessing adjustable parameter and the above-mentioned source-drain bias voltage, thereby obtaining an equivalent source-drain bias voltage corresponding to the source-drain bias voltage. Thus, by adjusting the above-mentioned third preprocessing adjustable parameter, the fourth preprocessing adjustable parameter, the fifth preprocessing adjustable parameter and the sixth preprocessing adjustable parameter, the equivalent source-drain bias voltage under different parameters can be obtained, thereby making the model parameter adaptation range of the semiconductor device model larger. Furthermore, the equivalent source-drain bias voltage can be obtained by multiplying the drain compression factor after the second preprocessing by the source-drain bias voltage, so that in the low source-drain bias voltage region, the drain compression factor makes the model more accurate.

[0051] Exemplarily, the second preprocessing may include:

[0052]

[0053]

[0054] Among them, V br is the breakdown voltage, M1 is the third pre-processing adjustable parameter, M2 is the fourth pre-processing adjustable parameter, M3 is the fifth pre-processing adjustable parameter, K2 is the sixth pre-processing adjustable parameter, V breff is the intermediate parameter of the equivalent breakdown voltage, V breff1 is the equivalent breakdown voltage.

[0055] In some optional embodiments, electrical characteristic parameters are obtained according to a preset algorithm and equivalent parameters, including: obtaining test data of a semiconductor device, the test data including at least a bias voltage value of the semiconductor device and a current value corresponding to the bias voltage value, the test data being used to characterize the electrical characteristics of the semiconductor device according to the bias voltage value and the current value; and obtaining electrical characteristic parameters according to the test data, equivalent parameters and a preset algorithm.

[0056] In the above embodiment, in order to make the semiconductor device model more accurate and the electrical characteristics of the semiconductor device model closer to the electrical characteristics of the actual semiconductor device, the above test data of the actual semiconductor device is first obtained, and then the test data is input into the preset algorithm, so that after the preset algorithm performs optimization calculations based on the above test data and equivalent parameters, the electrical characteristic parameters obtained can better reflect the nonlinear performance of the device.

[0057] For example, the electrical characteristic parameters include a current source model and a charge source model. The current source model can be obtained by mapping the gate-source bias voltage, the source-drain bias voltage, and the temperature, that is, the current source model I ds =f(V gs , V ds , T), the charge source model may include multiple, respectively, a gate-source charge source model, a source-drain charge source model and a gate-drain charge source model, the gate-source charge source model Q gs =(V gs , T), the source-drain charge source model Q ds =(V ds , T), the gate-drain charge source model Q gd =(V gd , T), where V gs is the gate-source bias voltage, V ds is the source-drain bias voltage, V gd is the gate-drain bias voltage, and T is the temperature.

[0058] The preset algorithm may include, but is not limited to, a physical method, an empirical fitting method, a neural network training method, etc. Optionally, a neural network training algorithm may be used to train the data after the first preprocessing, the data after the second preprocessing, and the test data to obtain a semiconductor device model. Since the parameters in the first preprocessing and the second preprocessing include adjustable parameters, the parameters of the semiconductor device model are adjustable. Therefore, whether in terms of model convergence, accuracy, simulation speed, or difficulty of model development, the model is significantly superior to existing models and has high commercial value.

[0059] In some optional embodiments, the bias voltage interval of the semiconductor device includes a gate-source bias voltage interval and a source-drain bias voltage interval, different bias voltage intervals of the gate-source bias voltage interval include a low gate-source bias voltage interval and a high gate-source bias voltage interval, and different bias voltage intervals of the source-drain bias voltage interval include a low source-drain bias voltage interval and a high source-drain bias voltage interval, and obtaining test data of the semiconductor device includes: obtaining first test data corresponding to a first test point, wherein the first test point is a test point in a low gate-source bias voltage region and a low source-drain bias voltage region; obtaining second test data corresponding to a second test point, wherein the second test point is a test point in a high gate-source bias voltage region and a high source-drain bias voltage region, and a step size of bias voltage values ​​between adjacent first test points is smaller than a step size of bias voltage values ​​between adjacent second test points.

[0060] Since the low gate-source bias voltage region and the low source-drain bias voltage region of the semiconductor device model are the locations where the device enters the saturation region from the linear region, the model accuracy of the low gate-source bias voltage region and the model accuracy of the low source-drain bias voltage region of the semiconductor device model have a greater impact on the RF simulation results. Therefore, in the above embodiment, in order to improve the model accuracy of the low gate-source bias voltage region and the model accuracy of the low source-drain bias voltage region of the semiconductor device model, more first test points are obtained in the low gate-source bias voltage region and the low source-drain bias voltage region. In order to avoid the extension of the test time caused by obtaining more first test points, and to avoid the problem of extending the model development cycle and test reliability, fewer second test points are obtained in the high gate-source bias voltage region and the high source-drain bias voltage region, and the step amount between two adjacent first test points is smaller than the step amount between two adjacent second test points. As a result, the model accuracy of the low gate-source bias voltage region and the model accuracy of the low source-drain bias voltage region are improved, and the problem of long modeling development cycle is solved.

[0061] In some optional embodiments, it also includes: obtaining post-processing adjustable parameters of the semiconductor device, the post-processing adjustable parameters including at least thermal effect parameters and breakdown voltage parameters; performing post-processing according to the current source model and the post-processing adjustable parameters to obtain a target current source model; and generating a semiconductor device model according to the target current source model, the charge source model, and the parasitic parameters.

[0062] In the above embodiment, in order to make the semiconductor device model satisfy the device physical mechanism under the breakdown voltage, the above current source model is post-processed to achieve the purpose that the semiconductor device model generated according to the above charge source model, the above parasitic parameters and the target current source model obtained after post-processing can satisfy the device physical mechanism under the breakdown voltage, and by post-processing the current source model, the interpolation and extrapolation of the generated semiconductor device model are more in line with the device physical laws, thereby improving the accuracy of model interpolation and extrapolation.

[0063] Exemplarily, post-processing the current source model includes:

[0064]

[0065] Among them, K1, ALPHA, Beta, VGEXP, and LAMBDA are all post-processing adjustable parameters.

[0066] The above-mentioned modeling method makes the generation of semiconductor device models fully automated, storing not only two-dimensional current data but also other intrinsic parameter data, so that the information of all bias points of the device is entered into the semiconductor device model, thereby well reflecting the nonlinear performance of the semiconductor device. Moreover, through the above-mentioned modeling method, the RF large signal model can be obtained in batches from TCAD process simulation data, so that the RF large signal model can be used for both process evaluation and chip design, thus realizing collaborative simulation of process and design, greatly accelerating the process optimization process, and greatly shortening the cycle from process to chip design and manufacturing, reducing the number of chip tape-outs, and saving costs.

[0067] Example 2

[0068] According to an embodiment of the present application, a device for implementing the above-mentioned semiconductor device modeling method is also provided. FIG3 is a structural block diagram of the semiconductor device modeling device according to Embodiment 2 of the present application. The semiconductor device model includes a parasitic part and an intrinsic part. The device includes: an acquisition module 302, a obtaining module 304, and a generation module 306. The device is described in detail below:

[0069] An acquisition module 302 is configured to acquire parasitic parameters and intrinsic parameters of a semiconductor device, wherein the parasitic parameters are used to form a parasitic part and the intrinsic parameters are used to form an intrinsic part;

[0070] An obtaining module 304 is configured to obtain electrical characteristic parameters of the intrinsic part according to a preset algorithm and the intrinsic parameters, wherein the electrical characteristic parameters include at least a current source model and a charge source model;

[0071] The generating module 306 is configured to generate a semiconductor device model according to the electrical characteristic parameters and parasitic parameters.

[0072] It should be noted here that the above-mentioned acquisition module 302, obtaining module 304 and generation module 306 correspond to steps S202 to S206 in Example 1, and the instances and application scenarios implemented by multiple modules and corresponding steps are the same, but are not limited to the contents disclosed in the above-mentioned Example 1.

[0073] Example 3

[0074] An embodiment of the present application may provide an electronic device, which may be any computer terminal device in a computer terminal group.

[0075] Optionally, in this embodiment, the electronic device may be located in at least one network device among a plurality of network devices of a computer network.

[0076] Alternatively, Figure 4 is a block diagram of an electronic device according to an exemplary embodiment. As shown in Figure 4 , the electronic device may include: one or more (only one is shown) processors 41; and a memory 42 for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement the semiconductor device modeling method of the first embodiment.

[0077] Among them, the memory can be used to store software programs and modules, such as the program instructions / modules corresponding to the modeling method and device of the semiconductor device in the embodiment of the present application. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, that is, realizing the above-mentioned modeling method of the semiconductor device. The memory may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include a memory remotely arranged relative to the processor, and these remote memories can be connected to the computer terminal via a network. Examples of the above-mentioned network include but are not limited to the Internet, corporate intranet, local area network, mobile communication network and their combinations.

[0078] The processor can call the information and application stored in the memory through the transmission device to perform the following steps: the semiconductor device model includes a parasitic part and an intrinsic part, and the modeling method of the semiconductor device includes: obtaining the parasitic parameters of the semiconductor device and the intrinsic parameters of the semiconductor device, wherein the parasitic parameters are used to form the parasitic part, and the intrinsic parameters are used to form the intrinsic part; according to the preset algorithm and the intrinsic parameters, the electrical characteristic parameters of the intrinsic part are obtained, and the electrical characteristic parameters include at least a current source model and a charge source model; according to the electrical characteristic parameters and the parasitic parameters, a semiconductor device model is generated.

[0079] Optionally, the processor may also execute the program code of the following steps: obtaining electrical characteristic parameters according to a preset algorithm and intrinsic parameters, including: preprocessing the intrinsic parameters to obtain equivalent parameters corresponding to the intrinsic parameters; obtaining electrical characteristic parameters according to the preset algorithm and equivalent parameters.

[0080] Optionally, the processor may further execute program code for the following steps: preprocessing the intrinsic parameters to obtain equivalent parameters corresponding to the intrinsic parameters, including: obtaining preset parameters of the semiconductor device, the preset parameters including at least a delay parameter, a threshold voltage, a subthreshold parameter, a leakage voltage coefficient, a preprocessing adjustable parameter, and a temperature; performing preprocessing based on the preset parameters and the intrinsic parameters to obtain equivalent parameters corresponding to the intrinsic parameters. Optionally, the processor may further execute program code for the following steps: the intrinsic parameters include at least a gate-source bias voltage and a source-drain bias voltage of the semiconductor device; preprocessing the intrinsic parameters to obtain equivalent parameters corresponding to the intrinsic parameters, including: performing a first preprocessing on the gate-source bias voltage to obtain an equivalent gate-source bias voltage; and performing a second preprocessing on the source-drain bias voltage to obtain an equivalent source-drain bias voltage.

[0081] Optionally, the processor may also execute the program code of the following steps: obtaining electrical characteristic parameters according to a preset algorithm and equivalent parameters, including: obtaining test data of the semiconductor device, the test data including at least a bias voltage value of the semiconductor device, and a current value corresponding to the bias voltage value, the test data being used to characterize the electrical characteristics of the semiconductor device according to the bias voltage value and the current value; obtaining electrical characteristic parameters according to the test data, the equivalent parameters and the preset algorithm.

[0082] Optionally, the processor may also execute program code for the following steps: the bias voltage interval of the semiconductor device includes a gate-source bias voltage interval and a source-drain bias voltage interval, different bias voltage intervals of the gate-source bias voltage interval include a low gate-source bias voltage interval and a high gate-source bias voltage interval, and different bias voltage intervals of the source-drain bias voltage interval include a low source-drain bias voltage interval and a high source-drain bias voltage interval; obtaining test data of the semiconductor device, including: obtaining first test data corresponding to a first test point, wherein the first test point is a test point in a low gate-source bias voltage region and a low source-drain bias voltage region; obtaining second test data corresponding to a second test point, wherein the second test point is a test point in a high gate-source bias voltage region and a high source-drain bias voltage region, and a step size of bias voltage values ​​between adjacent first test points is smaller than a step size of bias voltage values ​​between adjacent second test points.

[0083] Optionally, the above-mentioned processor can also execute the program code of the following steps: also including: obtaining post-processing adjustable parameters of the semiconductor device, the post-processing adjustable parameters including at least thermal effect parameters and breakdown voltage parameters; obtaining the target current source model based on the current source model and the post-processing adjustable parameters; generating a semiconductor device model based on the target current source model, the charge source model and the parasitic parameters.

[0084] Those skilled in the art will appreciate that the structure shown in FIG4 is merely illustrative. FIG4 does not limit the structure of the electronic device. For example, the electronic device may include more or fewer components (such as a network interface, a display device, etc.) than those shown in FIG4 , or may have a configuration different from that shown in FIG4 .

[0085] A person skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the hardware related to the terminal device through a program, and the program can be stored in a computer-readable storage medium, which may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0086] Example 4

[0087] In an exemplary embodiment, a computer-readable storage medium including instructions is further provided. When the instructions in the computer-readable storage medium are executed by a processor of a terminal, the terminal is enabled to perform the semiconductor device modeling method in the above-mentioned embodiment 1. Alternatively, the computer-readable storage medium may be a non-transitory computer-readable storage medium, for example, a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0088] Optionally, in this embodiment, the computer-readable storage medium may be used to store program codes executed by the semiconductor device modeling method provided in the first embodiment.

[0089] Optionally, in this embodiment, the computer-readable storage medium may be located in any computer terminal in a computer terminal group in a computer network, or in any mobile terminal in a mobile terminal group.

[0090] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: the semiconductor device model includes a parasitic part and an intrinsic part, and the modeling method of the semiconductor device includes: obtaining parasitic parameters of the semiconductor device and intrinsic parameters of the semiconductor device, wherein the parasitic parameters are used to form the parasitic part, and the intrinsic parameters are used to form the intrinsic part; according to a preset algorithm and the intrinsic parameters, the electrical characteristic parameters of the intrinsic part are obtained, and the electrical characteristic parameters include at least a current source model and a charge source model; based on the electrical characteristic parameters and the parasitic parameters, a semiconductor device model is generated.

[0091] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: obtaining electrical characteristic parameters according to a preset algorithm and intrinsic parameters, including: preprocessing the intrinsic parameters to obtain equivalent parameters corresponding to the intrinsic parameters; obtaining electrical characteristic parameters according to the preset algorithm and the equivalent parameters.

[0092] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: preprocessing the intrinsic parameters to obtain equivalent parameters corresponding to the intrinsic parameters, including: obtaining preset parameters of the semiconductor device, the preset parameters including at least delay parameters, threshold voltage, subthreshold parameters, leakage voltage coefficient, trap effect parameters, mobility parameters, preprocessing adjustable parameters and temperature; performing preprocessing according to the preset parameters and the intrinsic parameters to obtain equivalent parameters corresponding to the intrinsic parameters.

[0093] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: the intrinsic parameters include at least the gate-source bias voltage of the semiconductor device and the source-drain bias voltage of the semiconductor device, and the intrinsic parameters are preprocessed to obtain equivalent parameters corresponding to the intrinsic parameters, including: performing a first preprocessing on the gate-source bias voltage to obtain an equivalent gate-source bias voltage; performing a second preprocessing on the source-drain bias voltage to obtain an equivalent source-drain bias voltage.

[0094] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: obtaining electrical characteristic parameters according to a preset algorithm and equivalent parameters, including: obtaining test data of the semiconductor device, the test data including at least a bias voltage value of the semiconductor device, and a current value corresponding to the bias voltage value, the test data being used to characterize the electrical characteristics of the semiconductor device according to the bias voltage value and the current value; obtaining electrical characteristic parameters according to the test data, the equivalent parameters and the preset algorithm.

[0095] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for executing the following steps: the bias voltage interval of the semiconductor device includes a gate-source bias voltage interval and a source-drain bias voltage interval, different bias voltage intervals of the gate-source bias voltage interval include a low gate-source bias voltage interval and a high gate-source bias voltage interval, and different bias voltage intervals of the source-drain bias voltage interval include a low source-drain bias voltage interval and a high source-drain bias voltage interval; obtaining test data of the semiconductor device, including: obtaining first test data corresponding to a first test point, wherein the first test point is a test point in a low gate-source bias voltage region and a low source-drain bias voltage region; obtaining second test data corresponding to a second test point, wherein the second test point is a test point in a high gate-source bias voltage region and a high source-drain bias voltage region, and a step size of bias voltage values ​​between adjacent first test points is smaller than a step size of bias voltage values ​​between adjacent second test points.

[0096] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: also including: obtaining post-processing adjustable parameters of the semiconductor device, the post-processing adjustable parameters including at least thermal effect parameters and breakdown voltage parameters; performing post-processing according to the current source model and the post-processing adjustable parameters to obtain a target current source model; generating a semiconductor device model according to the target current source model, the charge source model and the parasitic parameters.

[0097] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0098] In the above embodiments of the present application, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0099] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0100] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0101] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0102] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, server or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program code.

[0103] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A semiconductor device modeling method, wherein the semiconductor device model includes a parasitic part and an intrinsic part, and the method include: Acquiring parasitic parameters of the semiconductor device and intrinsic parameters of the semiconductor device, wherein the parasitic parameters are used to form the parasitic part, and the intrinsic parameters are used to form the intrinsic part; According to a preset algorithm and the intrinsic parameters, electrical characteristic parameters of the intrinsic part are obtained, wherein the electrical characteristic parameters at least include a current source model and a charge source model; The semiconductor device model is generated according to the electrical characteristic parameters and the parasitic parameters.

2. The modeling method according to claim 1, in, The obtaining of electrical characteristic parameters according to the preset algorithm and the intrinsic parameters includes: Preprocessing the intrinsic parameters to obtain equivalent parameters corresponding to the intrinsic parameters; The electrical characteristic parameters are obtained according to the preset algorithm and the equivalent parameters.

3. The modeling method according to claim 2, in, The preprocessing of the intrinsic parameters to obtain equivalent parameters corresponding to the intrinsic parameters includes: Acquiring preset parameters of the semiconductor device, wherein the preset parameters include at least a delay parameter, a threshold voltage, a subthreshold parameter, a leakage voltage coefficient, a trap effect parameter, a mobility parameter, a pre-processing adjustable parameter, and a temperature; The preprocessing is performed according to the preset parameters and the intrinsic parameters to obtain the equivalent parameters corresponding to the intrinsic parameters.

4. The modeling method according to claim 2 or 3, in, The intrinsic parameters at least include a gate-source bias voltage of the semiconductor device and a source-drain bias voltage of the semiconductor device, and the preprocessing of the intrinsic parameters to obtain equivalent parameters corresponding to the intrinsic parameters includes: Performing a first preprocessing on the gate-source bias voltage to obtain an equivalent gate-source bias voltage; The source-drain bias voltage is subjected to a second preprocessing to obtain an equivalent source-drain bias voltage.

5. The modeling method according to claim 2, in, The obtaining of the electrical characteristic parameters according to the preset algorithm and the equivalent parameters includes: Acquiring test data of the semiconductor device, the test data comprising at least a bias voltage value of the semiconductor device and a current value corresponding to the bias voltage value, the test data being used to characterize electrical characteristics of the semiconductor device according to the bias voltage value and the current value; The electrical characteristic parameters are obtained according to the test data, the equivalent parameters and the preset algorithm.

6. The modeling method according to claim 5, in, The bias voltage interval of the semiconductor device includes a gate-source bias voltage interval and a source-drain bias voltage interval, the different bias voltage intervals of the gate-source bias voltage interval include a low gate-source bias voltage interval and a high gate-source bias voltage interval, the different bias voltage intervals of the source-drain bias voltage interval include a low source-drain bias voltage interval and a high source-drain bias voltage interval, and the acquiring of the test data of the semiconductor device includes: Acquire first test data corresponding to a first test point, wherein the first test point is a test point in the low gate-source bias voltage region and the low source-drain bias voltage region; Acquire second test data corresponding to a second test point, wherein the second test point is a test point possessed by the high gate-source bias voltage region and the high source-drain bias voltage region, and a step size of the bias voltage value between adjacent first test points is smaller than a step size of the bias voltage value between adjacent second test points.

7. The modeling method according to any one of claims 1 to 3, in, Also includes: Acquiring post-processing adjustable parameters of the semiconductor device, wherein the post-processing adjustable parameters at least include a thermal effect parameter and a breakdown voltage parameter; Performing post-processing according to the current source model and the post-processing adjustable parameters to obtain a target current source model; The semiconductor device model is generated according to the target current source model, the charge source model and the parasitic parameters.

8. A semiconductor device modeling device, in, The semiconductor device model includes a parasitic part and an intrinsic part, and the device includes: An acquisition module, used for acquiring parasitic parameters of a semiconductor device and intrinsic parameters of the semiconductor device, wherein the parasitic parameters are used to form the parasitic part, and the intrinsic parameters are used to form the intrinsic part; An obtaining module, used for obtaining electrical characteristic parameters of the intrinsic part according to a preset algorithm and the intrinsic parameters, wherein the electrical characteristic parameters at least include a current source model and a charge source model; A generating module is used to generate the semiconductor device model according to the electrical characteristic parameters and the parasitic parameters.

9. An electronic device, include: processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the semiconductor device modeling method according to any one of claims 1 to 7.

10. A computer-readable storage medium, in, When the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the semiconductor device modeling method according to any one of claims 1 to 7.

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