Multiplexer for neural network array

Abstract

Various examples of a multiplexer coupled to each row in a neural network array are disclosed. In one example, a system includes: an array of neural networks comprised of non-volatile memory cells, the array of neural networks including i rows, where i is a multiple of 2; j line registers, wherein j < i; the j digital-to-analog converters are used for converting the j groups of digital data received from the j row registers into j analog signals; and j multiplexers to route the j analog signals to a subset of the i rows in response to a control signal.

Description

[0001] Priority Declaration

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 442,724, filed on February 1, 2023, entitled “Input Multiplexors for Neural Network Array,” and U.S. Patent Application No. 18 / 135,664, entitled “Multiplexors For Neural Network Array.” Technical Field

[0003] Many examples of multiplexers for neural network arrays are disclosed. Background Art

[0004] Artificial neural networks simulate biological neural networks (the central nervous system of animals, especially the brain), and are used to estimate or approximate functions that may depend on a large number of inputs and are generally unknown. Artificial neural networks typically consist of layers of interconnected "neurons" that exchange messages with each other.

[0005] Figure 1 A neural network 100 is illustrated, with circles representing inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to the input and learn. Typically, a neural network includes multiple layers of inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. Neurons at each level make decisions based on data received from synapses, either individually or collectively.

[0006] One of the main challenges in developing artificial neural networks for high-performance information processing is the lack of adequate hardware technology. In fact, practical neural networks rely on a large number of synapses to achieve high connectivity between neurons, that is, very high computational parallelism. In principle, this complexity can be achieved using digital supercomputers or clusters of dedicated graphics processing units. However, in addition to being high-cost, these approaches are also mediocre in energy efficiency compared to biological networks, which consume less energy mainly due to the low-precision analog calculations they perform. CMOS analog circuits have been used in artificial neural networks, but given the large number of neurons and synapses, the synapses of most CMOS implementations are too large.

[0007] Applicants previously disclosed an artificial (simulated) neural network utilizing one or more nonvolatile memory arrays as synapses in U.S. Patent Application Publication 2017 / 0337466A1, which is incorporated herein by reference. The nonvolatile memory array operates as an analog neural memory and includes nonvolatile memory cells arranged in rows and columns. The neural network includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes: a source region and a drain region spaced apart formed in a semiconductor substrate, wherein a channel region extends between the source region and the drain region; a floating gate disposed over and insulated from a first portion of the channel region; and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells stores a weight value corresponding to a plurality of electrons on the floating gate. The plurality of memory cells multiply the first plurality of inputs by the stored weight values ​​to generate a first plurality of outputs.

[0008] Non-volatile memory cells

[0009] Non-volatile memory is known. For example, U.S. Patent No. 5,029,130 ​​("the '130 patent"), which is incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which is a type of flash memory cell. Such memory cells 210 are Figure 2 . Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from a first portion of the channel region 18 (and controls its electrical conductivity), and is formed over a portion of the source region 14. A wordline terminal 22 (which is typically coupled to a wordline) has a first portion disposed over and insulated from a second portion of the channel region 18 (and controls its electrical conductivity), and a second portion extending upward and over the floating gate 20. The floating gate 20 and the wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0010] Memory cell 210 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on wordline terminal 22, which causes the electrons on floating gate 20 to tunnel through the intervening insulator via Fowler-Nordheim (FN) tunneling from floating gate 20 to wordline terminal 22.

[0011] The memory cell 210 is programmed by source-side injection (SSI) with hot electrons by placing a positive voltage on the wordline terminal 22 and a positive voltage on the source region 14 (where electrons are placed on the floating gate). Electrons flow from the drain region 16 to the source region 14. When the electrons reach the gap between the wordline terminal 22 and the floating gate 20, they accelerate and become heated. Due to the electrostatic attraction from the floating gate 20, some of the heated electrons are injected through the gate oxide onto the floating gate 20.

[0012] Memory cell 210 is read by placing a positive read voltage across drain region 16 and wordline terminal 22 (which turns on the portion of channel region 18 below the wordline terminal). If floating gate 20 is positively charged (i.e., electrons are erased), the portion of channel region 18 below floating gate 20 is also turned on, and current will flow through channel region 18, which is sensed as an erased state or a "1" state. If floating gate 20 is negatively charged (i.e., programmed by electrons), the portion of the channel region below floating gate 20 is mostly or completely turned off, and no current (or very little current) will flow through channel region 18, which is sensed as a programmed state or a "0" state.

[0013] Table 1 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 210 for performing read, erase, and program operations:

[0014] Table 1: Figure 2 Operation of the flash memory unit 210

[0015] WL BL SL Read 2V-3V 0.6V-2V 0V Erase About 11V-13V 0V 0V programming 1V-2V 10.5μA-3μA 9V-10V

[0016] Other split gate memory cell configurations are known as other types of flash memory cells. For example, Figure 3 A quad-gate memory cell 310 is depicted, comprising a source region 14, a drain region 16, a floating gate 20 over a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) over a second portion of the channel region 18, a control gate 28 over the floating gate 20, and an erase gate 30 over the source region 14. This configuration is described in U.S. Patent 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates except the floating gate 20 are non-floating, meaning they are electrically connected or capable of being electrically connected to a voltage source. Programming is performed by heated electrons from the channel region 18 that inject themselves into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0017] Table 2 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 310 for performing read, erase, and program operations:

[0018] Table 2: Figure 3 Operation of the flash memory unit 310

[0019] WL / SG BL CG EG SL Read 1.0V-2V 0.6V-2V 0V-2.6V 0V-2.6V 0V Erase -0.5V / 0V 0V 0V / -8V 8V-12V 0V programming 1V 0.1μA-1μA 8V-11V 4.5V-9V 4.5V-5V

[0020] Figure 4 Depicted is a tri-gate memory cell 410, which is another type of flash memory cell. Figure 3 The memory cell 310 is identical to the memory cell 410 except that the memory cell 410 does not have a separate control gate. Except that no control gate bias is applied, the erase operation (thus erasing by using the erase gate) and the read operation are the same as Figure 3 The programming operation is also completed without a control gate bias, and therefore, a higher voltage is applied on the source line during the programming operation to compensate for the lack of control gate bias.

[0021] Table 3 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 410 for performing read, erase, and program operations:

[0022] Table 3: Figure 4 Operation of the flash memory unit 410

[0023] WL / SG BL EG SL Read 0.7V-2.2V 0.6V-2V 0V-2.6V 0V Erase -0.5V / 0V 0V 11.5V 0V programming 1V 0.2μA-3μA 4.5V 7V-9V

[0024] Figure 5 Depicted is a stacked gate memory cell 510, which is another type of flash memory cell. Figure 2 Memory cell 210 is similar to that of FIG2 except that floating gate 20 extends over the entire channel region 18 and control gate 22 (which will be coupled to the word line here) extends over floating gate 20, separated by an insulating layer (not shown). Erasing is performed by FN tunneling of electrons from the FG to the substrate, programming is performed by channel hot electron (CHE) injection at the region between channel 18 and drain region 16, by electrons flowing from source region 14 toward drain region 16, and read operations are similar to memory cell 210 with a higher control gate voltage.

[0025] Table 4 depicts typical voltage ranges that may be applied to the terminals of the memory cell 510 and the substrate 12 for performing read, erase, and program operations:

[0026] Table 4: Figure 5 Operation of the flash memory unit 510

[0027] CG BL SL substrate Read 2V-5V 0.6V-2V 0V 0V Erase -8V to -10V / 0V FLT FLT 8V-10V / 15V-20V programming 8V-12V 3V-5V 0V 0V

[0028] The methods and devices described herein can be applied to other non-volatile memory technologies such as, but not limited to, FINFET split-gate flash or stacked-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trapped in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trapped in nitride), ReRAM (resistive RAM), PCM (phase change memory), MRAM (magnetic RAM), FeRAM (ferroelectric RAM), CT (charge trapping) memory, CN (carbon tube) memory, OTP (two-level or multi-level one-time programmable) and CeRAM (correlated electron RAM), etc.

[0029] In order to utilize a memory array comprising one of the above-described types of nonvolatile memory cells in an artificial neural network, two modifications were made. First, the circuitry was configured so that each memory cell could be individually programmed, erased, and read without adversely affecting the memory states of other memory cells in the array, as explained further below. Second, continuous (analog) programming of the memory cells was provided.

[0030] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage device is effectively analog, or at least can store one of many discrete values ​​(such as 16 or 64 different values), which allows very precise and individual tuning of all the memory cells in the memory array, and makes the memory array ideal for storing and fine-tuning the synaptic weights of neural networks.

[0031] Neural Networks Using Nonvolatile Memory Cell Arrays

[0032] Figure 6 The present example conceptually illustrates a non-limiting example of a neural network 600 utilizing a non-volatile memory cell array. This example uses a non-volatile memory array neural network for a facial recognition application, but any other suitable application may also be implemented using a non-volatile memory array-based neural network.

[0033] For this example, S0 is the input layer, which is a 32×32 pixel RGB image with 5 bits of precision (i.e., three 32×32 pixel arrays, one for each color R, G, and B, with 5 bits of precision per pixel). Synapse CB1 from input layer S0 to layer C1 applies different sets of weights in some cases and shared weights in other cases, and scans the input image with a 3×3 pixel overlapping filter (kernel), shifting the filter by 1 pixel (or more than 1 pixel as dictated by the model). Specifically, the values ​​of 9 pixels in the 3×3 portion of the image (i.e., called the filter or kernel) are provided to synapse CB1, where these 9 input values ​​are multiplied by the appropriate weights, and after summing the outputs of the multiplications, a single output value is determined and provided by the first synapse of CB1 for generating a pixel in one of the feature maps of layer C1. The 3×3 filter is then shifted one pixel to the right within the input layer S0 (i.e., a column of three pixels on the right is added and a column of three pixels on the left is released), whereby the nine pixel values ​​in this newly positioned filter are provided to the synapse CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process continues until the 3×3 filter has scanned all three colors and all bits (precision values) over the entire 32×32 pixel image of the input layer S0. This process is then repeated using different sets of weights to generate different feature maps for layer C1 until all feature maps for layer C1 have been calculated.

[0034] At layer C1, in this example, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the product of the input and the kernel, so each feature map is a two-dimensional array, so in this example, layer C1 is composed of 16 layers of two-dimensional arrays (remember that the layers and arrays referred to in this article are logical relationships, not necessarily physical relationships, that is, arrays do not have to be oriented to physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of sixteen different sets of synaptic weights applied to the filter scan. The C1 feature maps can all relate to different aspects of the same image features, such as edge identification. For example, a first map (generated using a first set of weights, shared by all scans used to generate it) can identify circular edges, a second map (generated using a second set of weights different from the first) can identify rectangular edges, or the aspect ratio of certain features, and so on.

[0035] Before passing from layer C1 to layer S1, an activation function P1 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2×2 regions in each feature map. The purpose of pooling function P1 is to average neighboring locations (or a max function can also be used) to, for example, reduce dependencies on edge locations and reduce the size of the data before entering the next stage. At layer S1, there are 16 15×15 feature maps (i.e., sixteen different arrays, each with 15×15 pixels). Synapse CB2 from layer S1 to layer C2 scans the map in layer S1 using a 4×4 filter, where the filter is shifted by 1 pixel. At layer C2, there are 22 12×12 feature maps. Before passing from layer C2 to layer S2, an activation function P2 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2×2 regions in each feature map. At layer S2, there are 22 6×6 feature maps. An activation function (pooling) is applied to the synapse CB3 from layer S2 to layer C3, where each neuron in layer C3 is connected to each map in layer S2 via a corresponding synapse on CB3. At layer C3, there are 64 neurons. Synapse CB4 from layer C3 to output layer S3 completely connects C3 to S3, that is, every neuron in layer C3 is connected to every neuron in layer S3. The output at S3 includes 10 neurons, of which the highest output neuron determines the category. For example, this output can indicate the identification or classification of the content of the original image.

[0036] The synapses at each layer are implemented using an array or a portion of an array of non-volatile memory cells.

[0037] Figure 7 is a block diagram of a VMM system 32 that can be used for this purpose. The vector-matrix multiplication (VMM) system 32 includes non-volatile memory units and serves as a synapse between one layer and the next layer (such as Figure 6 CB1, CB2, CB3, and CB4 in FIG. 1 ). Specifically, the VMM system 32 includes a VMM array 33 (also referred to as a neural network array 33), which is a non-volatile memory cell array, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the corresponding inputs of the non-volatile memory cell array 33. The inputs to the VMM array 33 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the VMM array 33. Alternatively, the bit line decoder 36 can decode the output of the VMM array 33.

[0038] The VMM array 33 serves two purposes. First, it stores weights to be used by the VMM system 32. Second, the VMM array 33 effectively multiplies the inputs by the weights stored in the VMM array 33 and each output line (source line or bit line) adds them together to produce an output, which will serve as the input to the next layer or the final layer. By performing multiplication and addition functions, the VMM array 33 eliminates the need for separate multiplication and addition logic circuits and is also highly power-efficient due to its in-situ memory calculations.

[0039] The outputs of the VMM array 33 are provided to a differential summer (such as a summing operational amplifier or a summing current mirror) 38 which sums the outputs of the VMM array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform summing of positive and negative weights.

[0040] The summed output value of the difference summer 38 is then provided to the activation function block 39, which modifies the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The modified output value of the activation function block 39 becomes the next layer (e.g., Figure 6 The VMM array 33 is a synapse array formed by a plurality of synapses (which receive their inputs from an existing neuron layer or from an input layer such as an image database), and the summing operational amplifier 38 and the activation function block 39 are a plurality of neurons.

[0041] Figure 7 The inputs to the VMM system 32 (WLx, EGx, CGx, and optionally BLx and SLx) can be analog levels, binary levels, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog levels), and the outputs can be analog levels, binary levels, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0042] Figure 8 A neural network 800 is depicted. The neural network 800 includes a plurality of layers formed by the VMM system 32, here labeled as VMM systems 32a, 32b, 32c, 32d, and 32e. Figure 8As shown, the input (denoted as Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to the input VMM system 32a. The converted analog input can be a voltage or a current. The first level of input D / A conversion can be accomplished by using a function or LUT (lookup table) that maps the input Inputx to the appropriate analog levels for the matrix multiplier of the input VMM system 32a. Input conversion can also be accomplished by an analog-to-analog (A / A) converter to convert the external analog input into a mapped analog input for the input VMM system 32a.

[0043] The output generated by input VMM system 32a is provided as input to the next VMM system (hidden level 1) 32b, which in turn generates an output that is provided as input to the next VMM system (hidden level 2) 32c, and so on. The layers of VMM systems 32 serve as different layers of synapses and neurons in a convolutional neural network (CNN). Each VMM system 32a, 32b, 32c, 32d, and 32e may include a separate physical non-volatile memory array, or multiple VMM systems may utilize different portions of the same non-volatile memory array, or multiple VMM systems may utilize overlapping portions of the same physical non-volatile memory array. Figure 8 The example shown includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely an example, and that the system may include more than two hidden layers and more than two fully connected layers.

[0044] Vector-Matrix Multiplication (VMM) Array

[0045] Figure 9 A VMM array 900 is depicted that is particularly suitable for use in applications such as Figure 3 Memory cells 310 are shown and serve as synapses and components for neurons between the input layer and the next layer. (Those skilled in the art will appreciate that a VMM array may also be referred to as a neural network array.) VMM array 900 includes a memory array 901 of nonvolatile memory cells and a reference array 902 of nonvolatile reference memory cells (at the top of the array). Alternatively, another reference array may be placed at the bottom.

[0046] In VMM array 900, control gate lines (such as control gate line 903) extend in the vertical direction (so reference array 902 is orthogonal to control gate line 903 in the row direction), and erase gate lines (such as erase gate line 904) extend in the horizontal direction. Here, the inputs to VMM array 900 are provided on control gate lines (CG0, CG1, CG2, CG3), and the outputs of VMM array 900 appear on source lines (SL0, SL1). In one example, only even-numbered rows are used, and in another example, only odd-numbered rows are used. The current placed on each source line (SL0, SL1, respectively) performs a summation function of all currents from the memory cells connected to that particular source line.

[0047] As described herein for neural networks, the non-volatile memory cells of VMM array 900 (ie, memory cells 310 of VMM array 900 ) may be configured to operate in a sub-threshold region.

[0048] The nonvolatile reference memory cell and the nonvolatile memory cell described herein are biased in weak inversion (subthreshold region):

[0049] Ids=Io*e (Vg-Vth) / nVt =w*Io*e (Vg) / nvt ,

[0050] where w = e (-Vth) / nVt

[0051] Where Ids is the drain-to-source current; Vg is the gate voltage on the memory cell; Vth is the threshold voltage of the memory cell; Vt is the thermal voltage = k*T / q, where k is the Boltzmann constant, T is the temperature in Kelvin, and q is the electron charge; n is the slope factor = 1+(Cdep / Cox), where Cdep = the capacitance of the depletion layer and Cox is the capacitance of the gate oxide layer; Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is the product of (Wt / L)*u*Cox*(n-1)*Vt 2 is proportional to , where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0052] For an I-to-V logarithmic converter that uses a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert the input current to an input voltage:

[0053] Vg=n*Vt*log[Ids / wp*Io]

[0054] Wherein, wp is w of the reference memory cell or the peripheral memory cell.

[0055] For a memory array used as a vector matrix multiplier VMM array with current input, the output current is:

[0056] lout=wa*Io*e (Vg) / nVt ,Right now

[0057] lout=(wa / wp)*Iin=W*Iin

[0058] W=e (Vthp-Vtha) / nVt

[0059] Here, wa = w for each memory cell in the memory array.

[0060] Vthp is the effective threshold voltage of the peripheral memory cells, and Vtha is the effective threshold voltage of the main (data) memory cells. Note that the threshold voltage of the transistor is a function of the substrate body bias voltage, and the substrate body bias voltage, denoted as Vsb, can be modulated to compensate for various conditions at this temperature. The threshold voltage Vth can be expressed as:

[0061]

[0062] where Vth0 is the threshold voltage at zero substrate bias, is the surface potential, and gamma is the bulk effect parameter.

[0063] The word line or control gate may be used as the input to the memory cell for the input voltage.

[0064] Alternatively, the flash memory cells of the VMM array described herein may be configured to operate in the linear region:

[0065] Ids=β*(Vgs-Vth)*Vds;β=u*Cox*Wt / L

[0066] W=α(Vgs-Vth)

[0067] Meaning that the weight W in the linear region is proportional to (Vgs-Vth)

[0068] The word line or control gate or bit line or source line can serve as the input of the memory cell operating in the linear region. The bit line or source line can serve as the output of the memory cell.

[0069] For an IV linear converter, a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor operating in a linear region may be used to linearly convert an input / output current into an input / output voltage.

[0070] Alternatively, the memory cells of the VMM array described herein may be configured to operate in the saturation region:

[0071] Ids=1 / 2*β*(Vgs-Vth) 2 ;β=u*Cox*Wt / L

[0072] Wα(Vgs-Vth) 2 , which means the weight W and (Vgs-Vth) 2 Proportional

[0073] The word line, control gate, or erase gate can be used as the input of a memory cell operating in the saturation region. The bit line or source line can be used as the output of an output neuron.

[0074] Alternatively, the memory cells of the VMM array described herein may be used for all regions or combinations thereof (subthreshold, linear, or saturation regions) of each layer or multiple layers of a neural network.

[0075] Figure 7 Other examples of VMM systems 32 are described in US Patent No. 10,748,630, which is incorporated herein by reference. As described herein, source lines or bit lines can be used as neuron outputs (current summing outputs).

[0076] Figure 10 Depicted is a VMM array 1000 that is particularly suitable for use in applications such as Figure 2 Memory cell 210 is shown and serves as a synapse between the input layer and the next layer. VMM array 1000 includes a memory array 1003 of nonvolatile memory cells, a reference array 1001 of first nonvolatile reference memory cells, and a reference array 1002 of second nonvolatile reference memory cells. Reference arrays 1001 and 1002, arranged in the column direction of the array, are used to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second nonvolatile reference memory cells are diode-connected via a multiplexer 1014 (only partially depicted), into which the current inputs flow. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference microarray matrix (not shown).

[0077] Memory array 1003 serves two purposes. First, it stores the weights that the VMM array 1000 will use on its corresponding memory cells. Second, memory array 1003 effectively multiplies the inputs (i.e., current inputs provided in terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1001 and 1002 convert into input voltages to be supplied to word lines WL0, WL1, WL2, and WL3) by the weights stored in memory array 1003, and then adds all the results (memory cell currents) to produce an output on the corresponding bit lines (BL0 to BLN), which will be the input to the next layer or the input to the final layer. By performing multiplication and addition functions, memory array 1003 eliminates the need for separate multiplication logic circuits and addition logic circuits and is also highly power-efficient. Here, the voltage inputs are provided on word lines WL0, WL1, WL2, and WL3, and the outputs appear on the corresponding bit lines BL0 to BLN during a read (inference) operation. The current placed on each of the bit lines BL0 through BLN performs a summing function of the currents from all of the nonvolatile memory cells connected to that particular bit line.

[0078] Table 5 depicts the operating voltages and currents for VMM array 1000. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0079] Table 5: Figure 10 Operation of the VMM array 1000 :

[0080] WL WL-Not selected BL BL-Not selected SL SL-Not selected Read 1V-3.5V -0.5V / 0V 0.6V-2V(Ineuron) 0.6V-2V / 0V 0V 0V Erase About 5V-13V 0V 0V 0V 0V 0V programming 1V-2V -0.5V / 0V 0.1uA-3uA Vinh~2.5V 4V-10V 0V-1V / FLT

[0081] Figure 11 Depicted is a VMM array 1100 that is particularly suitable for use in applications such as Figure 2Memory cell 210 is shown and serves as a synapse and component for neurons between the input layer and the next layer. VMM array 1100 includes a memory array 1103 of nonvolatile memory cells, a reference array 1101 of first nonvolatile reference memory cells, and a reference array 1102 of second nonvolatile reference memory cells. Reference arrays 1101 and 1102 extend in the row direction of VMM array 1100. The VMM array is similar to VMM 1000, except that in VMM array 1100, the word lines extend in the vertical direction. Here, inputs are provided on word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on source lines (SL0, SL1) during a read operation. The current placed on each source line performs a summing function of all currents from the memory cells connected to that particular source line.

[0082] Table 6 depicts the operating voltages and currents for the VMM array 1100. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0083] Table 6: Figure 11 Operation of the VMM array 1100

[0084]

[0085] Figure 12 Depicted is a VMM array 1200 that is particularly suitable for use in applications such as Figure 3 Memory cell 310 is shown and serves as a synapse and component of neurons between the input layer and the next layer. VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of first nonvolatile reference memory cells, and a reference array 1202 of second nonvolatile reference memory cells. Reference arrays 1201 and 1202 are used to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first nonvolatile reference memory cell and the second nonvolatile reference memory cell are diode-connected via a multiplexer 1212 (only partially shown), with the current input flowing into them through BLR0, BLR1, BLR2, and BLR3. Multiplexers 1212 each include a corresponding multiplexer 1205 and a cascode transistor 1204 to ensure a constant voltage on a bit line (such as BLR0) for each of the first and second nonvolatile reference memory cells during a read operation. The reference cells are tuned to a target reference level.

[0086] The memory array 1203 serves two purposes. First, it stores the weights that will be used by the VMM array 1200. Second, the memory array 1203 effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which are converted by the reference arrays 1201 and 1202 into input voltages to be supplied to the control gates (CG0, CG1, CG2, and CG3)) by the weights stored in the memory array and then adds all the results (cell currents) to produce the output, which appears on BL0 to BLN and will be the input to the next layer or the input to the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also highly power-efficient. Here, the inputs are provided on the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0 to BLN) during a read operation. The current placed on each bit line performs a summing function of all the currents from the memory cells connected to that particular bit line.

[0087] The VMM array 1200 implements unidirectional tuning of the nonvolatile memory cells in the memory array 1203. That is, each nonvolatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is placed on the floating gate (causing an incorrect value to be stored in the cell), the cell is erased and the sequence of partial programming operations begins again. As shown, two rows sharing the same erase gate (such as EG0 or EG1) are erased together (this is called a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.

[0088] Table 7 depicts the operating voltages and currents for the VMM array 1200. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector than the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0089] Table 7: Figure 12 Operation of the VMM array 1200

[0090]

[0091] Figure 13 Depicted is a VMM array 1300 that is particularly suitable for use in applications such as Figure 3Memory cell 310 is shown and serves as a synapse and component of neurons between the input layer and the next layer. VMM array 1300 includes a memory array 1303 of nonvolatile memory cells, a reference array 1301 of first nonvolatile reference memory cells, and a reference array 1302 of second nonvolatile reference memory cells. EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while CG lines CG0, CG1, CG2, and CG3 and SL lines WL0, WL1, WL2, and WL3 extend horizontally. VMM array 1300 is similar to VMM array 1400, except that VMM array 1300 implements bidirectional tuning, whereby each individual cell can be fully erased, partially programmed, and partially erased as needed to achieve a desired charge on the floating gate due to the use of separate EG lines. As shown, reference arrays 1301 and 1302 convert input currents in terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 to be applied to the memory cells in the row direction (through the action of diode-connected reference cells via multiplexer 1314). The current outputs (neurons) are in bit lines BL0 through BLN, where each bit line sums all currents from the nonvolatile memory cells connected to that particular bit line.

[0092] Table 8 depicts the operating voltages and currents for the VMM array 1300. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector than the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0093] Table 8: Figure 13 Operation of the VMM array 1300

[0094]

[0095] Figure 14 Depicted is a VMM array 1400 that is particularly suitable for use in applications such as Figure 2 The memory cell 210 shown in FIG. 1 is used as a synapse and a component of a neuron between an input layer and a next layer. In the VMM array 1400, the input INPUT0 ... INPUT N On bit lines BL0...BL N The signals are received on the source lines SL0, SL1, SL2 and SL3, and outputs OUTPUT1, OUTPUT2, OUTPUT3 and OUTPUT4 are generated on the source lines SL0, SL1, SL2 and SL3, respectively.

[0096] Figure 15 Depicted is a VMM array 1500 that is particularly suitable for use in applications such as Figure 2 The memory cell 210 is shown and serves as a synapse and component of the neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2 and INPUT3 are received on source lines SL0, SL1, SL2 and SL3 respectively, and outputs OUTPUT0...OUTPUT N On bit lines BL0...BL N Generate on.

[0097] Figure 16 Depicted is a VMM array 1600 that is particularly suitable for use in applications such as Figure 2 The memory unit 210 shown in FIG. 2 is used as a synapse and a component of a neuron between an input layer and a next layer. In this example, the input INPUT0 ... INPUT M On word lines WL0...WL M Receive and output OUTPUT0......OUTPUT N On bit lines BL0...BL N Generate on.

[0098] Figure 17 Depicted is a VMM array 1700 that is particularly suitable for use in applications such as Figure 3 The memory unit 310 shown in FIG. 3 is used as a synapse and a component of a neuron between an input layer and a next layer. In this example, the input INPUT0 ... INPUT M On word lines WL0...WL M Receive and output OUTPUT0......OUTPUT N On bit lines BL0...BL N Generate on.

[0099] Figure 18 Depicted is a VMM array 1800 that is particularly suitable for use in applications such as Figure 4 The memory unit 410 shown in FIG. 4 is used as a synapse and component of the neurons between the input layer and the next layer. In this example, the input INPUT0 .....INPUT n On the vertical control gate lines CG0...CG N The outputs OUTPUT1 and OUTPUT2 are received on the source lines SL0 and SL1.

[0100] Figure 19Depicted is a VMM array 1900 that is particularly suitable for use in applications such as Figure 4 The memory unit 410 shown is used as a synapse and a component of the neurons between the input layer and the next layer. In this example, the input INPUT0...INPUT N Received on the gates of bit line control gates 1901-1, 1901-2, ..., 1901-(N-1), and 1901-N, which are coupled to bit lines BL0, BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8, BL9, BL10, BL11, BL12, BL13, BL14, BL15, N Example outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0101] Figure 20 Depicted is a VMM array 2000 particularly suitable for use in applications such as Figure 3 The memory unit 310 shown in FIG. Figure 5 The memory cell 510 shown and the Figure 7 The memory unit 710 shown in FIG. 7 is used as a synapse and a component of a neuron between an input layer and a next layer. In this example, the input INPUT0 ... INPUT m On word lines WL0...WL M Receive and output OUTPUT0......OUTPUT N On bit lines BL0...BL N Generate on.

[0102] Figure 21 Depicted is a VMM array 2100 that is particularly suitable for use in applications such as Figure 3 The memory unit 310 shown in FIG. Figure 5 The memory cell 510 shown and the Figure 7 The memory unit 710 shown in FIG. 7 is used as a synapse and a component of a neuron between an input layer and a next layer. In this example, the input INPUT0 ... INPUT M On the control gate line CG0...CG M Receive. Output OUTPUT0......OUTPUT N On the vertical source lines SL0...SL N Each source line SL I The source line coupled to all memory cells in column 1.

[0103] Figure 22 Depicted is a VMM array 2200 that is particularly suitable for use in applications such as Figure 3 The memory unit 310 shown in FIG. Figure 5 The memory cell 510 shown and the Figure 7 The memory unit 710 shown in FIG. 7 is used as a synapse and a component of a neuron between an input layer and a next layer. In this example, the input INPUT0 ... INPUT M On the control gate line CG0...CG M Receive. Output OUTPUT0......OUTPUT N On the vertical bit lines BL0...BL N On the generated, each bit line BL i The bit line coupled to all memory cells in column i.

[0104] The inputs to the VMM array can be analog levels, binary levels, pulses, time-modulated pulses, or digital bits (in which case a DAC is used to convert the digital bits to the appropriate input analog levels), and the outputs can be analog levels, binary levels, timed pulses, pulses, or digital bits (in which case an output ADC is used to convert the output analog levels to digital bits).

[0105] In general, for each memory cell in the VMM array, each weight W can be implemented by a single memory cell, a differential cell, or two hybrid memory cells (the average of the two cells). In the case of a differential cell, two memory cells are used to implement the weight W as a differential weight (W=W+-W-). In the case of two hybrid memory cells, two memory cells are used to implement the weight W as the average of the two cells.

[0106] Figure 23 A VMM system 2300 is depicted. In some examples, the weights W stored in the VMM array are stored as a differential pair W+ (positive weight) and W- (negative weight), where W=(W+)-(W-). In the VMM system 2300, half of the bit lines are designated as W+ lines, i.e., bit lines connected to memory cells that will store positive weights W+, and the other half of the bit lines are designated as W- lines, i.e., bit lines connected to memory cells that implement negative weights W-. The W- lines are interspersed between the W+ lines in an alternating manner. The subtraction operation is performed by a summing circuit (such as summing circuits 2301 and 2302), which receives current from the W+ line and the W- line. The output of the W+ line and the output of the W- are combined to effectively give W=W+-W- for each (W+, W-) cell pair for all (W+, W-) line pairs. While described above with respect to W− lines interspersed among W+ lines in an alternating manner, in other examples, the W+ lines and W− lines may be arbitrarily located anywhere in the array.

[0107] Figure 24Depicted is a VMM system 2400. In the VMM system 2400, positive weights W+ are implemented in a first array 2411 and negative weights W- are implemented in a second array 2412 that is separate from the first array, and the resulting weights are appropriately combined together by a summing circuit 2413.

[0108] Figure 25 A VMM system 2500 is depicted. The weights W stored in the VMM array are stored as a differential pair of W+ (positive weight) and W- (negative weight), where W=(W+)-(W-). VMM system 2500 includes array 2501 and array 2502. Half of the bit lines in each of arrays 2501 and 2502 are designated as W+ lines, i.e., bit lines connected to memory cells that will store positive weights W+, and the other half of the bit lines in each of arrays 2501 and 2502 are designated as W- lines, i.e., bit lines connected to memory cells that implement negative weights W-. The W- lines are interspersed between the W+ lines in an alternating manner. Subtraction operations are performed by summing circuits (such as summing circuits 2503, 2504, 2505, and 2506), which receive current from the W+ lines and the W- lines. The outputs of the W+ lines and the W- lines from each array 2501, 2502, respectively, are combined to effectively give W = W+ - W- for each (W+, W-) element pair for all (W+, W-) line pairs. Additionally, the W values ​​from each array 2501 and 2502 can be further combined by summing circuits 2507 and 2508 so that each W value is the result of subtracting the W value from array 2502 from the W value from array 2501, meaning that the final result from summing circuits 2507 and 2508 is the difference of two differences.

[0109] Each nonvolatile memory cell used in an analog neural memory system must be erased and programmed to hold a very specific and precise amount of charge (i.e., number of electrons) in the floating gate. For example, each floating gate should hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0110] Prior art systems experience significant leakage within the VMM array. Additionally, circuitry external to the VMM array in a VMM system takes up a significant amount of space within the semiconductor die. What is needed is a VMM system that includes circuitry that uses less space and a VMM array that results in less leakage than prior art systems. Summary of the Invention

[0111] Several examples of multiplexers for use with neural network arrays are disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0112] Figure 1 Depicted is an example neural network.

[0113] Figure 2 A split-gate flash memory cell is depicted.

[0114] Figure 3 Another split-gate flash memory cell is depicted.

[0115] Figure 4 Another split-gate flash memory cell is depicted.

[0116] Figure 5 Another split-gate flash memory cell is depicted.

[0117] Figure 6 Depicted is an example neural network.

[0118] Figure 7 An example VMM system is depicted.

[0119] Figure 8 Depicted is an example neural network.

[0120] Figure 9 Another example of a VMM array is depicted.

[0121] Figure 10 Another example of a VMM array is depicted.

[0122] Figure 11 Another example of a VMM array is depicted.

[0123] Figure 12 Another example of a VMM array is depicted.

[0124] Figure 13 Another example of a VMM array is depicted.

[0125] Figure 14 Depicts another example of a VMM array

[0126] Figure 15 Another example of a VMM array is depicted.

[0127] Figure 16 Another example of a VMM array is depicted.

[0128] Figure 17 Another example of a VMM array is depicted.

[0129] Figure 18 Another example of a VMM array is depicted.

[0130] Figure 19 Another example of a VMM array is depicted.

[0131] Figure 20 Another example of a VMM array is depicted.

[0132] Figure 21 Another example of a VMM array is depicted.

[0133] Figure 22 Another example of a VMM array is depicted.

[0134] Figure 23 Another example of a VMM system is depicted.

[0135] Figure 24 Another example of a VMM system is depicted.

[0136] Figure 25 Another example of a VMM system is depicted.

[0137] Figure 26 Depicts the VMM system.

[0138] Figure 27A A selected memory cell is depicted.

[0139] Figure 27B 、 Figure 27C and Figure 27D Unselected memory cells are depicted.

[0140] Figure 28 A VMM system including a source line pull-down circuit is depicted.

[0141] Figure 29 A VMM system including an input block coupled to a neural network array is depicted.

[0142] Figure 30 A VMM system including an input block coupled to a neural network array is depicted.

[0143] Figure 31 A VMM system including an input block coupled to a neural network array is depicted. DETAILED DESCRIPTION

[0144] VMM system architecture

[0145] Figure 26A block diagram of a VMM system 2600 is depicted. The VMM system 2600 includes a neural network array 2601 (which is a VMM array), a row decoder 2602, a high voltage decoder 2603, a column decoder 2604, a bit line driver 2605 (which may include bit line control circuitry for programming), an input circuit 2606, an output circuit 2607, a control logic component 2608, and a bias generator 2609. The VMM system 2600 also includes a high voltage generation block 2610, which includes a charge pump 2611, a charge pump regulator 2612, and a high voltage level generator 2613. The VMM system 2600 also includes an algorithm controller 2614, an analog circuit 2615, a control engine 2616 (which may include functions such as arithmetic functions, activation functions, embedded microcontroller logic, but is not limited thereto), a test control logic component 2617, and a static random access memory (SRAM) block 2618 (which is programmed / erased or weight tuned) to store intermediate data such as for input circuits (e.g., activation data) or output circuits (neuron output data, partial and output neuron data) or data for programming (such as data for an entire row or multiple rows). The neural network array 2601 includes an array of non-volatile memory cells arranged in rows and columns, wherein the non-volatile memory cells are Figure 2 、 Figure 3 、 Figure 4 or Figure 5 210, 310, 410, or 510, respectively, or other types known to those skilled in the art. In one example, the nonvolatile memory cell is as follows Figure 2 、 Figure 3 or Figure 4 In another example, the nonvolatile memory cell is as follows Figure 5 A stacked-gate flash memory cell in FIG.

[0146] Input circuitry 2606 may include various circuits such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter, digital-to-time modulated pulse converter), an AAC (analog-to-analog converter, such as a current-to-voltage converter, a logarithmic converter), a PAC (pulse-to-analog level converter), or any other type of converter. Input circuitry 2606 may implement one or more of normalization, linear or nonlinear up / down scaling functions, or arithmetic functions. Input circuitry 2606 may implement a temperature compensation function for the input level. Input circuitry 2606 may implement an activation function, such as a rectified linear activation function (ReLU) or a sigmoid. Input circuitry 2606 may store digital activation data to be applied as an input signal or combined with an input signal during programming or read operations. The digital activation data may be stored in registers. Input circuitry 2606 may include circuitry for driving array terminals, such as the CG, WL, EG, and SL lines, which may include sample-hold circuitry and buffers. The DAC may be used to convert the digital activation data into an analog input voltage for application to the array.

[0147] Output circuitry 2607 may include circuitry such as an ITV (current-to-voltage circuit), an ADC (analog-to-digital converter for converting analog neuron outputs into digital bits), an AAC (analog-to-analog converter, such as a current-to-voltage converter or a logarithmic converter), an APC (analog-to-pulse converter or an analog-to-time modulated pulse converter), or any other type of converter. Output circuitry 2607 may convert the array output into activation data. Output circuitry 2607 may implement an activation function, such as a ReLU or a sigmoid. Output circuitry 2607 may implement one or more of statistical normalization, regularization, up / down scaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, logarithm) for the neuron outputs. Output circuitry 2607 may implement a temperature compensation function for the neuron outputs or array outputs (such as bitline outputs) to maintain approximately constant power consumption of the array over a temperature range or to improve the accuracy of the array (neuron) outputs, such as by maintaining approximately the same IV slope over a temperature range. Output circuitry 2607 may include registers for storing output data.

[0148] Figure 27A Memory cell 2700 is depicted with an example of voltages applied when memory cell 2700 is selected for a read operation. In this example, 0.6V is applied to the bit line terminal of memory cell 2700, 1.4V is applied to its word line terminal, 1.5V is applied to its control gate terminal, and 0V is applied to its source line terminal.

[0149] Figure 27B 、 Figure 27C and Figure 27D Memory cell 2700 is depicted in three separate cases where the memory cell is not selected for a read operation, meaning that the memory cell 2700 is not intended to be read and is not intended to contribute to a read current in the bit line.

[0150] exist Figure 27B In the example of , 0.6V is applied to the bit line terminal, 0V is applied to the word line terminal, and 1.5V is applied to the control gate terminal. Figure 27C In the example of , 0.6V is applied to the bit line terminal, 1.4V is applied to the word line terminal, and 0V is applied to the control gate terminal. Figure 27D In the example, 0.6V is applied to the bit line terminal, 0V is applied to the word line terminal, and 0V is applied to the control gate terminal. In all three examples, a voltage of approximately 0.6V is applied to the source line terminal. Applying a voltage of approximately 0.6V to the source line terminal of the unselected memory cell 2700 is an inhibitory action to reduce leakage on the bit line of the unselected cell. This is because the bias is retained on the source of the transistor to reduce the equivalent gate to source voltage (vgs). That is, if the source line terminal is instead connected to ground (e.g., =0V), leakage through the memory cell 2700 to the bit line will occur. Applying a voltage of approximately 0.6V to the source line terminal of some or all of the unselected cells will reduce leakage compared to the case where the source line terminal is coupled to ground. Figure 26 Alternatively, the source lines of unselected memory cells may be allowed to float or biased at another voltage (e.g., >0.3V) to reduce or suppress leakage.

[0151] Figure 28 A VMM system 2800 is depicted. VMM system 2800 includes array 2601 and source line pull-down circuits (SLPNs) 2801. Only two rows and two columns of cells are shown here, but it should be understood that array 2601 may include more rows and more columns. Here, sector 2811 includes two rows of cells in array 2601. Source line pull-down circuits 2801 are provided on a per-sector basis.

[0152] Source line pull-down circuit 2801 includes NMOS transistors 2802, 2803, 2804, and 2805. NMOS transistor 2803 includes a first terminal coupled to line VBSL (which contains a voltage as described below), coupled to signal line SL0EN (which is an enable signal that connects source line SL0 to VBSL and is generated due to a sector decoding operation, wherein Figure 28 The sectors shown are selected or unselected, such as by Figure 26The NMOS transistor 2802 includes a first terminal coupled to the second terminal of the NMOS transistor 2803, a gate coupled to the signal line VCAS (which is a voltage applied to reduce stress on the NMOS transistors 2803 and 2805 when a high voltage is applied to the source line SL0 during a programming operation), and a second terminal coupled to the source line SL0. The NMOS transistor 2804 includes a first terminal coupled to the source line SL0, a gate coupled to the signal line VCAS, and a second terminal. The NMOS transistor 2805 includes a first terminal coupled to the second terminal of the NMOS transistor 2804, a gate coupled to the signal line VCAS, and a second terminal (which is complementary to SL0EN and is an enable signal that connects the source line SL0 to VBSL2 and is generated due to a sector decoding operation, wherein Figure 28 The sectors shown are selected or unselected, such as by Figure 26 A gate of the row decoder 2602 or the HV decoder 2603 in FIG, and a second terminal coupled to the signal line VBSL2 (which contains a voltage as described below).

[0153] During a read or verify operation (regardless of whether sector 2811 is selected), VBSL receives a first voltage (corresponding to 0V or 0.1V) from an external voltage source (not shown). Figure 27A The selection operation shown), and VBLSL2 receives a second voltage such as about 0.6V (corresponding to Figure 27B 、 Figure 27C and Figure 27D 1. The deselect operation shown in FIG. 1 is to reduce or suppress leakage. When sector 2811 is selected, SL0EN is asserted and SL0ENB is deasserted, and source line SL0 is coupled to VBSL, which means that SL0 receives a first voltage. When sector 2811 is not selected, SL0EN is deasserted and SL0ENB is asserted, and source line SL0 is coupled to VBSL2, which means that SL0 receives a second voltage.

[0154] Figure 29 to Figure 3 9 depicts various input multiplexing schemes that may be used in the VMM system 2600 to reduce the die space of the input circuitry 2606 used to provide input to the neural network array 2601.

[0155] Figure 29A VMM system 2900 is depicted that includes a neural network array 2601 and an input block 2910. The input block 2910 includes row registers 2901-1 through 2901-8, row tag registers 2902-1 through 2902-8 (optional) containing row tag bits, digital-to-analog converters (DACs) 2903-1 through 2903-8 (or, alternatively, row sample and hold buffers (not shown)), multiplexers 2904-1 through 2904-8, and source line pull-down circuits 2905 (which may include Figure 28 The use of row sample and hold buffers and row tag bits is described in U.S. patent application Ser. No. 18 / 077,686, filed on Dec. 8, 2022, and entitled “Input Circuit for Artificial Neural Network Array,” which is incorporated herein by reference.

[0156] In one example, DAC 2903 is an n-bit analog DAC, wherein the n bits received from row register 2901 are converted into an analog signal that is applied to neural network array 2601. In another example, the DAC is a 1-bit analog DAC, wherein the n bits received from row register 2901 are converted one bit at a time into an analog signal that is sequentially applied to neural network array 2601 in n separate operations, and the resulting output from neural network array 2601 is added to the output bit shift performed. In another example, the DAC is a pulse DAC, wherein the n bits received from register 2901 are converted into voltage pulses that are applied to neural network array 2601.

[0157] The neural network array 2601 includes rows 2906-1 to 2906-16. Here, only 16 rows are shown in the neural network array 2601, but it should be understood that the neural network array 2601 includes i rows, where i can be a multiple of 2 and can be less than or greater than 16. Similarly, only 8 row registers 2901, 8 tag registers 2902, 8 digital-to-analog converters 2903, and 8 multiplexers 2904 are shown, but it should be understood that the VMM system 2900 includes j row registers 2901, j tag registers 2902, j digital-to-analog converters 2903, and j multiplexers 2904, where j < i. In the example shown, j = i / 2.

[0158] In the prior art, if the array contains i rows, there are i row registers and i digital-to-analog converters, which means that each row has its own row register and digital-to-analog converter. In this example, there are i / 2 row registers, i / 2 row tag registers, i / 2 digital-to-analog converters, i / 2 source lines and i / 2 erase gate lines (i.e., j=i / 2), which means that the two rows share row registers, row tag registers, digital-to-analog converters, source lines and erase gate lines. The sharing of row registers, row tag registers and digital-to-analog converters is achieved by using multiplexers 2904. In this example, the corresponding multiplexers 2904 route the output of the digital-to-analog converter 2903 (or sample and hold buffer) to one of the two rows in the neural network array 2601. For example, multiplexer 2904-1 routes the output of digital-to-analog converter 2903-1 to row 2906-1 or row 2906-3 according to its control signal, and multiplexer 2904-2 routes the output of digital-to-analog converter 2903-2 to row 2906-2 or row 2906-4 according to its control signal, etc. Based on this wiring structure, a sector can include a pair of consecutive rows, and the rows of the sector can be accessed concurrently because no consecutive rows share the same multiplexer, but consecutive rows can share source lines and erase gate lines.

[0159] Figure 30 A VMM system 3000 is depicted that includes a neural network array 2601 and an input block 3010. The input block 3010 includes row registers 3001-1 through 3001-8, row tag registers 3002-1 through 3002-8 (optional) containing row tag bits, digital-to-analog converters 3003-1 through 3003-8, multiplexers 3004-1 through 3004-8, and a source line pull-down circuit 3005 (which may include Figure 28 2, 3006-1 through 3006-16. Here, only 16 rows are shown in the neural network array 2601, but it should be understood that the neural network array 2601 includes i rows, where i can be a multiple of 2 and can be less than or greater than 16. Similarly, only 8 row registers 3001, 8 row tag registers 3002, 8 digital-to-analog converters 3003, and 8 multiplexers 3004 are shown, but it should be understood that the VMM system 3000 includes j row registers 3001, j row tag registers 3002, j digital-to-analog converters 3003, and j multiplexers 3004, where j < i. In the example shown, j = i / 2.

[0160] In this example, there are i / 2 row registers, i / 2 row tag registers, i / 2 digital-to-analog converters, i / 2 source lines, and i / 2 erase gate lines (i.e., j=i / 2), which means that two rows share row registers, row tag registers, digital-to-analog converters, source lines, and erase gate lines. The sharing of row registers, row tag registers, and digital-to-analog converters is achieved by using multiplexer 3004. In this example, multiplexer 3004 routes the output of digital-to-analog converter 3003 to one of the two rows in neural network array 2601. For example, multiplexer 3004-1 routes the output of digital-to-analog converter 3003-1 to row 3006-1 or row 3006-5 according to its control signal, and multiplexer 3004-2 routes the output of digital-to-analog converter 3003-2 to row 3006-2 or row 3006-6 according to its control signal, and so on. In one example, a sector includes consecutive rows. In another example, a sector includes four consecutive rows. In either case, all rows in a sector can be accessed concurrently because no group of two or four consecutive rows shares the same multiplexer 3004.

[0161] Figure 31 A VMM system 3100 is depicted that includes a neural network array 2601 and an input block 3110. The input block 3110 includes row registers 3101-1 to 3101-4, row tag registers 3102-1 to 3102-4 (optional) containing row tag bits, digital-to-analog converters 3103-1 to 3103-4, multiplexers 3104-1 to 3104-4, and a source line pull-down circuit 3105 (which may include Figure 28 16). The neural network array 2601 includes rows 3106-1 to 3106-16. Here, only 16 rows are shown in the neural network array 2601, but it should be understood that the neural network array 2601 includes i rows, where i can be a multiple of 2 and can be less than or greater than 16. Similarly, only 4 row registers 3101, 4 row tag registers 3102, 4 digital-to-analog converters 3103, and 4 multiplexers 3104 are shown, but it should be understood that the VMM system 3100 includes j row registers 3101, j row tag registers 3102, j digital-to-analog converters 3103, and j multiplexers 3104, where j<i. In the example shown, j=i / 4.

[0162] In this example, there are i / 4 row registers, i / 4 row tag registers, i / 4 digital-to-analog converters (i.e., j=i / 4), i / 2 source lines, and i / 2 erase gate lines, which means that four rows share row registers, row tag registers, and digital-to-analog converters, where 2 source lines and 2 erase gate lines are used by groups of four rows. The sharing of row registers, row tag registers, and digital-to-analog converters is achieved by using multiplexer 3104. In this example, multiplexer 3104 routes the output of digital-to-analog converter 3103 to one of the four rows in neural network array 2601. For example, multiplexer 3104-1 routes the output of digital-to-analog converter 3103-1 to row 3106-1, 3106-3, 3106-5, or 3106-7 according to its control signal, multiplexer 3104-2 routes the output of digital-to-analog converter 3103-2 to row 3106-2, 3106-4, 3106-6, or 3106-8 according to its control signal, and so on. Based on this routing structure, rows in a sector formed by two consecutive rows can be accessed concurrently because no two consecutive rows share the same multiplexer.

[0163] It should be noted that, as used herein, the terms "above" and "on" both inclusively include "directly on" (no intervening materials, elements, or spaces disposed therebetween) and "indirectly on" (intervening materials, elements, or spaces disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (no intervening materials, elements, or spaces disposed therebetween) and "indirectly adjacent" (intervening materials, elements, or spaces disposed therebetween), "mounted to" includes "directly mounted to" (no intervening materials, elements, or spaces disposed therebetween) and "indirectly mounted to" (intervening materials, elements, or spaces disposed therebetween), and "electrically coupled to" includes "directly electrically coupled to" (no intervening materials or elements electrically connecting the elements together) and "indirectly electrically coupled to" (intervening materials or elements electrically connecting the elements together). For example, forming an element "above" a substrate may include forming the element directly on the substrate without intervening materials / elements therebetween, as well as forming the element indirectly on the substrate with one or more intervening materials / elements therebetween.

Claims

1. A system, comprising: A neural network array composed of non-volatile memory cells, the neural network array comprising i rows, where i is a multiple of 2; j row registers, where j <i; j digital-to-analog converters, the j digital-to-analog converters being configured to convert j groups of digital data received from the j row registers into corresponding j analog signals; and j multiplexers are configured to route the corresponding j analog signals to a subset of the i rows in response to a control signal. The system according to claim 1 , wherein j=i / 2. The system according to claim 1 , wherein j=i / 4.

4. The system according to claim 1, comprising: a source line pull-down circuit configured to pull the source line of the corresponding row of the nonvolatile memory cell array coupled to the source line to a first voltage when the corresponding row of the nonvolatile memory cell array coupled to the source line is selected during a read or verify operation, and to pull the source line to a second voltage when the corresponding row of the nonvolatile memory cell array coupled to the source line is not selected during a read or verify operation.

5. The system of claim 1, wherein the non-volatile memory cells are stacked gate flash memory cells.

6. The system of claim 1, wherein the non-volatile memory cells are split-gate flash memory cells.

7. A method comprising: j digital-to-analog converters convert j groups of digital data received from j row registers into j analog signals; as well as The j analog signals are routed by j multiplexers to a subset of rows within i rows in a neural network array composed of non-volatile memory cells, where i is a multiple of 2 and j <i。 The method according to claim 7 , wherein j=i / 2. The method according to claim 7 , wherein j=i / 4.

10. The method according to claim 7, comprising: When one or more rows coupled to a source line are selected during a read or verify operation, the source line is pulled to a first voltage.

11. The method according to claim 10, comprising: The source line is pulled to a second voltage when the one or more rows coupled to the source line are unselected during a read or verify operation.

12. The method of claim 7, wherein the non-volatile memory cell is a stacked gate flash memory cell.

13. The method of claim 7, wherein the non-volatile memory cells are split-gate flash memory cells.

14. A system comprising: A neural network array composed of non-volatile memory cells, the neural network array comprising i rows, where i is a multiple of 2; i / 2 source lines, wherein corresponding ones of the source lines are shared by a sector including two of the i rows; and A circuit for coupling a corresponding source line among the i / 2 source lines to a first voltage when one or more rows coupled to the corresponding source line are selected during a read or verify operation, and for coupling the corresponding source line to a second voltage when two rows coupled to the corresponding source line are not selected during a read or verify operation.

15. The system of claim 14, wherein the non-volatile memory cells are stacked gate flash memory cells.

16. The system of claim 14, wherein the non-volatile memory cells are split-gate flash memory cells.

17. The system according to claim 14, comprising: j row registers, where j <i; j digital-to-analog converters, the j digital-to-analog converters being configured to convert j groups of digital data received from the j row registers into j analog signals; and j multiplexers for routing the j analog signals to a subset of the i rows in response to a control signal during a read or verify operation. The system of claim 17 , wherein j=i / 2. The system of claim 17 , wherein j=i / 4.

20. The system of claim 14, comprising: i / 2 erase gate lines, wherein corresponding erase gate lines among the i / 2 erase gate lines are shared by sectors.

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