Display device

Abstract

An embodiment of the present invention discloses a pixel, a display device including the same, and a method for driving the same, in which the pixel is supplied with a first initialization voltage in a first period between a write period and a first emission period during a first scan period of a frame, and during a second scan period following the first scan period, the pixel is supplied with a second initialization voltage different from the first initialization voltage from a start of at least a second period before the second emission period.

Description

Technical Field

[0001] One or more embodiments relate to a pixel and a display device including the pixel. Background Art

[0002] Recently, the use of display devices has been diversified. The reduction in thickness and weight of display devices has increased the range of use of display devices.

[0003] Since the display device is used in various ways, various methods of designing the shape of the display device may be provided. In addition, functions that can be connected or linked to the display device are increasing.

[0004] It will be understood that this technical background section is intended, in part, to provide a useful context for understanding the technology. However, this background section may also include ideas, concepts, or understandings that were not part of what was known or understood by those skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the Invention

[0005] Technical issues One or more embodiments provide a display device with improved display quality. However, this purpose is merely illustrative, and the scope of the disclosure is not limited thereto.

[0006] Technical solutions to the problem The technical objectives to be achieved by the disclosure are not limited to the technical objectives described herein, and those skilled in the art will clearly understand other technical objectives not mentioned herein from the disclosed description.

[0007] According to one disclosed aspect, a display device includes a plurality of pixels, each of the plurality of pixels including: a light-emitting diode; a first transistor electrically connected to a drive voltage line and the light-emitting diode; a second transistor electrically connected to the first transistor and the light-emitting diode; and a third transistor electrically connected to the light-emitting diode and an initialization voltage line. The pixels may be configured to operate during a first scanning period and a second scanning period during a frame, the first scanning period including a write period for receiving a data signal and a first emission period for emitting light having a brightness corresponding to the data signal; and the second scanning period including a second emission period for holding the data signal and emitting light having a brightness corresponding to the held data signal. A gate of the second transistor may be configured to receive a first gate signal, a gate-on voltage, during the second scanning period. A gate of the third transistor may be configured to receive a second gate signal, a gate-on voltage, during a first period prior to the second emission period of the second scanning period. The initialization voltage line may be configured to receive a first initialization voltage during the first scanning period and to receive a second initialization voltage, different from the first initialization voltage, starting at a start time point of the first period of the second scanning period.

[0008] In a second period between the writing period and the first emission period, the gate of the second transistor may be configured to receive another first gate signal of the gate-on voltage, and the gate of the third transistor may be configured to receive another second gate signal of the gate-on voltage.

[0009] The pixel may further include a fourth transistor electrically connected to the data line and the gate of the first transistor, and the gate of the fourth transistor may be configured to receive a third gate signal of a gate-on voltage in a writing period.

[0010] The pixel may further include: a fifth transistor electrically connected to a driving voltage line and the first transistor; and a sixth transistor electrically connected to the gate of the first transistor and a reference voltage line, wherein, in a third period before a writing period of the first scanning period, the gate of the second transistor may be configured to receive a first gate signal of a gate-off voltage, the gate of the fifth transistor may be configured to receive a fourth gate signal of a gate-on voltage, and the gate of the sixth transistor may be configured to receive a fifth gate signal of a gate-on voltage.

[0011] In the second scan period, the gate of the fifth transistor may be configured to receive another fourth gate signal of a gate-on voltage during the second emission period, and the gate of the fifth transistor may be configured to receive a fourth gate signal of a gate-off voltage during a period other than the second emission period.

[0012] The plurality of pixels may include a first pixel emitting light of a first color and a second pixel emitting light of a second color, and a second initialization voltage supplied to the first pixel and a second initialization voltage supplied to the second pixel may be different from each other.

[0013] The gate of the fifth transistor may be configured to receive a fourth gate signal of a gate-on voltage during the second scan period.

[0014] The plurality of pixels may include a first pixel emitting light of a first color and a second pixel emitting light of a second color, and the second initialization voltage supplied to the first pixel and the second initialization voltage supplied to the second pixel may be different from each other.

[0015] The display device may further include a power supply circuit configured to output a first initialization voltage to the plurality of pixels during the first scan period and configured to output a second initialization voltage starting from a start time point of a first period of the second scan period.

[0016] According to another aspect of the disclosure, a display device includes a plurality of pixels, each of the plurality of pixels including: a light-emitting diode; a first transistor electrically connected to a drive voltage line and the light-emitting diode; a second transistor electrically connected to the first transistor and the light-emitting diode; and a third transistor electrically connected to the light-emitting diode and an initialization voltage line. The pixel can be configured to operate during a first scanning period and a second scanning period during a frame, the first scanning period including a write period for receiving a data signal and a first emission period for emitting light having a brightness corresponding to the data signal, and the second scanning period including a second emission period for holding the data signal and emitting light having a brightness corresponding to the held data signal. The gate of the second transistor can be configured to receive a first gate signal, a gate-on voltage, during the second scanning period. The initialization voltage line can be configured to receive a first initialization voltage until before the first emission period of the first scanning period, and to receive a second initialization voltage, different from the first initialization voltage, during the first emission period of the first scanning period and the second scanning period.

[0017] In a first period between the writing period and the first emission period, the gate of the second transistor may be configured to receive another first gate signal of the gate-on voltage, and the gate of the third transistor may be configured to receive a second gate signal of the gate-on voltage.

[0018] The pixel may further include a fourth transistor electrically connected to the data line and the gate of the first transistor, and the gate of the fourth transistor may be configured to receive a third gate signal of a gate-on voltage in a writing period.

[0019] The pixel may further include: a fifth transistor electrically connected to a driving voltage line and the first transistor; and a sixth transistor electrically connected to a gate of the first transistor and a reference voltage line, wherein, in a second period before a writing period of the first scanning period, the gate of the second transistor may be configured to receive a first gate signal of a gate-off voltage, the gate of the fifth transistor may be configured to receive a fourth gate signal of a gate-on voltage, and the gate of the sixth transistor may be configured to receive a fifth gate signal of a gate-on voltage.

[0020] In the second scan period, the gate of the fifth transistor may be configured to receive a fourth gate signal of a gate-on voltage during the second emission period and to receive a fourth gate signal of a gate-off voltage during periods other than the second emission period.

[0021] The plurality of pixels may include a first pixel emitting light of a first color and a second pixel emitting light of a second color, and a second initialization voltage supplied to the first pixel and a second initialization voltage supplied to the second pixel may be different from each other.

[0022] The gate of the fifth transistor may be configured to receive a fourth gate signal of a gate-on voltage during the second scan period.

[0023] The plurality of pixels may include a first pixel emitting light of a first color and a second pixel emitting light of a second color, and a second initialization voltage supplied to the first pixel and a second initialization voltage supplied to the second pixel may be different from each other.

[0024] The display device may further include a power supply circuit configured to output a first initialization voltage until before a first emission period of the first scan period and to output a second initialization voltage during the first emission period of the first scan period and the second scan period.

[0025] According to another aspect of the disclosure, a method for driving a display device is provided. The display device includes a plurality of pixels, each of the plurality of pixels including: a light-emitting diode; a first transistor electrically connected to the light-emitting diode; a second transistor electrically connected to the light-emitting diode; and a third transistor electrically connected to the light-emitting diode and an initialization voltage line. The pixels may be configured to operate during a frame period that may include a first scanning period and a second scanning period. The first scanning period includes a writing period for receiving a data signal and a first emission period for emitting light having a brightness corresponding to the data signal; and the second scanning period includes a second emission period for holding the data signal and emitting light having a brightness corresponding to the held data signal. In each pixel, the driving method includes: during a first period between the writing period and the first emission period of the first scanning period, a gate of the second transistor receives a first gate signal of a gate-on voltage, and a gate of the third transistor receives a second gate signal of a gate-on voltage. The driving method further includes: during a second scanning period, a gate of the second transistor receives another first gate signal of a gate-on voltage. The driving method further includes: during a second period of the second scanning period, before the second emission period, a gate of the third transistor receives another second gate signal of a gate-on voltage. The driving method further includes initializing the voltage line to receive a first initialization voltage during a first period of the first scan period and receiving a second initialization voltage different from the first initialization voltage from a start time point of at least a second period of the second scan period.

[0026] The pixel may further include a fifth transistor electrically connected to the driving voltage line and the first transistor, and in the second scanning period, the gate of the fifth transistor may receive a third gate signal of a gate-on voltage during the second emission period, and the gate of the fifth transistor receives a third gate signal of a gate-off voltage during a period other than the second emission period.

[0027] Advantageous Effects of the Invention According to one or more embodiments, a display device with improved display quality can be provided. Of course, the scope of the disclosure is not limited by these effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects and features of the disclosure will become more apparent by describing in detail the disclosed embodiments with reference to the accompanying drawings.

[0029] Figure 1a and Figure 1b is a view schematically showing a display device according to an embodiment.

[0030] Figure 2 is a view schematically showing a display device according to an embodiment.

[0031] Figure 3a and Figure 3b is a conceptual diagram for describing a driving method of a display device according to a driving frequency.

[0032] Figure 4 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment.

[0033] Figure 5 and Figure 6 is a schematic diagram for describing an embodiment of the present invention. Figure 4 FIG. 1 is a view of a signal of the pixel operation shown in FIG.

[0034] Figure 7 It shows that according to Figure 5 and Figure 6 A view of the brightness of a display device of an embodiment.

[0035] Figure 8 is a schematic diagram for describing an embodiment of the present invention. Figure 4 FIG. 1 is a view of a signal of the pixel operation shown in FIG.

[0036] Figures 9 to 11 is a schematic diagram for describing an embodiment of the present invention. Figure 4 FIG. 1 is a view of a signal of the pixel operation shown in FIG.

[0037] Figures 12 to 15 is a schematic diagram for describing an embodiment of the present invention. Figure 4 FIG. 1 is a view of a signal of the pixel operation shown in FIG.

[0038] Figure 16 It shows that according to Figures 8 to 15 A view of the brightness of a display device of an embodiment.

[0039] Figure 17 is a view for describing an output of an initialization voltage according to an embodiment.

[0040] Figure 18 is a schematic cross-sectional view showing the structure of a display element according to an embodiment.

[0041] Figures 19a to 21 is a schematic cross-sectional view showing the structure of a display element according to an embodiment.

[0042] Best Way According to one disclosed aspect, a display includes a plurality of pixels, each of the plurality of pixels including a light-emitting diode (LED), a first transistor electrically connected to a drive voltage line and the LED, a second transistor electrically connected to the first transistor and the LED, and a third transistor electrically connected to the LED and an initialization voltage line. The pixel can be configured to operate during a first scanning period and a second scanning period during a frame, the first scanning period including a writing period for receiving a data signal and a first emission period for emitting light having a brightness corresponding to the data signal, and the second scanning period including a second emission period for holding the data signal and emitting light having a brightness corresponding to the held data signal. The gate of the second transistor can also be configured to receive a first gate signal of a gate-on voltage during the second scanning period. The gate of the third transistor can be configured to receive a second gate signal of a gate-on voltage in a first period prior to the second emission period of the second scanning period. The initialization voltage line can be configured to receive a first initialization voltage during the first scanning period and to receive a second initialization voltage different from the first initialization voltage starting at a start time point of the first period of the second scanning period. DETAILED DESCRIPTION

[0043] The disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown. However, the disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the disclosure to those skilled in the art.

[0044] In the specification and claims, for the purposes of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or." For example, "A and / or B" may be understood to mean "A, B, or A and B." The terms "and" and "or" may be used in a conjunction or disjunction sense and may be understood to be equivalent to "and / or."

[0045] In the specification and claims, for the purposes of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" can be understood to mean "A, B, or A and B."

[0046] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the disclosure.

[0047] For ease of description, spatially relative terms such as "below," "under," "down," "above," "up," etc. may be used herein to describe the relationship between one element or component and another element or component as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, where the device shown in the accompanying drawings is flipped over, a device that is "below" or "beneath" another device may be placed "above" the other device. Thus, the illustrative term "below" may include both a lower position and an upper position. The device may also be oriented in other directions, and thus the spatially relative terms may be interpreted differently depending on the orientation.

[0048] The phrase "in a plan view" means viewing an object from the top, and the phrase "in a schematic cross-sectional view" means viewing a cross section of an object vertically cut from the side. Therefore, the expression "in a plan view" used herein may mean viewing an object from the top along the Figure 1a or Figure 1b The phrase "in a schematic cross-sectional view" means viewing the cross section from the side along the "x" or "y" direction along which the object is vertically cut, where the "x", "y", and "z" directions are perpendicular to each other. The "z" direction may also be referred to as the "thickness direction."

[0049] Because various modifications and various embodiments of the disclosure are possible, specific embodiments are shown in the drawings and described in detail in the detailed description. The effects and features of the disclosure and methods for achieving them will be apparent by reference to the embodiments described in detail below in conjunction with the drawings. However, the disclosure is not limited to the embodiments disclosed herein, but can be implemented in various forms.

[0050] In the following embodiments, the terms first, second, etc. are used to distinguish one element from other elements, and are not intended to be limiting.

[0051] The term "overlying" or variations thereof means that a first object can be above, below, or to one side of a second object, and vice versa. Additionally, the term "overlying" may include layering, stacking, facing, facing, extending over, covering, or partially covering, or any other suitable term as would be appreciated and understood by one of ordinary skill in the art.

[0052] When an element is described as “not overlying” another element or variations thereof, this can include the elements being spaced apart from each other, offset from each other, or set offset from each other, or any other appropriate terminology as will be appreciated and understood by those having ordinary skill in the art.

[0053] When the terms "includes," "comprising," and / or "having" and variations thereof are used in this specification, they indicate the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0054] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0055] It will be understood that when an element (or region, layer, portion, etc.) is referred to in the specification as being "on," "disposed on," "connected to," or "coupled to" another element, the element may be directly disposed on, directly connected to, or directly coupled to the other element, or an intervening element may be disposed therebetween. It will be understood that the term "connected to" or "coupled to" may include either a physical connection (or coupling) or an electrical connection (or coupling).

[0056] In the drawings, the size, thickness, ratio and dimensions of elements may be exaggerated for ease of description and clarity. Throughout the text, like numerals and / or reference characters refer to like elements.

[0057] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0058] The terms "facing" and "facing" mean that the first element may be directly or indirectly opposite to the second element. In the case where a third element is interposed between the first and second elements, the first and second elements may be understood to be indirectly opposite to each other although still facing each other.

[0059] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0060] When an element is referred to as being “in contact with” or “connected to” another element, the element may be “in electrical contact with” or “in physical contact with” the other element; or “indirect contact with” or “direct contact with” the other element.

[0061] A description that a component is "configured to" perform a specified operation may be defined as a situation where the component is configured and arranged with structural features that enable the component to perform the specified operation.

[0062] The embodiments may be described and illustrated in the drawings in the form of functional blocks, units and / or modules.

[0063] Those skilled in the art will understand that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc.) that can be formed using semiconductor-based manufacturing technology or other manufacturing technology.

[0064] Where the blocks, units and / or modules are implemented by a microprocessor or other similar hardware, they may be programmed and controlled using software (eg, microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software.

[0065] It is also contemplated that each block, unit and / or module may be implemented by dedicated hardware, or as a combination of dedicated hardware to perform some functions and a processor (eg, one or more programmed microprocessors and related circuits) to perform other functions.

[0066] Each block, unit and / or module of the embodiments may be physically divided into two or more interacting and separate blocks, units and / or modules without departing from the scope of the disclosure.

[0067] Furthermore, the blocks, units and / or modules of the embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the disclosure.

[0068] In the following embodiments, when X and Y are connected, this includes cases where X and Y are electrically connected, cases where X and Y are functionally connected, and cases where X and Y are directly connected. Here, X and Y can be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, the disclosure is not limited to predetermined connection relationships (e.g., the connection relationships indicated in the drawings or detailed description) and may also include connection relationships other than those indicated in the drawings or detailed description.

[0069] When X and Y are electrically connected, for example, one or more elements capable of electrically connecting X and Y (eg, switches, transistors, capacitors, inductors, resistors, diodes, etc.) may be connected between X and Y.

[0070] In the following embodiments, "on" used in relation to a device state may refer to the activated state of an element, while "off" may refer to the deactivated state of an element. "On" used in relation to a signal received by an element may refer to a signal that activates the element, while "off" may refer to a signal that deactivates the element. An element can be activated by either a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) can be activated by a low-level voltage, while an N-channel transistor (N-type transistor) can be activated by a high-level voltage. Therefore, it should be understood that the "on" voltages for a P-type transistor and an N-type transistor are opposite (low vs. high) voltage levels.

[0071] In the following embodiments, the x-direction, y-direction, and z-direction are not limited to the three axes on the Cartesian coordinate system and can be interpreted in a broad sense including the same. For example, the x-direction, y-direction, and z-direction may be perpendicular to each other, but may refer to different directions that are not orthogonal to each other.

[0072] The display device according to an embodiment can be a device for displaying moving or still images and can be used in display screens for various products such as portable electronic devices (e.g., mobile phones, smartphones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs)), televisions, laptop computers, monitors, billboards, and Internet of Things (IoT) devices. The display device 10 according to an embodiment can be used in wearable devices such as smartwatches, watch phones, glasses-type displays, or head-mounted displays (HMDs). The display device 10 according to an embodiment can also be used as a central information display (CID) display on a vehicle's dashboard, a center console panel or instrument panel, a rear-view mirror display that replaces a vehicle's side mirrors, and a display on the rear surface of a front seat. The display device can be a flexible device.

[0073] Figure 1a and Figure 1b is a view schematically showing a display device according to an embodiment. Figure 2 is a view schematically showing a display device according to an embodiment. Figure 3a and Figure 3b is a conceptual diagram for describing a driving method of a display device according to a driving frequency.

[0074] Reference Figure 1a and Figure 1b, the display device 10 may include a display area DA in which an image may be displayed and a peripheral area PA outside the display area DA. The display area DA may be completely surrounded by the peripheral area PA.

[0075] When the display area DA is viewed in a plan view along the "z" direction, the display area DA may have a rectangular shape. In embodiments, the display area DA may have a polygonal shape (such as a triangle, a pentagon, a hexagon, etc.), a circular shape, an elliptical shape, an atypical shape, etc. The corners of the display area DA may have a rounded shape. In embodiments, as Figure 1a As shown in , the display device 10 may have a display area DA having a shape in which the length in the x direction is greater than the length in the y direction. Figure 1b As shown in , the display device 10 may have a display area DA having a shape in which a length in the y direction is greater than a length in the x direction.

[0076] Reference Figure 2 The display device 10 according to the embodiment may include a pixel portion 11 , a gate driving circuit 13 , a data driving circuit 15 , a power supply circuit 17 , and a controller 19 .

[0077] The pixel portion 11 may be disposed in the display area DA. Various conductive lines for transmitting electrical signals applied to the display area DA, external circuits electrically connected to the pixel circuits, and pads (also known as "bonding pads" or "pads") to which a printed circuit board or driver IC chip may be attached may be located in the peripheral area PA. For example, the gate drive circuit 13, the data drive circuit 15, the power supply circuit 17, and the controller 19 may be disposed in the peripheral area PA.

[0078] like Figure 2 As shown in FIG, the gate lines GL, the data lines DL and the pixels PX electrically connected thereto may be arranged in the display area DA. The pixels PX may be arranged in a pattern such as a stripe pattern, a PenTile pattern or a TM Various arrangements are possible, such as a diamond arrangement (diamond arrangement) and a mosaic arrangement. Each pixel PX may include an organic light-emitting diode (OLED) as a display element (light-emitting device), and the organic light-emitting diode OLED may be electrically connected to a pixel circuit. The pixel circuit may include a transistor and at least one capacitor. The pixel PX may emit, for example, red, green, blue, or white light through the organic light-emitting diode OLED. Each pixel PX may be electrically connected to a corresponding gate line among the gate lines GL and a corresponding data line among the data lines DL.

[0079] Each gate line GL may extend in the x-direction (row direction) and may be electrically connected to pixels PX located in the same row. Each gate line GL may transmit a gate signal to pixels PX located in the same row. Each data line DL may extend in the y-direction (column direction) and may be electrically connected to pixels PX located in the same column. Each data line DL may transmit a data signal to pixels PX located in the same column in synchronization with the gate signal.

[0080] In an embodiment, the peripheral area PA may be a non-display area in which no pixels PX are arranged. In an embodiment, a portion of the peripheral area PA may be implemented as the display area DA. For example, the pixels PX may overlap the gate driver circuit 13 at at least one corner of the peripheral area PA. Thus, dead zones (defined as areas without functional utility) may be reduced and the display area DA may be expanded.

[0081] The gate drive circuit 13 may be electrically connected to the gate lines GL, may generate gate signals GS in response to control signals GCS from the controller 19, and may sequentially supply the gate signals GS to the gate lines GL. The gate lines GL may be electrically connected to the gates of the transistors included in the pixels PX. The gate signals GS may be gate control signals for controlling the on and off states of the transistors having gates electrically connected to the gate lines GL. The gate signals GS may be square wave signals including an on-voltage that may turn on (or "activate") the transistors and an off-voltage that may turn off (or "deactivate") the transistors.

[0082] exist Figure 2 , the pixel PX may be electrically connected to one gate line GL. However, this is merely an example, and the pixel PX may be electrically connected to two or more gate lines, and the gate driving circuit 13 may supply two or more gate signals GS having different timings to the corresponding gate lines GL, with the on-voltage applied thereto at the different timings.

[0083] The data driving circuit 15 may be electrically connected to the data line DL and may supply a data signal to the data line DL in response to a control signal DCS from the controller 19. The data signal supplied to the data line DL may be supplied to the pixel PX to which the gate signal is supplied. The data driving circuit 15 may output the input image data ( Figure 2 DATA) is converted into a data signal in the form of voltage or current. Figure 2 An example is shown in which the data driving circuit 15 outputs the data signal Vdata in the form of a voltage.

[0084] The power supply circuit 17 can generate voltages required to drive the pixel PX in response to a control signal PCS from the controller 19. The power supply circuit 17 can generate a first drive voltage ELVDD and a second drive voltage ELVSS, and supply the generated first drive voltage ELVDD and second drive voltage ELVSS to the pixel PX. The first drive voltage ELVDD can be a high-level voltage supplied to the first electrode (pixel electrode or anode) of the display element included in the pixel PX. The second drive voltage ELVSS can be a low-level voltage supplied to the second electrode (counter electrode or cathode) of the display element included in the pixel PX.

[0085] The controller 19 may generate control signals GCS, DCS, and PCS based on signals input from the outside, and may supply the control signals GCS, DCS, and PCS to the gate drive circuit 13, the data drive circuit 15, and the power supply circuit 17. The control signal GCS output to the gate drive circuit 13 may include a clock signal and a gate start signal. The control signal DCS output to the data drive circuit 15 may include a source start signal and a clock signal.

[0086] The display device 10 may include a display panel, and the display panel may include a substrate. Pixels PX may be arranged in a display area DA of the substrate. During the process of forming transistors constituting the pixel circuit in the display area DA of the substrate, part or all of the gate driver circuit 13 may be formed (e.g., directly formed) in the peripheral area PA of the substrate. The data driver circuit 15, the power supply circuit 17, and the controller 19 may be formed in the form of separate integrated circuit (IC) chips or a single IC circuit chip and may be provided on a flexible printed circuit board (FPCB) electrically connected to a pad provided on one side of the substrate. In an embodiment, the data driver circuit 15, the power supply circuit 17, and the controller 19 may be arranged on the substrate in a chip-on-glass (COG) or chip-on-plastic (COP) manner.

[0087] The display device 10 may support a variable refresh rate (VRR). The refresh rate may be the frequency at which data signals are written to the driver transistors of pixels PX. It may represent the screen scan rate, screen refresh rate, and the number of image frames (also referred to herein as "frames") displayed in one second. In embodiments, the refresh rate may be the output frequency of the gate driver circuit 13 and / or the data driver circuit 15. The frequency corresponding to the refresh rate may be the driving frequency. The display device 10 may adjust the output frequency of the gate driver circuit 13 and the output frequency of the data driver circuit 15 corresponding to the output frequency according to the driving frequency. A display device 10 supporting VRR may operate while varying the driving frequency within a range of a maximum driving frequency and a minimum driving frequency. For example, at a refresh rate of approximately 60 Hz, a gate signal for writing a data signal 60 times per second may be supplied to each horizontal line (row). The display device 10 may display an image while varying the driving frequency according to the refresh rate.

[0088] One frame 1F (eg, a single image frame) may include a first scanning period AS and one or more second scanning periods SS according to the driving frequency. Figure 3a As shown in FIG, in a display device 10 operating at a driving frequency of AHz, a frame 1F may include a first scanning period AS and a second scanning period SS. Figure 3b As shown in , in a display device 10 operating at a driving frequency of BHz lower than a driving frequency of AHz, a frame 1F may include one first scanning period AS and two or more second scanning periods SS. As the driving frequency decreases, the number of second scanning periods SS increases, and the length of the frame 1F may increase. In an embodiment, the frame 1F may include only one first scanning period AS.

[0089] The first scanning period AS can be defined as an address scanning period, during which the pixel PX emits light by writing a data signal to the pixel PX in response to the first gate signal GW. The operation in which the data signal is written from the data line DL to the pixel PX can also be referred to as a data programming operation. During the second scanning period SS, the first gate signal GW is not applied to the pixel PX. Therefore, the second scanning period SS can be defined as a self-scan period in which no data signal is written. During the second scanning period SS, the data signal written during the first scanning period AS can be maintained, and the pixel can emit light. The length of the second scanning period SS can be the same as the length of the first scanning period AS.

[0090] Figure 4 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment.

[0091] Reference Figure 4, the pixel PX may include a pixel circuit PC electrically connected to the gate line GL and the data line DL, and an organic light emitting diode OLED as a display element electrically connected to the pixel circuit PC.

[0092] The pixel PX may be electrically connected to a first gate line GWL for transmitting a first gate signal GW, a second gate line GIL for transmitting a second gate signal GI, a third gate line GRL for transmitting a third gate signal GR, a fourth gate line EML for transmitting a fourth gate signal EM, a fifth gate line EMBL for transmitting a fifth gate signal EMB, and a data line DL for transmitting a data signal Vdata. Since emission of the pixel PX may be controlled by the fourth gate signal EM and the fifth gate signal EMB, the fourth gate signal EM and the fifth gate signal EMB may be referred to as emission control signals, and the fourth gate line EML and the fifth gate line EMBL may be referred to as emission control lines.

[0093] In addition, the pixel PX may be electrically connected to a driving voltage line PL for transmitting a first driving voltage ELVDD, a reference voltage line VRL for transmitting a reference voltage Vref, and an initialization voltage line VL for transmitting an initialization voltage Vint.

[0094] exist Figure 2 In the pixel portion 11 shown in FIG, first to fifth gate lines may be provided, and the gate driving circuit 13 may apply a first gate signal GW, a second gate signal GI, a third gate signal GR, a fourth gate signal EM, and a fifth gate signal EMB to the first gate line GWL, the second gate line GIL, the third gate line GRL, the fourth gate line EML, and the fifth gate line EMBL, respectively. The power supply circuit 17 may generate a reference voltage Vref and an initialization voltage Vint to supply the reference voltage Vref and the initialization voltage Vint to the pixel PX.

[0095] The voltage level of the first driving voltage ELVDD may be higher than the voltage level of the second driving voltage ELVSS. The voltage level of the reference voltage Vref may be lower than the voltage level of the first driving voltage ELVDD. The voltage level of the initialization voltage Vint may be lower than the voltage level of the second driving voltage ELVSS.

[0096] In an embodiment, the transistor included in the pixel circuit PC may be an N-type oxide thin-film transistor. The oxide thin-film transistor may be a low-temperature polycrystalline oxide (LTPO) thin-film transistor in which the active pattern (semiconductor) includes an oxide. However, this is merely an example, and N-type transistors are not limited thereto. For example, the active pattern (semiconductor) included in the N-type transistor may include an inorganic semiconductor (e.g., amorphous silicon), polycrystalline silicon, an organic semiconductor, or the like, or a combination thereof.

[0097] The pixel circuit PC may include first to sixth transistors T1 to T6 and first and second capacitors C1 and C2. The first transistor T1 may be a driving transistor that outputs a driving current corresponding to a data signal, and the second to sixth transistors T2 to T6 may be switching transistors for transmitting signals. The first terminal (first electrode) and second terminal (second electrode) of each of the first to sixth transistors T1 to T6 may function as a source or a drain depending on the voltages of the first and second terminals. For example, depending on the voltages of the first and second terminals, the first terminal may function as a drain and the second terminal as a source, or the first terminal may function as a source and the second terminal as a drain. The node to which the first gate of the first transistor T1 is electrically connected may be defined as a first node N1, and the node to which the second terminal of the first transistor T1 is electrically connected may be defined as a second node N2.

[0098] The first transistor T1 may be electrically connected between the driving voltage line PL and the second node N2. The first transistor T1 may include a gate, a first terminal, and a second terminal electrically connected to the second node N2. The gate of the first transistor T1 may include a first gate electrically connected to the first node N1 and a second gate electrically connected to the second node N2. The first gate and the second gate may be arranged at different layers to face each other. For example, the first gate and the second gate of the first transistor T1 may be arranged to face each other with a semiconductor layer therebetween.

[0099] The first gate of the first transistor T1 can be electrically connected to the second terminal of the second transistor T2, the first terminal of the third transistor T3, and the first capacitor C1. The second gate of the first transistor T1 can be electrically connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first terminal of the first transistor T1 can be electrically connected to the driving voltage line PL via the fifth transistor T5, and the second terminal of the first transistor T1 can be electrically connected to the pixel electrode of the organic light emitting diode OLED via the sixth transistor T6. The first terminal of the first transistor T1 can be electrically connected to the second terminal of the fifth transistor T5. The second gate of the first transistor T1 can be electrically connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first transistor T1 can control the amount of driving current flowing through the organic light emitting diode OLED by receiving the data signal Vdata according to the switching operation of the second transistor T2.

[0100] The second transistor (write transistor) T2 can be electrically connected between the data line DL and the first gate of the first transistor T1. The second transistor T2 can include a gate electrically connected to the first gate line GWL, a first terminal electrically connected to the data line DL, and a second terminal electrically connected to the first node N1. The second terminal of the second transistor T2 can be electrically connected to the first gate of the first transistor T1, the first terminal of the third transistor T3, and the first capacitor C1. The second transistor T2 can be turned on by the first gate signal GW transmitted to the first gate line GWL. It can be configured to electrically connect the data line DL to the first node N1 and transmit the data signal Vdata transmitted to the data line DL to the first node N1.

[0101] The third transistor (first initialization transistor) T3 can be electrically connected between the first gate of the first transistor T1 and the reference voltage line VRL. The third transistor T3 can include a gate electrically connected to the third gate line GRL, a first terminal electrically connected to the first node N1, and a second terminal electrically connected to the reference voltage line VRL. The first terminal of the third transistor T3 can be electrically connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first capacitor C1. The third transistor T3 can be turned on by a third gate signal GR transmitted to the third gate line GRL and can transmit the reference voltage Vref transmitted to the reference voltage line VRL to the first node N1.

[0102] The fourth transistor (a second initialization transistor or reset transistor) T4 can be electrically connected between the sixth transistor T6 and the initialization voltage line VL. The fourth transistor T4 can be electrically connected between the organic light emitting diode OLED and the initialization voltage line VL. The fourth transistor T4 can include a gate electrically connected to the second gate line GIL, a first terminal electrically connected to the third node N3, and a second terminal electrically connected to the initialization voltage line VL. The first terminal of the fourth transistor T4 can be electrically connected to the second terminal of the sixth transistor T1 and the organic light emitting diode OLED. The fourth transistor T4 can be turned on by the second gate signal GI transmitted to the second gate line GIL and can transmit the initialization voltage Vint transmitted to the initialization voltage line VL to the third node N3.

[0103] A fifth transistor (first emission control transistor) T5 may be electrically connected between the driving voltage line PL and the first transistor T1. The fifth transistor T5 may include a gate electrically connected to the fourth gate line EML, a first terminal electrically connected to the driving voltage line PL, and a second terminal electrically connected to the first terminal of the first transistor T1. The fifth transistor T5 may be turned on or off based on a fourth gate signal EM transmitted to the fourth gate line EML.

[0104] The sixth transistor (second emission control transistor) T6 may be electrically connected between the first transistor T1 and the organic light emitting diode OLED. The sixth transistor T6 may be electrically connected between the second node N2 and the third node N3. The sixth transistor T6 may include a gate electrically connected to the fifth gate line EMBL, a first terminal electrically connected to the second node N2, and a second terminal electrically connected to the third node N3. The first terminal of the sixth transistor T6 may be electrically connected to the second terminal of the first transistor T1, the first capacitor C1, and the second capacitor C2. The second terminal of the sixth transistor T6 may be electrically connected to the first terminal of the fourth transistor T4 and the pixel electrode of the organic light emitting diode OLED. The sixth transistor T6 may be turned on or off based on a fifth gate signal EMB transmitted to the fifth gate line EMBL.

[0105] The first capacitor C1 may be electrically connected between the first gate of the first transistor T1 and the second terminal of the first transistor T1. The first electrode of the first capacitor C1 may be electrically connected to the first node N1, and the second electrode of the first capacitor C1 may be electrically connected to the second node N2. The first electrode of the first capacitor C1 may be electrically connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first terminal of the third transistor T3. The second electrode of the first capacitor C1 may be electrically connected to the second terminal and the gate of the first transistor T1, the second electrode of the second capacitor C2, and the first terminal of the sixth transistor T6. The first capacitor C1 may be a storage capacitor and may store the threshold voltage of the first transistor T1 and a voltage corresponding to the data signal Vdata.

[0106] The second capacitor C2 may be electrically connected between the driving voltage line PL and the second node N2. A first electrode of the second capacitor C2 may be electrically connected to the driving voltage line PL. A second electrode of the second capacitor C2 may be electrically connected to the second terminal and the second gate of the first transistor T1, as well as the second electrode of the first capacitor C1 and the first terminal of the sixth transistor T6. The capacitance of the first capacitor C1 may be greater than that of the second capacitor C2.

[0107] The organic light emitting diode OLED may be electrically connected to the first transistor T1 via the sixth transistor T6. The organic light emitting diode OLED may include a pixel electrode (anode) electrically connected to the third node N3 and a counter electrode (cathode) facing the pixel electrode. The counter electrode may receive the second driving voltage ELVSS. The counter electrode may be a common electrode shared by a plurality of pixels PX.

[0108] Figure 5 and Figure 6 is a schematic diagram for describing an embodiment of the present invention. Figure 4 FIG. 1 is a view of a signal of the pixel operation shown in FIG. Figure 7 It shows that according to Figure 5 and Figure 6 A view of the brightness of a display device of an embodiment.

[0109] In an embodiment, the frame 1F may include one first scanning period AS and at least one second scanning period SS. Figure 5 and Figure 6 An example is shown in which a frame 1F includes one first scanning period AS and one second scanning period SS.

[0110] Each of the first gate signal GW, the second gate signal GI, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB may have a high-level voltage (a first-level voltage) during some periods, and may have a low-level voltage (a second-level voltage) during some periods. Here, the high-level voltage may be a gate-on voltage for turning on the transistor, and the low-level voltage may be a gate-off voltage for turning off the transistor.

[0111] The first scanning period AS may include a first non-emission period NEP1 in which the pixel PX does not emit light and a first emission period EP1 in which the pixel PX emits light. The first non-emission period NEP1 may include a first period P1, a second period P2, a third period P3, and a fourth period P4.

[0112] The first period P1 may be a first initialization period (reset period), during which the first gate of the first transistor T1 is electrically connected to its first node N1 and the pixel electrode of the organic light emitting diode OLED is connected to its third node N3, which are initialized. During the first period P1, the second gate signal GI of the gate-on voltage may be supplied (applied) to the second gate line GIL. The fifth gate signal EMB of the gate-on voltage may be supplied to the fifth gate line EMBL in the first half of the first period P1, and the third gate signal GR of the gate-on voltage may be supplied to the third gate line GRL in the second half of the first period P1. During the first period P1, the first gate signal GW and the fourth gate signal EM of the gate-off voltage may be supplied to the pixel. The third gate signal GR of the gate-off voltage may be supplied to the pixel in the first half of the first period P1, and the fifth gate signal EMB of the gate-off voltage may be supplied to the pixel in the second half of the first period P1.

[0113] In the first half of the first period P1, the sixth transistor T6 can be turned on by the fifth gate signal EMB, and the fourth transistor T4 can be turned on by the second gate signal GI. Due to the sixth transistor T6 and the fourth transistor T4, the second node N2 and the third node N3 can change to a value between the emission voltage and the initialization voltage Vint (approximately the emission voltage). In the second half of the first period P1, the sixth transistor T6 can be turned off by the fifth gate signal EMB, the third transistor T3 can be turned on by the third gate signal GR, and the fourth transistor T4 can be turned on by the second gate signal GI. The first node N1 (e.g., the first gate of the first transistor T1) can be initialized to the reference voltage Vref by the turned-on third transistor T3. The third node N3 (e.g., the pixel electrode of the organic light emitting diode OLED) can be initialized to the initialization voltage Vint by the turned-off sixth transistor T6 and the turned-on fourth transistor T4. Since the pixel electrode of the organic light emitting diode OLED is reset to the initialization voltage Vint during the first period P1, the first period P1 can also be referred to as a reset period.

[0114] The second period P2 may be a compensation period in which the threshold voltage of the first transistor T1 is compensated. During the second period P2, the third gate signal GR of the gate-on voltage may be supplied to the third gate line GRL, and the fourth gate signal EM of the gate-on voltage may be supplied to the fourth gate line EML. The first gate signal GW, the second gate signal GI, and the fifth gate signal EMB of the gate-off voltage may be supplied to the pixel.

[0115] The third transistor T3 can be turned on by the third gate signal GR, and the fifth transistor T5 can be turned on by the fourth gate signal EM. Therefore, the reference voltage Vref can be supplied to the first node N1, and the first drive voltage ELVDD can be supplied to the first terminal of the first transistor T1, turning on the first transistor T1. When the voltage at the second terminal of the first transistor T1 drops to the difference (Vref-Vth) between the reference voltage Vref and the threshold voltage (Vth) of the first transistor T1, the first transistor T1 can be turned off. A voltage corresponding to the threshold voltage (Vth) of the first transistor T1 can be stored in the first capacitor C1 to compensate for the threshold voltage (Vth) of the first transistor T1.

[0116] The third period P3 may be a write period in which the data signal Vdata is supplied to the pixel. In the third period P3, the first gate signal GW of the gate-on voltage may be supplied to the first gate line GWL. The second gate signal GI, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB of the gate-off voltage may be supplied to the pixel.

[0117] The second transistor T2 can be turned on by the first gate signal GW. The turned-on second transistor T2 can be configured to transmit the data signal Vdata from the data line DL to the first node (i.e., the first gate of the first transistor T1). Therefore, the voltage of the first node N1 can change from the reference voltage Vref to a voltage corresponding to the data signal Vdata. The voltage of the second node N2 can change in response to the voltage change of the first node N1. The voltage of the second node N2 can be a voltage (Vref-Vth+α×(Vdata-Vref)) that changes according to the capacity ratio (α=C1 / (C1+C2)) between the first capacitor C1 and the second capacitor C2. Therefore, the threshold voltage (Vth) of the first transistor T1 and the voltage corresponding to the data signal Vdata can be charged into the first capacitor C1.

[0118] The fourth period P4 may be a second initialization period, which is a period for initializing the second node N2 to which the second terminal of the first transistor T1 is electrically connected and the third node N3 to which the pixel electrode of the organic light emitting diode OLED is connected, after data is written and before the first emission period EP1. In the fourth period P4, the second gate signal GI of the gate-on voltage may be supplied to the second gate line GIL, and then the fifth gate signal EMB of the gate-on voltage may be supplied to the fifth gate line EMBL. The first gate signal GW, the third gate signal GR, and the fourth gate signal EM of the gate-off voltage may be supplied to the pixel.

[0119] The fourth transistor T4 can be turned on by the second gate signal GI, and the initialization voltage Vint can be transmitted to the pixel electrode of the organic light emitting diode OLED through the turned-on fourth transistor T4. Subsequently, the sixth transistor T6 can be turned on by the fifth gate signal EMB, and the second node N2 and the third node N3 can share charges through the turned-on sixth transistor T6 and the fourth transistor T4.

[0120] The first emission period EP1 may be a period during which the organic light emitting diode OLED emits light. During the first emission period EP1, the fourth gate signal EM of the gate-on voltage may be supplied to the fourth gate line EML, and the fifth gate signal EMB of the gate-on voltage may be supplied to the fifth gate line EMBL. The first gate signal GW, the second gate signal GI, and the third gate signal GR may be gate-off voltages.

[0121] In the first emission period EP1, the fifth transistor T5 may be turned on by the fourth gate signal EM, and the first driving voltage ELVDD may be supplied to the first terminal of the first transistor T1 through the turned-on fifth transistor T5. The first transistor T1 may output a driving current (Id∝(Vgs-Vth) 2), the driving current has a magnitude corresponding to a voltage corresponding to the data signal Vdata stored in the first capacitor C1 (for example, a voltage (Vgs−Vth) obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the gate-source voltage (Vgs) of the first transistor T1), the driving current may flow through the sixth transistor T6 turned on by the fifth gate signal EMB, and the organic light emitting diode OLED may emit light having a brightness corresponding to the magnitude of the driving current.

[0122] The second scanning period SS may include a second non-emission period NEP2 in which the pixel PX does not emit light and a second emission period EP2 in which the pixel PX emits light. The second non-emission period NEP2 may include a fifth period P5 and a sixth period P6. Each of the fifth period P5 and the sixth period P6 may correspond to the first period P1 and the fourth period P4 of the first scanning period AS, respectively. The distance between the first period P1 and the fourth period P4 may be the same as the distance between the fifth period P5 and the sixth period P6. The second scanning period SS may not include a compensation period corresponding to the second period P2 of the first scanning period AS and a writing period corresponding to the third period P3 of the first scanning period AS.

[0123] The fifth period P5 may be a third initialization period (reset period) for initializing the third node N3 to which the pixel electrode of the organic light emitting diode OLED is connected. The fifth period P5 may correspond to the first period P1 of the first scanning period AS. During the fifth period P5, the second gate signal GI of the gate-on voltage may be supplied to the second gate line GIL. During the fifth period P5, the first gate signal GW, the third gate signal GR, and the fourth gate signal EM of the gate-off voltage may be supplied to the pixel.

[0124] In the first half of the fifth period P5, a fifth gate signal EMB of a gate-on voltage may be supplied to the fifth gate line EMBL. The sixth transistor T6 may be turned on by the fifth gate signal EMB, and the fourth transistor T4 may be turned on by the second gate signal GI. The second node N2 and the third node N3 may be electrically connected to each other through the turned-on sixth transistor T6 and the fourth transistor T4 to share charge, so that the second node N2 and the third node N3 may change to a value between the emission voltage and the initialization voltage Vint (approximately the emission voltage).

[0125] In the second half of the fifth period P5, a fifth gate signal EMB of a gate-off voltage may be supplied to the fifth gate line EMBL. The sixth transistor T6 may be turned off by the fifth gate signal EMB, so that the second node N2 and the third node N3 may be electrically isolated from each other. The third node N3 (e.g., the pixel electrode of the organic light emitting diode OLED) may be initialized to the initialization voltage Vint by the turned-on fourth transistor T4.

[0126] The sixth period P6 may be a fourth initialization period, during which the third node N3 electrically connected to the pixel electrode of the organic light emitting diode OLED is initialized before the second emission period EP2. The sixth period P6 may correspond to the fourth period P4 of the first scanning period AS. In the sixth period P6, the second gate signal GI of the gate-on voltage may be supplied to the second gate line GIL, and then the fifth gate signal EMB of the gate-on voltage may be supplied to the fifth gate line EMBL. The first gate signal GW, the third gate signal GR, and the fourth gate signal EM of the gate-off voltage may be supplied to the pixel.

[0127] The fourth transistor T4 may be turned on by the second gate signal GI, and the initialization voltage Vint may be transmitted to the pixel electrode of the organic light emitting diode OLED through the turned-on fourth transistor T4. Subsequently, the sixth transistor T6 may be turned on by the fifth gate signal EMB, and the second node N2 and the third node N3 may be electrically connected to each other through the turned-on sixth transistor T6 and the fourth transistor T4 to share charge, so that the second node N2 and the third node N3 may change to a value between the emission voltage and the initialization voltage Vint (approximately the emission voltage).

[0128] The second emission period EP2 may be a period during which the organic light emitting diode OLED emits light. The second emission period EP2 may correspond to the first emission period EP1 of the first scanning period AS. In the second emission period EP2, the fourth gate signal EM of the gate-on voltage may be supplied to the fourth gate line EML, and the fifth gate signal EMB of the gate-on voltage may be supplied to the fifth gate line EMBL. The first gate signal GW, the second gate signal GI, and the third gate signal GR may be gate-off voltages.

[0129] During the second emission period EP2, the fifth transistor T5 may be turned on by the fourth gate signal EM, and the first drive voltage ELVDD may be supplied to the first terminal of the first transistor T1 through the turned-on fifth transistor T5. The first transistor T1 may output a drive current having a magnitude corresponding to the voltage stored in the first capacitor C1 (i.e., the data signal Vdata). The drive current may flow through the organic light emitting diode OLED through the sixth transistor T6 turned on by the fifth gate signal EMB, and the organic light emitting diode OLED may emit light having a brightness corresponding to the magnitude of the drive current. During the second emission period EP2, the data signal Vdata stored in the first capacitor C1 may be a signal of the data signal supplied to the pixel PX during the third period P3 of the first scan period AS.

[0130] In an embodiment, Figure 6 As shown in FIG, the fifth gate signal EMB of the gate-on voltage may be supplied during the second scan period SS. For example, in the sixth period P6, the second gate signal GI of the gate-on voltage may be supplied to the second gate line GIL, and the fifth gate signal EMB of the gate-on voltage may be supplied to the fifth gate line EMBL. Therefore, the second node N2 and the third node N3 may be set to the initialization voltage Vint through the turned-on fourth transistor T4 and the turned-on sixth transistor T6.

[0131] according to Figure 6 The gate driving circuit 13 of the embodiment shown in FIG. 1 may supply the fifth gate signal EMB as a constant gate-on voltage without voltage level variation during the second scanning period SS, so that the ... Figure 5 Compared with the gate driving circuit 13 of the embodiment shown in , power consumption can be reduced.

[0132] exist Figure 5 and Figure 6 In the embodiment shown in FIG, the initialization voltage Vint supplied to the pixel electrode of the organic light emitting diode OLED by the fourth transistor T4 may be a first initialization voltage Vint1 having a constant value during one frame.

[0133] exist Figure 5In the embodiment shown in , when the first emission period EP1 starts, the voltage of the second terminal (second node N2) of the first transistor T1 may have a value between the voltage of the second node N2 set according to the data signal Vdata in the third period P3 and the first initialization voltage Vint1 of the third node N3 set in the fourth period P4. When the second emission period EP2 starts, the voltage of the second terminal of the first transistor T1 may have a value (approximate emission voltage) between the emission voltage and the first initialization voltage Vint1 of the third node N3 set in the sixth period P6.

[0134] exist Figure 6 In the embodiment shown in , when the first emission period EP1 starts, the voltage of the second terminal of the first transistor T1 may have a value between the voltage of the second node N2 set according to the data signal Vdata in the third period P3 and the first initialization voltage Vint1 of the third node N3 set in the fourth period P4. When the second emission period EP2 starts, the voltage of the second terminal of the first transistor T1 may be the first initialization voltage Vint1 of the third node N3 set in the sixth period P6.

[0135] exist Figure 6 In the embodiment shown in FIG, the voltage of the second terminal of the first transistor T1 may be less than that at the beginning of the second emission period EP2. Figure 5 In the embodiment shown in FIG, the voltage at the second terminal of the first transistor T1 is obtained when the second emission period EP2 starts. Figure 6 In the embodiment shown in FIG, a voltage difference between a voltage at the second terminal of the first transistor T1 at the start of the first emission period EP1 and a voltage at the second terminal of the first transistor T1 at the start of the second emission period EP2 may be greater than that at the start of the first emission period EP1. Figure 5 In the embodiment shown in , a voltage difference between a voltage of the second terminal of the first transistor T1 at the start of the first emission period EP1 and a voltage of the second terminal of the first transistor T1 at the start of the second emission period EP2 is shown.

[0136] Therefore, if Figure 7 As shown in Figure 5 Compared to the embodiment shown in Figure 6 In the embodiment shown in FIG, a transmission delay occurs, and according to Figure 6 The brightness of the display device of the embodiment shown in FIG. 1 in the second emission period EP2 (curve ①) may be lower than that according to FIG. Figure 5 The brightness of the display device of the embodiment shown in FIG. 1 in the second emission period EP2 (curve ②).

[0137] According to an embodiment, the display device 1 may supply a fifth gate signal EMB of a gate-on voltage to the fifth gate line EMBL in the second scanning period SS to reduce power consumption, and may supply a second initialization voltage Vint2 having a value higher than the first initialization voltage Vint1 at least before a start time point of a fifth period P5 of the second scanning period SS (i.e., before the initialization voltage is supplied to the pixel electrode of the organic light emitting diode OLED), thereby minimizing a brightness difference between the first scanning period AS and the second scanning period SS.

[0138] The second initialization voltage Vint2 may be a value set based on the emission voltage of each grayscale. For example, the second initialization voltage Vint2 may be an average value of the emission voltage of each grayscale. The emission voltage may be a voltage required for the emission of the organic light emitting diode OLED according to the grayscale of the data signal. The second initialization voltage Vint2 may have a higher voltage level than the first initialization voltage Vint1 and may have a lower voltage level than the voltage level of the emission voltage.

[0139] Figure 8 is a schematic diagram for describing an embodiment of the present invention. Figure 4 FIG. 1 is a view of a signal of the pixel operation shown in FIG.

[0140] exist Figure 8 The same reference numerals are used to refer to Figure 6 The periods and signals described herein are described, and redundant description thereof will be omitted. In addition to the voltage level of the initialization voltage Vint, Figure 8 The signals shown in Figure 6 The signals shown in are substantially the same or similar.

[0141] Reference Figure 8 The power supply circuit 17 may supply the initialization voltage Vint as the first initialization voltage Vint1 during the first scanning period AS, and may supply the initialization voltage Vint as the second initialization voltage Vint2 during the second scanning period SS. The voltage level of the second initialization voltage Vint2 may be higher than the voltage level of the first initialization voltage Vint1.

[0142] During the first half of the first period P1, the second gate signal GI of the gate-on voltage may be supplied to the second gate line GIL, and the fifth gate signal EMB of the gate-on voltage may be supplied to the fifth gate line EMBL. The first gate signal GW, the third gate signal GR, and the fourth gate signal EM of the gate-off voltage may be supplied to the pixel. The sixth transistor T6 may be turned on by the fifth gate signal EMB, and the fourth transistor T4 may be turned on by the second gate signal GI. Due to the turned-on sixth transistor T6 and fourth transistor T4, the second node N2 and the third node N3 may change to a value between the emission voltage and the first initialization voltage Vint1 (approximately the emission voltage).

[0143] During the second half of the first period P1, a second gate signal GI of a gate-on voltage may be supplied to the second gate line GIL, and a third gate signal GR of a gate-on voltage may be supplied to the third gate line GRL. A first gate signal GW, a fourth gate signal EM, and a fifth gate signal EMB of a gate-off voltage may be supplied to the pixel. The sixth transistor T6 may be turned off by the fifth gate signal EMB, the third transistor T3 may be turned on by the third gate signal GR, and the fourth transistor T4 may be turned on by the second gate signal GI. The first gate of the first transistor T1 may be initialized to a reference voltage Vref by the turned-on third transistor T3. The pixel electrode of the organic light emitting diode OLED may be initialized to a first initialization voltage Vint1 by the turned-off sixth transistor T6 and the turned-on fourth transistor T4.

[0144] During the second period P2, a third gate signal GR, which is a gate-on voltage, may be supplied to the third gate line GRL, and a fourth gate signal EM, which is a gate-on voltage, may be supplied to the fourth gate line EML. A first gate signal GW, a second gate signal GI, and a fifth gate signal EMB, which are gate-off voltages, may be supplied to the pixel. The third transistor T3 may be turned on by the third gate signal GR, and the fifth transistor T5 may be turned on by the fourth gate signal EM, thereby turning on the first transistor T1. When the voltage at the second terminal of the first transistor T1 drops to the difference (Vref-Vth) between the reference voltage Vref and the threshold voltage (Vth) of the first transistor T1, the first transistor T1 may be turned off, and a voltage corresponding to the threshold voltage (Vth) of the first transistor T1 may be stored in the first capacitor C1 to compensate for the threshold voltage (Vth) of the first transistor T1. Since the fourth transistor T4 and the sixth transistor T6 are turned off, the pixel electrode of the organic light emitting diode OLED may maintain the first initialization voltage Vint1.

[0145] During a third period P3, a first gate signal GW, which is a gate-on voltage, may be supplied to the first gate line GWL. A second gate signal GI, a third gate signal GR, a fourth gate signal EM, and a fifth gate signal EMB, which are gate-off voltages, may be supplied to the pixel. The second transistor T2 may be turned on by the first gate signal GW. The turned-on second transistor T2 may be configured to transmit the data signal Vdata from the data line DL to the first gate of the first transistor T1. Consequently, the threshold voltage (Vth) of the first transistor T1 and a voltage corresponding to the data signal Vdata may be charged into the first capacitor C1.

[0146] During a fourth period P4, a second gate signal GI of a gate-on voltage may be supplied to the second gate line GIL, and subsequently, a fifth gate signal EMB of a gate-on voltage may be supplied to the fifth gate line EMBL. A first gate signal GW, a third gate signal GR, and a fourth gate signal EM of a gate-off voltage may be supplied to the pixel. The fourth transistor T4 may be turned on by the second gate signal GI, and the first initialization voltage Vint1 may be transmitted to the pixel electrode of the organic light emitting diode OLED via the turned-on fourth transistor T4. Subsequently, the sixth transistor T6 may be turned on by the fifth gate signal EMB, and the second node N2 and the third node N3 may share charge via the turned-on sixth transistor T6 and the fourth transistor T4.

[0147] During the first emission period EP1, a fourth gate signal EM of a gate-on voltage may be supplied to the fourth gate line EML, and a fifth gate signal EMB of a gate-on voltage may be supplied to the fifth gate line EMBL. The first gate signal GW, the second gate signal GI, and the third gate signal GR may be gate-off voltages. The fifth transistor T5 may be turned on by the fourth gate signal EM, the first transistor T1 may output a driving current corresponding to the data signal Vdata stored in the first capacitor C1, and the driving current may flow through the organic light emitting diode OLED via the sixth transistor T6 turned on by the fifth gate signal EMB. The organic light emitting diode OLED may emit light having a brightness corresponding to the magnitude of the driving current.

[0148] During the fifth period P5, the second gate signal GI of the gate-on voltage may be supplied to the second gate line GIL, and the fifth gate signal EMB of the gate-on voltage may be supplied to the fifth gate line EMBL. The first gate signal GW, the third gate signal GR, and the fourth gate signal EM of the gate-off voltage may be supplied to the pixel. The sixth transistor T6 may be turned on by the fifth gate signal EMB, and the fourth transistor T4 may be turned on by the second gate signal GI. The second node N2 and the third node N3 may be set to the second initialization voltage Vint2 by the turned-on sixth transistor T6 and the fourth transistor T4.

[0149] During the sixth period P6, the second gate signal GI of the gate-on voltage may be supplied to the second gate line GIL, and the fifth gate signal EMB of the gate-on voltage may be supplied to the fifth gate line EMBL. The first gate signal GW, the third gate signal GR, and the fourth gate signal EM of the gate-off voltage may be supplied to the pixel. The sixth transistor T6 may be turned on by the fifth gate signal EMB, and the fourth transistor T4 may be turned on by the second gate signal GI. The second node N2 and the third node N3 may be set to the second initialization voltage Vint2 by the turned-on sixth transistor T6 and the fourth transistor T4.

[0150] In accordance with Figure 8 In the pixel PX of the embodiment shown in , at the start of the second emission period EP2, the voltage of the second terminal of the first transistor T1 may be the second initialization voltage Vint2 of the third node N3 set in the sixth period P6. Since the voltage level of the second initialization voltage Vint2 may be higher than the voltage level of the first initialization voltage Vint1, the voltage difference between the voltage of the second terminal of the first transistor T1 at the start of the first emission period EP1 and the voltage of the second terminal of the first transistor T1 at the start of the second emission period EP2 may be reduced, so that the brightness difference between the brightness of the display device in the first emission period EP1 and the brightness of the display device in the second emission period EP2 may be reduced. In addition, during the second scan period SS, power consumption can be reduced without a voltage change of the fifth gate signal EMB.

[0151] Figure 8 The embodiment shown in FIG. 5 is an example in which the second initialization voltage Vint2 may be supplied to the pixel PX at a start time point of the second scan period SS (ie, at a start time point of the fifth period P5 ).

[0152] Figures 9 to 11 is a schematic diagram for describing an embodiment of the present invention. Figure 4 A view of the signal of the pixel operation shown in FIG; Figures 9 to 11 In the Figure 8 The periods and signals described herein are described, and redundant descriptions thereof will be omitted.

[0153] Except for the supply time point of the second initialization voltage Vint2, Figure 9 The signals shown in Figure 8 The signals shown in are substantially the same or similar.

[0154] Reference Figure 9The power supply circuit 17 can supply the initialization voltage Vint of the first initialization voltage Vint1 during the first non-emission period NEP1 of the first scanning period AS, and can supply the initialization voltage Vint of the second initialization voltage Vint2 during the first emission period EP1 of the first scanning period AS and the second scanning period SS.

[0155] Figure 9 The embodiment shown in is an example in which the second initialization voltage Vint2 may be supplied to the pixel PX before the second scanning period SS starts (ie, before the fifth period P5 starts), and the second initialization voltage Vint2 may be supplied to the pixel PX from any time point of the first emission period EP1. Figure 9 In this embodiment, the second initialization voltage Vint2 may be supplied to the pixel PX starting from a start time point of the first emission period EP1.

[0156] In addition to the voltage level of the fourth gate voltage EM, Figure 10 The signals shown in Figure 8 The signals shown in are substantially the same or similar.

[0157] Reference Figure 10 The gate drive circuit 13 may output a fourth gate voltage EM, which is a gate-off voltage, during the first period P1, the third period P3, and the fourth period P4 of the first scanning period AS, and may output a fourth gate voltage EM, which is a gate-on voltage, during the remaining periods of the first scanning period AS and the second scanning period SS. The gate drive circuit 13 may output a fifth gate voltage EMB, which is a gate-on voltage, during the first emission period EP1 of the first scanning period AS and the second scanning period SS. In the second scanning period SS, the fourth gate signal EM, which is a gate-on voltage, may be supplied to the fourth gate line EML, and the fifth gate signal EMB, which is a gate-on voltage, may be supplied to the fifth gate line EMBL.

[0158] The power supply circuit 17 may output a first initialization voltage Vint1 during the first scan period AS, and may output a second initialization voltage Vint2 during the second scan period SS.

[0159] During the fifth and sixth periods P5 and P6, the second gate signal GI of the gate-on voltage may be supplied to the second gate line GIL, the fourth gate signal EM of the gate-on voltage may be supplied to the fourth gate line EML, and the fifth gate signal EMB of the gate-on voltage may be supplied to the fifth gate line EMBL. The first gate signal GW and the third gate signal GR of the gate-off voltage may be supplied to the pixel. The fifth transistor T5 may be turned on by the fourth gate signal EM, the sixth transistor T6 may be turned on by the fifth gate signal EMB, and the fourth transistor T4 may be turned on by the second gate signal GI. The second node N2 and the third node N3 may be set to the second initialization voltage Vint2 by the turned-on sixth transistor T6 and the fourth transistor T4.

[0160] In accordance with Figure 10 In the display device of the embodiment shown in , the gate driving circuit 13 can supply the fourth gate signal EM and the fifth gate signal EMB with a constant gate-on voltage without voltage level variation during the second scanning period SS, thereby reducing power consumption.

[0161] In addition to the voltage level of the fourth gate voltage EM, Figure 11 The signals shown in Figure 9 The signals shown in are substantially the same or similar.

[0162] Reference Figure 11 The gate driving circuit 13 may output the fourth gate voltage EM, which is a gate-off voltage, during the first period P1, the third period P3, and the fourth period P4 of the first scanning period AS, and may output the fourth gate voltage EM, which is a gate-on voltage, during the remaining periods of the first scanning period AS and the second scanning period SS. The gate driving circuit 13 may output the fifth gate voltage EMB, which is a gate-on voltage, in the first emission period EP1 of the first scanning period AS and the second scanning period SS.

[0163] The power supply circuit 17 may supply the initialization voltage Vint of the first initialization voltage Vint1 in the first non-emission period NEP1 of the first scan period AS, and may supply the initialization voltage Vint of the second initialization voltage Vint2 during the first emission period EP1 of the first scan period AS and the second scan period SS.

[0164] Figures 12 to 15 is a schematic diagram for describing an embodiment of the present invention. Figure 4 A signal view of the pixel operation is shown in FIG.

[0165] exist Figures 12 to 15 In the Figures 8 to 12 The periods and signals described herein are described, and redundant descriptions thereof will be omitted.

[0166] In addition to the initialization voltage Vint for each pixel, Figure 12 The signals shown in Figure 8 The signals shown in are substantially the same or similar.

[0167] The plurality of pixels PX arranged in the display area DA may include a first pixel PX1 emitting light of a first color, a second pixel PX2 emitting light of a second color, and a third pixel PX3 emitting light of a third color. For example, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be repeatedly arranged according to certain patterns in the x-direction and the y-direction. Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include Figure 4 The pixel circuit PC shown in FIG. 1 and the organic light emitting diode OLED as a display element electrically connected to the pixel circuit PC.

[0168] In an embodiment, taking into account the emission characteristics of the first pixel PX1, the second pixel PX2, and the third pixel PX3, different second initialization voltages Vint_R, Vint_G, and Vint_B may be supplied to the first pixel PX1, the second pixel PX2, and the third pixel PX3, respectively. For example, the pixel circuit PC of the first pixel PX1 may be electrically connected to the first initialization voltage line, the pixel circuit PC of the second pixel PX2 may be electrically connected to the second initialization voltage line, and the pixel circuit PC of the third pixel PX3 may be electrically connected to the third initialization voltage line. Figure 12 As shown in , starting from the start time point of the second scan period SS (for example, the start time point of the fifth period P5), the 2-1st initialization voltage Vint2R can be supplied to the first initialization voltage line, the 2-2nd initialization voltage Vint2G can be supplied to the second initialization voltage line, and the 2-3rd initialization voltage Vint2B can be supplied to the third initialization voltage line.

[0169] In addition to the supply time point of the initialization voltage Vint for each pixel, Figure 13 The signals shown in Figure 12 The signals shown in are substantially the same or similar. Figure 13 , starting from the start time point of the first emission period EP1, the 2-1st initialization voltage Vint2R may be supplied to the first initialization voltage line, the 2-2nd initialization voltage Vint2G may be supplied to the second initialization voltage line, and the 2-3rd initialization voltage Vint2B may be supplied to the third initialization voltage line.

[0170] In addition to the voltage level of the fourth gate voltage EM, Figure 14 The signals shown in Figure 12 The signals shown in are substantially the same or similar. Figure 14 The gate drive circuit 13 may output a fourth gate voltage EM, which is a gate-off voltage, during the first period P1, the third period P3, and the fourth period P4 of the first scanning period AS, and may output a fourth gate voltage EM, which is a gate-on voltage, during the remaining periods of the first scanning period AS and the second scanning period SS. The gate drive circuit 13 may output a fifth gate voltage EMB, which is a gate-on voltage, during the first emission period EP1 of the first scanning period AS and the second scanning period SS. In the second scanning period SS, the fourth gate signal EM, which is a gate-on voltage, may be supplied to the fourth gate line EML, and the fifth gate signal EMB, which is a gate-on voltage, may be supplied to the fifth gate line EMBL.

[0171] Starting from the start time point of the second scan period SS (ie, the start time point of the fifth period P5), the 2-1st initialization voltage Vint2R can be supplied to the first initialization voltage line, the 2-2nd initialization voltage Vint2G can be supplied to the second initialization voltage line, and the 2-3rd initialization voltage Vint2B can be supplied to the third initialization voltage line.

[0172] In addition to the supply timing of the initialization voltage Vint for each pixel, Figure 15 The signals shown in Figure 14 The signals shown in are substantially the same or similar. Figure 15 , starting from the start time point of the first emission period EP1, the 2-1st initialization voltage Vint2R may be supplied to the first initialization voltage line, the 2-2nd initialization voltage Vint2G may be supplied to the second initialization voltage line, and the 2-3rd initialization voltage Vint2B may be supplied to the third initialization voltage line.

[0173] exist Figures 12 to 15 In the embodiment shown in , a different second initialization voltage may be supplied to each of the first pixel PX1, the second pixel PX2, and the third pixel PX3, but embodiments of the inventive concept are not limited thereto. In an embodiment, the second initialization voltage supplied to at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be different from the second initialization voltage supplied to the remaining pixels. For example, the same second initialization voltage may be supplied to the second pixel PX2 and the third pixel PX3, and the second initialization voltage supplied to the first pixel PX1 may be different from the second initialization voltage supplied to the second pixel PX2 and the third pixel PX3.

[0174] Figure 16 It shows that according to Figures 8 to 15FIG. 1 is a diagram showing the brightness of a display device of an embodiment of the present invention. Figure 16 As shown in , the brightness of the display device in the first emission period EP1 of the first scanning period AS and the brightness of the display device in the second emission period EP2 of the second scanning period SS may be approximately similar.

[0175] Figure 17 is a view for describing an output of an initialization voltage according to an embodiment.

[0176] Reference Figure 17 , the display device 1 may include a data enable (DE) counter 191 , a scan period determination part 193 , a first voltage output part 195 , and a second voltage output part 197 .

[0177] The DE counter 191 can generate a data enable signal ( Figure 2 The first gate signal GW may be sequentially applied to the first gate line GWL from the first row (pixel line) to the last row in the third period P3 of each frame, and the data signal Vdata may be supplied to the pixel PX in response to the data enable signal DE.

[0178] The scanning period determining unit 193 can determine the first scanning period AS and the second scanning period SS based on the count value of the DE counter 191. The scanning period determining unit 193 can output a control signal including information about the change time point of the initialization voltage based on the frame rate of the display device and the count value of the data enable signal DE. In an embodiment, the control signal PCS output by the controller 19 may include information about the change time point of the initialization voltage. The change time point of the initialization voltage can be set to any time point in the period from the fourth period P4 of the first scanning period AS to the start time point of the second scanning period SS. For example, the change time point of the initialization voltage can be the start time point of the second scanning period SS or the start time point of the fifth period P5. As another example, the change time point of the initialization voltage can be before the start time point of the second scanning period SS or the start time point of the fifth period P5. For example, the change time point of the initialization voltage can be the start time point of the first emission period EP1 of the first scanning period AS.

[0179] The first voltage output section 195 may output the first initialization voltage Vint1, and the second voltage output section 197 may output the second initialization voltage Vint2 according to the control signal of the scan period determination section 193. In an embodiment, the first voltage output section 195 and the second voltage output section 197 may be separately implemented in different integrated circuits, or may be implemented together in the same integrated circuit.

[0180] exist Figure 17In the embodiment shown in , the DE counter 191 and the scan period determination section 193 may be included in the controller 19, and the first voltage output section 195 and the second voltage output section 197 may be included in the power supply circuit 17. In an embodiment, the DE counter 191 and the scan period determination section 193 may also be included in the power supply circuit 17.

[0181] Figure 18 is a schematic cross-sectional view showing the structure of a display element according to an embodiment. Figures 19a to 21 is a schematic cross-sectional view showing the structure of a display element according to an embodiment.

[0182] Reference Figure 18 The organic light emitting diode OLED as a display element according to the embodiment may include a pixel electrode 211 , an opposing electrode 215 , and an intermediate layer 213 between the pixel electrode (first electrode, anode) 211 and the opposing electrode (second electrode, cathode) 215 .

[0183] The pixel electrode 211 may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO), or a combination thereof. The pixel electrode 211 may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a combination thereof. For example, the pixel electrode 211 may have a three-layer structure of ITO / Ag / ITO.

[0184] The counter electrode 215 may be disposed on the intermediate layer 213. The counter electrode 215 may include a metal, alloy, conductive compound, or any combination thereof having a low work function. For example, the counter electrode 215 may include lithium (Li), Ag, Mg, Al, Al-Li, calcium (Ca), Mg-In, Mg-Ag, ytterbium (Yb), Ag-Yb, ITO, IZO, or any combination thereof. The counter electrode 215 may be a transmissive electrode, a semi-transmissive electrode, a reflective electrode, or any combination thereof.

[0185] The intermediate layer 213 may include a polymer or a low molecular weight organic material that emits light of a specific color. In addition to various organic materials, the intermediate layer 213 may also include a metal-containing compound such as an organometallic compound, an inorganic material such as a quantum dot, or a combination thereof.

[0186] In embodiments, the intermediate layer 213 may include an emissive layer and first and second functional layers below and above the emissive layer, respectively. The first functional layer may include, for example, a hole transport layer (HTL) or an HTL and a hole injection layer (HIL). The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first or second functional layer may be omitted. The first and second functional layers may be integrated with each other to correspond to the organic light emitting diode (OLED) included in the display area DA.

[0187] In one embodiment, the intermediate layer 213 may include two or more emitters sequentially stacked one above the other between the pixel electrode 211 and the counter electrode 215, and a charge generation layer (CGL) disposed between the two emitters. When the intermediate layer 213 includes the emitter and the charge generation layer (CGL), the organic light-emitting diode (OLED) may be a tandem light-emitting device. The organic light-emitting diode (OLED) may have a stacked structure of emitters, thereby enhancing color purity and emission efficiency.

[0188] An emissive portion may include an emissive layer and a first functional layer and a second functional layer disposed below and above the emissive layer, respectively. The charge generation layer (CGL) may include a negative charge generation layer and a positive charge generation layer. The use of the negative and positive charge generation layers allows for a tandem light-emitting device (OLED) with multiple emissive layers, further improving the emission efficiency.

[0189] The negative charge generation layer may be an n-type charge generation layer (CGL). The negative charge generation layer may supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. The positive charge generation layer may be a p-type charge generation layer (CGL). The positive charge generation layer may supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material.

[0190] In an embodiment, Figure 19a As shown in , the organic light emitting diode OLED may include a first emission unit EU1 including a first emission layer EML1 and a second emission unit EU2 including a second emission layer EML2, which may be sequentially stacked on each other. The charge generation layer CGL may be provided between the first emission unit EU1 and the second emission unit EU2. For example, the organic light emitting diode OLED may include a pixel electrode 211, a first emission layer EML1, a charge generation layer CGL, a second emission layer EML2, and a counter electrode 215. A first functional layer and a second functional layer may be included below and above the first emission layer EML1, respectively. A first functional layer and a second functional layer may be included below and above the second emission layer EML2, respectively. The first emission layer EML1 may be a blue emission layer, and the second emission layer EML2 may be a yellow emission layer.

[0191] In an embodiment, Figure 19b As shown in , the organic light emitting diode OLED may include a first emission unit EU1 and a third emission unit EU3 including a first emission layer EML1, and a second emission unit EU2 including a second emission layer EML2. The first charge generation layer CGL1 may be arranged between the first emission unit EU1 and the second emission unit EU2, and the second charge generation layer CGL2 may be arranged between the second emission unit EU2 and the third emission unit EU3. For example, the organic light emitting diode OLED may include a pixel electrode 211, a first emission layer EML1, a first charge generation layer CGL1, a second emission layer EML2, a second charge generation layer CGL2, a first emission layer EML1, and a counter electrode 215, which may be stacked one on top of the other. A first functional layer and a second functional layer may be included below and above the first emission layer EML1, respectively. A first functional layer and a second functional layer may be included below and above the second emission layer EML2, respectively. The first emission layer EML1 may be a blue emission layer, and the second emission layer EML2 may be a yellow emission layer.

[0192] In an embodiment, in addition to the second emission layer EML2, the organic light emitting diode OLED may further include a third emission layer EML3 and / or a fourth emission layer EML4 included in the second emission unit EU2 and which may contact (e.g., directly contact) the second emission layer EML2 below and / or above the second emission layer EML2. Here, direct contact may mean that no other layer is provided between the second emission layer EML2 and the third emission layer EML3 and / or between the second emission layer EML2 and the fourth emission layer EML4. The third emission layer EML3 may be a red emission layer, and the fourth emission layer EML4 may be a green emission layer.

[0193] For example, Figure 19c As shown in , the organic light emitting diode OLED may include a pixel electrode 211, a first emission layer EML1, a first charge generation layer CGL1, a third emission layer EML3, a second emission layer EML2, a second charge generation layer CGL2, a first emission layer EML1, and an opposing electrode 215, which may be sequentially stacked on one another. Figure 19d In another example shown in , the organic light emitting diode OLED may include a pixel electrode 211, a first emission layer EML1, a first charge generation layer CGL1, a third emission layer EML3, a second emission layer EML2, a fourth emission layer EML4, a second charge generation layer CGL2, a first emission layer EML1 and a counter electrode 215, which may be stacked sequentially on one another.

[0194] Figure 20a It shows Figure 19c A schematic cross-sectional view of an example of an organic light-emitting diode, Figure 20b It shows Figure 19d Schematic cross-sectional view of an example of an organic light emitting diode.

[0195] Reference Figure 20a The organic light emitting diode OLED may include a first emission unit EU1, a second emission unit EU2, and a third emission unit EU3 that may be sequentially stacked one on top of the other. A first charge generation layer CGL1 may be disposed between the first emission unit EU1 and the second emission unit EU2, and a second charge generation layer CGL2 may be disposed between the second emission unit EU2 and the third emission unit EU3. Each of the first charge generation layer CGL1 and the second charge generation layer CGL2 may include a negative charge generation layer nCGL and a positive charge generation layer pCGL.

[0196] The first emission unit EU1 may include a blue emission layer BEML. The first emission unit EU1 may further include a HIL and an HTL between the pixel electrode 211 and the blue emission layer BEML. In an embodiment, a p-doped layer may further be included between the HIL and the HTL. The p-doped layer may be formed by doping the HIL with a p-type dopant material. In an embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may further be included between the blue emission layer BEML and the HTL. The blue light auxiliary layer may increase the luminous efficiency of the blue emission layer BEML. The blue light auxiliary layer may adjust the hole charge balance to increase the luminous efficiency of the blue emission layer BEML. The electron blocking layer may prevent electrons from being injected into the HTL. The buffer layer may compensate for the resonance distance according to the wavelength of light emitted from the emission layer.

[0197] The second emission unit EU2 may include a yellow emission layer YEML and a red emission layer REML below and in contact with (e.g., directly in contact with) the yellow emission layer YEML. The second emission unit EU2 may also include an HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red emission layer REML, and may also include an electron transport layer (ETL) between the yellow emission layer YEML and the second charge generation layer CGL2.

[0198] The third emission unit EU3 may include a blue emission layer BEML. The third emission unit EU3 may also include an HTL between the positive charge generation layer pCGL of the second charge generation layer CGL2 and the blue emission layer BEML. The third emission unit EU3 may also include an electron transport layer (ETL) and an electron injection layer (EIL) between the blue emission layer BEML and the counter electrode 215. The ETL may be a single layer or a multilayer. In an embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may be further included between the blue emission layer BEML and the HTL. At least one of a hole blocking layer and a buffer layer may also be included between the blue emission layer BEML and the ETL. The hole blocking layer may prevent holes from being injected into the ETL.

[0199] Figure 20b The organic light emitting diode OLED shown in Figure 20a The difference between the organic light emitting diode OLED shown in FIG is that the stacking structure of the second emission unit EU2 is different from that of the organic light emitting diode OLED shown in FIG. Figure 20a The stacking structure of the organic light emitting diode OLED shown in FIG. Figure 20b The second emission unit EU2 may include a yellow emission layer YEML, a red emission layer REML below the yellow emission layer YEML and in contact with (e.g., directly in contact with) the yellow emission layer YEML, and a green emission layer GEML above the yellow emission layer YEML and in contact with (e.g., directly in contact with) the yellow emission layer YEML. The second emission unit EU2 may also include an HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red emission layer REML, and may also include an ETL between the green emission layer GEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0200] Figure 21 is a schematic cross-sectional view showing the structure of a pixel of the display device according to the embodiment.

[0201] Reference Figure 21 , the display device may include pixels. The plurality of pixels may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a pixel electrode 211, an opposing electrode 215, and an intermediate layer 213. In an embodiment, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel. Here, the pixel may include an organic light emitting diode OLED as a display element, and the organic light emitting diode OLED of each pixel may be electrically connected to the pixel circuit.

[0202] The pixel electrode 211 may be independently provided in each of the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 .

[0203] The intermediate layer 213 of the organic light emitting diode OLED of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a first emission unit EU1 and a second emission unit EU2 that may be sequentially stacked on each other, and a charge generation layer CGL between the first emission unit EU1 and the second emission unit EU2. The charge generation layer CGL may include a negative charge generation layer nCGL and a positive charge generation layer pCGL. The charge generation layer CGL may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0204] The first emission part EU1 of the first pixel PX1 may include a HIL, an HTL, a red emission layer REML, and an ETL, which may be sequentially stacked on one another on the pixel electrode 211. The first emission part EU1 of the second pixel PX2 may include a HIL, an HTL, a green emission layer GEML, and an ETL, which may be sequentially stacked on one another on the pixel electrode 211. The first emission part EU1 of the third pixel PX3 may include a HIL, an HTL, a blue emission layer BEML, and an ETL, which may be sequentially stacked on one another on the pixel electrode 211. Each of the HIL, HTL, and ETL of the first emission part EU1 may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0205] The second emission unit EU2 of the first pixel PX1 may include an HTL, an auxiliary layer AXL, a red emission layer REML, and an ETL that may be sequentially stacked on the charge generation layer CGL. The second emission unit EU2 of the second pixel PX2 may include an HTL, a green emission layer GEML, and an ETL that may be sequentially stacked on the CGL. The second emission unit EU2 of the third pixel PX3 may include an HTL, a blue emission layer BEML, and an ETL that may be sequentially stacked on the charge generation layer CGL. Each of the ETL and the HTL of the second emission unit EU1 may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3. In an embodiment, at least one of a hole blocking layer and a buffer layer may be further included between the emission layer and the ETL in the second emission unit EU2 of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0206] The thickness H1 of the red emission layer REML, the thickness H2 of the green emission layer GEML, and the thickness H3 of the blue emission layer BEML can be determined according to the resonance distance. The auxiliary layer AXL is an additional layer for matching the resonance distance and can include a resonance auxiliary material. For example, the auxiliary layer AXL and the HTL can include the same material.

[0207] exist Figure 21In the embodiment, the auxiliary layer AXL is provided only in the first pixel PX1, but the disclosed embodiments are not limited thereto. For example, the auxiliary layer AXL may be provided in at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3 to match the resonance distances between the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0208] The display device may further include a capping layer 217 disposed outside the counter electrode 215. The capping layer 217 may enhance emission efficiency based on the principle of constructive interference. Thus, the light extraction efficiency of the organic light emitting diode OLED may be improved, and thus the emission efficiency of the organic light emitting diode OLED may be enhanced.

[0209] Embodiments have been disclosed herein, and although terms are employed, they are used and interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to those skilled in the art, features, characteristics, and / or elements described in connection with an embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically stated. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the disclosure as set forth in the appended claims.

Claims

1. A display device, comprising: a plurality of pixels, each pixel of the plurality of pixels comprising: light-emitting diodes; a first transistor electrically connected to a driving voltage line and the light emitting diode; a second transistor electrically connected to the first transistor and the light emitting diode; and A third transistor is electrically connected to the light emitting diode and an initialization voltage line, wherein Each pixel is configured to operate in a first scanning period and a second scanning period during one frame, the first scanning period including a writing period for receiving a data signal and a first emission period for emitting light having a brightness corresponding to the data signal, and the second scanning period including a second emission period for holding the data signal and emitting light having a brightness corresponding to the held data signal, The gate of the second transistor is configured to receive a first gate signal of a gate-on voltage during the second scanning period, The gate of the third transistor is configured to receive a second gate signal of a gate-on voltage in a first period before the second emission period of the second scanning period, and The initialization voltage line is configured to receive a first initialization voltage during the first scan period, and is configured to receive a second initialization voltage different from the first initialization voltage starting from a start time point of the first period of the second scan period.

2. The display device according to claim 1, wherein In a second period between the writing period and the first emission period, the gate of the second transistor is configured to receive another first gate signal of a gate-on voltage, and the gate of the third transistor is configured to receive another second gate signal of a gate-on voltage.

3. The display device according to claim 2, wherein The pixel further includes a fourth transistor electrically connected to a data line and a gate of the first transistor, and The gate of the fourth transistor is configured to receive a third gate signal of a gate-on voltage in the writing period.

4. The display device according to claim 3, wherein The pixel further comprises: a fifth transistor electrically connected to the driving voltage line and the first transistor; and a sixth transistor electrically connected to the gate of the first transistor and a reference voltage line, In which, in a third period before the writing period of the first scanning period, the gate of the second transistor is configured to receive a first gate signal of a gate-off voltage, the gate of the fifth transistor is configured to receive a fourth gate signal of a gate-on voltage, and the gate of the sixth transistor is configured to receive a fifth gate signal of a gate-on voltage.

5. The display device according to claim 4, wherein In the second scanning period, the gate of the fifth transistor is configured to receive another fourth gate signal of a gate-on voltage during the second emission period, and the gate of the fifth transistor is configured to receive a fourth gate signal of a gate-off voltage during a period other than the second emission period. The display device according to claim 5 , wherein: The plurality of pixels include a first pixel emitting light of a first color and a second pixel emitting light of a second color, and A second initialization voltage supplied to the first pixel and a second initialization voltage supplied to the second pixel are different from each other.

7. The display device according to claim 4, wherein The gate of the fifth transistor is configured to receive a fourth gate signal of a gate-on voltage during the second scan period.

8. The display device according to claim 7, wherein The plurality of pixels include a first pixel emitting light of a first color and a second pixel emitting light of a second color, A second initialization voltage supplied to the first pixel and a second initialization voltage supplied to the second pixel are different from each other.

9. The display device according to claim 1 further comprises a power supply circuit, which is configured to output the first initialization voltage to the plurality of pixels during the first scanning period, and is configured to output the second initialization voltage starting from a starting time point of the first period of the second scanning period.

10. A display device, comprising: a plurality of pixels, each pixel of the plurality of pixels comprising: light-emitting diodes; a first transistor electrically connected to a driving voltage line and the light emitting diode; a second transistor electrically connected to the first transistor and the light emitting diode; and A third transistor is electrically connected to the light emitting diode and an initialization voltage line, wherein Each pixel is configured to operate in a first scanning period and a second scanning period during one frame, the first scanning period including a writing period for receiving a data signal and a first emission period for emitting light having a brightness corresponding to the data signal, and the second scanning period including a second emission period for holding the data signal and emitting light having a brightness corresponding to the held data signal, The gate of the second transistor is configured to receive a first gate signal of a gate-on voltage during the second scan period, and The initialization voltage line is configured to receive a first initialization voltage until before the first emission period of the first scan period, and receive a second initialization voltage different from the first initialization voltage during the first emission period and the second scan period of the first scan period.

11. The display device according to claim 10, wherein In a first period between the writing period and the first emission period, the gate of the second transistor is configured to receive another first gate signal of a gate-on voltage, and the gate of the third transistor is configured to receive a second gate signal of a gate-on voltage.

12. The display device according to claim 11, wherein The pixel further includes a fourth transistor electrically connected to a data line and a gate of the first transistor, and the gate of the fourth transistor is configured to receive a third gate signal of a gate-on voltage in the writing period.

13. The display device according to claim 12, wherein The pixel further comprises: a fifth transistor electrically connected to the driving voltage line and the first transistor; and a sixth transistor electrically connected to the gate of the first transistor and a reference voltage line, In which, in a second period before the writing period of the first scanning period, the gate of the second transistor is configured to receive a first gate signal of a gate-off voltage, the gate of the fifth transistor is configured to receive a fourth gate signal of a gate-on voltage, and the gate of the sixth transistor is configured to receive a fifth gate signal of a gate-on voltage.

14. The display device according to claim 13, wherein In the second scanning period, the gate of the fifth transistor is configured to receive a fourth gate signal of a gate-on voltage during the second emission period and to receive a fourth gate signal of a gate-off voltage during a period other than the second emission period.

15. The display device according to claim 14, wherein The plurality of pixels include a first pixel emitting light of a first color and a second pixel emitting light of a second color, and A second initialization voltage supplied to the first pixel and a second initialization voltage supplied to the second pixel are different from each other.

16. The display device according to claim 13, wherein The gate of the fifth transistor is configured to receive a fourth gate signal of a gate-on voltage during the second scan period.

17. The display device according to claim 16, wherein The plurality of pixels include a first pixel emitting light of a first color and a second pixel emitting light of a second color, and A second initialization voltage supplied to the first pixel and a second initialization voltage supplied to the second pixel are different from each other.

18. The display device according to claim 10 further comprises a power supply circuit, which is configured to output the first initialization voltage to the multiple pixels until before the first emission period of the first scanning period, and to output the second initialization voltage during the first emission period of the first scanning period and the second scanning period.

19. A method for driving a display device comprising a plurality of pixels, each of the plurality of pixels comprising: light-emitting diodes; a first transistor electrically connected to a driving voltage line and the light emitting diode; a second transistor electrically connected to the first transistor and the light emitting diode; as well as A third transistor is electrically connected to the light emitting diode and an initialization voltage line, wherein Each pixel is configured to operate in a first scanning period and a second scanning period during one frame, the first scanning period including a writing period for receiving a data signal and a first emission period for emitting light having a brightness corresponding to the data signal, and the second scanning period including a second emission period for holding the data signal and emitting light having a brightness corresponding to the held data signal, In each of the pixels, In a first period between the writing period and the first emission period of the first scanning period, the gate of the second transistor receives a first gate signal of a gate-on voltage, and the gate of the third transistor receives a second gate signal of a gate-on voltage, The gate of the second transistor receives another first gate signal of a gate-on voltage during the second scanning period, In a second period before the second emission period in the second scanning period, the gate of the third transistor receives a second gate signal of a gate-on voltage, and The initialization voltage line receives a first initialization voltage during the first period of the first scan period, and receives a second initialization voltage different from the first initialization voltage from a start time point of at least the second period of the second scan period.

20. The method for driving a display device according to claim 19, wherein: Each pixel further includes a fifth transistor electrically connected to the driving voltage line and the first transistor, and In each of the pixels, in the second scanning period, the gate of the fifth transistor receives a third gate signal of a gate-on voltage during the second emission period, and the gate of the fifth transistor receives a third gate signal of a gate-off voltage during a period other than the second emission period.

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