Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes: an insulating layer including a first layer having a first filler and a second layer disposed on the first layer; a pad portion disposed on the second layer of the insulating layer; and a metal layer disposed on the pad portion, in which the pad portion includes a first portion overlapping the first filler of the first layer in a horizontal direction, and a second portion not overlapping the first filler of the first layer in the horizontal direction.

Description

Technical Field

[0001] Embodiments relate to a circuit board and a semiconductor package including the circuit board. Background Art

[0002] As the performance of electronic and electrical products continues to improve, technologies for arranging more semiconductor devices on a limited-size semiconductor package substrate are being proposed and researched. However, since typical semiconductor packaging is based on mounting a single semiconductor device, there are limitations in achieving the desired performance.

[0003] Therefore, a semiconductor package has recently been provided that uses multiple circuit boards to mount multiple semiconductor devices. This semiconductor package has a structure in which multiple semiconductor devices are interconnected horizontally and / or vertically on the circuit boards. Consequently, this semiconductor package offers the advantages of efficiently utilizing the mounting area of ​​the semiconductor devices and transmitting high-speed signals through short signal transmission paths between the semiconductor devices.

[0004] Furthermore, semiconductor packaging used in products providing the Internet of Things (IoT), autonomous vehicles, and high-performance servers is expanding its concept to include semiconductor chips. This is because: with the trend toward higher integration, the number of semiconductor devices and / or the size of each semiconductor device are increasing, but due to mask limitations, etc., the functional parts of semiconductor devices are being separated into individual chips. Therefore, the concept is expanding to include semiconductor chips.

[0005] Therefore, mutual communication between semiconductor devices and / or semiconductor chips has become important, and thus, there has been a trend to arrange an interposer between a circuit board of a semiconductor package and the semiconductor device.

[0006] The interposer can be used as a redistribution layer, which gradually increases the width or depth of the circuit pattern from the semiconductor device to the semiconductor package to facilitate mutual communication between semiconductor devices and / or semiconductor chips, or interconnect the semiconductor device with a semiconductor package circuit board, thereby smoothly transmitting electrical signals between the semiconductor device and the semiconductor package circuit board having a relatively large circuit pattern (compared to the circuit pattern of the semiconductor device).

[0007] Meanwhile, as the pitch of semiconductor device terminals becomes increasingly finer, the electrode portion provided on the package substrate and / or interposer has a pad portion disposed on the uppermost side and protruding above the upper surface of the insulating layer. The pad portion may be an electrode electrically connected to the semiconductor device terminal.

[0008] The manufacturing process of the package substrate and / or the interposer may include etching the upper surface of the insulating layer so that the pad portion completely buried in the insulating layer protrudes above the insulating layer.

[0009] In this case, the insulating layer includes a reinforcing member such as a filler, and due to the reinforcing member provided within the insulating layer, the upper surface of the insulating layer after etching may have an uneven height. For example, the upper surface of the insulating layer can be etched using a dry method using plasma or a wet method using a chemical agent. The resin of the insulating layer can be removed by the dry method using plasma or the wet method using a chemical agent, but the reinforcing member containing SiO2 or TiO2 will not be removed. Therefore, when etching the upper surface of the insulating layer, at least a portion of the reinforcing member provided in the insulating layer may be exposed to the upper surface of the insulating layer or may be removed from the insulating layer.

[0010] Therefore, the upper surface of the insulating layer after etching includes a first region formed by the resin of the insulating layer removed by etching, a second region formed by the exposed reinforcing member, and a third region formed by the space in which the reinforcing member was removed. In this case, the insulating layer may have different heights in the first to third regions. Due to this height deviation, there may be a problem of increased deviation in the adhesion between the insulating layer and the pad portion, which may reduce the reliability of the adhesion between the insulating layer and the pad portion.

[0011] Furthermore, when the height of the upper surface of the insulating layer is uneven, a metal layer disposed on the pad portion may have height deviations, and this may cause problems such as the semiconductor device being unable to be stably positioned on the pad portion.

[0012] Furthermore, when the reinforcing member is exposed on the upper surface of the insulating layer after etching, the metal layer may come into contact with the reinforcing member of the insulating layer, thereby degrading the electrical properties of the metal layer. For example, the dielectric constant of the reinforcing member may be higher than that of the resin of the insulating layer, and due to the high dielectric constant of the reinforcing member, there is a problem of increased transmission loss of signals transmitted through the metal layer. Furthermore, the adhesion between the reinforcing member and the metal layer may be weaker than the adhesion between the reinforcing member and the resin of the insulating layer, resulting in a problem of reduced reliability of the adhesion between the metal layer and the insulating layer.

[0013] Therefore, a new method is needed that can improve the flatness of the insulating layer while improving the electrical characteristics of the electrode portion by preventing the reinforcement member from being exposed on the upper surface of the insulating layer after etching, and further improve the adhesion between the electrode portion and the insulating layer. Summary of the Invention

[0014] Technical issues

[0015] The embodiment provides a circuit board having improved flatness and a semiconductor package including the same.

[0016] Furthermore, the embodiment provides a circuit board capable of improving adhesion between an insulating layer and an electrode part, and a semiconductor package including the same.

[0017] Furthermore, the embodiment provides a circuit board capable of improving electrical characteristics of an electrode part and a semiconductor package including the same.

[0018] Furthermore, the embodiment provides a circuit board capable of minimizing height deviation of an electrode part and a semiconductor package including the same.

[0019] Furthermore, the embodiment provides a circuit board capable of solving the problem of significant warping in a specific direction and a semiconductor package including the same.

[0020] The technical problems to be solved by the proposed embodiments are not limited to the above-mentioned technical problems; rather, those skilled in the art to which the proposed embodiments pertain may clearly understand other technical problems not mentioned from the following description.

[0021] Technical Solution

[0022] According to an embodiment, a circuit board includes: an insulating layer, the insulating layer including a first layer having a first filler, and a second layer arranged on the first layer; a pad portion, the pad portion being arranged on the insulating layer; and a metal layer, the metal layer being arranged on the pad portion, wherein the pad portion includes a first portion overlapping with the first filler of the first layer of the insulating layer in a horizontal direction, and a second portion not overlapping with the first filler of the first layer in a horizontal direction.

[0023] Furthermore, the resin of the first layer and the resin of the second layer of the insulating layer include the same insulating material.

[0024] Furthermore, the resin of the first layer and the resin of the second layer of the insulating layer include different insulating materials.

[0025] Furthermore, the second layer of the insulating layer comprises a second filler.

[0026] Furthermore, the diameter of the first filler is the same as the diameter of the second filler.

[0027] Furthermore, the content of the first filler in the first layer of the insulating layer is greater than the content of the second filler in the second layer.

[0028] Furthermore, the diameter of the second filler is smaller than the diameter of the first filler.

[0029] Furthermore, the resin of each of the first layer and the second layer includes one of ABF (Ajinomoto laminated film), FR-4, BT (bismaleimide triazine), and PID (photo-imaging dielectric resin).

[0030] Furthermore, the pad portion is arranged in a recess provided at the upper surface of the insulating layer.

[0031] Furthermore, the recess has a through hole penetrating the second layer of the insulating layer, and the pad portion is arranged in the through hole.

[0032] Furthermore, the concave portion has a groove portion connected to the through hole and provided on the upper surface of the first layer of the insulating layer, and the pad portion is arranged within the through hole and the groove portion.

[0033] Furthermore, the second portion of the pad part overlaps the second layer of the insulating layer in a horizontal direction.

[0034] Furthermore, the second layer of the insulating layer has concavo-convex portions, and the metal layer has convex portions corresponding to the concavo-convex portions.

[0035] Furthermore, the curvature of the concavo-convex portion is different from the curvature of the first filler.

[0036] In addition, the circuit board also includes a protective layer arranged on the metal layer, and the second part of the pad portion includes: a first area overlapping with the second layer of the insulating layer in a horizontal direction; and a second area arranged on the first area and overlapping with the protective layer in a horizontal direction.

[0037] Furthermore, the protective layer has an opening that vertically overlaps the metal layer and penetrates the upper and lower surfaces of the protective layer.

[0038] Furthermore, a width of the opening in the horizontal direction is smaller than a width of at least one of the pad portion and the metal layer in the horizontal direction.

[0039] Furthermore, the second portion of the pad part includes a slope whose width increases toward the first portion.

[0040] In addition, the second portion includes a spacer portion provided between the slope surface of the second portion and the inner wall of the through hole of the second layer, and the metal layer is arranged in the spacer portion and in contact with the slope surface of the second portion and the inner wall of the through hole of the second layer.

[0041] The insulating layer includes a plurality of insulating layers stacked in a vertical direction, and an uppermost insulating layer among the plurality of insulating layers includes a first layer and a second layer, and the remaining insulating layers among the plurality of insulating layers except the uppermost insulating layer do not include the second layer.

[0042] In addition, the circuit board further includes a connecting member buried in the insulating layer.

[0043] At the same time, according to one embodiment, a semiconductor package includes the above-mentioned circuit board, a joint portion arranged on the metal layer of the circuit board, and a semiconductor device arranged on the joint portion, wherein the semiconductor device has a first terminal portion overlapping with the connecting member in the vertical direction; and a second terminal portion not overlapping with the connecting member in the vertical direction.

[0044] Beneficial effects

[0045] The embodiment can improve the flatness of a circuit board and a semiconductor package including the same, and can stably mount a semiconductor device.

[0046] Specifically, the circuit board of the embodiment and the semiconductor package including the circuit board include an insulating layer containing a filler, a pad portion arranged on the insulating layer, and a metal layer arranged on the pad portion. In addition, the pad portion includes a first portion that overlaps with the filler of the insulating layer in the horizontal direction, and a second portion that does not overlap with the filler of the insulating layer in the horizontal direction. At this time, the insulating layer includes a first layer with a reinforcing member and a second layer without a reinforcing member. In addition, the first portion of the pad portion overlaps with the first layer of the insulating layer in the horizontal direction, and the second portion overlaps with the second layer of the insulating layer in the horizontal direction. Therefore, the embodiment can prevent the reinforcing member from being arranged on the second layer, so that the height of the upper surface of the second layer can be uniform as a whole.

[0047] Furthermore, the embodiment can also improve adhesion between the metal layer disposed on the pad portion and the insulating layer.

[0048] That is, the upper surface of the insulating layer is positioned lower than the upper surface of the pad portion. In addition, the upper surface of the insulating layer is positioned higher than the lower surface of the pad portion. In other words, at least a portion of the pad portion is embedded in the insulating layer, and at least the remaining portion protrudes above the insulating layer. To this end, embodiments perform a process of reducing the thickness of the insulating layer by etching a localized area of ​​the insulating layer while the upper surface of the insulating layer is positioned at a height higher than the upper surface of the pad portion.

[0049] At this time, if a reinforcing member is provided throughout the entire area of ​​the insulating layer, the flatness of the upper surface of the insulating layer may be reduced during the process of etching the insulating layer to reduce its thickness. In other words, if the process of etching the insulating layer to reduce its thickness is performed while the reinforcing member is provided throughout the entire area of ​​the insulating layer, the reinforcing member provided in the insulating layer may be exposed on the upper side of the insulating layer. In addition, if the reinforcing member provided in the insulating layer is exposed on the upper side, the adhesion between the insulating layer and the metal layer described later may be reduced. For example, the adhesion between the reinforcing member and the metal layer may be weaker than the adhesion between the resin of the insulating layer and the metal layer. Due to this, the adhesion between the insulating layer and the metal layer may be reduced, and the metal layer may be peeled off from the insulating layer. In addition, when the metal layer contacts the reinforcing member, due to the relatively high dielectric constant of the reinforcing member, the electrical signal and / or power transmitted through the metal layer may be lost.

[0050] Furthermore, when a process of etching the insulating layer to reduce its thickness is performed while reinforcing members are provided throughout the entire insulating layer, at least some of the reinforcing members provided in the insulating layer may be removed, thereby potentially forming a recessed portion on the upper surface of the insulating layer. This recessed portion is the space created by the removal of the reinforcing members. In this case, the depth of the recessed portion may be greater than the depth of other portions of the upper surface of the insulating layer. Due to this, when a recessed portion exists on the upper surface of the insulating layer, the following problem may arise: the metal layer may not be able to completely fill the recessed portion, thereby potentially forming a gap between the insulating layer and the metal layer. Furthermore, when a recessed portion having a relatively large depth exists on the upper surface of the insulating layer, stress acting on the insulating layer may be concentrated on the recessed portion, which may reduce the physical and / or electrical reliability of the semiconductor package.

[0051] In contrast, the insulating layer of the embodiment includes a first layer and a second layer. Furthermore, the first layer of the insulating layer includes a resin and a reinforcing member, while the second layer does not include a reinforcing member but only includes the resin. Therefore, the embodiment can prevent the reinforcing member from being exposed on the upper surface of the insulating layer after etching, thereby making the height of the upper surface of the insulating layer uniform.

[0052] Therefore, the embodiment can improve the flatness of the circuit board and the semiconductor package including the circuit board. In addition, the metal layer arranged on the pad portion does not contact the reinforcing member, so the embodiment can improve the electrical characteristics of the metal layer while enhancing the adhesion between the metal layer and the insulating layer.

[0053] In addition, the embodiments can prevent stress from being concentrated at a specific location on the upper surface of the insulating layer by ensuring that the upper surface of the insulating layer has a uniform height. Further, the stress can be evenly distributed over the entire area, thereby improving the physical and electrical reliability of the semiconductor package.

[0054] Furthermore, the embodiment can prevent a bonding part disposed on the metal layer from penetrating into a gap between the metal layer and the insulating layer by enhancing adhesion between the metal layer and the insulating layer.

[0055] Therefore, the embodiment can suppress the formation of a relatively brittle intermetallic compound (IMC) between the bonding portion and the pad portion, thereby improving the physical and electrical reliability of the semiconductor package.

[0056] Furthermore, the embodiment can prevent the semiconductor package from being greatly warped in a specific direction by providing the first layer with the reinforcement member and the second layer without the reinforcement member as an insulating layer, thereby stably mounting the semiconductor device and further stably operating the semiconductor device.

[0057] Specifically, the circuit board and the semiconductor package including the circuit board may warp significantly in a specific direction. This may be due to the difference in thermal expansion coefficient between the insulating layer and the protective layer, the difference in thickness of each layer in the insulating layer, the difference in density of the electrode portion arranged on the surface of each layer of the insulating layer, and the difference in thickness of the electrode portion arranged on the surface of each layer of the insulating layer. At this time, the embodiment provides a second layer of the insulating layer without a reinforcement member on the uppermost side of the circuit board. The second layer of the insulating layer may have a thermal expansion coefficient matching function, which alleviates the difference in thermal expansion coefficient between different insulating layers, thereby preventing the circuit board from warping significantly in a specific direction. For example, in a state where the second layer is not provided on the insulating layer, the circuit board may warp downward at both ends. At this time, the second layer provided on the insulating layer can cause the two ends of the circuit board to warp upward, thereby ultimately allowing the circuit board to maintain a flat state without warping.

[0058] Furthermore, a concavo-convex portion is provided on the upper surface of the second layer of the insulating layer. This concavo-convex portion can be provided on the upper surface of the second layer during the process of etching the second layer of the insulating layer to reduce the thickness of the second layer. In this case, the embodiment forms the concavo-convex portion by etching the second layer of the insulating layer without the reinforcement member. Therefore, the reinforcement member is not exposed through the concavo-convex portion, thereby allowing the concavo-convex portion to have a uniform depth on the upper surface of the second layer. The concavo-convex portion contacts at least a portion of the metal layer arranged on the pad portion. As a result, the embodiment can further improve the adhesion between the insulating layer and the metal layer.

[0059] In this case, the concave-convex portion has a specific curvature. In this case, the curvature of the concave-convex portion is different from the curvature of the reinforcing member provided in the first layer of the insulating layer. Here, the different curvature may mean that the reinforcing member is not exposed upward through the concave-convex portion. Alternatively, the different curvature may also mean that: in the process of etching the insulating layer to reduce the thickness of the insulating layer, the reinforcing member is not removed from the insulating layer, and therefore, the concave-convex portion does not include a portion formed by removing the reinforcing member. Thus, the embodiment can improve the physical reliability and / or electrical reliability of the semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 is a cross-sectional view of a semiconductor package according to a first embodiment.

[0061] Figure 2 It shows Figure 1 A diagram of a semiconductor package, which includes a semiconductor device mounted on a circuit board.

[0062] Figure 3a is a diagram showing the first embodiment of the present invention. Figure 1 Magnified view of the region (R1).

[0063] Figure 3b is a diagram showing a method according to the second embodiment Figure 1 Magnified view of the region (R1).

[0064] Figure 3c is a diagram showing a method according to the third embodiment Figure 1 Magnified view of the region (R1).

[0065] Figure 4 is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0066] Figure 5 is a cross-sectional view showing a semiconductor package according to a third embodiment.

[0067] Figure 6 is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0068] Figure 7 is a cross-sectional view showing a partial area of ​​a semiconductor package according to a fifth embodiment.

[0069] Figure 8 is a cross-sectional view showing a partial area of ​​a semiconductor package according to a sixth embodiment.

[0070] Figure 9 is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

[0071] Figures 10 to 24 The process sequence is shown Figure 1 FIG. 1 shows a method for manufacturing a semiconductor package. DETAILED DESCRIPTION

[0072] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein the same figure numerals are used to represent the same or similar elements, and their repeated description will be omitted. The suffixes "module" and "part" of the components used in the following description are given or mixed only for the convenience of writing the specification, and do not themselves have meanings or functions that distinguish each other. Moreover, in the following description of the embodiments of the present invention, when it is determined that a detailed description of the relevant technology may obscure the key points of the embodiments disclosed herein, the detailed description of the relevant technology will be omitted. Moreover, the included drawings are used to provide a further understanding of the present invention, and these drawings are incorporated into and constitute a part of this specification, and it should be understood that the present invention is intended to cover all variations, equivalents or alternatives that fall within the spirit and scope of the present invention.

[0073] Terms including ordinal numbers such as "first" and "second" may be used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another.

[0074] When a component is referred to as being “connected” or “in contact with” another component, it can be directly connected or engaged with the other component, but it should be understood that other components may exist between the two. When a component is referred to as being “directly connected” or “in direct contact with” another component, it should be understood that no other components exist between the two.

[0075] Unless the context clearly implies otherwise, a singular expression also includes a plural expression.

[0076] In this application, terms such as "including" or "having" are used to indicate the presence of features, numbers, steps, operations, components, parts or combinations thereof described in the specification. However, it should be understood that these terms do not exclude the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0077] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0078] -Electronic equipment-

[0079] Before describing the embodiments, an electronic device to which the semiconductor package of the present embodiment is applied will be briefly described. The electronic device includes a mainboard (not shown). The mainboard can be physically and / or electrically connected to various components. For example, the mainboard can be connected to the semiconductor package of the present embodiment. Various semiconductor devices can be mounted on the semiconductor package.

[0080] Semiconductor devices may include active devices and / or passive devices. Active devices may be semiconductor chips in the form of integrated circuits (ICs), in which hundreds to millions of devices are integrated into a single semiconductor device. Semiconductor devices may include logic chips, memory chips, and the like. Logic chips may include central processing units (CPUs), graphics processing units (GPUs), and the like. For example, a logic chip may be an application processor (AP) chip (including at least one of a central processing unit (CPU), graphics processing unit (GPU), digital signal processor, encryption processor, microprocessor, and microcontroller), an analog-to-digital converter, an application-specific integrated circuit (ASIC), and the like, or a chipset including a specific combination of the chips listed above.

[0081] The memory chip may be a stacked memory such as HBM. The memory chip may also include a memory chip such as a volatile memory (such as DRAM), a non-volatile memory (such as ROM), or a flash memory.

[0082] Furthermore, the semiconductor device may be an integrated passive device (IPD). Furthermore, the semiconductor device may be a multilayer ceramic capacitor (MLCC) or a silicon-based capacitor.

[0083] On the other hand, the product group of the semiconductor package to which the present embodiment is applied may be any one of CSP (chip scale package), FC-CSP (flip chip scale package), FC-BGA (flip chip ball grid array), POP (stacked package) and SIP (system in package), but is not limited thereto.

[0084] Furthermore, the electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a display, a tablet computer, a laptop computer, a netbook, a television, a video game console, a smart watch, an automobile, etc. However, the present embodiment is not limited thereto, but may also be any other electronic device that processes data in addition to these.

[0085] - Semiconductor packaging -

[0086] Figure 1 is a cross-sectional view showing a semiconductor package according to a first embodiment, Figure 2 It shows Figure 1 A diagram of a semiconductor package having a semiconductor device mounted on a circuit board, Figure 3a is a diagram showing the first embodiment of the present invention. Figure 1 An enlarged view of region R1, Figure 3b is a diagram showing a method according to the second embodiment Figure 1 An enlarged view of region R1, and Figure 3c is a diagram showing a method according to the third embodiment Figure 1 Magnified view of region R1.

[0087] Reference Figures 1 to 3c , the semiconductor package includes a circuit board.

[0088] In one embodiment, the circuit board is a packaging substrate. For example, the circuit board is disposed between the mainboard of an electronic device and semiconductor devices 320 and 330 and is capable of electrically connecting them. The circuit board can electrically connect semiconductor devices 320 and 330 horizontally and vertically connect semiconductor devices 320 and 330 to the mainboard of the electronic device.

[0089] In another embodiment, the circuit board refers to a relay substrate disposed between the package substrate and the semiconductor devices 320 and 330. For example, the relay substrate may be an interposer. In other words, the circuit board may electrically connect the semiconductor devices 320 and 330 horizontally and electrically connect the semiconductor devices 320 and 330 to the package substrate vertically.

[0090] The semiconductor package includes semiconductor devices 320 and 330 electrically connected on a circuit board.

[0091] The semiconductor devices 320 and 330 may include a first semiconductor device 320 and a second semiconductor device 330, but are not limited thereto. For example, three or more semiconductor devices may be arranged on a circuit board, or one semiconductor device may be arranged on a circuit board.

[0092] The semiconductor package includes a bonding portion 310 disposed between semiconductor devices 320 , 330 and a circuit board. The bonding portion 310 electrically connects terminals 325 , 335 of the semiconductor devices 320 , 330 to an electrode portion (specifically, the metal layer 140 ) of the circuit board.

[0093] The bonding portion 310 electrically connects the electrode portion of the circuit board and the terminals 325 and 335 of the semiconductor devices 320 and 330 by using at least one bonding method of wire bonding, solder bonding, or direct metal bonding.

[0094] The wire bonding method refers to electrically connecting the electrode portion of the circuit board and the terminals 325 and 335 of the semiconductor devices 320 and 330 using a conductor such as gold (Au).

[0095] The solder bonding method electrically connects the electrode portion of the circuit board and the terminals 325 and 335 of the semiconductor devices 320 and 330 using a material containing at least one of Sn, Ag, and Cu.

[0096] The direct metal bonding method involves applying heat and pressure between the electrode portion of the circuit board and the terminals 325, 335 of the semiconductor devices 320, 330 to cause recrystallization without using solder, wire, conductive adhesive, etc., thereby directly bonding the electrode portion of the circuit board to the terminals 325, 335 of the semiconductor devices 320, 330. In this case, the bonding portion 310 may refer to a metal layer formed between the electrode portion of the circuit board and the terminals 325, 335 of the semiconductor devices 320, 330 by recrystallization.

[0097] For example, the joint 310 can electrically connect the electrode portion of the circuit board to the terminals 325 and 335 of the semiconductor devices 320 and 330 using a thermocompression bonding method. The thermocompression bonding method can reduce the volume of the joint 310 and prevent short circuits between multiple joints. Therefore, the thermocompression bonding method may be advantageous when the terminals 325 and 335 of the semiconductor devices 320 and 330 and / or the electrode portion of the circuit board have a fine pitch.

[0098] According to one embodiment, the semiconductor package includes a connection member 200 embedded in a circuit board.

[0099] The connection member 200 partially overlaps the semiconductor devices 320 and 330 arranged on the circuit board in a vertical direction.

[0100] The connection member 200 electrically connects a portion of the terminal 325 of the first semiconductor device 320 and a portion of the terminal 335 of the second semiconductor device 330 .

[0101] The semiconductor device may be mounted on the circuit board as a functionally separated core unit, or a plurality of semiconductor devices having different functions (e.g., a CPU and a GPU, or a GPU and an HBM) may be mounted on the circuit board, and the connection member 200 may function to electrically connect them in the horizontal direction.

[0102] In one embodiment, the connection member 200 is an inorganic bridge. For example, the inorganic bridge can be a silicon bridge. For example, the connection member 200 can include a silicon substrate and a redistribution layer.

[0103] In another embodiment, the connecting member 200 is an organic bridge. For example, the connecting member 200 may include an organic material. For example, the connecting member 200 may include an organic substrate in which the silicon substrate of the inorganic bridge is rearranged as an organic substrate.

[0104] The connection member 200 includes a connection pad 210. The connection pad 210 of the connection member 200 is electrically connected to the electrode portion of the circuit board. In addition, the electrode portion of the circuit board is electrically connected to the terminals 325 and 335 of the semiconductor devices 320 and 330. Therefore, the connection member 200 electrically connects the terminals 325 and 335 of the semiconductor devices 320 and 330.

[0105] Furthermore, a bonding member 220 is disposed between the connection member 200 and the electrode portion 120 of the substrate. The bonding member 220 is provided between the connection pads 210 of the connection member 200 and the electrode portion 120. The bonding member 220 can electrically connect the connection pads 210 of the connection member 200 by fixing them to the electrode portion 120.

[0106] The circuit board electrically connected to the connection member 200 and the semiconductor devices 320 and 330 is described in detail below.

[0107] The circuit board includes an insulating layer 110. Insulating layer 110 can be made of an organic material without reinforcing members. This organic material has excellent workability, allowing for a thinner circuit board and miniaturization of the electrode portion 120 provided on the circuit board. For example, materials such as ABF (Ajinomoto Laminated Film), a product of Ajinomoto Co., Ltd., FR-4, BT (Bismaleimide Triazine), and PID (Photo Imageable Dielectric Resin) can be used for insulating layer 110.

[0108] The insulating layer 110 may be provided in a form in which a plurality of layers are stacked. Figure 1 As shown, the insulating layer 110 may include first to fourth insulating layers 111, 112, 113, and 114, but is not limited thereto. For example, the insulating layer 110 may include three or fewer insulating layers, or five or more insulating layers.

[0109] In one embodiment, the plurality of layers of the insulating layer 110 may be provided with the same insulating material, but is not limited thereto, and at least one layer of the plurality of layers of the insulating layer 110 may be provided with an insulating material different from at least one other layer.

[0110] When the insulating layer 110 is provided with multiple layers, the interfaces between the multiple layers may not be easy to distinguish. In this case, the interfaces between these layers can be distinguished by the electrode portion 120 arranged in the insulating layer 110. The electrode portion 120 includes a first electrode portion 121 and a second electrode portion 122. The first electrode portion 121 is arranged at the interface between the multiple layers of the insulating layer 110. The first electrode portion 121 may include a pad and / or a trace and may be referred to as a wiring electrode portion. The second electrode portion 122 may be referred to as a via electrode portion or a through-electrode portion. The second electrode portion 122 electrically connects the first electrode portions 121 arranged in different layers in the vertical direction. At this time, the width of the first electrode portion 121 in the horizontal direction is different from the width of the second electrode portion 122 in the horizontal direction. Therefore, the difference between the width of the first electrode portion 121 in the horizontal direction and the width of the second electrode portion 122 in the horizontal direction can be used to distinguish the interfaces of the multiple layers of the insulating layer 110. In addition, the inclination angle of the side surface of the first electrode portion 121 is different from the inclination angle of the side surface of the second electrode portion 122. Therefore, interfaces of the plurality of layers of the insulating layer 110 may be distinguished using a difference between an inclination angle of the side surface of the first electrode portion 121 and an inclination angle of the side surface of the second electrode portion 122 .

[0111] However, even if the plurality of layers of the insulating layer 110 include the same insulating material, interfaces therebetween can be distinguished.

[0112] Through the stacked structure of the insulating layer 110 , the circuit board of this embodiment can electrically connect the semiconductor devices 320 and 330 with the package substrate and / or the main board.

[0113] Insulation layer 110 includes a resin and a reinforcing member disposed within the resin. For example, each of first to fourth insulation layers 111, 112, 113, and 114 includes a resin and a reinforcing member. Here, "reinforcing member" may refer to a filler and can be distinguished from glass fiber. A reinforcing member may refer to a filler having a specific diameter. The reinforcing members may be arranged to have any size and may be dispersed throughout each of first to fourth insulation layers 111, 112, 113, and 114.

[0114] In this case, the reinforcing members provided in at least one of the first to fourth insulating layers 111, 112, 113, and 114 may have a different arrangement structure than the reinforcing members provided in at least another layer. The term "arrangement structure" may refer to the arrangement positions of the reinforcing members provided in the insulating layers. Therefore, a different arrangement structure may mean that the arrangement position of the reinforcing members provided in at least one insulating layer is different from the arrangement position of the reinforcing members provided in at least another insulating layer.

[0115] For example, the reinforcing members provided in at least one of the first to fourth insulating layers 111, 112, 113 and 114 may be arranged in certain areas other than specific areas in the entire area in the thickness direction of the corresponding insulating layer, and the reinforcing members provided in at least one other layer may be arranged to be distributed in the entire area in the thickness direction of the corresponding insulating layer.

[0116] Specifically, an arrangement structure of the reinforcement member provided in the first insulation layer 111 disposed on the uppermost side of the semiconductor package among the first to fourth insulation layers 111 , 112 , 113 and 114 may be different from an arrangement structure of the reinforcement member provided in the second to fourth insulation layers 112 , 113 and 114 .

[0117] That is, the reinforcing member provided in the first insulating layer 111 may be provided in certain areas of the entire area in the thickness direction of the first insulating layer 111. For example, the first insulating layer 111 may be divided into a first layer 111-1 and a second layer 111-2 located on the first layer 111-1. The first layer 111-1 of the first insulating layer 111 may be the lower area of ​​the first insulating layer 111, and the second layer 111-2 of the first insulating layer 111 may be the upper area of ​​the first insulating layer 111 excluding the first layer 111-1. Here, the first layer 111-1 and the second layer 111-2 of the first insulating layer 111 may refer to areas along the thickness direction of a single insulating layer where the reinforcing member is provided and areas where the reinforcing member is not provided, or may refer to multiple layers including layers where the reinforcing member is provided and layers where the reinforcing member is not provided.

[0118] First layer 111-1 of first insulating layer 111 includes resin and reinforcing members 111F disposed within the resin. For example, reinforcing members 111F are arranged so as to be dispersed throughout the resin of first layer 111-1 of first insulating layer 111. Furthermore, second layer 111-2 of first insulating layer 111 does not include any reinforcing members. For example, second layer 111-2 of first insulating layer 111 may include only resin and, therefore, may be referred to as a filler-free resin layer. A filler-free resin layer may refer to a layer without any reinforcing members, such as fillers, but is not limited thereto. For example, a filler-free resin layer may refer to a layer having a reinforcing member smaller in size than that of first layer 111-1 of first insulating layer 111, or may refer to a layer having a reinforcing member content less than that of first layer 111-1 of first insulating layer 111. According to the technical concept of the present invention, the second layer 111 - 2 of the first insulating layer 111 can be freely used within a range where problems such as peeling do not occur by controlling the difference in thermal expansion rate from the first layer 111 - 1 of the first insulating layer 111 .

[0119] refer to Figures 3a to 3c , the second layer 111 - 2 of the first insulating layer 111 may have a reinforcing member, or may not have a reinforcing member.

[0120] refer to Figure 3a , the first layer 111 - 1 of the first insulating layer 111 may have the reinforcing member 111F, while the second layer 111 - 2 of the first insulating layer 111 may not have the reinforcing member.

[0121] In this case, the filler-free resin layer provided as the second layer 111-2 of the first insulating layer 111 may refer to a layer without a reinforcing member. Therefore, according to one embodiment, by using the second layer 111-2 of the first insulating layer 111 without a reinforcing member, the reinforcing member (e.g., filler) may not be exposed on the upper side of the first insulating layer 111, thereby improving the adhesion between the plurality of insulating layers and minimizing the electrical loss of the electrode portion.

[0122] refer to Figure 3b, the first layer 111-1 of the first insulating layer 111 may include a first reinforcing member 111F, such as a first filler. The second layer 111-2 of the first insulating layer 111 may include a second reinforcing member 111-2F, such as a second filler. In this case, the diameter of the first reinforcing member 111F may be the same as the diameter of the second reinforcing member 111-2F. In this case, the content of the second reinforcing member 111-2F in the second layer 111-2 of the first insulating layer 111 may be less than the content of the first reinforcing member 111F in the first layer 111-1. Therefore, according to another embodiment, by using the second layer 111-2 of the first insulating layer 111 with a relatively small content of the second reinforcing member 111-2F, the reinforcing member (such as the filler) can be prevented from being exposed on the upper side of the first insulating layer 111, thereby improving the adhesion between the multiple insulating layers and minimizing electrical loss in the electrode portion.

[0123] refer to Figure 3c The first layer 111-1 of the first insulating layer 111 may include a first reinforcing member 111F, such as a first filler. The second layer 111-2 of the first insulating layer 111 may include a second reinforcing member 111-2F, such as a second filler. In this case, the diameter of the first reinforcing member 111F may be different from the diameter of the second reinforcing member 111-2F. Preferably, the diameter of the first reinforcing member 111F may be larger than the diameter of the second reinforcing member 111-2F. Furthermore, the content of the second reinforcing member 111-2F in the second layer 111-2 of the first insulating layer 111 may be less than the content of the first reinforcing member 111F in the first layer 111-1. Therefore, according to another embodiment, by using the second layer 111-2 of the first insulating layer 111 having the second reinforcing member 111-2F with a relatively smaller diameter, the reinforcing member (e.g., filler) is prevented from being exposed on the upper side of the first insulating layer 111, thereby improving the adhesion between the multiple insulating layers and minimizing electrical loss in the electrode portion. For the sake of convenience, the following description will be given assuming that the second layer 111 - 2 of the first insulating layer 111 does not have a reinforcing member.

[0124] Therefore, the first insulating layer 111 includes a first layer 111-1 having the reinforcing member 111F and a second layer 111-2 having no reinforcing member. Thus, the present embodiment can improve the flatness of the semiconductor package and enable the semiconductor device to be stably mounted.

[0125] For example, this embodiment can allow the second layer 111-2 of the first insulating layer 111 to have no reinforcing member, so that the height of the upper surface of the second layer 111-2 can be uniform as a whole. In addition, this embodiment can improve the adhesion with the metal layer 140 arranged on the first insulating layer 111. In addition, this embodiment can prevent the semiconductor package from warping significantly in a specific direction. In addition, this embodiment can improve the physical reliability and / or electrical reliability of the semiconductor package. In addition, as described above, the fact that the second layer 111-2 of the first insulating layer 111 does not have a reinforcing member may mean that a reinforcing member with a relatively small content and / or a reinforcing member with a relatively small diameter can be provided.

[0126] The upper surface of first insulating layer 111 is positioned lower than the upper surface of pad portion 130 described below. In addition, the upper surface of first insulating layer 111 is positioned higher than the lower surface of pad portion 130. That is, at least a portion of pad portion 130 is embedded in first insulating layer 111, and at least the remaining portion of pad portion 130 protrudes above first insulating layer 111. To this end, in this embodiment, a process of etching a portion of first insulating layer 111 to reduce the thickness of the first insulating layer is performed while the upper surface of first insulating layer 111 is positioned at a height higher than the upper surface of pad portion 130.

[0127] At this time, if reinforcing member 111F is provided throughout first insulating layer 111, the flatness of the upper surface of first insulating layer 111 may be reduced during the process of etching first insulating layer 111 to reduce its thickness. In other words, if the process of etching first insulating layer 111 to reduce its thickness is performed while reinforcing member 111F is provided throughout first insulating layer 111, the reinforcing member provided in first insulating layer 111 may be exposed on the upper side of first insulating layer 111. Furthermore, if reinforcing member 111F provided in first insulating layer 111 is exposed on the upper side, the adhesion between insulating layer 110 and metal layer 140, described later, may be reduced. For example, the adhesion between reinforcing member 111F and metal layer 140 may be weaker than the adhesion between the resin of insulating layer 110 and metal layer 140. As a result, the adhesion between insulating layer 110 and metal layer 140 may be reduced, and metal layer 140 may be peeled off from insulating layer 110. Furthermore, if the metal layer 140 contacts the reinforcing member 111F, loss of electrical signals and / or power transmitted through the metal layer 140 may occur because the reinforcing member 111F has a relatively high dielectric constant.

[0128] Furthermore, when etching the first insulating layer 111 to reduce its thickness while reinforcing member 111F is provided throughout the entire region of the first insulating layer 111, at least a portion of the reinforcing member provided in the first insulating layer 111 may be removed. Consequently, a recessed portion may be formed on the upper surface of the first insulating layer 111. This recessed portion is the space created by the removal of the reinforcing member. In this case, the recessed portion may have a greater depth than other portions of the upper surface of the first insulating layer 111. Therefore, if the recessed portion exists on the upper surface of the first insulating layer 111, the metal layer 140 may not completely fill the recessed portion, resulting in a gap between the first insulating layer 111 and the metal layer 140. Furthermore, if the recessed portion exists on the upper surface of the first insulating layer 111, stress acting on the insulating layer 110 may be concentrated on the recessed portion, potentially reducing the physical and / or electrical reliability of the semiconductor package.

[0129] In contrast, the first insulating layer 111 of the present embodiment includes a first layer 111-1 and a second layer 111-2. The first layer 111-1 of the first insulating layer 111 includes a resin and a reinforcing member 111F, while the second layer 111-2 does not include a reinforcing member.

[0130] Therefore, this embodiment can prevent the reinforcing member 111F from being exposed on the upper surface of the first insulating layer 111 after etching, and thus can make the height of the upper surface of the first insulating layer 111 uniform.

[0131] Furthermore, by preventing the metal layer 140 disposed on the pad portion 130 from contacting the reinforcing member 111F, the present embodiment can improve the electrical characteristics of the metal layer 140 while improving the adhesion between the metal layer 140 and the insulating layer 110 .

[0132] In addition, by making the upper surface of the first insulating layer 111 have a uniform height, this embodiment can prevent stress from being concentrated at a specific position on the upper surface of the first insulating layer 111. Further, it can also evenly distribute stress to the entire area, thereby improving the physical reliability and electrical reliability of the semiconductor package.

[0133] In addition, by improving the adhesion between the metal layer 140 and the insulating layer 110 , the present embodiment can prevent the bonding portion 310 disposed on the metal layer 140 from penetrating or diffusing into the gap between the metal layer 140 and the insulating layer 110 .

[0134] Therefore, the present embodiment can suppress the formation of a relatively brittle intermetallic compound (IMC) between the bonding portion 310 and the pad portion 130 , and can accordingly improve the physical reliability and electrical reliability of the semiconductor package.

[0135] In addition, by providing the first insulating layer 111 with a first layer 111-1 having a reinforcing member 111F and a second layer 111-2 without a reinforcing member, this embodiment can prevent the semiconductor package from significantly warping in a specific direction, thereby giving the semiconductor package an advantage in warping control, thereby enabling the semiconductor device to be stably installed and also enabling the semiconductor device to operate stably.

[0136] Specifically, if the first insulating layer 111 has only the first layer 111-1 and no second layer 111-2, the semiconductor package may warp significantly in a specific direction. This may occur due to the difference in thermal expansion coefficient between the insulating layer 110 and the protective layer 170, the difference in thickness of each layer of the insulating layer 110, the difference in density of the electrode portion 120 provided on the surface of each layer of the insulating layer 110, and the difference in thickness of the electrode portion 120 provided on the surface of each layer of the insulating layer 110. At this time, the present embodiment enables the second layer 111-2 of the first insulating layer 111 without the reinforcement member to be provided on the uppermost side of the circuit board. At this time, the thermal expansion coefficient of the second layer 111-2 of the first insulating layer 111 is different from the thermal expansion coefficient of each layer of the first layer 111-1, the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114 and the protective layer 170 of the first insulating layer 111. For example, the second layer 111-2 of the first insulating layer 111 can serve as a buffer layer that mitigates the difference in thermal expansion coefficients between the multiple layers of the insulating layer 110 and the protective layer 170. Therefore, the second layer 111-2 of the first insulating layer 111 can have a thermal expansion coefficient matching function that mitigates the difference in thermal expansion coefficients between the insulating layer 110 and the protective layer 170, thereby preventing the circuit board from significantly warping in a specific direction. For example, when the second layer 111-2 is not provided on the first insulating layer 111, the two ends of the circuit board may bend downward. At this time, the second layer 111-2 provided on the first insulating layer 111 can cause the two ends of the circuit board to bend upward, thereby ultimately allowing the circuit board to maintain a flat state without bending. In addition, this embodiment can easily control the warping of the circuit board by adjusting the thickness of the second layer 111-2 of the first insulating layer 111, thereby enabling the embodiment to improve the physical reliability and / or electrical reliability of the semiconductor package.

[0137] In addition, refer to Figures 3a to 3c, a concavo-convex portion 111T is provided on the upper surface of the second layer 111-2 of the first insulating layer 111. In the process of reducing the thickness of the second layer 111-2 of the first insulating layer 111 by etching, the concavo-convex portion 111T can be provided on the upper surface of the second layer 111-2. In this case, the present embodiment forms the concavo-convex portion 111T by etching the second layer 111-2 of the first insulating layer 111 without the reinforcement member. Therefore, the reinforcement member is not exposed through the concavo-convex portion 111T, thereby allowing the concavo-convex portion 111T to be provided at a uniform depth on the upper surface of the second layer 111-2. The concavo-convex portion 111T contacts at least a portion of the metal layer 140 arranged on the pad portion 130. As a result, the present embodiment can further improve the adhesion between the first insulating layer 111 and the metal layer 140.

[0138] The concave-convex portion 111T has a specific curvature. Here, the curvature of the concave-convex portion 111T is different from the curvature of the reinforcing member 111F provided in the first layer 111-1 of the first insulating layer 111. This different curvature may mean that the reinforcing member 111F is not exposed upward through the concave-convex portion 111T. Alternatively, the different curvature may mean that during the process of etching the first insulating layer 111 to reduce its thickness, the reinforcing member 111F is not separated from the first insulating layer 111, and thus the concave-convex portion 111T does not include a concave portion formed by the separation of the reinforcing member 111F. As a result, this embodiment can improve the physical and / or electrical reliability of the semiconductor package.

[0139] The second layer 111-2 of the first insulating layer 111 has a predetermined thickness T1. The thickness T1 of the second layer 111-2 of the first insulating layer 111 may refer to the vertical distance from the upper surface of the second layer 111-2 to the lower surface of the second layer 111-2, but is not limited thereto. For example, the thickness T1 of the second layer 111-2 may also refer to the vertical distance from the bottom surface of the concave-convex portion 111T to the lower surface of the second layer 111-2.

[0140] At this time, the thickness T1 of the second layer 111-2 ranges from 1 μm to 5.5 μm. For example, the thickness T1 of the second layer 111-2 ranges from 1.5 μm to 5.0 μm. For example, the thickness T1 of the second layer 111-2 ranges from 1.5 μm to 4.5 μm. If the thickness T1 of the second layer 111-2 is less than 1 μm, the effect of not having the reinforcing member in the first insulating layer 111 may be minimal. For example, if the thickness T1 of the second layer 111-2 is less than 1 μm, the effect of improving the flatness of the semiconductor package, improving the adhesion between the insulating layer and the metal layer, preventing the semiconductor package from warping, or suppressing the formation of intermetallic compounds may be insufficient. Furthermore, if the thickness T1 of the second layer 111-2 is less than 1 μm, at least a portion of the reinforcing member 111F disposed in the first region 111-2 of the first insulating layer 111 may be exposed upward due to process deviations in the etching process of the first insulating layer 111. In addition, if the thickness T1 of the second layer 111-2 exceeds 5.5 μm, the content of the reinforcing member provided in the first insulating layer 111 may be reduced, and thus the rigidity of the circuit board may be reduced. In addition, if the thickness of the first layer 111-1 of the first insulating layer 111 is increased to prevent the rigidity of the circuit board from being reduced, the thickness of the semiconductor package may increase, and thus miniaturization of the semiconductor package may be difficult.

[0141] In one embodiment, the first insulating layer 111 is configured as a single layer. For example, the first layer 111-1 and the second layer 111-2 of the first insulating layer 111 are configured as a single layer. In this embodiment, the reinforcing member 111F may be provided only in the first layer 111-1, excluding the second layer 111-2, within the single-layer first insulating layer 111. For example, in this embodiment, while the reinforcing member 111F is provided in both the first layer 111-1 and the second layer 111-2 of the first insulating layer 111, a metal member having a protrusion may be pressed against the second layer 111-2 of the first insulating layer 111, thereby moving the reinforcing member 111F provided in the second layer 111-2 of the first insulating layer 111 to the first layer 111-1 of the first insulating layer 111. Thus, the first layer 111-1 of the first insulating layer 111 may be provided with the reinforcing member 111F, while the second layer 111-2 may not be provided with the reinforcing member. At this time, the resin of the first layer 111 - 1 and the resin of the second layer 111 - 2 of the first insulating layer 111 are made of the same material, and therefore, the interface between the first layer 111 - 1 and the second layer 111 - 2 may be indistinguishable.

[0142] In another embodiment, the first insulating layer 111 may have multiple layers. For example, the first insulating layer 111 may have a structure in which a first layer 111-1 and a second layer 111-2 are bonded. For example, the first insulating layer 111 may have a first layer 111-1 provided with a reinforcing member, and a second layer 111-2 stacked on the first layer 111-1 without the reinforcing member. In this case, the resin of the first layer 111-1 and the resin of the second layer 111-2 may contain the same insulating material. In this case, the interface between the first layer 111-1 and the second layer 111-2 may be indistinguishable. In contrast, even if the resin of the first layer 111-1 and the resin of the second layer 111-2 contain the same insulating material, the interface between the first layer 111-1 and the second layer 111-2 may be distinguishable due to the difference in molecular weight at the bonding interface during the bonding process. Furthermore, the resin of the first layer 111-1 and the resin of the second layer 111-2 may contain different insulating materials. In this case, the interface between the first layer 111-1 and the second layer 111-2 may be distinguishable.

[0143] At this time, the resin of the first layer 111-1 and the resin of the second layer 111-2 of the first insulating layer 111 may include any one of a thermosetting resin, a thermoplastic resin or a photocurable resin, and for example, may be any one of polyimide (PI), polyethylene terephthalate (PET), propylene glycol, polycarbonate (PC), COC (cyclic olefin copolymer), COP (cyclic olefin polymer), photoisotropic polycarbonate (PC), photoisotropic polymethyl methacrylate (PMMA), ABF (Ajinomoto laminated film), FR-4, BT (bismaleimide triazine) and PID (photoimaging dielectric resin).

[0144] Furthermore, each of the second insulating layer 112 , the third insulating layer 113 , and the fourth insulating layer 114 , in addition to the first insulating layer 111 , may be provided with a reinforcing member over the entire area in the thickness direction, thereby improving the rigidity of the circuit board.

[0145] In addition, refer to Figures 3a to 3c , a protrusion 112T protruding toward the upper surface of the first insulating layer 111 is provided at the interface between the first insulating layer 111 and the second insulating layer 112. For example, a concave surface recessed toward the upper surface of the first insulating layer 111 may be provided on the lower surface of the first insulating layer 111, and a convex surface corresponding to the concave surface of the first insulating layer 111 may be provided on the upper surface of the second insulating layer 112. This can form a groove having a certain depth on the lower surface of the first insulating layer 111, and the second insulating layer 112 can fill the groove formed on the lower surface of the first insulating layer 111, thereby providing a protrusion 112T on the upper surface of the second insulating layer 112.

[0146] The raised portion 112T does not overlap with the connecting member 200 in the vertical direction at the interface between the first insulating layer 111 and the second insulating layer 112. For example, the interface between the first insulating layer 111 and the second insulating layer 112 includes an overlapping region that overlaps with the connecting member 200 in the vertical direction. In addition, the raised portion 112T can be arranged at a position spaced a certain distance from the overlapping region in the horizontal direction. The raised portion 112T can have a closed loop shape surrounding the periphery of the overlapping region, but is not limited thereto. For example, the raised portion 112T can be provided with a plurality of raised patterns spaced apart from each other around the overlapping region. The raised portion 112T can serve as an alignment mark (alignment pit) while guiding the attachment position of the connecting member 200 during the manufacturing process of the semiconductor package, so as to align the electrode portion 120 with the connecting pad 210 of the connecting member 200. For example, the connection member 200 may be attached to the electrode portion 120 with the connection pad 210 facing downward, and this may make it difficult to accurately align the connection pad 210 of the connection member 200 with the electrode portion 120. Therefore, the present embodiment may provide a protrusion 112T corresponding to the alignment mark corresponding to the position to which the connection member 200 is to be attached, thereby improving the alignment between the connection pad 210 of the connection member 200 and the electrode portion 120.

[0147] In addition, the circuit board includes an electrode portion 120 disposed on the insulating layer 110. The electrode portion 120 includes a first electrode portion 121 and a second electrode portion 122 that are distinguished according to position and function.

[0148] The first electrode portion 121 may be horizontally arranged between each of the plurality of layers of the insulating layer 110 , and the second electrode portion 122 may be vertically arranged and penetrate each of the plurality of layers of the insulating layer 110 .

[0149] The electrode portion 120 is divided into a plurality of groups. The electrode portion 120 includes a first group of electrode portions that overlap with the semiconductor devices 320, 330 and the connecting member 200 in the vertical direction. In addition, the electrode portion 120 includes a second group of electrode portions that overlap with the first group of electrode portions in the horizontal direction but do not overlap with the connecting member 200 in the vertical direction. The first group of electrode portions overlaps with the semiconductor devices 320 and 330 in the vertical direction. In other words, the second group of electrode portions are electrode portions that overlap with the connecting member 200 and the semiconductor devices 320, 330 in the vertical direction, respectively, while the first group of electrode portions are electrode portions that do not overlap with the connecting member 200 in the vertical direction but overlap with the semiconductor devices 320 and 330.

[0150] At least one of the width of the first electrode portion, the width of the second electrode portion, and the spacing between the plurality of first electrode portions spaced apart in the horizontal direction in the first group of electrode portions may be different from the width of the first electrode portion, the width of the second electrode portion, and the spacing between the plurality of first electrode portions spaced apart in the horizontal direction in the second group of electrode portions. For example, at least one of the width of the first electrode portion, the width of the second electrode portion, and the spacing between the plurality of first electrode portions spaced apart in the horizontal direction in the first group of electrode portions may be smaller than the width of the first electrode portion, the width of the second electrode portion, and the spacing between the plurality of first electrode portions spaced apart in the horizontal direction in the second group of electrode portions.

[0151] Thus, this embodiment can arrange both the first electrode portion and the second electrode portion in the first group of electrode portions within a limited space, and can stably electrically connect the semiconductor devices 320 and 330 and the connection member 200 .

[0152] The first electrode portion 120 includes a pad portion 130 disposed on the uppermost side of the circuit board. Pad portion 130 is provided on the first insulating layer 111. Pad portion 130 is connected to a terminal of the semiconductor device and can therefore be referred to as a bump. Furthermore, the first electrode portion 120 includes a lower pad portion 150 disposed on the lowermost side of the circuit board. Lower pad portion 150 can serve as a terminal for connection to an external substrate (e.g., a package substrate or a motherboard).

[0153] The pad portion 130 is arranged in the recess 111R provided on the upper surface of the first insulating layer 111. The recess 111R penetrates the second layer 111-2 of the first insulating layer 111. Therefore, the recess 111R includes a through hole (111R1, see FIG. 111) penetrating the second layer 111-2 of the first insulating layer 111. Figure 4 ). In addition, the recess 111R is concavely provided on the upper surface of the first layer 111-1 of the first insulating layer 111. Therefore, the recess 111R has a groove portion (111R2, see Figure 4 ) and a through hole 111R1 penetrating the second layer 111 - 2 of the first insulating layer 111. Therefore, the pad portion 130 is provided to penetrate the second layer 111 - 2 of the first insulating layer 111.

[0154] The pad portion 130 can be divided into multiple parts in the vertical direction. For example, the pad portion 130 has a first portion that overlaps with the reinforcing member of the insulating layer 110 in the horizontal direction, and a second portion that is arranged on the first portion and does not overlap with the reinforcing member of the insulating layer 110 in the horizontal direction. Specifically, the pad portion 130 includes a plurality of first pads 131 that overlap with the connecting member 200 in the vertical direction, and a plurality of second pads 132 that overlap with the first pads 131 in the horizontal direction but do not overlap with the connecting member 200 in the vertical direction. Each of the plurality of first pads 131 and the plurality of second pads 132 of the pad portion 130 is arranged in a recess 111R provided on the upper surface of the first insulating layer 111.

[0155] Furthermore, the plurality of first pads 131 include a first portion 131-1 that horizontally overlaps with the reinforcing member of the insulating layer 110, and a second portion 131-2 that horizontally does not overlap with the reinforcing member of the insulating layer 110. Furthermore, the plurality of second pads 132 include a first portion 132-1 that horizontally overlaps with the reinforcing member of the insulating layer 110, and a second portion 132-2 that horizontally does not overlap with the reinforcing member of the insulating layer 110. At this point, the second portion 131-2 and 132-2 of each of the plurality of first pads 131 and the plurality of second pads 132 horizontally overlaps with the insulating layer 110, but does not horizontally overlap with the reinforcing member of the insulating layer 110. That is, the second portion 131-2 and 132-2 of each of the plurality of first solder pads 131 and the plurality of second solder pads 132 overlaps with the second layer 111-2 of the first insulating layer 111 in the horizontal direction, and therefore does not overlap with the reinforcement member 111F provided in the first insulating layer 111 in the horizontal direction. As a result, this embodiment can improve the flatness of the semiconductor package and enable stable attachment of the semiconductor device. In other words, by preventing the second portion 131-2 and 132-2 of each of the plurality of first solder pads 131 and the plurality of second solder pads 132 from overlapping with the reinforcement member of the insulating layer 110 in the horizontal direction, the flatness of the metal layer 140 arranged on the first solder pads 131 and the second solder pads 132 can be improved. Furthermore, the adhesion between the metal layer 140 and the insulating layer 110 and the adhesion between the metal layer 140 and the solder pad portion 130 can be improved. In addition, the present embodiment can minimize the stress caused by the thermal stress transferred to the second portion 131-2 and 132-2 of each of the multiple first solder pads 131 and the multiple second solder pads 132, thereby improving the physical reliability and / or electrical reliability of the multiple first solder pads 131 and the multiple second solder pads 132.

[0156] In addition, each of the plurality of first pads 131 overlaps with the connecting member 200 in the vertical direction, and each of the plurality of second pads 132 does not overlap with the connecting member 200 in the vertical direction, and therefore, they have different widths in the horizontal direction. For example, the width of each of the plurality of first pads 131 in the horizontal direction can be smaller than the width of each of the plurality of second pads 132 in the horizontal direction. As a result, this embodiment can improve the circuit integration of the pad portion 130, thereby shortening the length of the electrode line connected to the semiconductor device. Therefore, this embodiment can improve signal transmission characteristics by minimizing signal transmission loss and further reduce the volume of the semiconductor package.

[0157] Furthermore, the upper surfaces of the first and second pads 131 and 132 of this embodiment are located on the same plane, thereby allowing a semiconductor device to be stably coupled to the first and second pads 131 and 132 .

[0158] In addition, the circuit board also includes a metal layer 140 disposed on the pad portion 130. The metal layer 140 may be provided on the upper surface and side surfaces of the pad portion 130. The lower surface of the metal layer 140 contacts the upper surface of the second layer 111-2 of the first insulating layer 111. In this case, the concave-convex portion 111T is provided on the upper surface of the second layer 111-2, and therefore, the metal layer 140 may have a convex portion corresponding to the concave-convex portion 111T.

[0159] Specifically, metal layer 140 includes multiple first metal layers 141 arranged on multiple first pads 131, and multiple second metal layers 142 arranged on multiple second pads 132. Furthermore, each of the multiple first metal layers 141 has a lower surface having a raised portion 141B corresponding to the raised portion 111T provided on the upper surface of second layer 111-2 of first insulating layer 111. Furthermore, each of the multiple second metal layers 142 has a lower surface having a raised portion 142B corresponding to the raised portion 111T provided on the upper surface of second layer 111-2 of first insulating layer 111. Thus, this embodiment can increase the contact area between metal layer 140 and insulating layer 110, thereby improving the adhesion between metal layer 140 and insulating layer 110. Furthermore, by allowing metal layer 140 to contact second layer 111-2 of first insulating layer 111, this embodiment can minimize height deviations of the upper surfaces of each of the plurality of first metal layers 141 and the plurality of second metal layers 142, thereby allowing the semiconductor device to be stably mounted. Furthermore, by improving the adhesion between each of the plurality of first metal layers 141 and the plurality of second metal layers 142 and insulating layer 110, this embodiment can prevent intermetallic compounds from penetrating between joint portion 310 and pad portion 130, thereby further improving the physical and / or electrical reliability of the semiconductor package.

[0160] The plurality of first metal layers 141 and the plurality of second metal layers 142 may be a bonding portion at which a bonding part 310 such as solder for bonding with a semiconductor device is arranged.

[0161] At this time, the plurality of first metal layers 141 and the plurality of second metal layers 142 include a metal material different from the first pads 131 and the second pads 132. For example, the plurality of first metal layers 141 and the plurality of second metal layers 142 may include a metal material that prevents the intermetallic compound from penetrating in a direction toward the first pads 131 and the second pads 132.

[0162] For example, the plurality of first metal layers 141 and the plurality of second metal layers 142 may include nickel. Furthermore, when the plurality of first metal layers 141 and the plurality of second metal layers 142 include nickel, the adhesion between the pad portion 130 and the joint portion 310 can be improved, and further, the diffusion of intermetallic compounds can be prevented. For example, intermetallic compounds have problems with poor mechanical and electrical reliability. In particular, when the pad portion 130 includes copper, mechanical reliability issues (e.g., cracking and / or degradation of electrical characteristics) and / or electrical reliability issues caused by intermetallic compounds may be further exacerbated. In this case, when the plurality of first metal layers 141 and the plurality of second metal layers 142 include nickel and are disposed around the exposed surface of each of the first pads 131 and the second pads 132, the diffusion of solder, such as solder, from the joint portion 310 can be prevented, thereby preventing the formation of intermetallic compounds, thereby improving the electrical and mechanical reliability of the semiconductor package. Furthermore, the plurality of first metal layers 141 and the plurality of second metal layers 142 are in contact with the second layer 111-2 of the first insulating layer 111 (the flatness of the second layer 111-2 of the first insulating layer 111 is improved compared to the prior art), thereby further improving the adhesion therebetween and thereby further preventing the infiltration of intermetallic compounds. In this case, the plurality of first metal layers 141 and the plurality of second metal layers 142 may include a metal other than nickel. For example, the plurality of first metal layers 141 and the plurality of second metal layers 142 may include gold and / or palladium.

[0163] Figure 4 is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0164] refer to Figure 4 ,and Figure 1 Compared with the semiconductor package of FIG. 1 , the semiconductor package may have a pad portion 130 and a metal layer 140 of different shapes. Figure 1 The same configurations of the semiconductor packages are given the same reference numerals, and detailed descriptions thereof will be omitted.

[0165] refer to Figure 4 , the pad portion 130A includes a tapered inclined side surface.

[0166] For example, the side surface of the pad portion 130A includes a portion where the inclination changes. Here, the portion where the inclination changes not only means that the direction of the inclination changes but also the degree of the inclination changes.

[0167] That is, pad portion 130A horizontally overlaps first layer 111-1 of first insulating layer 111 and thus includes first portion 130A-1 that horizontally overlaps reinforcing member 111F. Furthermore, pad portion 130A horizontally overlaps second layer 111-2 of first insulating layer 111 and thus includes second portion 130A-2 that does not horizontally overlap reinforcing member 111F. Furthermore, second portion 130A-2 of pad portion 130A includes a tapered, inclined side surface whose width varies along the vertical direction.

[0168] The side surface of the second portion 130A-2 of the pad portion 130A may include a first slope 130A-2S1, the width of which gradually increases toward the lower surface of the pad portion 130A. The first slope 130A-2S1 is adjacent to the upper surface 130A-2T of the pad portion 130A. Furthermore, the side surface of the second portion 130A-2 of the pad portion 130A includes a second slope 130A-2S2, which is different from the first slope 130A-2S1. The second slope 130A-2S2 may be perpendicular to the upper surface 130A-2T or the lower surface of the pad portion 130A, but is not limited thereto. Furthermore, the side surface of the first portion 130A-1 of the pad portion 130A has the same slope 130A-1S as the second slope 130A-2S2 of the second portion 130A-2. That is, the pad portion 130A includes a first slope surface 130A-2S1 and a second slope surface 130A-2S2. Figure 4 In the embodiment, second portion 130A-2 of pad portion 130A includes first slope 130A-2S1 and second slope 130A-2S2, and first insulating layer 111 includes slope 130A-1S corresponding to second slope 130A-2S2, but the present invention is not limited thereto. For example, the side surface of second portion 130A-2 of pad portion 130A may entirely include only first slope 130A-2S1, and first portion 130A-1 of pad portion 130A may include both the first slope and the second slope. Alternatively, the side surface of second portion 130A-2 of pad portion 130A may entirely include only the first slope, and first portion 130A-1 may entirely include only the second slope.

[0169] The angle between the upper surface 130A-2T of the pad portion 130A and the first slope 130A-2S1 is an obtuse angle. The angle between the upper surface 130A-2T of the pad portion 130A and the first slope 130A-2S1 may be in a range of 95 to 160 degrees. The angle between the upper surface 130A-2T of the pad portion 130A and the first slope 130A-2S1 may be in a range of 100 to 150 degrees. The angle between the upper surface 130A-2T of the pad portion 130A and the first slope 130A-2S1 may be in a range of 105 to 140 degrees. If the angle between the upper surface 130A-2T of the pad portion 130A and the first slope 130A-2S1 is less than 95 degrees, the effect of increasing the contact area between the pad portion 130A and the metal layer 140A may be insufficient, which may lead to problems such as the metal layer 140A peeling off from the pad portion 130A. For example, the circuit board may expand and / or contract due to thermal stress, which may lead to mechanical reliability issues such as the pad portion 130A and the metal layer 140A peeling off from each other. In addition, if the angle between the upper surface 130A-2T of the pad portion 130A and the first slope 130A-2S1 exceeds 160 degrees, the width difference between the upper surface and the lower surface of the pad portion 130A may increase. In addition, as the width difference between the upper surface and the lower surface of the pad portion 130A increases, the transmission loss of the signal transmitted through the pad portion 130A may increase, which may lead to deterioration of the signal transmission characteristics. Furthermore, as the difference in width between the upper and lower surfaces of the pad portion 130A increases, the area of ​​the upper surface of the pad portion 130A may decrease, and thus, the semiconductor device may not be stably arranged on the pad portion 130A.

[0170] In addition, the first slope 130A-2S1 and the second slope 130A-2S2 of the pad portion 130A can be achieved by a process of flattening the pad portion 130A or a pretreatment process before forming the metal layer 140A. As a result, this embodiment can minimize changes in the characteristics of the signal transmitted through the pad portion 130A. For example, impedance matching can be performed by adjusting the thickness and / or width of the pad portion 130A. At this time, if the multiple pads of the pad portion 130A have different thicknesses and / or heights due to plating deviations, the impedance characteristics may change accordingly, which may cause electrical reliability issues. Therefore, in this embodiment, the pad portion 130A includes the first slope 130A-2S1 and the second slope 130A-2S2, thereby improving the adhesion between the pad portion 130A and the metal layer 140A while preventing changes in the electrical characteristics of the pad portion 130A. In an embodiment, the pad portion 130A includes a first slope 130A- 2S1 and a second slope 130A- 2S2 through a planarization process or a pretreatment process, thereby improving the flatness of the upper surface of the pad portion 130A or preventing foreign matter from remaining on the upper surface of the pad portion 130A, thereby improving electrical characteristics.

[0171] At this time, at least a portion of the first slope surface 130A-2S1 of the pad portion 130A does not contact the insulating layer 110. Preferably, at least a portion of the first slope surface 130A-2S1 of the pad portion 130A may overlap with the second layer 111-2 of the first insulating layer 111 in the horizontal direction without contacting the second layer 111-2.

[0172] That is, pad portion 130A is disposed in recess 111R provided in first insulating layer 111. Recess 111R includes a through hole 111R1 extending through second layer 111-2 of first insulating layer 111, and a groove portion 111R2 disposed in first layer 111-1. In this case, the inner wall of through hole 111R1 in second layer 111-2 may be spaced a certain distance apart in the horizontal direction from first slope 130A-2S1 of pad portion 130A. For example, a spacer may be provided between the inner wall of through hole 111R1 in second layer 111-2 and first slope 130A-2S1 of pad portion 130A.

[0173] Therefore, metal layer 140A can contact first slope surface 130A-2S1 of pad portion 130A and the inner wall of through hole 111R1 of second layer 111-2. In other words, metal layer 140A can be provided to fill the gap. In other words, metal layer 140A is provided to cover first slope surface 130A-2S1 of pad portion 130A. The side surface of metal layer 140A has a slope surface 140AS corresponding to first slope surface 130A-2S1 of pad portion 130A.

[0174] Therefore, this embodiment can further improve the adhesion between the insulating layer 110 , the pad portion 130A, and the metal layer 140A, and thus can improve the electrical reliability and / or mechanical reliability of the semiconductor package.

[0175] Figure 5 is a cross-sectional view showing a semiconductor package according to a third embodiment.

[0176] refer to Figure 5 , the semiconductor package can Figure 4 The difference is that it further includes a protective layer 180 arranged on the metal layer 140A. Figure 4 The same configurations of the semiconductor packages are given the same reference numerals, and detailed descriptions thereof will be omitted.

[0177] The semiconductor package further includes a protection layer 180 disposed on the insulating layer 110 .

[0178] The protective layer 180 is disposed on the second layer 111-2 of the first insulating layer 111. In addition, the protective layer 180 is disposed on the metal layer 140A.

[0179] Protective layer 180 includes opening 180R. Opening 180R vertically overlaps metal layer 140A. Therefore, at least a portion of the upper surface of metal layer 140A is not covered by protective layer 180. In addition, the portion of the upper surface of metal layer 140A not covered by protective layer 180 can serve as a bump for electrical connection to a semiconductor device.

[0180] When protective layer 180 is provided, this embodiment can solve the problem of electrical short circuits caused by connecting multiple adjacent bonding portions during the process of arranging bonding portions 310 on metal layer 140A, thereby further improving the electrical reliability of the semiconductor package. In addition, protective layer 180 can be additionally arranged on second layer 111-2 of first insulating layer 111 to further facilitate warpage control of the semiconductor package, thereby improving the physical and / or electrical reliability of the semiconductor package.

[0181] Protective layer 180 has raised portions 180B. Specifically, protective layer 180 has raised portions 180B that fill the concave-convex portions 111T provided on the upper surface of second layer 111-2 of first insulating layer 111. Thus, this embodiment can further improve the adhesion between protective layer 180 and insulating layer 110, thereby resolving the issue of protective layer 180 peeling off from insulating layer 110, and stably protect at least a portion of metal layer 140A through protective layer 180. Furthermore, because protective layer 180 is arranged to cover at least a portion of metal layer 140A, this embodiment can further prevent intermetallic compounds from penetrating into the interface between insulating layer 110 and metal layer 140A, thereby further improving the physical and / or mechanical reliability of the semiconductor package.

[0182] Figure 6 is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0183] refer to Figure 6 , the semiconductor package may be different from Figure 5 The difference is that the width of the opening in the protective layer is greater than the width of the metal layer 140A. Figure 5 The same configurations of the semiconductor packages are given the same reference numerals, and detailed descriptions thereof will be omitted.

[0184] The semiconductor package further includes a protection layer 180A disposed on the insulating layer 110 .

[0185] The protective layer 180A is disposed on the second layer 111-2 of the first insulating layer 111. In addition, the protective layer 180A is disposed on the metal layer 140A.

[0186] The protective layer 180A has an opening 180AR that vertically overlaps the metal layer 140A. The horizontal width of the opening 180AR may be greater than the horizontal width of the metal layer 140A. For example, the metal layer 140A may not contact the protective layer 180A.

[0187] Thus, this embodiment can increase the volume of the bonding portion 310 disposed on the metal layer 140A, thereby improving the bonding strength with the semiconductor device.

[0188] Figure 7 is a cross-sectional view showing a part of a region of a semiconductor package according to a fifth embodiment.

[0189] refer to Figure 7 , the semiconductor package may be different from Figure 6 The difference is that the metal layer has a structure that penetrates the protective layer and protrudes above the protective layer. Figure 6 The same configurations of the semiconductor packages are given the same reference numerals, and detailed descriptions thereof will be omitted.

[0190] The semiconductor package includes a metal layer 140B disposed on a pad portion 130A.

[0191] At this time, the metal layer 140B may be different from the previous embodiment in that the metal layer 140B is formed after the protective layer 180B is formed. Therefore, the metal layer 140B may penetrate the protective layer 180B while protruding above the protective layer 180B.

[0192] The width of the opening of the protective layer 180B is greater than that of the pad portion 130A. Therefore, an inner wall of the opening of the protective layer 180B and an inner wall of the through hole 111R1 provided in the second layer 111 - 2 of the first insulating layer 111 may have a step.

[0193] The metal layer 140B is disposed on the pad portion 130A. In addition, the metal layer 140B is disposed on the protective layer 180B. The metal layer 140B may protrude above the protective layer 180B while filling the opening of the protective layer 180B. Therefore, the metal layer 140B may be divided into a plurality of regions in the vertical direction.

[0194] Metal layer 140B may include a first portion 140B1 protruding above protective layer 180B. The horizontal width of first portion 140B1 of metal layer 140B is greater than the width of the opening of protective layer 180B. Therefore, at least a portion of first portion 140B1 of metal layer 140B contacts the upper surface of protective layer 180B. The side surface of first portion 140B1 of metal layer 140B may have a slope that increases in width downward.

[0195] Furthermore, the metal layer 140B includes a second portion 140B2 that penetrates the opening of the protective layer 180B and contacts an inner wall of the opening of the protective layer 180B.

[0196] Furthermore, the metal layer 140B includes a third portion 140B3 that fills a gap between the inner wall of the through hole 111R1 of the second layer 111 - 2 of the first insulating layer 111 and the first slope surface 130A- 2S1 of the pad portion 130A.

[0197] Therefore, the side surface of metal layer 140B may have steps in the horizontal direction. For example, the side surfaces of the first to third portions of metal layer 140B may have steps. As a result, this embodiment can further increase the contact area between metal layer 140B and protective layer 180B or pad portion 130A, thereby further improving the adhesion therebetween.

[0198] Furthermore, metal layer 140B protrudes above protective layer 180B, thereby improving the alignment between metal layer 140B and the terminals of the semiconductor device. For example, in this embodiment, when performing thermocompression bonding to reduce the volume of connecting members such as solder, the protrusion of metal layer 140B above protective layer 180B can improve the positional alignment between the terminals of the semiconductor device and metal layer 140B during the thermocompression bonding process.

[0199] Furthermore, in this embodiment, since the first insulating layer 111 includes the first layer 111-1 and the second layer 111-2, the flatness of the upper surface of the protective layer 180B disposed on the second layer 111-2 can be improved, thereby improving the flatness of the metal layer 140B disposed on the protective layer 180B.

[0200] Figure 8 is a cross-sectional view showing a part of a region of a semiconductor package according to a sixth embodiment.

[0201] refer to Figure 8 , the semiconductor package can be used with Figure 7 The difference is that the width of the opening of the protective layer is smaller than the width of the pad portion. Figure 7 The same configurations of the semiconductor packages are given the same reference numerals, and detailed descriptions thereof will be omitted.

[0202] Protective layer 180C is disposed on second layer 111-2 of first insulating layer 111 and pad portion 130A. The width of the opening of protective layer 180C is smaller than the width of the upper surface of second portion 130A-2 of pad portion 130A. Therefore, protective layer 180C may be disposed to fill the gap between the inner wall of through hole 111R1 of second layer 111-2 of first insulating layer 111 and first slope 130A-2S1 of the side surface of pad portion 130A.

[0203] The metal layer 140C is arranged on the pad portion 130A. In addition, the metal layer 140C is arranged on the protective layer 180C. At this time, the metal layer 140C includes a first portion 140C1 arranged on the protective layer 180C and a second portion 140C2 that penetrates the protective layer 180C. At this time, the width of the first portion 140C1 and the second portion 140C2 of the metal layer 140C is less than the width of the pad portion 130A. As a result, the present embodiment can further reduce the width of the metal layer 140C, thereby reducing the pitch between the adjacent multiple metal layers. In addition, when the pitch between adjacent metal layers remains the same as in the previous embodiment, the present embodiment can increase the spacing between adjacent metal layers, thereby solving the problem of electrical short circuit caused by the multiple metal layers being connected to each other.

[0204] Figure 9 is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

[0205] refer to Figure 9 ,and Figure 4 Compared with the semiconductor package of the second embodiment, the semiconductor package of the seventh embodiment may have a difference in the thickness of the second layer 111 - 2 of the first insulating layer 111 .

[0206] That is, the semiconductor package of the seventh embodiment has the insulating layer 110. The insulating layer 110 includes a first insulating layer 111 disposed on the uppermost side.

[0207] The first insulating layer 111 includes a first layer 111 - 1 having a reinforcing member and a second layer 111 - 2 having no reinforcing member.

[0208] At this time, the upper surface of the first layer 111-1 is positioned lower than the lower surface of the pad portion 130A. In addition, the lower surface of the second layer 111-2 is positioned lower than the lower surface of the pad portion 130A. Therefore, the pad portion 130A as a whole may not overlap with the reinforcing member of the pad portion 130A in the horizontal direction. For example, the pad portion 130A may not overlap with the first layer 111-1 of the first insulating layer 111 in the horizontal direction, and may overlap with the second layer 111-2 in the horizontal direction. In addition, at least a portion of the side surface of the second electrode portion 122 that passes through the first layer 111-1 may be surrounded by the second layer 111-2 of the first insulating layer 111.

[0209] Therefore, in this embodiment, the warping characteristics of the semiconductor package can be controlled by increasing the thickness of the second layer 111 - 2 of the first insulating layer 111 , thereby solving the problem of the semiconductor package being significantly bent in a specific direction.

[0210] The present embodiment can improve the flatness of a circuit board and a semiconductor package including the circuit board, and can stably mount a semiconductor device.

[0211] Specifically, the circuit board of this embodiment and the semiconductor package including the circuit board include an insulating layer containing a filler, a pad portion arranged on the insulating layer, and a metal layer arranged on the pad portion. In addition, the pad portion includes a first portion that overlaps with the filler of the insulating layer in the horizontal direction, and a second portion that does not overlap with the filler of the insulating layer in the horizontal direction. At this time, the insulating layer includes a first layer with a reinforcing member and a second layer without a reinforcing member. In addition, the first portion of the pad portion overlaps with the first layer of the insulating layer in the horizontal direction, and the second portion overlaps with the second layer of the insulating layer in the horizontal direction. Therefore, this embodiment can prevent the reinforcing member from being arranged on the second layer, thereby making the height of the upper surface of the second layer uniform as a whole.

[0212] Furthermore, the present embodiment can improve the adhesion between the metal layer disposed on the pad portion and the insulating layer.

[0213] That is, the upper surface of the insulating layer is positioned lower than the upper surface of the pad portion. Furthermore, the upper surface of the insulating layer is positioned higher than the lower surface of the pad portion. That is, at least a portion of the pad portion is embedded in the insulating layer, and at least the remaining portion protrudes above the insulating layer. To this end, this embodiment performs a thickness reduction process by etching a portion of the insulating layer while the upper surface of the insulating layer is positioned higher than the upper surface of the pad portion.

[0214] At this time, if the reinforcing member is provided throughout the entire area of ​​the insulating layer, the flatness of the upper surface of the insulating layer may be reduced during the process of etching the insulating layer to reduce its thickness. In other words, if the process of etching the insulating layer to reduce its thickness is performed while the reinforcing member is provided throughout the entire area of ​​the insulating layer, the reinforcing member provided in the insulating layer may be exposed to the upper surface of the insulating layer. Furthermore, if the reinforcing member provided in the insulating layer is exposed to this upper surface, the adhesion between the insulating layer and the metal layer described later may be reduced. For example, the adhesion between the reinforcing member and the metal layer may be weaker than the adhesion between the resin of the insulating layer and the metal layer. Due to this, the adhesion between the insulating layer and the metal layer may be reduced, and the metal layer may be peeled off from the insulating layer. In addition, when the metal layer contacts the reinforcing member, due to the relatively high dielectric constant of the reinforcing member, the electrical signals and / or power transmitted through the metal layer may be lost.

[0215] Furthermore, when a process of etching the insulating layer to reduce its thickness is performed while reinforcing members are provided throughout the entire region of the insulating layer, at least some of the reinforcing members provided in the insulating layer may be removed, thereby potentially forming a recessed portion on the upper surface of the insulating layer. The recessed portion is the space created by the removal of the reinforcing members. In this case, the recessed portion may have a greater depth than other portions of the upper surface of the insulating layer. Due to this, when a recessed portion exists on the upper surface of the insulating layer, the following problem may arise: namely, the metal layer may not be able to completely fill the recessed portion, thereby potentially forming a gap between the insulating layer and the metal layer. Furthermore, when a recessed portion having a relatively large depth exists on the upper surface of the insulating layer, the stress acting on the insulating layer may be concentrated on the recessed portion, which may reduce the physical reliability and / or electrical reliability of the semiconductor package.

[0216] In contrast, the insulating layer of the embodiment includes a first layer and a second layer. Furthermore, the first layer of the insulating layer includes a resin and a reinforcing member, while the second layer does not include a reinforcing member but only includes the resin. Therefore, the embodiment can prevent the reinforcing member from being exposed on the upper surface of the insulating layer after etching, thereby making the height of the upper surface of the insulating layer uniform.

[0217] Therefore, the embodiment can improve the flatness of the circuit board and the semiconductor package including the circuit board. In addition, the metal layer arranged on the pad portion does not contact the reinforcing member. Therefore, the embodiment can improve the electrical characteristics of the metal layer while enhancing the adhesion between the metal layer and the insulating layer.

[0218] In addition, the embodiments can prevent stress from being concentrated at a specific location on the upper surface of the insulating layer by ensuring that the upper surface of the insulating layer has a uniform height. Further, the stress can be evenly distributed over the entire area, thereby improving the physical and electrical reliability of the semiconductor package.

[0219] Furthermore, the embodiment can prevent a bonding portion disposed on a metal layer from penetrating into a gap between the metal layer and the insulating layer by enhancing adhesion between the metal layer and the insulating layer.

[0220] Therefore, the embodiment can suppress the formation of a relatively brittle intermetallic compound (IMC) between the bonding portion and the pad portion, thereby improving the physical and electrical reliability of the semiconductor package.

[0221] Furthermore, the embodiment can prevent the semiconductor package from being greatly warped in a specific direction by providing the first layer with the reinforcement member and the second layer without the reinforcement member as an insulating layer, thereby stably mounting the semiconductor device and further stably operating the semiconductor device.

[0222] Specifically, the circuit board and the semiconductor package including the circuit board may warp significantly in a specific direction. This may be due to the difference in thermal expansion coefficient between the insulating layer and the protective layer, the difference in thickness of each layer in the insulating layer, the difference in density of the electrode portion arranged on the surface of each layer of the insulating layer, and the difference in thickness of the electrode portion arranged on the surface of each layer of the insulating layer. At this time, the embodiment provides a second layer of the insulating layer without a reinforcement member on the uppermost side of the circuit board. The second layer of the insulating layer may have a thermal expansion coefficient matching function, which alleviates the difference in thermal expansion coefficient between different insulating layers, thereby preventing the circuit board from warping significantly in a specific direction. For example, in a state where the second layer is not provided on the insulating layer, the circuit board may warp downward at both ends. At this time, the second layer provided on the insulating layer can cause the two ends of the circuit board to warp upward, thereby ultimately allowing the circuit board to maintain a flat state without warping.

[0223] Furthermore, a concavo-convex portion is provided on the upper surface of the second layer of the insulating layer. This concavo-convex portion can be provided on the upper surface of the second layer during the process of etching the second layer of the insulating layer to reduce the thickness of the second layer. In this case, the embodiment forms the concavo-convex portion by etching the second layer of the insulating layer without the reinforcement member. Therefore, the reinforcement member is not exposed through the concavo-convex portion, thereby allowing the concavo-convex portion to have a uniform depth on the upper surface of the second layer. The concavo-convex portion contacts at least a portion of the metal layer arranged on the pad portion. As a result, the embodiment can further improve the adhesion between the insulating layer and the metal layer.

[0224] In this case, the concave-convex portion has a specific curvature. In this case, the curvature of the concave-convex portion is different from the curvature of the reinforcing member provided in the first layer of the insulating layer. Here, the different curvature may mean that the reinforcing member is not exposed upward through the concave-convex portion. Alternatively, the different curvature may also mean that: in the process of etching the insulating layer to reduce the thickness of the insulating layer, the reinforcing member is not removed from the insulating layer, and therefore, the concave-convex portion does not include a portion formed by removing the reinforcing member. Thus, the embodiment can improve the physical reliability and / or electrical reliability of the semiconductor package.

[0225] Figures 10 to 24 The process sequence is shown Figure 1 FIG. 1 shows a method for manufacturing a semiconductor package.

[0226] Reference Figure 10This embodiment prepares an insulating member serving as a foundation for manufacturing a circuit board. This insulating member may be a carrier board CB. For example, the carrier board CB may include a carrier insulating layer CB1 and carrier metal layers CB2 and CB3. The carrier metal layers CB2 and CB3 may have a two-layer structure. For example, the carrier metal layers CB2 and CB3 may be metal layers comprising different metal materials. The first carrier metal layer CB2 may be disposed below the carrier insulating layer CB1. The first carrier metal layer CB2 may comprise a first metal material. The first metal material may comprise copper. The carrier insulating layer CB1 and the first carrier metal layer CB2 may be a copper-clad laminate (CCL). The second carrier metal layer CB3 may be disposed below the first carrier metal layer CB2. The second carrier metal layer CB3 may comprise a second metal material different from the first metal material. The second metal material may comprise nickel. For example, the second carrier metal layer CB2 may be made of a metal material that is not etched by the etching solution used to etch the first metal material. Thus, this embodiment can prevent the pad portion 130 from being etched during the seed layer etching process included in the circuit board manufacturing process. Thus, this embodiment can minimize the height difference between the plurality of first pads and the plurality of second pads of the pad portion 130. Figure 10 The first and second carrier metal layers CB2 and CB3 are shown as being arranged on one surface of the carrier insulating layer CB1, but the present embodiment is not limited thereto. For example, the first and second carrier metal layers CB2 and CB3 may be arranged on both sides of the carrier insulating layer CB1, respectively. In this case, a process of simultaneously manufacturing multiple circuit boards on both sides of the carrier insulating layer CB1 can be performed.

[0227] Reference Figure 11 In this embodiment, a process of forming the pad portion 130 on the second carrier metal layer CB3 may be performed. The pad portion 130 may be formed by electroplating on the second carrier metal layer CB3 as a seed layer.

[0228] Reference Figure 12 In this embodiment, a process of laminating a second layer 111-2 of the first insulating layer 111 on the second carrier metal layer CB3 may be performed, with the second layer 111-2 covering a portion of the pad portion 130. The second layer 111-2 does not have a reinforcing member. In this case, after the second layer 111-2 is arranged to completely cover the pad portion 130, a process of etching the second layer to reduce its thickness may be performed so that it covers a portion of the side surface of the pad portion 130.

[0229] Next, refer to Figure 13, the present embodiment may perform a process of stacking the first layer 111-1 of the first insulating layer 111 on the second layer 111-2. At this time, although it is shown that the first layer 111-1 and the second layer 111-2 are stacked separately, the present embodiment is not limited thereto. For example, if the first layer 111-1 and the second layer 111-2 are provided as a single layer, the process may be performed at once. Figure 12 and Figure 13 The process in.

[0230] Next, refer to Figure 14 In this embodiment, a process of forming the electrode portion 120 on the first insulating layer 111 may be performed. When forming the electrode portion 120, the embodiment may form a recessed portion 111T on the surface of the first layer 111-1 of the first insulating layer 111. The recessed portion 111T may be provided to surround the portion of the electrode portion that vertically overlaps with the connection member 200.

[0231] Next, refer to Figure 15 , the present embodiment may perform a process of arranging the bonding member 220 on the electrode portion using the recessed portion 111T as an alignment mark and a process of attaching the connection member 200 .

[0232] Next, refer to Figure 16 , this embodiment can manufacture a multi-layer substrate by repeatedly performing an insulating layer stacking process and an electrode portion forming process.

[0233] Next, refer to Figure 17 In this embodiment, a process of removing the carrier board CB can be performed. To this end, a process of removing the carrier insulating layer CB1 can be performed. Subsequently, a process of removing the first carrier metal layer CB2 can be performed. In this case, the second carrier metal layer CB3 comprises a different metal material than the first carrier metal layer CB2 and therefore may not be removed during the process of removing the first carrier metal layer CB2.

[0234] Next, refer to Figure 18 In this embodiment, the second carrier metal layer CB3 may be removed by etching. In this case, the second carrier metal layer CB3 includes a different metal material from the pad portion 130, so the pad portion 130 may not be removed during the process of removing the second carrier metal layer CB3.

[0235] Next, refer to Figure 19In this embodiment, a process of removing a portion of the second layer 111-2 of the first insulating layer 111 by etching to reduce the thickness of the second layer 111-2 can be performed. Therefore, the upper surface of the second layer 111-2 of the first insulating layer 111 can be positioned lower than the upper surface of the pad portion 130. In addition, the second layer 111-2 is not provided with a reinforcement member. Therefore, the pad portion 130 includes a region that overlaps with the second layer 111-2 in the horizontal direction but does not overlap with the reinforcement member in the horizontal direction.

[0236] In this manner, the present embodiment may form the first insulating layer 111 positioned lower than the upper surface of the pad portion 130 , including the first layer 111 - 1 provided with the reinforcement member and the second layer 111 - 2 without the reinforcement member.

[0237] At this time, Figures 10 to 19 , the substrate manufacturing process is performed in a state where the second layer 111 - 2 of the first insulating layer 111 is preferentially stacked, but it is not limited thereto.

[0238] For example, this embodiment can omit Figure 12 The process of stacking the second layer 111-2 of the first insulating layer 111 is omitted, and the process of stacking the first layer 111-1 is directly performed. In this case, as Figure 20 As shown, after the carrier plate is removed, the first layer 111 - 1 of the first insulating layer 111 may be disposed to entirely cover the side surface of the pad part 130 .

[0239] Next, refer to Figure 21 In this embodiment, the first layer 111 - 1 of the first insulating layer 111 may be removed by etching to reduce the thickness of the first layer. Therefore, the first layer 111 - 1 of the first insulating layer 111 is positioned lower than the upper surface of the pad portion 130 .

[0240] Afterwards, refer to Figure 22 In this embodiment, a process of stacking the second layer 111 - 2 on the first layer 111 - 1 of the first insulating layer 111 is performed. At this time, the second layer 111 - 2 may be provided to entirely cover the upper surface of the pad portion 130 .

[0241] Next, refer to Figure 23 In this embodiment, the second layer 111 - 2 may be removed by etching to reduce the thickness of the second layer. Therefore, the upper surface of the second layer 111 - 2 may be positioned lower than the upper surface of the pad portion 130 .

[0242] Next, refer to Figure 24, this embodiment may perform a process of forming metal layer 140 on pad portion 130 . In addition, this embodiment may perform a process of forming protection layer 170 under fourth insulating layer 114 and a process of forming lower metal layer 160 under lower pad portion 150 .

[0243] On the other hand, when the circuit board having the above-mentioned characteristics of the present invention is used in IT equipment or household appliances such as smart phones, server computers, and televisions, functions such as signal transmission or power supply can be stably performed. For example, when the circuit board having the characteristics of the present invention performs the semiconductor packaging function, the circuit board can be used to safely protect the semiconductor chip from external moisture or pollutants, or alternatively, it can solve the problems of leakage current, electrical short circuit between terminals, and electrical open circuit of terminals that supply power to the semiconductor chip. In addition, when assuming the signal transmission function, the noise problem can be solved. Thus, the circuit board having the above-mentioned characteristics of the present invention can maintain the stable function of IT equipment or household appliances, so that the entire product and the circuit board to which the present invention is applied can achieve functional integrity or technical linkage with each other.

[0244] When a circuit board having the aforementioned characteristics of the present invention is used in transportation equipment such as vehicles, it can resolve distortion issues in signals transmitted to the transportation equipment. Alternatively, it can further enhance the safety of the transportation equipment by safely protecting the semiconductor chips controlling the transportation equipment from external influences and addressing issues such as leakage current, electrical shorts between terminals, or electrical opens in terminals supplying power to the semiconductor chips. Consequently, the transportation equipment and the circuit board incorporating the present invention can achieve functional integration or technical linkage.

[0245] The characteristics, structures, and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. In addition, the characteristics, structures, and effects shown in each of these embodiments can even be combined or modified with respect to other embodiments by a person skilled in the art to which the embodiments belong. Therefore, it should be understood that the contents related to such combinations and such modifications are included in the scope of the embodiments.

[0246] The above description focuses on the embodiments, but it is only illustrative and not intended to limit the embodiments. Those skilled in the art will appreciate that various modifications and applications not shown above can be made without departing from the essential features of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. Furthermore, it should be understood that differences associated with such variations and applications are included within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: an insulating layer comprising a first layer having a first filler and a second layer disposed on the first layer; a pad portion, the pad portion being arranged on the insulating layer; as well as a metal layer disposed on the pad portion, The pad portion includes a first portion overlapping with the first filler of the first layer of the insulating layer along a horizontal direction, and a second portion not overlapping with the first filler of the first layer along the horizontal direction.

2. The circuit board according to claim 1, wherein The resin of the first layer and the resin of the second layer of the insulating layer include the same insulating material.

3. The circuit board according to claim 1, wherein The resin of the first layer and the resin of the second layer of the insulating layer include different insulating materials.

4. The circuit board according to claim 1, wherein The second layer of the insulating layer includes a second filler.

5. The circuit board according to claim 4, wherein The diameter of the first filler is the same as the diameter of the second filler.

6. The circuit board according to claim 4, wherein A content of the first filler in the first layer of the insulating layer is greater than a content of the second filler in the second layer.

7. The circuit board according to claim 4, wherein The diameter of the second filler is smaller than the diameter of the first filler.

8. The circuit board according to claim 2, wherein: The resin of each of the first layer and the second layer includes one of ABF (Ajinomoto build-up film), FR-4, BT (bismaleimide triazine), and PID (photo-imaging dielectric resin).

9. The circuit board according to any one of claims 1 to 8, wherein: The pad portion is arranged in a recess provided at the upper surface of the insulating layer.

10. The circuit board according to claim 9, wherein The recess has a through hole penetrating the second layer of the insulating layer, and Wherein, the pad portion is arranged in the through hole.

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