Power amplification system, digital pre-distortion method and digital pre-distortion circuit

Abstract

A power amplification system (7) is provided with: a power amplifier (2); an output switching circuit (30) configured to selectively output at least one of the plurality of discrete voltages to the power amplifier (2); a first filter circuit (41) connected to a path (44) connecting the output switching circuit (30) and the power amplifier (2); a second filter circuit (42) that is switchably connected to the path (44); and a DPD circuit (71) configured so as to predistort the input signal of the power amplifier (2), (i) when the second filter circuit (42) is not connected to the path (44), the DPD circuit (71) predistorts the input signal of the power amplifier (2) using a first parameter set in a first mathematical model, and (ii) when the second filter circuit (42) is connected to the path (44), the DPD circuit (71) predistorts the input signal of the power amplifier (2) using a second parameter set in a second mathematical model. The DPD circuit (71) predistorts the input signal of the power amplifier (2) using a second set of parameters in a second mathematical model, the first and second sets of parameters being at least partially different from each other.

Description

Technical Field

[0001] The invention relates to a power amplification system, a digital predistortion method and a digital predistortion circuit. Background Art

[0002] In recent years, improvements in power added efficiency have been achieved by applying tracking technology to power amplifier circuits. Patent Document 1 discloses a tracking circuit for digital envelope tracking (D-ET), which supplies a power supply voltage that changes over time to multiple discrete levels (hereinafter referred to as "discrete voltages"). Furthermore, Patent Document 2 discloses a tracking circuit for symbol power tracking (SPT), which supplies multiple discrete voltages.

[0003] Patent Document 1: U.S. Patent No. 8,829,993

[0004] Patent Document 2: U.S. Patent No. 10,686,407

[0005] When supplying multiple discrete voltages to a power amplifier, digital pre-distortion (DPD) is used to reduce the nonlinear distortion caused by the power amplifier operating in a nonlinear region. DPD reduces the nonlinear distortion generated in the power amplifier by pre-distorting the input signal to the power amplifier. However, when supplying multiple discrete voltages to the power amplifier, further reduction of nonlinear distortion is desired. Summary of the Invention

[0006] Therefore, the present invention provides a power amplification system, a digital predistortion method, and a digital predistortion circuit, which can reduce nonlinear distortion.

[0007] A power amplifier system according to one embodiment of the present invention includes: a first power amplifier; an output switching circuit configured to selectively output at least one of a plurality of discrete voltages to the first power amplifier; a filter circuit switchably connected to a first path connecting the output switching circuit and the first power amplifier; and a digital predistortion circuit configured to predistort a first input signal of the first power amplifier, wherein: (i) when the filter circuit is not connected to the first path, the digital predistortion circuit predistorts the first input signal using a first parameter set in a first mathematical model; and (ii) when the filter circuit is connected to the first path, the digital predistortion circuit predistorts the first input signal using a second parameter set in a second mathematical model, wherein the first parameter set and the second parameter set are at least partially different from each other.

[0008] In a digital predistortion method according to one embodiment of the present invention, a mathematical model and a parameter set for digital predistortion are determined based on the attenuation band of a variable filter circuit connected between an output switching circuit and a power amplifier. The output switching circuit selectively supplies at least one of a plurality of discrete voltages to the power amplifier, and the input signal of the power amplifier is predistorted using the parameter set determined in the determined mathematical model.

[0009] A digital predistortion circuit according to one embodiment of the present invention includes: (i) a first path for selectively supplying at least one of a plurality of discrete voltages to a first power amplifier; and when a filter circuit switchably connected to the first path is not connected to the first path, the digital predistortion circuit predistorts a first input signal of the first power amplifier using a first parameter set in a first mathematical model; and (ii) when the filter circuit is connected to the first path, the digital predistortion circuit predistorts the first input signal using a second parameter set in a second mathematical model, wherein the first parameter set and the second parameter set are at least partially different from each other.

[0010] According to a power amplification system and the like involved in one technical solution of the present invention, nonlinear distortion can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A This is a graph showing an example of the transition of the power supply voltage in the APT (Average Power Tracking) mode.

[0012] Figure 1B This is a graph showing an example of the transition of the power supply voltage in the A-ET (Analog Envelope Tracking) mode.

[0013] Figure 1C This is a graph showing an example of the transition of the power supply voltage in the D-ET mode.

[0014] Figure 2 This is a circuit configuration diagram of the communication device according to Embodiment 1.

[0015] Figure 3 This is a circuit configuration diagram of the tracking circuit according to the first embodiment.

[0016] Figure 4 This is a flowchart showing the DPD method according to the first embodiment.

[0017] Figure 5 This is a partial circuit configuration diagram of a tracking circuit according to Modification 1 of Embodiment 1.

[0018] Figure 6This is a partial circuit configuration diagram of a tracking circuit according to a second modification of the first embodiment.

[0019] Figure 7 This is a partial circuit configuration diagram of a tracking circuit according to Modification 3 of Embodiment 1.

[0020] Figure 8 This is a circuit configuration diagram of a communication device according to Embodiment 2.

[0021] Figure 9 This is a circuit configuration diagram of a tracking circuit according to the second embodiment.

[0022] Figure 10 This is a partial circuit configuration diagram of a tracking circuit according to Modification 1 of Embodiment 2.

[0023] Figure 11 This is a partial circuit configuration diagram of a tracking circuit according to a second variation of the second embodiment.

[0024] Figure 12 This is a circuit configuration diagram of a communication device according to Embodiment 3.

[0025] Figure 13 This is a circuit configuration diagram of a tracking circuit according to the third embodiment.

[0026] Figure 14 This is a partial circuit configuration diagram of a tracking circuit according to Modification 1 of Embodiment 3. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments of the present invention will be described in detail using the accompanying drawings. Furthermore, the embodiments described below are general or specific examples. The numerical values, shapes, materials, components, configurations of components, and connection methods shown in the following embodiments are merely examples and do not limit the present invention.

[0028] In addition, each figure is a schematic diagram in which emphasis, omission, or ratio adjustment are appropriately performed to illustrate the present invention, and is not necessarily a strict illustration, and may differ from the actual shape, positional relationship, and ratio. In each figure, substantially the same structure is marked with the same reference numerals, and repeated descriptions may be omitted or simplified.

[0029] In the circuit structure of the present invention, "connection" includes not only direct connection using connection terminals and / or wiring conductors, but also electrical connection via other circuit elements. "Direct connection" means direct connection using connection terminals and / or wiring conductors without passing through other circuit elements. "C is connected between A and B" means that one end of C is connected to A and the other end of C is connected to B, which means that it is connected in series with the path connecting A and B. "The path connecting A and B" means a path composed of conductors that electrically connect A and B.

[0030] Furthermore, "A is connected to the path" encompasses not only the case where one end of A is connected to one end of the path and the other end of A is connected to the other end of the path (hereinafter also referred to as a series connection), but also the case where one end of A is connected to the path and the other end of A is grounded (hereinafter also referred to as a shunt connection). "A is switchably connected to the path" means that the connection and disconnection between A and the path can be switched, meaning that A is connected to the path via a switch. Furthermore, "A is connected to the path" encompasses "A is switchably connected to the path."

[0031] In the following description, a "terminal" means a point where a conductor within an element ends. Furthermore, when the impedance of the conductors between elements is sufficiently low, a terminal is interpreted not only as a single point but also as any point on the conductors between elements or as the entire conductor.

[0032] The “attenuation band of the filter circuit” means the portion of the frequency spectrum attenuated by the filter circuit, and is defined as a frequency band where the output power is attenuated by 15 dB or more compared to the maximum output power.

[0033] In addition, terms such as "parallel" and "perpendicular" that indicate the relationship between elements, terms such as "rectangular" that indicate the shape of an element, and numerical ranges mean not only strict meanings but also include substantially equivalent ranges, such as errors of several percent.

[0034] First, as a technology for efficiently amplifying high-frequency signals, we will explain the tracking mode, which supplies a power supply voltage dynamically adjusted over time based on the high-frequency signal to a power amplifier. Tracking mode refers to a mode in which the power supply voltage applied to the power amplifier is dynamically adjusted. There are several types of tracking modes, but here we will refer to Figures 1A to 1C The APT mode, A-ET mode and D-ET mode are explained. Figures 1A to 1C In FIG, the horizontal axis represents time and the vertical axis represents voltage. In addition, the thick solid line represents the power supply voltage, and the thin solid line (waveform) represents the modulation wave.

[0035] Figure 1AThis is a graph showing an example of the power supply voltage transition in the APT mode. In the APT mode, the power supply voltage is varied to a plurality of discrete voltage levels per frame based on average power. As a result, the power supply voltage signal forms a rectangular wave.

[0036] A frame is the unit that makes up a high-frequency signal (modulated wave). For example, in 5GNR (5th Generation New Radio) and LTE (Long Term Evolution), a frame consists of 10 subframes, each of which contains multiple time slots, and each time slot consists of multiple symbols. A subframe is 1ms long, and a frame is 10ms long.

[0037] Furthermore, a mode in which the voltage level is varied in units of one frame or larger based on average power is called an APT mode, to distinguish it from a mode in which the voltage level is varied in units smaller than one frame (eg, subframe, slot, or symbol).

[0038] Figure 1B : is a graph showing an example of the transition of the power supply voltage in the A-ET mode. In the A-ET mode, the power supply voltage is continuously varied based on the envelope signal to track the envelope of the modulation wave.

[0039] The envelope signal is a signal representing the envelope of the modulated wave. The envelope value is, for example, (I 2 +Q 2 ). Here, (I, Q) represents a constellation point. A constellation point is a point on a constellation diagram that represents a digitally modulated signal. (I, Q) is determined by the baseband integrated circuit (IC) based on transmission information, for example.

[0040] Figure 1C This graph shows an example of the power supply voltage transition in ET mode. In D-ET mode, the power supply voltage is varied to multiple discrete voltage levels within a frame based on an envelope signal, thereby tracking the envelope of the modulated wave. As a result, the power supply voltage signal forms a rectangular wave.

[0041] (Implementation Method 1)

[0042] Hereinafter, embodiment 1 will be described.

[0043] [1.1 Circuit Structure of Communication Device 6]

[0044] First, refer to Figure 2 Next, the circuit configuration of the communication device 6 according to this embodiment will be described. Figure 2 It is a circuit configuration diagram of the communication device 6 according to this embodiment.

[0045] also, Figure 2 This is an exemplary circuit configuration, and the communication device 6 can be implemented using any of a variety of circuit implementations and circuit technologies. Therefore, the description of the communication device 6 provided below should not be interpreted in a limiting sense.

[0046] The communication device 6 involved in this embodiment corresponds to a user equipment (UE) in a cellular network, typically a mobile phone, smartphone, tablet computer, wearable device, etc. Furthermore, the communication device 6 may also be an IoT (Internet of Things) sensor device, medical / healthcare equipment, an unmanned aerial vehicle (UAV) (so-called drone), or an automated guided vehicle (AGV). Furthermore, the communication device 6 may also function as a base station (BS) in a cellular network.

[0047] like Figure 2 As shown, the communication device 6 includes a tracking circuit 1, a power amplifier 2, an RFIC (Radio Frequency Integrated Circuit) 3, a BBIC 4, and an antenna 5. The power amplifier system 7 also includes the tracking circuit 1, the power amplifier 2, and the RFIC 3.

[0048] The tracking circuit 1 can supply a plurality of discrete voltages as the power supply voltage Vcc to the power amplifier 2 in the tracking mode. In this embodiment, the D-ET mode and the APT mode are used as the tracking mode, but the present invention is not limited thereto.

[0049] The power amplifier 2 is an example of a first power amplifier and is connected between the RFIC 3 and the antenna 5. The power amplifier 2 is also connected to the tracking circuit 1. The power amplifier 2 can amplify the high-frequency signal RF (an example of a first input signal) supplied from the RFIC 3 using the power supply voltage Vcc supplied from the tracking circuit 1.

[0050] RFIC 3 is an example of a signal processing circuit that processes a high-frequency signal. RFIC 3 can receive a digital IQ signal from BBIC 4 and supply a high-frequency signal RF to the power amplifier 2. The internal structure of RFIC 3 will be described later.

[0051] BBIC 4 is a baseband signal processing circuit that performs signal processing using a frequency band lower than the high-frequency signal RF. For example, BBIC 4 digitally modulates bit sequences representing image signals for display and / or audio signals for communication via a speaker, generating digital IQ signals. These generated digital IQ signals are supplied to RFIC 3. BBIC 4 may not be included in communication device 6.

[0052] The antenna 5 transmits the high-frequency signal RF amplified by the power amplifier 2 to the outside of the communication device 6. In addition, the antenna 5 may not be included in the communication device 6.

[0053] [1.2 Internal structure of RFIC3]

[0054] While referring to Figure 2 The internal structure of RFIC 3 will be described. RFIC 3 includes a DPD circuit 71, a digital-to-analog converter (DAC) 72, and a quadrature modulator 73. RFIC 3 may also include a control unit (not shown) for controlling tracking circuit 1. Furthermore, some or all of the functions of RFIC 3 as a control unit may be implemented externally.

[0055] The DPD circuit 71 can predistort the digital IQ signal supplied from the BBIC 4 using a mathematical model for DPD. For example, the DPD circuit 71 can generate a digital IQ signal that has been predistorted from the digital IQ signal. The predistorted digital IQ signal is supplied to the DAC 72. Alternatively, the DPD circuit 71 can skip the DPD process. In this case, the DPD circuit 71 can supply the digital IQ signal supplied from the BBIC 4 (i.e., the non-predistorted digital IQ signal) to the DAC 72.

[0056] The DAC 72 can convert the digital IQ signal supplied from the DPD circuit 71 into an analog IQ signal. The converted analog IQ signal is supplied to the quadrature modulator 73. A conventional DAC can be used as the DAC 72, and there is no need to limit it in particular.

[0057] The quadrature modulator 73 can generate a high-frequency signal RF by performing quadrature modulation and up-conversion on the analog IQ signal supplied from the DAC 72. The generated high-frequency signal RF is supplied to the power amplifier 2. A conventional quadrature modulator can be used as the quadrature modulator 73, and there is no particular limitation.

[0058] also, Figure 2The circuit configuration of RFIC 3 is an example and is not limited thereto. For example, part or all of the DPD circuit 71, DAC 72, and quadrature modulator 73 may not be included in RFIC 3. For example, the DPD circuit 71 may be included in BBIC 4.

[0059] Here, a description will be given of a mathematical model used for DPD in the DPD circuit 71. In this embodiment, as the mathematical model used for DPD, a mathematical model that incorporates memory effects or a mathematical model that does not incorporate memory effects can be used.

[0060] The memory effect is defined as the change in distortion of a power amplifier due to past input signals. Therefore, a mathematical model incorporating the memory effect models not only the distortion due to the current input signal but also the change in distortion due to past input signals. Therefore, while a mathematical model incorporating the memory effect can reduce nonlinear distortion compared to a mathematical model without the memory effect, the computational load increases.

[0061] Here, a specific example of a mathematical model that does not incorporate the memory effect will be described.

[0062] [Mathematical formula 1]

[0063]

[0064] x[n]:predistorted signal

[0065] r[n]:original input signal

[0066] c i :DPD coefficients

[0067] N:polynomial order

[0068] The above equation (1) is an example of a polynomial used in a mathematical model that does not incorporate memory effects. A mathematical model using equation (1) is called a memoryless polynomial model. In equation (1), the current input signal r[n] is multiplied by the exponentially scaled input signal. The polynomial degree N and the DPD coefficient c are i It is a parameter set of the memoryless polynomial model, which can be predetermined through experiments and / or experience, and is, for example, stored in advance in a memory (not shown) included in RFIC3.

[0069] In equation (1), increasing the polynomial degree N can reduce nonlinear distortion, but there is a concern about an increase in computational load. Furthermore, since equation (1) does not take into account memory effects, it is limited in reducing nonlinear distortion in memoryless polynomial models.

[0070] Next, a specific example of a mathematical model incorporating the memory effect will be described.

[0071] [Mathematical formula 2]

[0072]

[0073] x[n]:predistorted signal

[0074] r[n]:original input signal

[0075] c qi :DPD coefficients

[0076] Q: memory depth

[0077] N:polymomial order

[0078] The above formula (2) is an example of a polynomial used in a mathematical model that incorporates memory effects. A mathematical model using formula (2) is called a memory polynomial model (MPM). In formula (2), for each input signal r[nq] from the past Q to the current 0, the input signal is multiplied by the exponential input signal. The polynomial degree N, the memory depth Q, and the DPD coefficient c are qi The parameter set for the MPM can be predetermined through experiments and / or experience, and can be stored in advance in a memory (not shown) included in the RFIC 3 , for example.

[0079] In formula (2), if the polynomial degree N and the memory depth Q increase, the nonlinear distortion is expected to decrease, but there are concerns about the increase in the number of parameters, the increase in the computational load, and the DPD coefficient c. qi The reduction of convergence in decision making.

[0080] [Mathematical formula 3]

[0081]

[0082] x[n]:predistorted signal

[0083] r[n]:original input signal

[0084] c qi , d qmi , e qmi :DPD coefficients

[0085] Q:sync memory depth

[0086] N:sync order

[0087] Q d :lag memory depth

[0088] M d :maximum lag

[0089] N d :lag order

[0090] Q e :lead memory depth

[0091] M e :maximum lead

[0092] N e :lead order

[0093] The above formula (3) is another example of a polynomial used in a mathematical model that incorporates memory effects. The mathematical model using formula (3) is called a generalized memory polynomial model (GMP). In formula (3), the sync term (3-1) is combined with the Lag term (3-2) and the Lead term (3-3). The sync term (3-1) is the same as the term in formula (2) used for MPM. In the Lag term (3-2), the input signal is multiplied by the past input signal after exponentialization. In the Lead term (3-3), the input signal is multiplied by the future input signal after exponentialization. The order of each term N, N d and N e , memory depth Q and DPD coefficient c qi d qmi and e qmi The parameter set for GMP can be predetermined through experiments and / or experience, and can be stored in advance in a memory (not shown) included in the RFIC 3 , for example.

[0094] In formula (3), if the memory depth of each item is Q, Q d , Q e and cross width M d 、M eIf the nonlinear distortion is increased, it can be expected to decrease, but there are concerns about the increase in the number of parameters, the increase in the calculation load, and the DPD coefficient c qi d qmi and e qmi The reduction of convergence in decision making.

[0095] The effect of reducing nonlinear distortion increases in the order of the memoryless polynomial model, MPM, and GMP, but the number of parameters increases, and the computational load (i.e., power consumption) also increases. Specifically, the GMP model reduces nonlinear distortion compared to the MPM and the memoryless polynomial model, while the MPM reduces nonlinear distortion compared to the memoryless polynomial model. Conversely, the memoryless polynomial model reduces the computational load compared to the MPM and GMP, while the MPM reduces the computational load compared to the GMP. Furthermore, the memoryless polynomial model reduces the amount of memory required to store parameters compared to the MPM and GMP, while the MPM reduces the amount of memory required to store parameters compared to the GMP.

[0096] Furthermore, mathematical models that incorporate memory effects are not limited to MPM and GMP. In other words, mathematical models that incorporate memory effects can use mathematical formulas other than equations (2) and (3). Furthermore, mathematical models that do not incorporate memory effects are not limited to memoryless polynomial models. In other words, mathematical models that incorporate memory effects can use mathematical formulas other than equation (1).

[0097] [1.3 Circuit Structure of Tracking Circuit 1]

[0098] Next, refer to Figure 2 The circuit configuration of the tracking circuit 1 will be described. The tracking circuit 1 includes a pre-regulator circuit 10 , a switched capacitor circuit 20 , an output switch circuit 30 , a first filter circuit 41 , a second filter circuit 42 , switches S56 and S57 , and a digital control circuit 60 .

[0099] The pre-regulator circuit 10 is capable of converting an input voltage supplied from a DC power supply (not shown) into a regulated voltage using a power inductor. The pre-regulator circuit 10 includes a power inductor and a switch. A power inductor refers to an inductor used for stepping up and / or stepping down a DC (Direct Current) voltage. The power inductor is configured in series in the DC path. In addition, the power inductor can also be connected between the DC path and the ground (i.e., configured in parallel in the DC path). Such a pre-regulator circuit 10 is sometimes also referred to as a magnetic regulator or a DC / DC converter.

[0100] The switched capacitor circuit 20 includes a plurality of capacitors and a plurality of switches, and can generate a plurality of discrete voltages each having a plurality of discrete voltage levels based on the voltage supplied from the pre-regulator circuit 10. The switched capacitor circuit 20 is sometimes also referred to as a switched-capacitor voltage balancer.

[0101] The output switch circuit 30 is capable of selectively outputting at least one of the plurality of discrete voltages generated by the switched capacitor circuit 20 to the power amplifier 2 .

[0102] The first filter circuit 41 and the second filter circuit 42 can attenuate noise from the multiple discrete voltages supplied to the power amplifier 2. The first filter circuit 41 and the second filter circuit 42 are sometimes referred to as pulse shaping networks or transition shaping filters. Furthermore, one of the first filter circuit 41 and the second filter circuit 42 may not be included in the tracking circuit 1. Conversely, only one of the first filter circuit 41 and the second filter circuit 42 may be included in the tracking circuit 1.

[0103] Switches S56 and S57 are examples of a first switch and a second switch, respectively, and serve as on / off switches for the first filter circuit 41 and the second filter circuit 42. Switch S56 is connected between the output switch circuit 30 and the first filter circuit 41. Switch S57 is connected between the output switch circuit 30 and the second filter circuit 42. Furthermore, one of switches S56 and S57 may not be included in the tracking circuit 1. In other words, only one of switches S56 and S57 may be included in the tracking circuit 1.

[0104] The digital control circuit 60 can control the pre-regulator circuit 10 , the switched capacitor circuit 20 , the output switch circuit 30 , and the switches S56 and S57 based on the digital control signal from the RFIC 3 .

[0105] Furthermore, the tracking circuit 1 may not include the pre-regulator circuit 10, the switched capacitor circuit 20, the output switch circuit 30, the first and second filter circuits 41 and 42, the switches S56 and S57, and part of the digital control circuit 60. For example, the tracking circuit 1 may not include the pre-regulator circuit 10. Furthermore, for example, the tracking circuit 1 may not include the first and second filter circuits 41 and 42, the switches S56 and S57. Furthermore, any combination of the pre-regulator circuit 10, the switched capacitor circuit 20, the output switch circuit 30, the first and second filter circuits 41 and 42, and the switches S56 and S57 may be integrated into a single circuit. Furthermore, the tracking circuit 1 may include multiple voltage supply circuits in place of the pre-regulator circuit 10 and the switched capacitor circuit 20, as described in Patent Document 2. In this case, the output switch circuit 30 may be configured to select at least one of the multiple voltage supply circuits.

[0106] Next, refer to Figure 3 The circuit configuration of each circuit included in the tracking circuit 1 will be described. Figure 3 2 is a circuit configuration diagram of the tracking circuit 1 according to this embodiment.

[0107] also, Figure 3 This is an exemplary circuit configuration, and the tracking circuit 1 can be implemented using any of a variety of circuit implementations and circuit technologies. Therefore, the description of the tracking circuit 1 provided below should not be interpreted in a limiting sense.

[0108] [1.3.1 Circuit Structure of Switched Capacitor Circuit 20]

[0109] First, refer to Figure 3 , while explaining the circuit structure of the switched capacitor circuit 20. Figure 3 As shown, the switched capacitor circuit 20 includes capacitors C11 to C16, capacitors C10, C20, C30, and C40, and switches S11 to S14, S21 to S24, S31 to S34, and S41 to S44. Energy and charge are input from the pre-regulator circuit 10 to the switched capacitor circuit 20 via nodes N1 to N4, and are then extracted from the switched capacitor circuit 20 to the output switch circuit 30 via nodes N1 to N4.

[0110] Capacitors C11-C16 each function as a flying capacitor (sometimes also called a fly-by capacitor). Specifically, capacitors C11-C16 are used to step up or step down the regulated voltage supplied from pre-regulator circuit 10. More specifically, capacitors C11-C16 transfer charge between capacitors C11-C16 and nodes N1-N4 so that voltages V1-V4 (relative to ground potential) satisfying V1:V2:V3:V4 = 1:2:3:4 are maintained at the four nodes N1-N4. These voltages V1-V4 correspond to multiple discrete voltages, each having a plurality of discrete voltage levels.

[0111] Capacitor C11 has two electrodes. One of the two electrodes of capacitor C11 is connected to one end of switch S11 and one end of switch S12. The other of the two electrodes of capacitor C11 is connected to one end of switch S21 and one end of switch S22.

[0112] The capacitor C12 has two electrodes. One of the two electrodes of the capacitor C12 is connected to one end of the switch S21 and one end of the switch S22. The other of the two electrodes of the capacitor C12 is connected to one end of the switch S31 and one end of the switch S32.

[0113] The capacitor C13 has two electrodes. One of the two electrodes of the capacitor C13 is connected to one end of the switch S31 and one end of the switch S32. The other of the two electrodes of the capacitor C13 is connected to one end of the switch S41 and one end of the switch S42.

[0114] Capacitor C14 has two electrodes. One of the two electrodes of capacitor C14 is connected to one end of switch S13 and one end of switch S14. The other of the two electrodes of capacitor C14 is connected to one end of switch S23 and one end of switch S24.

[0115] The capacitor C15 has two electrodes. One of the two electrodes of the capacitor C15 is connected to one end of the switch S23 and one end of the switch S24. The other of the two electrodes of the capacitor C15 is connected to one end of the switch S33 and one end of the switch S34.

[0116] Capacitor C16 has two electrodes. One of the two electrodes of capacitor C16 is connected to one end of switch S33 and one end of switch S34. The other of the two electrodes of capacitor C16 is connected to one end of switch S43 and one end of switch S44.

[0117] The group of capacitors C11 and C14 , the group of capacitors C12 and C15 , and the group of capacitors C13 and C16 can each be charged and discharged complementarily by repeating the first stage and the second stage.

[0118] Specifically, in the first phase, switches S12, S13, S22, S23, S32, S33, S42, and S43 are turned on. Consequently, for example, one of the two electrodes of capacitor C12 is connected to node N3, the other of the two electrodes of capacitor C12 and one of the two electrodes of capacitor C15 are connected to node N2, and the other of the two electrodes of capacitor C15 is connected to node N1.

[0119] On the other hand, in the second phase, switches S11, S14, S21, S24, S31, S34, S41, and S44 are turned on. Consequently, for example, one of the two electrodes of capacitor C15 is connected to node N3, the other of the two electrodes of capacitor C15 and one of the two electrodes of capacitor C12 are connected to node N2, and the other of the two electrodes of capacitor C12 is connected to node N1.

[0120] By repeating the first and second stages, for example, when one of capacitors C12 and C15 is charged from node N2, the other of capacitors C12 and C15 can be discharged to capacitor C30. That is, capacitors C12 and C15 can be charged and discharged in a complementary manner.

[0121] The pair of capacitors C11 and C14 and the pair of capacitors C13 and C16 also repeat the first stage and the second stage, thereby enabling complementary charging and discharging, similar to the pair of capacitors C12 and C15 .

[0122] Each of the capacitors C10 , C20 , C30 , and C40 functions as a smoothing capacitor. That is, each of the capacitors C10 , C20 , C30 , and C40 is used to hold and smooth the voltages V1 to V4 at the nodes N1 to N4 .

[0123] Capacitor C10 is connected between node N1 and ground. Specifically, one of the two electrodes of capacitor C10 is connected to node N1. On the other hand, the other of the two electrodes of capacitor C10 is grounded.

[0124] Capacitor C20 is connected between nodes N2 and N1. Specifically, one of the two electrodes of capacitor C20 is connected to node N2. On the other hand, the other of the two electrodes of capacitor C20 is connected to node N1.

[0125] Capacitor C30 is connected between nodes N3 and N2. Specifically, one of the two electrodes of capacitor C30 is connected to node N3. On the other hand, the other of the two electrodes of capacitor C30 is connected to node N2.

[0126] Capacitor C40 is connected between nodes N4 and N3. Specifically, one of the two electrodes of capacitor C40 is connected to node N4. On the other hand, the other of the two electrodes of capacitor C40 is connected to node N3.

[0127] The switch S11 is connected between one of the two electrodes of the capacitor C11 and the node N3. Specifically, one end of the switch S11 is connected to one of the two electrodes of the capacitor C11. On the other hand, the other end of the switch S11 is connected to the node N3.

[0128] The switch S12 is connected between one of the two electrodes of the capacitor C11 and the node N4. Specifically, one end of the switch S12 is connected to one of the two electrodes of the capacitor C11. On the other hand, the other end of the switch S12 is connected to the node N4.

[0129] Switch S21 is connected between one of the two electrodes of capacitor C12 and node N2. Specifically, one end of switch S21 is connected to one of the two electrodes of capacitor C12 and the other of the two electrodes of capacitor C11. On the other hand, the other end of switch S21 is connected to node N2.

[0130] Switch S22 is connected between one of the two electrodes of capacitor C12 and node N3. Specifically, one end of switch S22 is connected to one of the two electrodes of capacitor C12 and the other of the two electrodes of capacitor C11. On the other hand, the other end of switch S22 is connected to node N3.

[0131] Switch S31 is connected between the other of the two electrodes of capacitor C12 and node N1. Specifically, one end of switch S31 is connected to the other of the two electrodes of capacitor C12 and one of the two electrodes of capacitor C13. On the other hand, the other end of switch S31 is connected to node N1.

[0132] Switch S32 is connected between the other of the two electrodes of capacitor C12 and node N2. Specifically, one end of switch S32 is connected to the other of the two electrodes of capacitor C12 and one of the two electrodes of capacitor C13. Meanwhile, the other end of switch S32 is connected to node N2. In other words, the other end of switch S32 is connected to the other end of switch S21.

[0133] The switch S41 is connected between the other of the two electrodes of the capacitor C13 and the ground. Specifically, one end of the switch S41 is connected to the other of the two electrodes of the capacitor C13. On the other hand, the other end of the switch S41 is grounded.

[0134] Switch S42 is connected between the other of the two electrodes of capacitor C13 and node N1. Specifically, one end of switch S42 is connected to the other of the two electrodes of capacitor C13. On the other hand, the other end of switch S42 is connected to node N1. In other words, the other end of switch S42 is connected to the other end of switch S31.

[0135] Switch S13 is connected between one of the two electrodes of capacitor C14 and node N3. Specifically, one end of switch S13 is connected to one of the two electrodes of capacitor C14. On the other hand, the other end of switch S13 is connected to node N3. In other words, the other end of switch S13 is connected to the other end of switch S11 and the other end of switch S22.

[0136] Switch S14 is connected between one of the two electrodes of capacitor C14 and node N4. Specifically, one end of switch S14 is connected to one of the two electrodes of capacitor C14. On the other hand, the other end of switch S14 is connected to node N4. In other words, the other end of switch S14 is connected to the other end of switch S12.

[0137] Switch S23 is connected between one of the two electrodes of capacitor C15 and node N2. Specifically, one end of switch S23 is connected to one of the two electrodes of capacitor C15 and the other of the two electrodes of capacitor C14. Meanwhile, the other end of switch S23 is connected to node N2. In other words, the other end of switch S23 is connected to the other end of switch S21 and the other end of switch S32.

[0138] Switch S24 is connected between one of the two electrodes of capacitor C15 and node N3. Specifically, one end of switch S24 is connected to one of the two electrodes of capacitor C15 and the other of the two electrodes of capacitor C14. On the other hand, the other end of switch S24 is connected to node N3. In other words, the other end of switch S24 is connected to the other end of switch S11, the other end of switch S22, and the other end of switch S13.

[0139] Switch S33 is connected between the other of the two electrodes of capacitor C15 and node N1. Specifically, one end of switch S33 is connected to the other of the two electrodes of capacitor C15 and one of the two electrodes of capacitor C16. On the other hand, the other end of switch S33 is connected to node N1. In other words, the other end of switch S33 is connected to the other end of switch S31 and the other end of switch S42.

[0140] Switch S34 is connected between the other of the two electrodes of capacitor C15 and node N2. Specifically, one end of switch S34 is connected to the other of the two electrodes of capacitor C15 and one of the two electrodes of capacitor C16. On the other hand, the other end of switch S34 is connected to node N2. In other words, the other end of switch S34 is connected to the other end of switch S21, the other end of switch S32, and the other end of switch S23.

[0141] The switch S43 is connected between the other of the two electrodes of the capacitor C16 and the ground line. Specifically, one end of the switch S43 is connected to the other of the two electrodes of the capacitor C16. On the other hand, the other end of the switch S43 is grounded.

[0142] Switch S44 is connected between the other of the two electrodes of capacitor C16 and node N1. Specifically, one end of switch S44 is connected to the other of the two electrodes of capacitor C16. Meanwhile, the other end of switch S44 is connected to node N1. In other words, the other end of switch S44 is connected to the other end of switch S31, the other end of switch S42, and the other end of switch S33.

[0143] The first group of switches, including switches S12, S13, S22, S23, S32, S33, S42, and S43, and the second group of switches, including switches S11, S14, S21, S24, S31, S34, S41, and S44, are switched on and off in a complementary manner based on control signal S2. Specifically, in the first phase, the switches in the first group are on, while the switches in the second group are off. Conversely, in the second phase, the switches in the first group are off, while the switches in the second group are on.

[0144] For example, in one of the first and second phases, capacitors C11 to C13 are charged to capacitors C10 to C40, while in the other phase, capacitors C14 to C16 are charged to capacitors C10 to C40. That is, capacitors C10 to C40 are always charged from capacitors C11 to C13 or capacitors C14 to C16. Therefore, current flows rapidly from nodes N1 to N4 to the output switch circuit 30, rapidly replenishing charge at nodes N1 to N4. This suppresses fluctuations in the potential of nodes N1 to N4.

[0145] By operating in this manner, switched capacitor circuit 20 maintains approximately equal voltages across capacitors C10, C20, C30, and C40. Specifically, at the four nodes labeled V1 to V4, voltages V1 to V4 (relative to ground potential) are maintained in the order V1:V2:V3:V4 = 1:2:3:4. The voltage levels of voltages V1 to V4 correspond to the multiple discrete voltage levels that can be supplied to output switch circuit 30 via switched capacitor circuit 20.

[0146] Furthermore, the voltage ratio (V1:V2:V3:V4) is not limited to (1:2:3:4). For example, the voltage ratio (V1:V2:V3:V4) may be (1:2:4:8).

[0147] in addition, Figure 3 The structure of the switched capacitor circuit 20 shown is an example and is not limited thereto. Figure 3 In the example, the switched capacitor circuit 20 is configured to supply four discrete voltages, but the number of discrete voltages is not limited to this. The switched capacitor circuit 20 may also be configured to supply any number of two or more discrete voltages. For example, when supplying two discrete voltages, the switched capacitor circuit 20 may include at least capacitors C12 and C15, switches S21 to S24, and switches S31 to S34.

[0148] [1.3.2 Circuit Structure of Output Switch Circuit 30]

[0149] Next, refer to Figure 3 The circuit structure of the output switch circuit 30 will be described. Figure 3 As shown, the output switch circuit 30 includes input terminals 131 to 134 , switches S51 to S54 , and an output terminal 130 .

[0150] The output terminal 130 is connected to the first filter circuit 41 and the second filter circuit 42. The output terminal 130 is a terminal for supplying a power supply voltage selected from the voltages V1 to V4 to the power amplifier 2 via the first filter circuit 41 and / or the second filter circuit 42.

[0151] Input terminals 131 to 134 are connected to nodes N4 to N1 of the switched capacitor circuit 20 , respectively. Input terminals 131 to 134 are terminals for receiving voltages V4 to V1 from the switched capacitor circuit 20 .

[0152] The switch S51 is connected between the input terminal 131 and the output terminal 130. Specifically, the switch S51 has a terminal connected to the input terminal 131 and a terminal connected to the output terminal 130. In this connection configuration, the switch S51 is switched on / off by the control signal S3, thereby switching between the connection and disconnection between the input terminal 131 and the output terminal 130.

[0153] The switch S52 is connected between the input terminal 132 and the output terminal 130. Specifically, the switch S52 has a terminal connected to the input terminal 132 and a terminal connected to the output terminal 130. In this connection configuration, the switch S52 is switched on / off by the control signal S3, thereby switching between the connection and disconnection between the input terminal 132 and the output terminal 130.

[0154] The switch S53 is connected between the input terminal 133 and the output terminal 130. Specifically, the switch S53 has a terminal connected to the input terminal 133 and a terminal connected to the output terminal 130. In this connection configuration, the switch S53 is switched on / off by the control signal S3, thereby switching between the connection and disconnection between the input terminal 133 and the output terminal 130.

[0155] The switch S54 is connected between the input terminal 134 and the output terminal 130. Specifically, the switch S54 has a terminal connected to the input terminal 134 and a terminal connected to the output terminal 130. In this connection configuration, the switch S54 is switched on / off by the control signal S3, thereby switching between the connection and disconnection between the input terminal 134 and the output terminal 130.

[0156] These switches S51 to S54 are controlled to be exclusively turned on. That is, only one of the switches S51 to S54 is turned on, and the remaining switches S51 to S54 are turned off. This allows the output switch circuit 30 to output one voltage selected from the voltages V1 to V4.

[0157] also, Figure 3 The illustrated structure of the output switch circuit 30 is merely an example and is not intended to be limiting. Specifically, switches S51-S54 may be configured to selectively connect at least one of the four input terminals 131-134 to the output terminal 130. For example, the output switch circuit 30 may further include a switch connected between switches S51-S53, switch S54, and the output terminal 130. Furthermore, for example, the output switch circuit 30 may further include a switch connected between switches S51 and S52, switches S53 and S54, and the output terminal 130.

[0158] Furthermore, when voltages of two discrete voltage levels are supplied from the switched capacitor circuit 20 , the output switch circuit 30 only needs to include at least two of the switches S51 to S54 .

[0159] [1.3.3 Circuit Structure of Pre-regulator Circuit 10]

[0160] Next, refer to Figure 3 , while explaining the structure of the pre-regulator circuit 10. Figure 3 As shown, the pre-regulator circuit 10 includes an input terminal 110 , output terminals 111 to 114 , switches S61 to S63 , S71 , and S72 , a power inductor L71 , and capacitors C61 to C64 .

[0161] The input terminal 110 is a terminal for inputting a DC voltage. In other words, the input terminal 110 is a terminal for receiving an input voltage from the DC power supply 50 .

[0162] The output terminal 111 is an output terminal for the voltage V4. That is, the output terminal 111 is a terminal for supplying the voltage V4 to the switched capacitor circuit 20. The output terminal 111 is connected to the node N4 of the switched capacitor circuit 20.

[0163] Output terminal 112 is an output terminal for voltage V3. In other words, output terminal 112 is a terminal for supplying voltage V3 to switched capacitor circuit 20. Output terminal 112 is connected to node N3 of switched capacitor circuit 20.

[0164] The output terminal 113 is an output terminal for the voltage V2. That is, the output terminal 113 is a terminal for supplying the voltage V2 to the switched capacitor circuit 20. The output terminal 113 is connected to the node N2 of the switched capacitor circuit 20.

[0165] Output terminal 114 is an output terminal for voltage V1. In other words, output terminal 114 is a terminal for supplying voltage V1 to switched capacitor circuit 20. Output terminal 114 is connected to node N1 of switched capacitor circuit 20.

[0166] Switch S71 is connected between input terminal 110 and one end of power inductor L71. Specifically, switch S71 has a terminal connected to input terminal 110 and a terminal connected to one end of power inductor L71. In this connection structure, by switching switch S71 on and off based on control signal S1, the connection between input terminal 110 and one end of power inductor L71 can be switched.

[0167] Switch S72 is connected between one end of the power inductor L71 and the ground line. Specifically, switch S72 has a terminal connected to one end of the power inductor L71 and a terminal connected to the ground. In this connection structure, by switching switch S72 on and off based on control signal S1, the connection between one end of the power inductor L71 and the ground line can be switched.

[0168] The switch S61 is connected between the other end of the power inductor L71 and the output terminal 111. Specifically, the switch S61 has a terminal connected to the other end of the power inductor L71 and a terminal connected to the output terminal 111. In this connection structure, by switching the switch S61 on and off based on the control signal S1, the connection and disconnection between the other end of the power inductor L71 and the output terminal 111 can be switched.

[0169] The switch S62 is connected between the other end of the power inductor L71 and the output terminal 112. Specifically, the switch S62 has a terminal connected to the other end of the power inductor L71 and a terminal connected to the output terminal 112. In this connection structure, by switching the switch S62 on and off based on the control signal S1, the connection and disconnection between the other end of the power inductor L71 and the output terminal 112 can be switched.

[0170] The switch S63 is connected between the other end of the power inductor L71 and the output terminal 113. Specifically, the switch S63 has a terminal connected to the other end of the power inductor L71 and a terminal connected to the output terminal 113. In this connection structure, by switching the switch S63 on and off based on the control signal S1, the connection and disconnection between the other end of the power inductor L71 and the output terminal 113 can be switched.

[0171] One of the two electrodes of the capacitor C61 is connected to the switch S61 and the output terminal 111. The other of the two electrodes of the capacitor C61 is connected to the switch S62, the output terminal 112, and one of the two electrodes of the capacitor C62.

[0172] One of the two electrodes of capacitor C62 is connected to switch S62, output terminal 112, and the other of the two electrodes of capacitor C61. The other of the two electrodes of capacitor C62 is connected to a path connecting switch S63, output terminal 113, and one of the two electrodes of capacitor C63.

[0173] One of the two electrodes of capacitor C63 is connected to switch S63, output terminal 113, and the other of the two electrodes of capacitor C62. The other of the two electrodes of capacitor C63 is connected to output terminal 114 and one of the two electrodes of capacitor C64.

[0174] One of the two electrodes of the capacitor C64 is connected to the output terminal 114 and the other of the two electrodes of the capacitor C63 , and the other of the two electrodes of the capacitor C64 is grounded.

[0175] Switches S61-S63 are controlled to be exclusively on. That is, only one of switches S61-S63 is on, and the remaining switches S61-S63 are off. By turning on only one of switches S61-S63, pre-regulator circuit 10 can change the voltage supplied to switched capacitor circuit 20 to a voltage level of voltages V2-V4.

[0176] The pre-regulator circuit 10 configured in this manner can supply electric charge to the switched capacitor circuit 20 via at least one of the output terminals 111 to 114 .

[0177] Furthermore, in the case where the input voltage can be converted into a regulated voltage, the pre-regulator circuit 10 only needs to include at least the switches S71 and S72 and the power inductor L71 .

[0178] [1.3.4 Circuit Structure of the First Filter Circuit 41 and the Second Filter Circuit 42]

[0179] Next, refer to Figure 3 , while describing the circuit configurations of the first filter circuit 41 and the second filter circuit 42 according to this embodiment.

[0180] The first filter circuit 41 is switchably connected to a path 44 (an example of a first path) connecting the output switch circuit 30 and the power amplifier 2. Specifically, the first filter circuit 41 is connected between the output switch circuit 30 and the power amplifier 2 via a switch S56. The first filter circuit 41 includes a parallel circuit (LC parallel circuit) of an inductor L51 and a capacitor C51. One end of the parallel circuit of the inductor L51 and the capacitor C51 is connected to the output switch circuit 30 via a switch S56, and the other end of the parallel circuit of the inductor L51 and the capacitor C51 is connected to the power amplifier 2. Furthermore, the first filter circuit 41 is not limited to an LC parallel circuit.

[0181] The second filter circuit 42 is switchably connected to the path 44. Specifically, the second filter circuit 42 is connected in parallel with the first filter circuit 41 between the output switch circuit 30 and the power amplifier 2 via a switch S57. The second filter circuit 42 includes a parallel circuit of an inductor L52 and a capacitor C52. One end of the parallel circuit of the inductor L52 and capacitor C52 is connected to the output switch circuit 30 via a switch S57, and the other end of the parallel circuit of the inductor L52 and capacitor C52 is connected to the power amplifier 2. Furthermore, the second filter circuit 42 is not limited to an LC parallel circuit.

[0182] Switches S56 and S57 switch the connection of the first filter circuit 41 and the second filter circuit 42. This allows the first filter circuit 41 and the second filter circuit 42 to vary the attenuation band of the band-stop filter used to remove noise from a plurality of discrete voltages in path 44. In other words, the first filter circuit 41 and the second filter circuit 42 function as a variable filter circuit capable of switching between a plurality of attenuation bands.

[0183] The first filter circuit 41 and the second filter circuit 42 according to the present embodiment can realize the following three types of band rejection filters (i) to (iii) by controlling the opening and closing of the switches S56 and S57 .

[0184] (i) By closing switch S56 and opening switch S57, the first filter circuit 41 is connected to the path 44, and the second filter circuit 42 is disconnected from the path 44. Thus, in the path 44, the first filter circuit 41 functions as a band-stop filter, and the second filter circuit 42 does not function as a band-stop filter.

[0185] (ii) By closing the switch S56 and the switch S57, the first filter circuit 41 and the second filter circuit 42 are connected to the path 44. Thus, in the path 44, the first filter circuit 41 and the second filter circuit 42 function as band-stop filters.

[0186] (iii) By opening switch S56 and closing switch S57, the second filter circuit 42 is connected to the path 44, and the first filter circuit 41 is disconnected from the path 44. Thus, in the path 44, the second filter circuit 42 functions as a band-stop filter, and the first filter circuit 41 does not function as a band-stop filter.

[0187] For example, the opening and closing of switches S56 and S57 can be controlled based on the channel bandwidth (i.e., modulation bandwidth) of the high-frequency signal. Furthermore, if the power amplifier 2 is capable of amplifying high-frequency signals in multiple frequency bands, the opening and closing of switches S56 and S57 can also be controlled based on, for example, the frequency band of the high-frequency signal. Furthermore, the opening and closing of switches S56 and S57 can be controlled based on a combination of the channel bandwidth of the high-frequency signal and the frequency bands. The opening and closing control of switches S56 and S57 is not limited to the above.

[0188] Furthermore, the switch S56 may not be included in the tracking circuit 1. In this case, the first filter circuit 41 and the second filter circuit 42 cannot realize the band-stop filter of (iii) above, but can realize both the band-stop filters of (i) and (ii) above.

[0189] The present inventors have discovered that in such a power amplification system 7, the linearity of the power amplifier 2 is changed by the filter circuit connected to the path 44. Therefore, in this embodiment, the DPD circuit 71 switches the mathematical model and / or its parameter set used for DPD according to (i) to (iii) above. Specifically, the DPD circuit 71 can calculate the predistorted signal using the following mathematical model and / or its parameter set in (i) to (iii) above.

[0190] (i) The DPD circuit 71 calculates the predistorted signal using a first set of parameters in a first mathematical model.

[0191] (ii) The DPD circuit 71 calculates the predistorted signal using the second parameter set in the second mathematical model.

[0192] (iii) The DPD circuit 71 calculates the predistorted signal using the third parameter set in the third mathematical model.

[0193] To summarize, the relationship between the on / off states of the first filtering circuit 41 and the second filtering circuit 42 and the parameter set used in the mathematical model for DPD is shown in Table 1 below.

[0194] [Table 1]

[0195]

[0196] Furthermore, in the above description, the first, second, and third mathematical models may be different from each other, or may be the same in any combination. For example, any two of the first, second, and third mathematical models may be the same mathematical model, or may be different from the remaining one. Alternatively, for example, the first, second, and third mathematical models may all be the same mathematical model. Alternatively, for example, the first, second, and third mathematical models may be different mathematical models. Furthermore, the first, second, and third mathematical models may be independent of each other, and any one of a memoryless polynomial model, an MPM, a GMP, or other mathematical model may be used.

[0197] Furthermore, the first through third parameter sets differ from each other at least in part. That is, at least one of the first through third parameter sets includes a parameter not included in the remaining parameter sets, or a parameter having a different value from the remaining parameter sets. Furthermore, each parameter set only needs to include at least one parameter and does not necessarily need to include multiple parameters.

[0198] [1.3.5 Circuit Structure of Digital Control Circuit 60]

[0199] Next, the circuit structure of the digital control circuit 60 will be described. Figure 3 As shown, the digital control circuit 60 includes a first controller 61 and a second controller 62 .

[0200] The first controller 61 can generate control signals S1 to S4 by processing a serial data signal (DATA) based on a clock signal (CLK) supplied from the RFIC 3. Here, a serial data signal refers to a data signal transmitted one bit at a time using one signal line or line.

[0201] Control signal S1 is a signal for controlling the opening and closing of switches S61 to S63, S71, and S72 included in pre-regulator circuit 10. Control signal S2 is a signal for controlling the opening and closing of switches S11 to S14, S21 to S24, S31 to S34, and S41 to S44 included in switched capacitor circuit 20. Control signal S3 is a signal for controlling the opening and closing of switches S51 to S54 included in output switch circuit 30 when the APT mode is applied to power amplifier 2. Control signal S4 is a signal for controlling the opening and closing of switches S56 and S57 used in first filter circuit 41 and second filter circuit 42.

[0202] The clock signal used to process the serial data signal by the first controller 61 uses a signal line different from the serial data signal, but the present invention is not limited thereto. For example, the clock signal can also be transmitted using the same signal line as the serial data signal.

[0203] In the present embodiment, one serial data signal is used to control the pre-regulator circuit 10 , the switched capacitor circuit 20 , the output switch circuit 30 , and the switches S56 and S57 . However, a plurality of serial data signals may be used.

[0204] The second controller 62 can process the digital control logic (DCL) signals (DCL1, DCL2) supplied from the RFIC 3 to generate a control signal S5. The DCL signal is an example of a parallel data signal. Here, a parallel data signal means a data signal transmitted simultaneously and in parallel using multiple signal lines or circuits.

[0205] When the D-ET mode is applied to the power amplifier 2, the RFIC 3 generates DCL signals (DCL1, DCL2) based on the envelope signal of the high-frequency signal. Therefore, the control signal S5 is a signal used to control the opening and closing of switches S51 to S54 included in the output switch circuit 30 when the D-ET mode is applied to the power amplifier 2.

[0206] Each DCL signal (DCL1, DCL2) is a 1-bit signal. Voltages V1 through V4 are each represented by a combination of two 1-bit signals. For example, V1, V2, V3, and V4 are represented by "00," "01," "10," and "11," respectively. Gray code can also be used to represent voltage levels.

[0207] In this embodiment, two DCL signals are used to control the output switch circuit 30 in the D-ET mode. However, the number of DCL signals is not limited to this. For example, an arbitrary number of DCL signals, from one to three or more, may be used depending on the number of voltage levels selectable by each output switch circuit 30. Furthermore, the digital control signals used to control the output switch circuit 30 are not limited to DCL signals.

[0208] [1.4DPD method]

[0209] Next, refer to Figure 4 Next, the DPD method according to this embodiment will be described. Figure 4 Flowchart showing the DPD method according to this embodiment.

[0210] First, RFIC3 determines a mathematical model for DPD and a parameter set for the mathematical model based on the attenuation band of the variable filter circuit implemented by the first filter circuit 41, the second filter circuit 42, and switches S56 and S57 (S10). For example, as shown in (i) of Table 1, when the attenuation band is formed by the first filter circuit 41, a first mathematical model and a first parameter set are determined. Furthermore, as shown in (ii) of Table 1, when the attenuation band is formed by the first filter circuit 41 and the second filter circuit 42, a second mathematical model and a second parameter set are determined. Furthermore, as shown in (iii) of Table 1, when the attenuation band is formed by the second filter circuit 42, a third mathematical model and a third parameter set are determined.

[0211] More specifically, when the attenuation band of the variable filter circuit is wider than the threshold bandwidth, a first parameter set may be determined, and when the attenuation band of the variable filter circuit is not wider than the threshold bandwidth, a second parameter set having fewer parameters than the first parameter set may be determined. Furthermore, the threshold bandwidth can be predetermined through experimentation and / or experience.

[0212] Furthermore, the attenuation band of the variable filter circuit implemented by first and second filter circuits 41 and 42 and switches S56 and S57 is determined by measuring the attenuation characteristics from output terminal 130 of output switch circuit 30 to the output terminal connected to power amplifier 2 of tracking circuit 1. A network analyzer is used to measure the attenuation characteristics. Alternatively, the attenuation band can be measured by measuring the frequency characteristics of the output voltage at the output terminal connected to power amplifier 2 of tracking circuit 1 using a spectrum analyzer or oscilloscope.

[0213] RFIC3 predistorts the input signal of power amplifier 2 using the determined parameter set in the determined mathematical model (S20). For example, DPD circuit 71 calculates a predistorted digital IQ signal using the determined parameter set (e.g., polynomial degree N, memory depth Q, and DPD coefficients cqi) in the mathematical model (e.g., equation (2)) and converts the calculated predistorted digital IQ signal into a predistorted analog IQ signal. Furthermore, quadrature modulator 73 generates a predistorted high-frequency signal RF by performing quadrature modulation and up-conversion on the predistorted analog IQ signal supplied from DPD circuit 71.

[0214] [1.5 Effects, etc.]

[0215] As described above, the power amplifier system 7 according to the present embodiment includes: a power amplifier 2; an output switch circuit 30 configured to selectively output at least one of a plurality of discrete voltages to the power amplifier 2; a second filter circuit 42 switchably connected to a path 44 connecting the output switch circuit 30 and the power amplifier 2; and a DPD circuit 71 configured to predistort an input signal of the power amplifier 2. (i) When the second filter circuit 42 is not connected to the path 44, the DPD circuit 71 predistorts the input signal of the power amplifier 2 using a first parameter set in a first mathematical model; and (ii) When the second filter circuit 42 is connected to the path 44, the DPD circuit 71 predistorts the input signal of the power amplifier 2 using a second parameter set in a second mathematical model, wherein the first parameter set and the second parameter set are at least partially different from each other.

[0216] Thus, the mathematical model and / or parameter set are switched depending on whether the second filter circuit 42 is connected to the path 44 for supplying a plurality of discrete voltages to the power amplifier 2. Therefore, the input signal of the power amplifier 2 can be predistorted using a mathematical model and parameter set that linearly changes depending on whether the second filter circuit 42 is connected or disconnected from the path 44, thereby reducing nonlinear distortion in the power amplifier 2. For example, if the connection or disconnection of the second filter circuit 42 is switched based on the channel bandwidth of the input signal of the power amplifier 2, the input signal of the power amplifier 2 can be predistorted using a mathematical model and parameter set that corresponds to the channel bandwidth, further reducing nonlinear distortion in the power amplifier 2.

[0217] Furthermore, for example, the power amplification system 7 according to the present embodiment may further include a first filter circuit 41 switchably connected to the path 44. (i) When the first filter circuit 41 is connected to the path 44 and the second filter circuit 42 is not connected to the path 44, the DPD circuit 71 may predistort the input signal of the power amplifier 2 using a first parameter set in a first mathematical model. (ii) When the first filter circuit 41 is connected to the path 44 and the second filter circuit 42 is connected to the path 44, the DPD circuit 71 may predistort the input signal of the power amplifier 2 using a second parameter set in a second mathematical model. (iii) When the first filter circuit 41 is not connected to the path 44 and the second filter circuit 42 is connected to the path 44, the DPD circuit 71 may predistort the input signal of the power amplifier 2 using a third parameter set in a third mathematical model. The first to third parameter sets may be at least partially different from each other.

[0218] Thus, the mathematical model and / or parameter set are switched depending on whether the path 44 for supplying a plurality of discrete voltages to the power amplifier 2 is connected to the first filter circuit 41 and whether it is connected to the second filter circuit 42. Therefore, the input signal of the power amplifier 2 can be predistorted using a mathematical model and parameter set suitable for the power amplifier 2, thereby reducing nonlinear distortion in the power amplifier 2.

[0219] In addition, for example, in the power amplification system 7 involved in this embodiment, the first filter circuit 41 can also be connected between the output switch circuit 30 and the power amplifier 2, and the second filter circuit 42 can also be connected between the output switch circuit 30 and the power amplifier 2 in parallel with the first filter circuit 41. The power amplification system 7 can also include: a switch S56, connected between the output switch circuit 30 and the first filter circuit 41; and a switch S57, connected between the output switch circuit 30 and the second filter circuit 42.

[0220] Thus, when the first filter circuit 41 and the second filter circuit 42 are connected in series with the path 44 , nonlinear distortion in the power amplifier 2 can be reduced.

[0221] In the DPD method according to this embodiment, a mathematical model and a parameter set for DPD are determined based on the attenuation band of a variable filter circuit connected between an output switch circuit 30 that selectively supplies at least one of a plurality of discrete voltages to the power amplifier and the power amplifier 2 (S10). The input signal of the power amplifier is predistorted using the determined parameter set in the determined mathematical model (S20).

[0222] Thus, the mathematical model and / or parameter set are switched according to the attenuation band of the variable filter circuit (e.g., first filter circuit 41, second filter circuit 42, and switches S56 and S57) connected between the output switch circuit 30 that supplies a plurality of discrete voltages to the power amplifier 2 and the power amplifier 2. Consequently, the input signal of the power amplifier 2 can be predistorted using a mathematical model and parameter set that linearly changes according to the attenuation band of the variable filter circuit and is suitable for the power amplifier 2, thereby reducing nonlinear distortion in the power amplifier 2. For example, when the attenuation band of the variable filter circuit is changed according to the channel bandwidth of the input signal of the power amplifier 2, the input signal of the power amplifier 2 can also be predistorted using a mathematical model and parameter set that corresponds to the channel bandwidth, further reducing nonlinear distortion in the power amplifier 2.

[0223] In addition, for example, in the DPD method involved in this embodiment, in determining the mathematical model and parameter set (S20), a first parameter set can be determined when the attenuation band of the variable filter circuit is wider than the threshold bandwidth, and a second parameter set with fewer parameters than the first parameter set can be determined when the attenuation band of the variable filter circuit is not wider than the threshold bandwidth.

[0224] Therefore, when the attenuation bandwidth is narrow and the channel bandwidth of the high-frequency signal RF is narrow, reducing the number of parameters can reduce the calculation load of DPD and thus reduce power consumption. On the other hand, when the attenuation bandwidth and the channel bandwidth of the high-frequency signal RF are wide, increasing the number of parameters can reduce nonlinear distortion in power amplifier 2.

[0225] (i) Path 44 is used to selectively supply at least one of a plurality of discrete voltages to power amplifier 2, and when second filter circuit 42 switchably connected to path 44 is not connected to path 44, a first input signal of power amplifier 2 is predistorted using a first parameter set in a first mathematical model; and (ii) when second filter circuit 42 is connected to path 44, the first input signal is predistorted using a second parameter set in a second mathematical model, the first parameter set and the second parameter set being at least partially different from each other.

[0226] Thus, the mathematical model and / or parameter set are switched depending on whether the second filter circuit 42 is connected to the path 44 for supplying a plurality of discrete voltages to the power amplifier 2. Therefore, the input signal of the power amplifier 2 can be predistorted using a mathematical model and parameter set that linearly changes depending on whether the second filter circuit 42 is connected or disconnected from the path 44, thereby reducing nonlinear distortion in the power amplifier 2. For example, when the connection and disconnection of the second filter circuit 42 are switched depending on the channel bandwidth of the input signal of the power amplifier 2, the input signal of the power amplifier 2 can also be predistorted using a mathematical model and parameter set that corresponds to the channel bandwidth, further reducing nonlinear distortion in the power amplifier 2.

[0227] Furthermore, for example, in the digital predistortion circuit 71 according to the present embodiment, (i) when the first filter circuit 41 switchably connected to the path 44 is connected to the path 44 and the second filter circuit 42 is not connected to the path 44, the first input signal may be predistorted using the first parameter set in the first mathematical model; (ii) when the first filter circuit 41 is connected to the path 44 and the second filter circuit 42 is connected to the path 44, the first input signal may be predistorted using the second parameter set in the second mathematical model; and (iii) when the first filter circuit 41 is not connected to the path 44 and the second filter circuit 42 is connected to the path 44, the first input signal may be predistorted using the third parameter set in the third mathematical model. The first to third parameter sets may be at least partially different from each other.

[0228] Thus, the mathematical model and / or parameter set are switched depending on whether the path 44 for supplying a plurality of discrete voltages to the power amplifier 2 is connected to the first filter circuit 41 or to the second filter circuit 42. Therefore, the input signal of the power amplifier 2 can be predistorted using a mathematical model and parameter set suitable for the power amplifier 2, thereby reducing nonlinear distortion in the power amplifier 2.

[0229] (Variation 1 of Implementation Example 1)

[0230] Next, a first variation of the first embodiment will be described. This variation differs from the first embodiment primarily in the circuit configurations of the first and second filter circuits. This variation will be described below, focusing on the differences from the first embodiment, with reference to the accompanying drawings.

[0231] Note that the circuit configuration of the communication device 6 according to this modification is the same as that of the first embodiment except for a portion of the tracking circuit 1 , and therefore illustration and description thereof will be appropriately omitted.

[0232] [2.1 Circuit Structure of Tracking Circuit 1]

[0233] While referring to Figure 5 Next, the circuit configuration of the tracking circuit 1 according to this modification will be described. Figure 5 FIG. 1 is a partial circuit configuration diagram of the tracking circuit 1 according to this modification.

[0234] also, Figure 5 This is an exemplary circuit configuration, and the tracking circuit 1 can be implemented using any of a variety of circuit implementations and circuit technologies. Therefore, the description of the tracking circuit 1 provided below should not be interpreted in a limiting sense.

[0235] The tracking circuit 1 according to this modification includes a first filter circuit 41A, a second filter circuit 42A, and switches S56A and S57A instead of the first filter circuit 41 , the second filter circuit 42 , and the switches S56 and S57 of the first embodiment.

[0236] The first filter circuit 41A is switchably connected to the path 44. Specifically, the first filter circuit 41A is connected between the path 44 and the ground via a switch S56A. The first filter circuit 41A includes a series circuit (LC series circuit) of an inductor L51A and a capacitor C51A. One end of the series circuit of the inductor L51A and the capacitor C51A is connected to the path 44 via a switch S56A, and the other end of the series circuit of the inductor L51A and the capacitor C51A is grounded. Furthermore, the first filter circuit 41A is not limited to an LC series circuit.

[0237] Second filter circuit 42A is switchably connected to path 44, which connects output switch circuit 30 and power amplifier 2. Specifically, second filter circuit 42A is connected between path 44 and ground via switch S57A. Second filter circuit 42A includes a series circuit of inductor L52A and capacitor C52A. One end of the series circuit of inductor L52A and capacitor C52A is connected to path 44 via switch S57A, and the other end of the series circuit of inductor L52A and capacitor C52A is grounded. Furthermore, second filter circuit 42A is not limited to an LC series circuit.

[0238] The first filter circuit 41A and the second filter circuit 42A are sometimes referred to as pulse shaping networks or over-shaping filters. Furthermore, one of the first filter circuit 41A and the second filter circuit 42A may not be included in the tracking circuit 1. Conversely, only one of the first filter circuit 41A and the second filter circuit 42A may be included in the tracking circuit 1.

[0239] The switch S56A is an example of a first switch and serves as an on / off switch for the first filter circuit 41A. The switch S56A is connected between the path 44 and the first filter circuit 41A.

[0240] The switch S57A is an example of a second switch and serves as an on / off switch for the second filter circuit 42A. The switch S57A is connected between the path 44 and the second filter circuit 42A.

[0241] Switches S56A and S57A switch the connection of first filter circuit 41A and second filter circuit 42A. This allows first filter circuit 41A and second filter circuit 42A, in path 44, to vary the attenuation band of the band-stop filter used to remove noise from multiple discrete voltages. In other words, first filter circuit 41A and second filter circuit 42A function as variable filter circuits capable of switching multiple attenuation bands.

[0242] The first filter circuit 41A and the second filter circuit 42A according to this modification can realize the following three types of band rejection filters (i) to (iii) by controlling the opening and closing of the switches S56A and S57A.

[0243] (i) By closing switch S56A and opening switch S57A, first filter circuit 41A is connected to path 44, while second filter circuit 42A is disconnected from path 44. Thus, in path 44, first filter circuit 41A functions as a band-stop filter, while second filter circuit 42A does not function as a band-stop filter.

[0244] (ii) By closing the switch S56A and the switch S57A, the first filter circuit 41A and the second filter circuit 42A are connected to the path 44. Thus, in the path 44, the first filter circuit 41A and the second filter circuit 42A function as band-stop filters.

[0245] (iii) By opening switch S56A and closing switch S57A, second filter circuit 42A is connected to path 44, while first filter circuit 41A is disconnected from path 44. Consequently, in path 44, second filter circuit 42A functions as a band-stop filter, while first filter circuit 41A does not function as a band-stop filter.

[0246] Similar to the switches S56 and S57 in the first embodiment, the opening and closing of the switches S56A and S57A can be controlled based on, for example, the channel bandwidth and / or frequency band of the high-frequency signal RF.

[0247] As in Embodiment 1, the DPD circuit 71 according to this variation can switch the mathematical model and / or its parameter set used for DPD according to (i) to (iii) above. The relationship between the on / off states of the first filter circuit 41A and the second filter circuit 42A in this variation and the parameter set used for the mathematical model used for DPD is summarized in Table 2 below.

[0248] [Table 2]

[0249]

[0250] In Table 2, the first mathematical model, the second mathematical model, and the third mathematical model may be different from each other, or may be the same in any combination. In addition, the first to third parameter sets are at least partially different from each other.

[0251] Furthermore, the switch S56A may not be included in the tracking circuit 1. In this case, the first filter circuit 41A and the second filter circuit 42A cannot realize the band-stop filter of (iii) above, but can realize both the band-stop filters of (i) and (ii) above.

[0252] Furthermore, while at least one of switches S56A and S57A is closed in (i) to (iii) above, both switches S56A and S57A may be open. In this case, both first filter circuit 41A and second filter circuit 42A in path 44 do not function as band-stop filters. In other words, the variable filter circuit formed by first filter circuit 41A and second filter circuit 42A may not have an effective attenuation band.

[0253] [2.2 Effects, etc.]

[0254] As described above, in the power amplification system 7 involved in this variation, the first filter circuit 41A can also be connected between the path 44 and the ground, and the second filter circuit 42A can also be connected between the path 44 and the ground in parallel with the first filter circuit 41A. The power amplification system 7 can also include: a switch S56A connected between the path 44 and the first filter circuit 41A; and a switch S57A connected between the path 44 and the second filter circuit 42A.

[0255] Thus, even when the first filter circuit 41A and the second filter circuit 42A are connected to the path 44 in a shunt manner, nonlinear distortion in the power amplifier 2 can be reduced.

[0256] (Variation 2 of Implementation 1)

[0257] Next, a second variation of the first embodiment will be described. This variation differs from the first embodiment and its first variation primarily in the circuit configurations of the first and second filter circuits. This variation will be described below, focusing on the differences from the first embodiment and its first variation, with reference to the accompanying drawings.

[0258] Note that the circuit configuration of the communication device 6 according to this modification is the same as that of the first embodiment except for a portion of the tracking circuit 1 , and therefore illustration and description thereof will be appropriately omitted.

[0259] [3.1 Circuit Structure of Tracking Circuit 1]

[0260] While referring to Figure 6 Next, the circuit configuration of the tracking circuit 1 according to this modification will be described. Figure 6 FIG. 1 is a partial circuit configuration diagram of the tracking circuit 1 according to this modification.

[0261] also, Figure 6 This is an exemplary circuit configuration, and the tracking circuit 1 can be implemented using any of a variety of circuit implementations and circuit technologies. Therefore, the description of the tracking circuit 1 provided below should not be interpreted in a limiting sense.

[0262] The tracking circuit 1 according to this modification includes a first filter circuit 41A, a second filter circuit 42B, and a switch S56B instead of the first filter circuit 41 , the second filter circuit 42 , and the switches S56 and S57 of the first embodiment.

[0263] The first filter circuit 41A is switchably connected to the path 44. Specifically, the first filter circuit 41A is connected between the path 44 and the ground via the switch S56B. In the first filter circuit 41A, one end of the series circuit of the inductor L51A and the capacitor C51A is connected to the portion of the path 44 between the inductor L52B and the power amplifier 2, and the other end of the series circuit of the inductor L51A and the capacitor C51A is grounded.

[0264] Second filter circuit 42B is switchably connected to path 44. Specifically, second filter circuit 42B includes a series circuit of inductor L52B, inductor L51A, and capacitor C51A. One end of inductor L52B is connected to output switching circuit 30, and the other end of inductor L52B is connected to power amplifier 2. Second filter circuit 42B is sometimes referred to as a pulse shaping network or an over-shaping filter.

[0265] Switch S56B is a switch that switches between the first filter circuit 41A and the second filter circuit 42B. Switch S56B is connected in parallel with inductor L52B. That is, one end of switch S56B is connected to one end of inductor L52B, and the other end of switch S56B is connected to the other end of inductor L52B.

[0266] Switch S56B switches the connection between first filter circuit 41A and second filter circuit 42B. This allows first filter circuit 41A and second filter circuit 42B to vary the attenuation band of the band-stop filter used to remove noise from multiple discrete voltages in path 44. In other words, first filter circuit 41A and second filter circuit 42B function as a variable filter circuit capable of switching multiple attenuation bands.

[0267] The first filter circuit 41A and the second filter circuit 42B according to this modification can realize two types of band rejection filters shown in the following (i) to (ii) by controlling the opening and closing of the switch S56B.

[0268] (i) By closing the switch S56B, the first filter circuit 41A is connected to the path 44. Thus, in the path 44, the first filter circuit 41A functions as a band-stop filter, and the second filter circuit 42B does not function as a band-stop filter.

[0269] (ii) By opening the switch S56B, the second filter circuit 42B is connected to the path 44. Thus, in the path 44, the first filter circuit 41A does not function as a band-stop filter, and the second filter circuit 42B functions as a band-stop filter.

[0270] Similar to the switches S56 and S57 in the first embodiment, the opening and closing of the switch S56B can be controlled based on, for example, the channel bandwidth and / or frequency band of the high-frequency signal RF.

[0271] The DPD circuit 71 according to this variation can switch the mathematical model and / or its parameter set used for DPD according to (i) and (ii) above. The relationship between the on / off states of the first filter circuit 41A and the second filter circuit 42B in this variation and the parameter set used in the mathematical model for DPD is summarized in Table 3 below.

[0272] [Table 3]

[0273]

[0274] Furthermore, in Table 3, the first mathematical model and the second mathematical model may be different from each other or the same. In addition, the first parameter set and the second parameter set are at least partially different from each other.

[0275] [3.2 Effects, etc.]

[0276] As described above, in the power amplifier system 7 involved in this variant, the first filter circuit 41A can also include a series circuit of an inductor L51A and a capacitor C51A connected between the path 44 and the ground, the second filter circuit 42B can also include the inductor L51A and the capacitor C51A, and the inductor L52B connected between the output switching circuit 30 and the power amplifier 2, and the power amplifier system 7 can also have a switch S56B connected in parallel with the inductor L52B.

[0277] Thus, even when the first filter circuit 41A is connected to the path 44 in shunt and the second filter circuit 42B is connected to the path 44 in series, nonlinear distortion in the power amplifier 2 can be reduced.

[0278] (Variation 3 of Implementation 1)

[0279] Next, a third variation of the first embodiment will be described. This variation differs from the first embodiment primarily in that the second filter circuit is not included in the tracking circuit. This variation will be described below, focusing on the differences from the first embodiment, with reference to the accompanying drawings.

[0280] Note that the circuit configuration of the communication device 6 according to this modification is the same as that of the first embodiment except for a portion of the tracking circuit 1 , and therefore illustration and description thereof will be appropriately omitted.

[0281] [4.1 Circuit Structure of Tracking Circuit 1]

[0282] While referring to Figure 7 Next, the circuit configuration of the tracking circuit 1 according to this modification will be described. Figure 7 FIG. 1 is a partial circuit configuration diagram of the tracking circuit 1 according to this modification.

[0283] also, Figure 7 This is an exemplary circuit configuration, and the tracking circuit 1 can be implemented using any of a variety of circuit implementations and circuit technologies. Therefore, the description of the tracking circuit 1 provided below should not be interpreted in a limiting sense.

[0284] The tracking circuit 1 according to this variation does not include the second filter circuit 42 of the first embodiment. Accordingly, the switch S57 functions as a switch that switches between connecting and disconnecting the bypass path of the first filter circuit 41. Specifically, the switch S57 is connected between the output switch circuit 30 and the power amplifier 2 without passing through the first filter circuit 41. More specifically, one end of the switch S57 is connected to one end of the first filter circuit 41 via the switch S56, and the other end of the switch S57 is connected to the other end of the first filter circuit 41.

[0285] exist Figure 7 In the example, switches S56 and S57 are used to switch the first filter circuit 41 on and off. This allows the first filter circuit 41 to vary the attenuation band of the band-stop filter used to remove noise from multiple discrete voltages in path 44. More specifically, switches S56 and S57 can switch the presence or absence of the band-stop filter in path 44. In other words, the first filter circuit 41 functions as a variable filter circuit capable of switching the presence or absence of the attenuation band.

[0286] The first filter circuit 41 according to this modification example can achieve the following (i) to (ii) by controlling the opening and closing of the switches S56 and S57 .

[0287] (i) By opening the switch S56 and closing the switch S57, the first filter circuit 41 is disconnected from the path 44. Thus, in the path 44, the first filter circuit 41 does not function as a band-stop filter.

[0288] (ii) By closing the switch S56 and opening the switch S57A, the first filter circuit 41 is connected to the path 44. Thus, in the path 44, the first filter circuit 41 functions as a band-stop filter.

[0289] As in the first embodiment, the opening and closing of the switches S56 and S57 can be controlled based on, for example, the channel bandwidth and / or frequency band of the high-frequency signal RF.

[0290] As in Embodiment 1, the DPD circuit 71 of this variation can switch the mathematical model and / or its parameter set used for DPD according to (i) and (ii) above. The relationship between the on / off state of the first filter circuit 41 in this variation and the parameter set used in the mathematical model for DPD is summarized in Table 4 below.

[0291] [Table 4]

[0292]

[0293] Furthermore, in Table 7, the first mathematical model and the second mathematical model may be different from each other or the same. In addition, the first parameter set and the second parameter set are at least partially different from each other.

[0294] [4.2 Effects, etc.]

[0295] As described above, in the power amplification system 7 involved in this variant, the first filter circuit 41 can also be connected between the output switch circuit 30 and the power amplifier 2, and the power amplification system 7 can also include: a switch S56, connected between the output switch circuit 30 and the first filter circuit 41; and a switch S57, connected between the output switch circuit 30 and the power amplifier 2 without passing through the first filter circuit 41.

[0296] Thus, the mathematical model and / or parameter set can be switched according to whether the first filter circuit 41 is connected in series with the path 44 or not, thereby reducing the nonlinear distortion in the power amplifier 2 .

[0297] (Implementation Method 2)

[0298] Next, Embodiment 2 will be described. This embodiment differs from Embodiment 1 primarily in that a power supply voltage is supplied from a tracking circuit to two power amplifiers. This embodiment will be described below, focusing on differences from Embodiment 1, with reference to the accompanying drawings.

[0299] [5.1 Circuit Structure of Communication Device 6A]

[0300] While referring to Figure 8 Next, a circuit configuration of a communication device 6A according to this embodiment will be described. Figure 8 It is a circuit configuration diagram of a communication device 6A according to this embodiment.

[0301] also, Figure 8 This is an exemplary circuit configuration, and the communication device 6A can be implemented using any of a variety of circuit implementations and circuit technologies. Therefore, the description of the communication device 6A provided below should not be interpreted in a limiting sense.

[0302] like Figure 8 As shown, communication device 6A includes tracking circuit 1A, first and second power amplifiers 2A and 2B, RFIC 3, BBIC 4, and antennas 5A and 5B. Furthermore, power amplification system 7A includes tracking circuit 1A, first and second power amplifiers 2A and 2B, and RFIC 3.

[0303] Tracking circuit 1A can supply a plurality of discrete voltages exclusively to first power amplifier 2A and second power amplifier 2B as power supply voltages Vcc1 and Vcc2 in tracking mode. In this embodiment, D-ET mode and APT mode are used as tracking modes, but the present invention is not limited thereto.

[0304] The first power amplifier 2A is connected between the RFIC 3 and the antenna 5A. Furthermore, the first power amplifier 2A is connected to the tracking circuit 1A. The first power amplifier 2A can amplify the high-frequency signal RF1 (an example of a first input signal) supplied from the RFIC 3 using the power supply voltage Vcc1 supplied from the tracking circuit 1A.

[0305] The second power amplifier 2B is connected between the RFIC 3 and the antenna 5B. Furthermore, the second power amplifier 2B is connected to the tracking circuit 1A. The second power amplifier 2B can amplify the high-frequency signal RF2 (an example of a second input signal) supplied from the RFIC 3 using the power supply voltage Vcc2 supplied from the tracking circuit 1A.

[0306] RFIC3 is an example of a signal processing circuit that processes high-frequency signals. RFIC3 can receive digital IQ signals from BBIC4 and supply high-frequency signal RF1 to first power amplifier 2A. Furthermore, RFIC3 can receive digital IQ signals from BBIC4 and supply high-frequency signal RF2 to second power amplifier 2B. The internal structure of RFIC3 is the same as that of Embodiment 1, so its description is omitted.

[0307] BBIC4 is a baseband signal processing circuit that performs signal processing using a frequency band lower than that of high-frequency signals RF1 and RF2. BBIC4 digitally modulates bit sequences representing image signals for display and / or audio signals for communication via a speaker, generating digital IQ signals. These generated digital IQ signals are supplied to RFIC3. BBIC4 may not be included in communication device 6A.

[0308] Antenna 5A transmits high-frequency signal RF1 amplified by first power amplifier 2A to the outside of communication device 6A. Antenna 5B transmits high-frequency signal RF2 amplified by second power amplifier 2B to the outside of communication device 6A. Antennas 5A and / or 5B may not be included in communication device 6A.

[0309] [5.2 Circuit Structure of Tracking Circuit 1A]

[0310] Next, refer to Figure 8 The circuit configuration of the tracking circuit 1A will be described. The tracking circuit 1A includes a pre-regulator circuit 10, a switched capacitor circuit 20, an output switch circuit 30, a first filter circuit 41, a second filter circuit 42, a switch S56C, and a digital control circuit 60. The pre-regulator circuit 10, the switched capacitor circuit 20, and the digital control circuit 60 are the same as those in the first embodiment, and therefore their description is omitted.

[0311] The output switch circuit 30 can selectively output at least one of the plurality of discrete voltages generated by the switched capacitor circuit 20 exclusively to the first power amplifier 2A and the second power amplifier 2B.

[0312] The first filter circuit 41 and the second filter circuit 42 can attenuate noise from a plurality of discrete voltages supplied to the first power amplifier 2A and the second power amplifier 2B.

[0313] The switch S56C is an example of a first switch and serves as an on / off switch for the second filter circuit 42. The switch S56C is connected between the output switch circuit 30 and the second filter circuit 42.

[0314] [5.2.1 Circuit Structure of the First Filter Circuit 41 and the Second Filter Circuit 42]

[0315] Next, refer to Figure 9 Next, the circuit configurations of the first filter circuit 41 and the second filter circuit 42 included in the tracking circuit 1A will be described. Figure 9 2 is a circuit configuration diagram of a tracking circuit 1A according to this embodiment.

[0316] also, Figure 9 This is an exemplary circuit configuration, and the tracking circuit 1A can be implemented using any of a variety of circuit implementations and circuit technologies. Therefore, the following description of the tracking circuit 1A should not be interpreted in a limiting sense.

[0317] The circuit configurations of the pre-regulator circuit 10 , the switched capacitor circuit 20 , the output switch circuit 30 , and the digital control circuit 60 are the same as those in the first embodiment, and therefore their descriptions are omitted.

[0318] The first filter circuit 41 is connected to a first path 441, which connects the output switch circuit 30 to the first power amplifier 2A, and a second path 442, which connects the output switch circuit 30 to the second power amplifier 2B. Specifically, the first filter circuit 41 is connected between the output switch circuit 30 and the first power amplifier 2A. In the first filter circuit 41, one end of the parallel circuit of the inductor L51 and the capacitor C51 is connected to the output switch circuit 30, and the other end of the parallel circuit of the inductor L51 and the capacitor C51 is connected to the first power amplifier 2A.

[0319] The second filter circuit 42 is switchably connected to the first path 441 and the second path 442. Specifically, the second filter circuit 42 is connected between the output switch circuit 30 and the second power amplifier 2B via a switch S56C. In the second filter circuit 42, one end of the parallel circuit of the inductor L52 and the capacitor C52 is connected to the output switch circuit 30 via the switch S56C, and the other end of the parallel circuit of the inductor L52 and the capacitor C52 is connected to the second power amplifier 2B.

[0320] The second filter circuit 42 connected in this manner is switched on and off by switch S56C. Consequently, the second filter circuit 42 can change the attenuation band of the band-stop filter used to remove noise from multiple discrete voltages in the first path 441 and the second path 442. In other words, the first filter circuit 41 and the second filter circuit 42 function as a variable filter circuit capable of switching multiple attenuation bands.

[0321] The first filter circuit 41 and the second filter circuit 42 according to the present embodiment can realize the following three types of band rejection filters (i) to (iii) by controlling the opening and closing of the switch S56C.

[0322] (i) When the high-frequency signal RF1 is amplified by the first power amplifier 2A, the switch S56C is opened, thereby connecting the first filter circuit 41 to the first path 441 and disconnecting the second filter circuit 42 from the first path 441. As a result, in the first path 441, the first filter circuit 41 functions as a band-stop filter, while the second filter circuit 42 does not function as a band-stop filter.

[0323] (ii) When the high-frequency signal RF1 is amplified by the first power amplifier 2A, the switch S56C is closed, thereby connecting the first filter circuit 41 and the second filter circuit 42 to the first path 441. As a result, in the first path 441, the first filter circuit 41 and the second filter circuit 42 function as band-stop filters.

[0324] (iii) When the high-frequency signal RF2 is amplified by the second power amplifier 2B, the switch S56C is closed, thereby connecting the first filter circuit 41 and the second filter circuit 42 to the second path 442. As a result, the first filter circuit 41 and the second filter circuit 42 function as band-stop filters in the second path 442.

[0325] For example, the opening and closing of the switch S56C can be controlled based on a power amplifier for amplifying the high-frequency signal, a channel bandwidth of the high-frequency signal, a frequency band of the high-frequency signal, or any combination thereof.

[0326] The DPD circuit 71 according to this embodiment can switch the mathematical model and / or its parameter set used for DPD according to the above (i) to (iii). In this embodiment, the relationship between the on / off state of the first power amplifier 2A and the second power amplifier 2B, the on / off state of the first filter circuit 41 and the second filter circuit 42, and the parameter set used in the mathematical model for DPD is summarized in the following Table 5.

[0327] [Table 5]

[0328]

[0329] In Table 5, the first mathematical model, the second mathematical model, and the third mathematical model may be different from each other, or may be the same in any combination. In addition, the first to third parameter sets are at least partially different from each other.

[0330] Furthermore, the tracking circuit 1A may further include an additional switch connected between the output switch circuit 30 and the first filter circuit 41. In this case, the first filter circuit 41 and the second filter circuit 42 can realize the following band-stop filter (iv) in addition to the above (i) to (iii).

[0331] (iv) When the high-frequency signal RF2 is amplified by the second power amplifier 2B, the additional switch is opened and the switch S56C is closed, so that the second path 442 is disconnected from the first filter circuit 41 and connected to the second filter circuit 42. As a result, in the second path 442, the first filter circuit 41 does not function as a band-stop filter, and the second filter circuit 42 functions as a band-stop filter.

[0332] [5.3 Effects, etc.]

[0333] As described above, the power amplification system 7A according to the present embodiment includes: a first power amplifier 2A and a second power amplifier 2B; an output switch circuit 30 configured to selectively output at least one of a plurality of discrete voltages to the first power amplifier 2A and the second power amplifier 2B; a first filter circuit 41 connected to a first path 441 connecting the output switch circuit 30 and the first power amplifier 2A, and connected to a second path 442 connecting the output switch circuit 30 and the second power amplifier 2B; a second filter circuit 42 configured to be switchably connected to the first path 441 and to be switchably connected to the second path 442; and a DPD circuit 71 configured to switch the first input signal of the first power amplifier 2A and the second input signal of the second power amplifier 2B. The second input signal of the power amplifier 2B is predistorted. When the first power amplifier 2A amplifies the first input signal, (i) when the second filter circuit 42 is not connected to the first path 441, the DPD circuit 71 predistorts the first input signal using the first parameter set in the first mathematical model; (ii) when the second filter circuit 42 is connected to the first path 441, the DPD circuit 71 predistorts the first input signal using the second parameter set in the second mathematical model; and when the second power amplifier 2B amplifies the second input signal, (iii) when the second filter circuit 42 is connected to the second path 442, the DPD circuit 71 predistorts the second input signal using the third parameter set in the third mathematical model, where the first to third parameter sets are at least partially different from each other.

[0334] Thus, the mathematical model and / or parameter set are switched depending on whether the second filter circuit 42 is connected to the first path 441 for supplying multiple discrete voltages to the first power amplifier 2A. Therefore, the input signal of the first power amplifier 2A can be predistorted using a mathematical model and parameter set that linearly changes depending on whether the second filter circuit 42 is connected to the first path 441, thereby reducing nonlinear distortion in the first power amplifier 2A. Furthermore, according to this embodiment, the mathematical model and / or parameter set are switched depending on the first power amplifier 2A and the second power amplifier 2B. Therefore, the input signals of the first power amplifier 2A and the second power amplifier 2B can be predistorted using mathematical models and parameter sets that are respectively suitable for the first power amplifier 2A and the second power amplifier 2B, thereby reducing nonlinear distortion in the first power amplifier 2A and the second power amplifier 2B.

[0335] In addition, for example, in the power amplification system 7A involved in this embodiment, the first filter circuit 41 can also be connected between the output switch circuit 30 and the first power amplifier 2A, and the second filter circuit 42 can also be connected between the output switch circuit 30 and the second power amplifier 2B. The power amplification system can also have a switch S56C connected between the output switch circuit 30 and the second filter circuit 42.

[0336] Thus, when the first filter circuit 41 is connected in series with the first path 441 and the second filter circuit 42 is connected in series with the second path 442 , nonlinear distortion in the first power amplifier 2A and the second power amplifier 2B can be reduced.

[0337] Furthermore, regarding the DPD circuit 71 according to this embodiment, when the first power amplifier 2A amplifies the first input signal, (i) when the second filter circuit 42 is not connected to the first path 441, the DPD circuit 71 predistorts the first input signal of the first power amplifier 2A using the first parameter set in the first mathematical model. (ii) when the second filter circuit 42 is connected to the first path 441, the DPD circuit 71 predistorts the first input signal using the second parameter set in the second mathematical model. When the second power amplifier 2B amplifies the second input signal, (iii) when the second filter circuit 42 is connected to the second path 442, the DPD circuit 71 predistorts the second input signal using the third parameter set in the third mathematical model. The first to third parameter sets are at least partially different from each other.

[0338] Thus, the mathematical model and / or parameter set are switched depending on whether the second filter circuit 42 is connected to the first path 441 for supplying multiple discrete voltages to the first power amplifier 2A. Therefore, the input signal of the first power amplifier 2A can be predistorted using a mathematical model and parameter set that linearly changes depending on whether the second filter circuit 42 is connected to the first path 441, thereby reducing nonlinear distortion in the first power amplifier 2A. Furthermore, according to this embodiment, the mathematical model and / or parameter set are switched depending on the first power amplifier 2A and the second power amplifier 2B. Therefore, the input signals of the first power amplifier 2A and the second power amplifier 2B can be predistorted using mathematical models and parameter sets that are respectively suitable for the first power amplifier 2A and the second power amplifier 2B, thereby reducing nonlinear distortion in the first power amplifier 2A and the second power amplifier 2B.

[0339] (Variation 1 of Implementation 2)

[0340] Next, a first variation of the second embodiment will be described. This variation differs from the second embodiment primarily in the configurations of the first and second filter circuits. With reference to the accompanying drawings, this variation will be described below, focusing on the differences from the second embodiment and the first variation of the first embodiment.

[0341] Note that the circuit configuration of the communication device 6A according to this modification is the same as that of the second embodiment except for a portion of the tracking circuit 1A, and therefore illustration and description thereof will be appropriately omitted.

[0342] [6.1 Circuit Structure of Tracking Circuit 1A]

[0343] Referring to the circuit structure of the tracking circuit 1A according to this modification Figure 10 While explaining. Figure 10 FIG. 1 is a partial circuit configuration diagram of a tracking circuit 1A according to this modification.

[0344] also, Figure 10 This is an exemplary circuit configuration, and the tracking circuit 1A can be implemented using any of a variety of circuit implementations and circuit technologies. Therefore, the following description of the tracking circuit 1A should not be interpreted in a limiting sense.

[0345] A tracking circuit 1A according to this modification includes a first filter circuit 41A, a second filter circuit 42A, and a switch S56D instead of the first filter circuit 41 , the second filter circuit 42 , and the switch S56C of the second embodiment.

[0346] The first filter circuit 41A is connected to the first path 441 and the second path 442. Specifically, the first filter circuit 41A is connected between the first path 441 and the second path 442 and the ground. In the first filter circuit 41A, one end of the series circuit of the inductor L51A and the capacitor C51A is connected to the first path 441 and the second path 442, and the other end of the series circuit of the inductor L51A and the capacitor C51A is grounded.

[0347] The second filter circuit 42A is switchably connected to the first path 441 and the second path 442. Specifically, the second filter circuit 42A is connected between the first path 441 and the second path 442 and the ground via a switch S56D. In the second filter circuit 42A, one end of the series circuit of the inductor L52A and the capacitor C52A is connected to the first path 441 and the second path 442 via the switch S56D, and the other end of the series circuit of the inductor L52A and the capacitor C52A is grounded.

[0348] The switch S56D is an example of a first switch and serves as an on / off switch for the second filter circuit 42A. The switch S56D is connected between the first path 441 and the second filter circuit 42A.

[0349] Switch S56D switches the connection of first filter circuit 41A and second filter circuit 42A. This allows first filter circuit 41A and second filter circuit 42A to vary the attenuation band of the band-stop filters used to remove noise from multiple discrete voltages. In other words, first filter circuit 41A and second filter circuit 42A function as variable filter circuits capable of switching multiple attenuation bands.

[0350] The first filter circuit 41A and the second filter circuit 42A according to this modification example realize the following three types of band rejection filters (i) to (iii) by controlling the opening and closing of the switch S56D.

[0351] (i) When the high-frequency signal RF1 is amplified by the first power amplifier 2A, the switch S56D is opened, thereby connecting the first filter circuit 41A to the first path 441 and disconnecting the second filter circuit 42A from the first path 441. As a result, in the first path 441, the first filter circuit 41A functions as a band-stop filter, while the second filter circuit 42A does not function as a band-stop filter.

[0352] (ii) When the high-frequency signal RF1 is amplified by the first power amplifier 2A, closing the switch S56D connects the first filter circuit 41A and the second filter circuit 42A to the first path 441. As a result, the first filter circuit 41A and the second filter circuit 42A function as band-stop filters in the first path 441.

[0353] (iii) When the high-frequency signal RF2 is amplified by the second power amplifier 2B, the switch S56D is closed, thereby connecting the first filter circuit 41A and the second filter circuit 42A to the second path 442. As a result, the first filter circuit 41A and the second filter circuit 42A function as band-stop filters in the second path 442.

[0354] (iv) When the high-frequency signal RF2 is amplified by the second power amplifier 2B, the switch S56D is opened, thereby connecting the first filter circuit 41A to the second path 442 and disconnecting the second filter circuit 42A from the second path 442. As a result, in the second path 442, the first filter circuit 41A functions as a band-stop filter, while the second filter circuit 42A does not function as a band-stop filter.

[0355] Similar to the switch S56C in embodiment 2, the opening and closing of such a switch S56D can be controlled based on, for example, a power amplifier for amplifying the high-frequency signal, the channel bandwidth of the high-frequency signal, the frequency band of the high-frequency signal, or any combination thereof.

[0356] The DPD circuit 71 according to this variation can switch the mathematical model and / or its parameter set used for DPD according to (i) to (iv) above. In this variation, the relationship between the on / off state of the first power amplifier 2A and the second power amplifier 2B, the on / off state of the first filter circuit 41A and the second filter circuit 42A, and the parameter set used in the mathematical model for DPD is summarized in Table 6 below.

[0357] [Table 6]

[0358]

[0359] In Table 6, the first to fourth mathematical models may be different from each other, or may be the same in any combination. In addition, the first to fourth parameter sets may be at least partially different from each other.

[0360] Furthermore, tracking circuit 1A may further include an additional switch connected between first path 441 and first filter circuit 41A. In this case, first filter circuit 41A and second filter circuit 42A can implement the band-stop filters described in (v) and (vi) below, in addition to implementing (i) to (iv) above.

[0361] (v) When the high-frequency signal RF1 is amplified by the first power amplifier 2A, the additional switch is opened and the switch S56D is closed, so that the first filter circuit 41A is disconnected from the first path 441 and the second filter circuit 42A is connected to the first path 441. As a result, in the first path 441, the first filter circuit 41A does not function as a band-stop filter, and the second filter circuit 42A functions as a band-stop filter.

[0362] (vi) When the high-frequency signal RF2 is amplified by the second power amplifier 2B, the additional switch is opened and the switch S56D is closed, so that the first filter circuit 41A is disconnected from the second path 442 and the second filter circuit 42A is connected to the second path 442. As a result, in the second path 442, the first filter circuit 41A does not function as a band-stop filter, and the second filter circuit 42A functions as a band-stop filter.

[0363] [6.2 Effects, etc.]

[0364] As described above, in the power amplification system 7A involved in this variation, the first filter circuit 41A can also be connected between the first path 441 and the ground, the second filter circuit 42A can also be connected between the second path 442 and the ground, and the power amplification system 7A can further include a switch S56D connected between the second path 442 and the second filter circuit 42.

[0365] Thus, when the first filter circuit 41A and the second filter circuit 42A are connected to the first path 441 and the second path 442 in a shunt manner, nonlinear distortion in the first power amplifier 2A and the second power amplifier 2B can be reduced.

[0366] (Variation 2 of Implementation Example 2)

[0367] Next, a second variation of the second embodiment will be described. This variation differs from the second embodiment and its first variation primarily in the configuration of the first and second filter circuits. This variation will be described below, focusing on the differences from the second embodiment and its first variation, with reference to the accompanying drawings.

[0368] Note that the circuit configuration of the communication device 6A according to this modification is the same as that of the second embodiment except for a portion of the tracking circuit 1A, and therefore illustration and description thereof will be appropriately omitted.

[0369] [7.1 Circuit Structure of Tracking Circuit 1A]

[0370] While referring to Figure 11 Next, a circuit configuration of a tracking circuit 1A according to this modification will be described. Figure 11 FIG. 1 is a partial circuit configuration diagram of a tracking circuit 1A according to this modification.

[0371] also, Figure 11 This is an exemplary circuit configuration, and the tracking circuit 1A can be implemented using any of a variety of circuit implementations and circuit technologies. Therefore, the following description of the tracking circuit 1A should not be interpreted in a limiting sense.

[0372] A tracking circuit 1A according to this modification includes a first filter circuit 41A, a second filter circuit 42C, a third filter circuit 43C, and switches S56E and S57E instead of the first filter circuit 41 , the second filter circuit 42 , and the switch S56C of the second embodiment.

[0373] The first filter circuit 41A is switchably connected to the first path 441. Specifically, in the first filter circuit 41A, one end of the series circuit of the inductor L51A and the capacitor C51A is connected to the first path 441 via the switch S56E, and the other end of the series circuit of the inductor L51A and the capacitor C51A is grounded.

[0374] The second filter circuit 42C is switchably connected to the first path 441 and the second path 442. Specifically, the second filter circuit 42C includes a series circuit of an inductor L52C, an inductor L51A, and a capacitor C51A. One end of the series circuit of the inductor L52C, the inductor L51A, and the capacitor C51A is connected to the first path 441 and the second path 442 via a switch S57E, and the other end of the series circuit of the inductor L52C, the inductor L51A, and the capacitor C51A is grounded.

[0375] The third filter circuit 43C is switchably connected to the second path 442. Specifically, the third filter circuit 43C includes an inductor L52C and a series circuit of an inductor L51A and a capacitor C51A. One end of the inductor L52C is connected to the output switching circuit 30 via a switch S56E, and the other end of the inductor L52C is connected to the second power amplifier 2B. One end of the series circuit of the inductor L51A and capacitor C51A is connected to the second path 442 via a switch S56E, and the other end of the series circuit of the inductor L51A and capacitor C51A is grounded. In other words, the third filter circuit 43C differs from the second filter circuit 42C in that the inductor L52C and the second path 442 are connected in series, not in a shunt connection.

[0376] Switch S56E is an on / off switch for the first filter circuit 41A and the third filter circuit 43C. Switch S56E is connected between the first path 441 and the first filter circuit 41A, and between the output switch circuit 30 and the third filter circuit 43C. Specifically, one end of switch S56E is connected to the first path 441 and the output switch circuit 30, and the other end of switch S56E is connected to inductors L51A and L52C.

[0377] Switch S57E is an on / off switch for second filter circuit 42C. Switch S57E is connected between first path 441 and second filter circuit 42C, and between output switch circuit 30 and second power amplifier 2B. Specifically, one end of switch S57E is connected to first path 441 and output switch circuit 30, while the other end of switch S57E is connected to inductor L52C and second power amplifier 2B.

[0378] Switches S56E and S57E switch the connection of first filter circuit 41A, second filter circuit 42C, and third filter circuit 43C. This allows first filter circuit 41A, second filter circuit 42C, and third filter circuit 43C to vary the attenuation band of the band-stop filters used to remove noise from multiple discrete voltages. In other words, first filter circuit 41A, second filter circuit 42C, and third filter circuit 43C function as a variable filter circuit capable of switching multiple attenuation bands.

[0379] The first filter circuit 41A, the second filter circuit 42C, and the third filter circuit 43C according to this modification can realize the following four types of band rejection filters (i) to (iv) by controlling the opening and closing of the switches S56E and S57E.

[0380] (i) When the high-frequency signal RF1 is amplified by the first power amplifier 2A, by closing the switch S56E and opening the switch S57E, the first path 441 is connected to the first filter circuit 41A and disconnected from the second filter circuit 42C. As a result, in the first path 441, the first filter circuit 41A functions as a band-stop filter, while the second filter circuit 42C does not function as a band-stop filter.

[0381] (ii) When the high-frequency signal RF1 is amplified by the first power amplifier 2A, by opening switch S56E and closing switch S57E, the first path 441 is disconnected from the first filter circuit 41A and connected to the second filter circuit 42C. Consequently, the second filter circuit 42C functions as a band-stop filter in the first path 441.

[0382] (iii) When the high-frequency signal RF2 is amplified by the second power amplifier 2B, by opening switch S56E and closing switch S57E, the second path 442 is connected to the second filter circuit 42C and disconnected from the third filter circuit 43C. Consequently, the second filter circuit 42C functions as a band-stop filter in the second path 442.

[0383] (iv) When the high-frequency signal RF2 is amplified by the second power amplifier 2B, by opening switch S56E and closing switch S57E, the second path 442 is disconnected from the second filter circuit 42C and connected to the third filter circuit 43C. As a result, the third filter circuit 43C functions as a band-stop filter in the second path 442.

[0384] Similar to the switch S56C of embodiment 2, the opening and closing of such switches S56E and S57E can be controlled based on, for example, a power amplifier for amplifying high-frequency signals, a channel bandwidth of high-frequency signals, a frequency band of high-frequency signals, or any combination thereof.

[0385] In this variation, DPD circuit 71 can switch the mathematical model and / or its parameter set used for DPD according to (i) to (iv) above. In this variation, the relationship between the on / off states of first power amplifier 2A and second power amplifier 2B, the on / off states of first filter circuit 41A, second filter circuit 42C, and third filter circuit 43C, and the parameter set used in the mathematical model used for DPD is summarized in Table 7 below.

[0386] [Table 7]

[0387]

[0388] In Table 7, the first to fourth mathematical models may be different from each other, or may be the same in any combination. In addition, the first to fourth parameter sets may be at least partially different from each other.

[0389] [7.2 Effects, etc.]

[0390] As described above, the power amplification system 7A involved in this variant example can also include a third filter circuit 43C, the first filter circuit 41A can also include a series circuit of an inductor L51A and a capacitor C51A switchably connected between the first path 441 and the ground, the second filter circuit 42C can also include a series circuit of inductors L51A and L52C and a capacitor C51A switchably connected between the first path 441 and the second path 442 and the ground, the third filter circuit 43C can also include the inductor L51A and the capacitor C51A, and the inductor L52C connected between the output switch circuit 30 and the second power amplifier 2B, and the power amplification system 7A can further include: a switch S56E connected between the first path 441 and the first filter circuit 41A; and a switch S57E connected between the first path 441 and the second filter circuit 42C.

[0391] Thus, when the first filter circuit 41A and the second filter circuit 42C are switchably connected to the first path 441 and the second filter circuit 42C and the third filter circuit 43C are switchably connected to the second path 442, nonlinear distortion in the first power amplifier 2A and the second power amplifier 2B can be reduced.

[0392] (Implementation 3)

[0393] Next, Embodiment 3 will be described. This embodiment differs from Embodiments 1 and 2 primarily in that the power supply voltage is supplied from the tracking circuit to the three power amplifiers. This embodiment will be described below, focusing on the differences from Embodiments 1 and 2, with reference to the accompanying drawings.

[0394] [8.1 Circuit Structure of Communication Device 6B]

[0395] While referring to Figure 12 Next, a circuit configuration of the communication device 6B according to this embodiment will be described. Figure 12 It is a circuit configuration diagram of the communication device 6B according to this embodiment.

[0396] also, Figure 12 This is an exemplary circuit configuration, and the communication device 6B can be implemented using any of a variety of circuit implementations and circuit technologies. Therefore, the following description of the communication device 6B should not be interpreted in a limiting sense.

[0397] like Figure 12 As shown, communication device 6B includes tracking circuit 1B, first to third power amplifiers 2A to 2C, RFIC 3, BBIC 4, and antennas 5A to 5C. Furthermore, power amplifier system 7B includes tracking circuit 1B, first to third power amplifiers 2A to 2C, and RFIC 3.

[0398] Tracking circuit 1B can supply a plurality of discrete voltages as power supply voltages Vcc1 to Vcc3 exclusively to first to third power amplifiers 2A to 2C in tracking mode. In this embodiment, D-ET mode and APT mode are used as tracking modes, but the present invention is not limited thereto.

[0399] The first power amplifier 2A is connected between the RFIC 3 and the antenna 5A. Furthermore, the first power amplifier 2A is connected to the tracking circuit 1B. The first power amplifier 2A can amplify the high-frequency signal RF1 (an example of a first input signal) supplied from the RFIC 3 using the power supply voltage Vcc1 supplied from the tracking circuit 1B.

[0400] The second power amplifier 2B is connected between the RFIC 3 and the antenna 5B. Furthermore, the second power amplifier 2B is connected to the tracking circuit 1B. The second power amplifier 2B can amplify the high-frequency signal RF2 (an example of a second input signal) supplied from the RFIC 3 using the power supply voltage Vcc2 supplied from the tracking circuit 1B.

[0401] The third power amplifier 2C is connected between the RFIC 3 and the antenna 5C. Furthermore, the third power amplifier 2C is connected to the tracking circuit 1B. The third power amplifier 2C can amplify the high-frequency signal RF3 (an example of a third input signal) supplied from the RFIC 3 using the power supply voltage Vcc3 supplied from the tracking circuit 1B.

[0402] RFIC3 is an example of a signal processing circuit that processes high-frequency signals. RFIC3 can receive digital IQ signals from BBIC4 and supply high-frequency signal RF1 to first power amplifier 2A. Furthermore, RFIC3 can receive digital IQ signals from BBIC4 and supply high-frequency signal RF2 to second power amplifier 2B. Furthermore, RFIC3 can receive digital IQ signals from BBIC4 and supply high-frequency signal RF3 to third power amplifier 2C. The internal structure of RFIC3 is the same as that of Embodiment 1, and therefore its description will be omitted.

[0403] BBIC4 is a baseband signal processing circuit that performs signal processing using a frequency band lower than that of high-frequency signals RF1-RF3. BBIC4 digitally modulates bit sequences representing image signals for display and / or audio signals for speakerphone calls, generating digital IQ signals. These generated digital IQ signals are supplied to RFIC3. BBIC4 may not be included in communication device 6B.

[0404] Antenna 5A transmits high-frequency signal RF1 amplified by first power amplifier 2A to the outside of communication device 6B. Antenna 5B transmits high-frequency signal RF2 amplified by second power amplifier 2B to the outside of communication device 6B. Antenna 5C transmits high-frequency signal RF3 amplified by third power amplifier 2C to the outside of communication device 6B. Antennas 5A, 5B, 5C, or any combination thereof may not be included in communication device 6B.

[0405] [8.2 Circuit Structure of Tracking Circuit 1B]

[0406] Next, refer to Figure 12 The circuit configuration of the tracking circuit 1B will be described. The tracking circuit 1B includes a pre-regulator circuit 10, a switched capacitor circuit 20, an output switch circuit 30, a first filter circuit 41, a second filter circuit 42, and a third filter circuit 43, switches S56C and S57F, and a digital control circuit 60. The pre-regulator circuit 10, the switched capacitor circuit 20, and the digital control circuit 60 are the same as those in the first embodiment, and therefore their description is omitted.

[0407] The output switch circuit 30 can selectively and exclusively output at least one of the plurality of discrete voltages generated by the switched capacitor circuit 20 to the first to third power amplifiers 2A to 2C.

[0408] The first filter circuit 41 , the second filter circuit 42 , and the third filter circuit 43 can attenuate noise from a plurality of discrete voltages supplied to the first to third power amplifiers 2A to 2C.

[0409] Switches S56C and S57F are examples of first and second switches, respectively, and serve as on / off switches for the second filter circuit 42 and the third filter circuit 43. Switch S56C is connected between the output switch circuit 30 and the second filter circuit 42, and switch S57F is connected between the output switch circuit 30 and the third filter circuit 43.

[0410] [8.2.1 Circuit Structure of Third Filter Circuit 43]

[0411] Next, refer to Figure 13 Next, the circuit configuration of the third filter circuit 43 included in the tracking circuit 1B will be described. Figure 13 2 is a circuit configuration diagram of a tracking circuit 1B according to this embodiment.

[0412] also, Figure 13 This is an exemplary circuit configuration, and the tracking circuit 1B can be implemented using any of a variety of circuit implementations and circuit technologies. Therefore, the description of the tracking circuit 1B provided below should not be interpreted in a limiting sense.

[0413] The circuit configurations of the pre-regulator circuit 10 , the switched capacitor circuit 20 , the output switch circuit 30 , the first filter circuit 41 , the second filter circuit 42 , and the digital control circuit 60 are the same as those in the first or second embodiment, and thus their description is omitted.

[0414] The third filter circuit 43 is switchably connected to the first path 441, the second path 442, and the third path 443 (an example of a third path) connecting the output switch circuit 30 and the second power amplifier 2B. Specifically, the third filter circuit 43 is connected between the output switch circuit 30 and the third power amplifier 2C via a switch S57F. The third filter circuit 43 includes a parallel circuit of an inductor L53 and a capacitor C53. One end of the parallel circuit of the inductor L53 and the capacitor C53 is connected to the output switch circuit 30 via a switch S57F, and the other end of the parallel circuit of the inductor L53 and the capacitor C53 is connected to the third power amplifier 2C. Furthermore, the third filter circuit 43 is not limited to an LC parallel circuit.

[0415] The third filter circuit 43 connected in this manner is switched on and off by switch S57F. This allows the third filter circuit 43 to vary the attenuation band of the band-stop filter used to remove noise from multiple discrete voltages in the first path 441 through the third path 443. In other words, the first filter circuit 41, the second filter circuit 42, and the third filter circuit 43 function as a variable filter circuit capable of switching multiple attenuation bands.

[0416] The first filter circuit 41 , the second filter circuit 42 , and the third filter circuit 43 according to this embodiment can realize eight types of band rejection filters shown in the following (i) to (viii) by controlling the opening and closing of the switches S56C and S57F.

[0417] (i) When the high-frequency signal RF1 is amplified by the first power amplifier 2A, by opening switches S56C and S57F, the first filter circuit 41 is connected to the first path 441, while the second filter circuit 42 and the third filter circuit 43 are disconnected from the first path 441. As a result, in the first path 441, the first filter circuit 41 functions as a band-stop filter, while the second filter circuit 42 and the third filter circuit 43 do not function as band-stop filters.

[0418] (ii) When the high-frequency signal RF1 is amplified by the first power amplifier 2A, by closing the switch S56C and opening the switch S57F, the first filter circuit 41 and the second filter circuit 42 are connected to the first path 441, and the third filter circuit 43 is disconnected from the first path 441. As a result, in the first path 441, the first filter circuit 41 and the second filter circuit 42 function as band-stop filters, and the third filter circuit 43 does not function as a band-stop filter.

[0419] (iii) When the high-frequency signal RF1 is amplified by the first power amplifier 2A, the switch S56C is opened and the switch S57F is closed, thereby connecting the first filter circuit 41 and the third filter circuit 43 to the first path 441, and disconnecting the second filter circuit 42 from the first path 441. As a result, in the first path 441, the first filter circuit 41 and the third filter circuit 43 function as band-stop filters, while the second filter circuit 42 does not function as a band-stop filter.

[0420] (iv) When the high-frequency signal RF1 is amplified by the first power amplifier 2A, by closing switches S56C and S57F, the first filter circuit 41, the second filter circuit 42, and the third filter circuit 43 are connected to the first path 441. As a result, in the first path 441, the first filter circuit 41, the second filter circuit 42, and the third filter circuit 43 function as band-stop filters.

[0421] (v) When the high-frequency signal RF2 is amplified by the second power amplifier 2B, the switch S56C is closed and the switch S57F is opened, thereby connecting the first filter circuit 41 and the second filter circuit 42 to the second path 442, and disconnecting the third filter circuit 43 from the second path 442. As a result, in the second path 442, the first filter circuit 41 and the second filter circuit 42 function as band-stop filters, while the third filter circuit 43 does not function as a band-stop filter.

[0422] (vi) When the high-frequency signal RF2 is amplified by the second power amplifier 2B, by closing switches S56C and S57F, the first filter circuit 41, the second filter circuit 42, and the third filter circuit 43 are connected to the second path 442. As a result, in the second path 442, the first filter circuit 41, the second filter circuit 42, and the third filter circuit 43 function as band-stop filters.

[0423] (vii) When the third power amplifier 2C amplifies the high-frequency signal RF3, by opening the switch S56C and closing the switch S57F, the first filter circuit 41 and the third filter circuit 43 are connected to the third path 443, and the second filter circuit 42 is disconnected from the third path 443. As a result, in the third path 443, the first filter circuit 41 and the third filter circuit 43 function as band-stop filters, and the second filter circuit 42 does not function as a band-stop filter.

[0424] (viii) When the third power amplifier 2C amplifies the high-frequency signal RF3, by closing switches S56C and S57F, the first filter circuit 41, the second filter circuit 42, and the third filter circuit 43 are connected to the third path 443. Thus, in the third path 443, the first filter circuit 41, the second filter circuit 42, and the third filter circuit 43 function as band-stop filters.

[0425] Similar to the switch S56C of embodiment 2, the opening and closing of such switches S56C and S57F can be controlled based on, for example, a power amplifier for amplifying high-frequency signals, a channel bandwidth of high-frequency signals, a frequency band of high-frequency signals, or any combination thereof.

[0426] The DPD circuit 71 according to this embodiment can switch the mathematical model and / or its parameter set used for DPD according to the above (i) to (viii). In this embodiment, the relationship between the on / off state of the first power amplifier 2A, the second power amplifier 2B, and the third power amplifier 2C, the on / off state of the first filter circuit 41, the second filter circuit 42, and the third filter circuit 43, and the parameter set used in the mathematical model for DPD is summarized in Table 8 below.

[0427] [Table 8]

[0428]

[0429] Furthermore, in Table 8, the first to eighth mathematical models may be different from each other, or may be the same in any combination. In addition, the first to eighth parameter sets may be at least partially different from each other.

[0430] Furthermore, the tracking circuit 1B may further include an additional switch connected between the output switch circuit 30 and the first filter circuit 41. In this case, the first filter circuit 41, the second filter circuit 42, and the third filter circuit 43 can implement the band-stop filters (ix) to (xii) below in addition to the above (i) to (viii).

[0431] (ix) When the high-frequency signal RF2 is amplified by the second power amplifier 2B, the additional switch and the switch S57F are opened, and the switch S56C is closed. This disconnects the first filter circuit 41 and the third filter circuit 43 from the second path 442, and connects the second filter circuit 42 to the second path 442. Consequently, in the second path 442, the first filter circuit 41 and the third filter circuit 43 do not function as band-stop filters, and the second filter circuit 42 functions as a band-stop filter.

[0432] (x) When the high-frequency signal RF2 is amplified by the second power amplifier 2B, the additional switch is opened and the switches S56C and S57F are closed, so that the first filter circuit 41 is disconnected from the second path 442, and the second filter circuit 42 and the third filter circuit 43 are connected to the second path 442. As a result, in the second path 442, the first filter circuit 41 does not function as a band-stop filter, and the second filter circuit 42 and the third filter circuit 43 function as band-stop filters.

[0433] (xi) When the high-frequency signal RF3 is amplified by the third power amplifier 2C, the additional switch and the switch S56C are opened, and the switch S57F is closed. This disconnects the first filter circuit 41 and the second filter circuit 42 from the third path 443, and connects the third filter circuit 43 to the third path 443. Consequently, in the third path 443, the first filter circuit 41 and the second filter circuit 42 do not function as band-stop filters, and the third filter circuit 43 functions as a band-stop filter.

[0434] (xii) When the third power amplifier 2C amplifies the high-frequency signal RF3, the additional switch is opened and the switches S56C and S57F are closed, so that the first filter circuit 41 is disconnected from the third path 443, and the second filter circuit 42 and the third filter circuit 43 are connected to the third path 443. As a result, in the third path 443, the first filter circuit 41 does not function as a band-stop filter, and the second filter circuit 42 and the third filter circuit 43 function as band-stop filters.

[0435] [8.3 Effects, etc.]

[0436] As described above, the power amplification system 7B according to this embodiment includes: a first power amplifier 2A, a second power amplifier 2B, and a third power amplifier 2C; an output switch circuit 30 configured to selectively output at least one of a plurality of discrete voltages to the first power amplifier 2A, the second power amplifier 2B, and the third power amplifier 2C; a first filter circuit 41 connected to a first path 441 connecting the output switch circuit 30 to the first power amplifier 2A, a second path 442 connecting the output switch circuit 30 to the second power amplifier 2B, and a third path 443 connecting the output switch circuit 30 to the third power amplifier 2C; a second filter circuit 42 switchably connected to the first path 441, the second path 442, and the third path 443; and a third filter circuit 43 switchably connected to the first path 441, the second path 442, and the third path 443.and a DPD circuit configured to predistort a first input signal of the first power amplifier 2A, a second input signal of the second power amplifier 2B, and a third input signal of the third power amplifier 2C. When the first power amplifier 2A amplifies the first input signal, (i) when the second filter circuit 42 and the third filter circuit 43 are not connected to the first path 441, the DPD circuit predistorts the first input signal using a first parameter set in a first mathematical model. (ii) when the second filter circuit 42 is connected to the first path 441 and the third filter circuit 43 is not connected to the first path 441, the DPD circuit predistorts the first input signal using a second parameter set in a second mathematical model. (iii) when the second filter circuit 42 is not connected to the first path 441 and the third filter circuit 43 is connected to the first path 441, the DPD circuit predistorts the first input signal using a third parameter set in a third mathematical model. (iv) when the second filter circuit 42 and the third filter circuit 43 are connected to the first path 441, the DPD circuit predistorts the first input signal using a fourth parameter set in a fourth mathematical model. The DPD circuit predistorts the first input signal. When the second power amplifier 2B amplifies the second input signal, (v) when the second filter circuit 42 is connected to the second path 442 and the third filter circuit 43 is not connected to the second path 442, the DPD circuit predistorts the second input signal using a fifth parameter set in a fifth mathematical model. (vi) when the second filter circuit 42 and the third filter circuit 43 are connected to the second path 442, the DPD circuit predistorts the second input signal using a sixth parameter set in a sixth mathematical model. When the third power amplifier 2C amplifies the third input signal, (vii) when the second filter circuit 42 is not connected to the third path 443 and the third filter circuit 43 is connected to the third path 443, the DPD circuit predistorts the third input signal using a seventh parameter set in a seventh mathematical model. (viii) when the second filter circuit 42 and the third filter circuit 43 are connected to the third path 443, the DPD circuit predistorts the third input signal using an eighth parameter set in an eighth mathematical model. The first through eighth parameter sets are at least partially different from one another.

[0437] Thus, the mathematical model and / or parameter set are switched depending on whether the first path 441 for supplying multiple discrete voltages to the first power amplifier 2A is connected to the second filter circuit 42 and whether it is connected to the third filter circuit 43. Therefore, the input signal of the first power amplifier 2A can be predistorted using a mathematical model and parameter set that linearly changes depending on whether the second filter circuit 42 and the third filter circuit 43 are connected to the first path 441, thereby reducing nonlinear distortion in the first power amplifier 2A. Furthermore, according to this embodiment, the mathematical model and / or parameter set are switched depending on whether the third filter circuit 43 is connected to the second path 442 for supplying multiple discrete voltages to the second power amplifier 2B. Therefore, the input signal of the second power amplifier 2B can be predistorted using a mathematical model and parameter set that linearly changes depending on whether the third filter circuit 43 is connected to the second path 442, thereby reducing nonlinear distortion in the second power amplifier 2B. Furthermore, according to this embodiment, the mathematical model and / or parameter set is switched depending on whether the second filter circuit 42 is connected to the third path 443 for supplying multiple discrete voltages to the third power amplifier 2C. Therefore, the input signal of the third power amplifier 2C can be predistorted using a mathematical model and parameter set that linearly changes depending on whether the second filter circuit 42 is connected to the third path 443, thereby reducing nonlinear distortion in the third power amplifier 2C. Furthermore, according to this embodiment, the mathematical model and / or parameter set is switched depending on the first to third power amplifiers 2A to 2C. Therefore, the input signals of the first to third power amplifiers 2A to 2C can be predistorted using mathematical models and parameter sets that are respectively suitable for the first to third power amplifiers 2A to 2C, thereby reducing nonlinear distortion in the first to third power amplifiers 2A to 2C.

[0438] In addition, for example, in the power amplification system 7B involved in this embodiment, the first filter circuit 41 can also be connected between the output switch circuit 30 and the first power amplifier 2A, the second filter circuit 42 can also be connected between the output switch circuit 30 and the second power amplifier 2B, and the third filter circuit 43 can also be connected between the output switch circuit 30 and the third power amplifier 2C. The power amplification system 7B can also include: a switch S56C, connected between the output switch circuit 30 and the second filter circuit 42; and a switch S57F, connected between the output switch circuit 30 and the third filter circuit 43.

[0439] Thus, when the first filter circuit 41 is connected in series with the first path 441 , the second filter circuit 42 is connected in series with the second path 442 , and the third filter circuit 43 is connected in series with the third path 443 , nonlinear distortion in the first to third power amplifiers 2A to 2C can be reduced.

[0440] Furthermore, regarding the DPD circuit 71 according to this embodiment, when the first power amplifier 2A amplifies the first input signal, (i) when the second filter circuit 42 and the third filter circuit 43 are not connected to the first path 441, the DPD circuit 71 predistorts the first input signal using the first parameter set in the first mathematical model. (ii) when the second filter circuit 42 is connected to the first path 441 and the third filter circuit 43 is not connected to the first path 441, the DPD circuit 71 predistorts the first input signal using the second parameter set in the second mathematical model. (iii) when the second filter circuit 42 is not connected to the first path 441 and the third filter circuit 43 is connected to the first path 441, the DPD circuit 71 predistorts the first input signal using the third parameter set in the third mathematical model. (iv) when the second filter circuit 42 and the third filter circuit 43 are connected to the first path 441, the DPD circuit 71 predistorts the first input signal using the fourth parameter set in the fourth mathematical model. In the case of a large second input signal, (v) when the second filter circuit 42 is connected to the second path 442 and the third filter circuit 43 is not connected to the second path 442, the DPD circuit 71 predistorts the second input signal using a fifth parameter set in a fifth mathematical model. (vi) when the second filter circuit 42 and the third filter circuit 43 are connected to the second path 442, the DPD circuit 71 predistorts the second input signal using a sixth parameter set in a sixth mathematical model. When the third power amplifier 2C amplifies the third input signal, (vii) when the second filter circuit 42 is not connected to the third path 443 and the third filter circuit 43 is connected to the third path 443, the DPD circuit 71 predistorts the third input signal using a seventh parameter set in a seventh mathematical model. (viii) when the second filter circuit 42 and the third filter circuit 43 are connected to the third path 443, the DPD circuit 71 predistorts the third input signal using an eighth parameter set in an eighth mathematical model. The first to eighth parameter sets are at least partially different from each other.

[0441] Thus, the mathematical model and / or parameter set are switched depending on whether the first path 441 for supplying multiple discrete voltages to the first power amplifier 2A is connected to the second filter circuit 42 and whether it is connected to the third filter circuit 43. Therefore, the input signal of the first power amplifier 2A can be predistorted using a mathematical model and parameter set that linearly changes depending on whether the second filter circuit 42 and the third filter circuit 43 are connected to the first path 441, thereby reducing nonlinear distortion in the first power amplifier 2A. Furthermore, according to this embodiment, the mathematical model and / or parameter set are switched depending on whether the third filter circuit 43 is connected to the second path 442 for supplying multiple discrete voltages to the second power amplifier 2B. Therefore, the input signal of the second power amplifier 2B can be predistorted using a mathematical model and parameter set that linearly changes depending on whether the third filter circuit 43 is connected to the second path 442, thereby reducing nonlinear distortion in the second power amplifier 2B. Furthermore, according to this embodiment, the mathematical model and / or parameter set is switched depending on whether the second filter circuit 42 is connected to the third path 443 for supplying multiple discrete voltages to the third power amplifier 2C. Therefore, the input signal of the third power amplifier 2C can be predistorted using a mathematical model and parameter set that linearly changes depending on whether the second filter circuit 42 is connected to the third path 443, thereby reducing nonlinear distortion in the third power amplifier 2C. Furthermore, according to this embodiment, the mathematical model and / or parameter set is switched depending on the first to third power amplifiers 2A to 2C. Therefore, the input signals of the first to third power amplifiers 2A to 2C can be predistorted using mathematical models and parameter sets that are respectively suitable for the first to third power amplifiers 2A to 2C, thereby reducing nonlinear distortion in the first to third power amplifiers 2A to 2C.

[0442] (Variation 1 of Implementation 3)

[0443] Next, a first variation of the third embodiment will be described. This variation differs from the third embodiment primarily in the configurations of the first, second, and third filter circuits. With reference to the accompanying drawings, this variation will be described below, focusing on the differences from the third embodiment and the first variation of the second embodiment.

[0444] Note that the circuit configuration of the communication device 6B according to this modification is the same as that of the first modification of the second embodiment and the third embodiment except for a portion of the tracking circuit 1B, and therefore illustration and description thereof will be appropriately omitted.

[0445] [9.1 Circuit Structure of Tracking Circuit 1B]

[0446] While referring to Figure 14 Next, a circuit configuration of a tracking circuit 1B according to this modification will be described. Figure 14 FIG. 1 is a partial circuit configuration diagram of a tracking circuit 1B according to this modification.

[0447] also, Figure 14 This is an exemplary circuit configuration, and the tracking circuit 1B can be implemented using any of a variety of circuit implementations and circuit technologies. Therefore, the description of the tracking circuit 1B provided below should not be interpreted in a limiting sense.

[0448] The tracking circuit 1B according to this modification includes a first filter circuit 41A, a second filter circuit 42A, a third filter circuit 43A, and switches S56D and S57G instead of the first filter circuit 41, the second filter circuit 42, the third filter circuit 43, and the switches S56C and S57F of the third embodiment.

[0449] The third filter circuit 43A is switchably connected to the first through third paths 441 through 443. Specifically, the third filter circuit 43A is connected between the first through third paths 441 through 443 and the ground via a switch S57G. The third filter circuit 43A includes a series circuit of an inductor L53A and a capacitor C53A. One end of the series circuit of the inductor L53A and capacitor C53A is connected to the first through third paths 441 through 443 via a switch S57G, while the other end of the series circuit of the inductor L53A and capacitor C53A is grounded. Furthermore, the third filter circuit 43A is not limited to an LC series circuit.

[0450] The switch S57G is an example of a second switch and serves as an on / off switch for the third filter circuit 43A. The switch S57G is connected between the third path 443 and the third filter circuit 43A.

[0451] Switch S57G switches the third filter circuit 43A connected in this manner on and off. This allows the third filter circuit 43A to vary the attenuation band of the band-stop filter used to remove noise from multiple discrete voltages in the first through third paths 441 and 443. In other words, the first, second, and third filter circuits 41A, 42A, and 43A function as a variable filter circuit capable of switching multiple attenuation bands.

[0452] The first filter circuit 41A, the second filter circuit 42A, and the third filter circuit 43A according to this modification can realize twelve types of band rejection filters shown in the following (i) to (xii) by controlling the opening and closing of the switches S56D and S57G.

[0453] (i) When the high-frequency signal RF1 is amplified by the first power amplifier 2A, by opening switches S56D and S57G, the first filter circuit 41A is connected to the first path 441, while the second filter circuit 42A and the third filter circuit 43A are disconnected from the first path 441. As a result, in the first path 441, the first filter circuit 41A functions as a band-stop filter, while the second filter circuit 42A and the third filter circuit 43A do not function as band-stop filters.

[0454] (ii) When the high-frequency signal RF1 is amplified by the first power amplifier 2A, by closing the switch S56D and opening the switch S57G, the first filter circuit 41A and the second filter circuit 42A are connected to the first path 441, and the third filter circuit 43A is disconnected from the first path 441. As a result, in the first path 441, the first filter circuit 41A and the second filter circuit 42A function as band-stop filters, while the third filter circuit 43A does not function as a band-stop filter.

[0455] (iii) When the high-frequency signal RF1 is amplified by the first power amplifier 2A, the switch S56D is opened and the switch S57G is closed, thereby connecting the first filter circuit 41A and the third filter circuit 43A to the first path 441, and disconnecting the second filter circuit 42A from the first path 441. As a result, in the first path 441, the first filter circuit 41A and the third filter circuit 43A function as band-stop filters, while the second filter circuit 42A does not function as a band-stop filter.

[0456] (iv) When the high-frequency signal RF1 is amplified by the first power amplifier 2A, by closing switches S56D and S57G, the first filter circuit 41A, the second filter circuit 42A, and the third filter circuit 43A are connected to the first path 441. As a result, in the first path 441, the first filter circuit 41A, the second filter circuit 42A, and the third filter circuit 43A function as band-stop filters.

[0457] (v) When the high-frequency signal RF2 is amplified by the second power amplifier 2B, the switch S56D is closed and the switch S57G is opened, thereby connecting the first filter circuit 41A and the second filter circuit 42A to the second path 442, and disconnecting the third filter circuit 43A from the second path 442. As a result, in the second path 442, the first filter circuit 41A and the second filter circuit 42A function as band-stop filters, while the third filter circuit 43A does not function as a band-stop filter.

[0458] (vi) When the high-frequency signal RF2 is amplified by the second power amplifier 2B, by closing switches S56D and S57G, the first filter circuit 41A, the second filter circuit 42A, and the third filter circuit 43A are connected to the second path 442. As a result, in the second path 442, the first filter circuit 41A, the second filter circuit 42A, and the third filter circuit 43A function as band-stop filters.

[0459] (vii) When the high-frequency signal RF3 is amplified by the third power amplifier 2C, the switch S56D is opened and the switch S57G is closed, thereby connecting the first filter circuit 41A and the third filter circuit 43A to the third path 443, and disconnecting the second filter circuit 42A from the third path 443. As a result, in the third path 443, the first filter circuit 41A and the third filter circuit 43A function as band-stop filters, while the second filter circuit 42A does not function as a band-stop filter.

[0460] (viii) When the third power amplifier 2C amplifies the high-frequency signal RF3, by closing switches S56D and S57G, the first filter circuit 41A, the second filter circuit 42A, and the third filter circuit 43A are connected to the third path 443. Thus, in the third path 443, the first filter circuit 41A, the second filter circuit 42A, and the third filter circuit 43A function as band-stop filters.

[0461] (ix) When the high-frequency signal RF2 is amplified by the second power amplifier 2B, the switches S56D and S57G are opened, thereby connecting the first filter circuit 41A to the second path 442 and disconnecting the second filter circuit 42A and the third filter circuit 43A from the second path 442. As a result, in the second path 442, the first filter circuit 41A functions as a band-stop filter, while the second filter circuit 42A and the third filter circuit 43A do not function as band-stop filters.

[0462] (x) When the high-frequency signal RF2 is amplified by the second power amplifier 2B, the switch S56D is opened and the switch S57G is closed, thereby connecting the first filter circuit 41A and the third filter circuit 43A to the second path 442, and disconnecting the second filter circuit 42A from the second path 442. As a result, in the second path 442, the first filter circuit 41A and the third filter circuit 43A function as band-stop filters, while the second filter circuit 42A does not function as a band-stop filter.

[0463] (xi) When the third power amplifier 2C amplifies the high-frequency signal RF3, by opening switches S56D and S57G, the first filter circuit 41A is connected to the third path 443, while the second filter circuit 42A and the third filter circuit 43A are disconnected from the third path 443. As a result, in the third path 443, the first filter circuit 41A functions as a band-stop filter, while the second filter circuit 42A and the third filter circuit 43A do not function as band-stop filters.

[0464] (xii) When the high-frequency signal RF3 is amplified by the third power amplifier 2C, by closing the switch S56D and opening the switch S57G, the first filter circuit 41A and the second filter circuit 42A are connected to the third path 443, while the third filter circuit 43A is disconnected from the third path 443. As a result, in the third path 443, the first filter circuit 41A and the second filter circuit 42A function as band-stop filters, while the third filter circuit 43A does not function as a band-stop filter.

[0465] Similar to switches S56C and S57F in embodiment 3, the opening and closing of such switches S56D and S57G can be controlled based on, for example, a power amplifier for amplifying high-frequency signals, the channel bandwidth of high-frequency signals, the frequency band of high-frequency signals, or any combination thereof.

[0466] The DPD circuit 71 according to this variation can switch the mathematical model and / or its parameter set used for DPD according to (i) to (xii) above. In this variation, the relationship between the on / off states of the first power amplifier 2A, the second power amplifier 2B, and the third power amplifier 2C, the on / off states of the first filter circuit 41A, the second filter circuit 42A, and the third filter circuit 43A, and the parameter set used in the mathematical model for DPD is summarized in Table 9 below.

[0467] [Table 9]

[0468]

[0469] In Table 9, the first to twelfth mathematical models may be different from each other, or may be the same in any combination. In addition, the first to twelfth parameter sets may be at least partially different from each other.

[0470] [9.2 Effects, etc.]

[0471] As described above, in the power amplification system 7B involved in this variation, the first filter circuit 41A can also be connected between the first path 441 and the ground, the second filter circuit 42A can also be connected between the second path 442 and the ground, and the third filter circuit 43A can also be connected between the third path 443 and the ground. The power amplification system 7B can further include: a switch S56D connected between the second path 442 and the second filter circuit 42A; and a switch S57G connected between the third path 443 and the third filter circuit 43A.

[0472] Thus, when the first to third filter circuits 41A to 43A are connected in shunt to the first to third paths 441 to 443 , nonlinear distortion in the first to third power amplifiers 2A to 2C can be reduced.

[0473] (Other Embodiments)

[0474] While the power amplifier system and DPD method according to the present invention have been described above based on the embodiments and their variations, the power amplifier system and DPD method according to the present invention are not limited to the aforementioned embodiments and their variations. Other embodiments implemented by combining arbitrary components of the aforementioned embodiments and their variations, variations resulting from various modifications conceived by those skilled in the art to the aforementioned embodiments and their variations without departing from the spirit of the present invention, and various devices incorporating the aforementioned power amplifier system are also encompassed by the present invention.

[0475] For example, in the circuit configurations of the various circuits involved in the above-described embodiments, other circuit elements and wiring may be inserted between the paths connecting the various circuit elements and signal paths disclosed in the drawings. For example, a filter may be inserted between the DAC 72 and the orthogonal modulator 73. Furthermore, for example, a filter may be inserted between the power amplifier 2 and the antenna 5.

[0476] Furthermore, in the above embodiment, multiple discrete voltages are supplied to the output switch circuit from a switched capacitor circuit, but the present invention is not limited thereto. For example, multiple voltages may be supplied from multiple DC-DC converters. Furthermore, when the voltage levels of the multiple discrete voltages are equally spaced, the use of a switched capacitor circuit is preferred, as it effectively reduces the size of the tracking module.

[0477] Furthermore, in the above embodiment, four discrete voltages are supplied to the power amplifier. However, the number of discrete voltages is not limited to four. For example, as long as the plurality of discrete voltages includes at least a voltage corresponding to the maximum output power and a voltage corresponding to the most frequently generated output power, the power added efficiency can be improved.

[0478] Industrial applicability

[0479] The present invention can be widely used in communication devices such as mobile phones as a power amplification system for amplifying high-frequency signals.

[0480] Description of Reference Signs

[0481] 1. 1A, 1B…tracking circuit; 2…power amplifier; 2A…first power amplifier; 2B…second power amplifier; 2C…third power amplifier; 3…RFIC; 4…BBIC; 5. 5A, 5B, 5C…antenna; 6. 6A, 6B…communication device; 7. 7A, 7B…power amplification system; 10…pre-regulator circuit; 20…switched capacitor circuit; 30…output switching circuit; 41. 41A…first filtering circuit; 42. 42A, 42B, 42C…second filtering circuit; 43. 43A, 43C…third filtering circuit; 44…path; 60…digital control circuit; 61…first controller; 62…second controller; 71…DPD circuit; 72…DAC; 73…quadrature modulator; 441…first path; 442…second path; 443…third path.

Claims

1. A power amplification system, wherein: have: a first power amplifier; an output switching circuit configured to selectively output at least one of a plurality of discrete voltages to the first power amplifier; a filter circuit switchably connected to a first path, wherein the first path connects the output switch circuit and the first power amplifier; as well as a digital predistortion circuit configured to predistort the first input signal of the first power amplifier; (i) when the filter circuit is not connected to the first path, the digital predistortion circuit predistorts the first input signal using a first parameter set in a first mathematical model; (ii) when the filter circuit is connected to the first path, the digital predistortion circuit predistorts the first input signal using a second parameter set in a second mathematical model; The first parameter set and the second parameter set are at least partially different from each other.

2. The power amplification system according to claim 1, wherein: The above-mentioned filtering circuit is a second filtering circuit, The power amplification system further includes a first filter circuit, the first filter circuit being switchably connected to the first path. (i) when the first filter circuit is connected to the first path and the second filter circuit is not connected to the first path, the digital predistortion circuit predistorts the first input signal using the first parameter set in the first mathematical model; (ii) when the first filter circuit is connected to the first path and the second filter circuit is connected to the first path, the digital predistortion circuit predistorts the first input signal using the second parameter set in the second mathematical model; (iii) when the first filter circuit is not connected to the first path and the second filter circuit is connected to the first path, the digital predistortion circuit predistorts the first input signal using a third parameter set in a third mathematical model; The first to third parameter sets are at least partially different from each other.

3. The power amplification system according to claim 2, wherein: The first filter circuit is connected between the output switch circuit and the first power amplifier. The second filter circuit is connected in parallel with the first filter circuit between the output switch circuit and the first power amplifier. The power amplification system further comprises: A first switch connected between the output switch circuit and the first filter circuit; and The second switch is connected between the output switch circuit and the second filter circuit.

4. The power amplification system according to claim 2, wherein: The first filter circuit is connected between the first path and the ground line. The second filter circuit is connected in parallel with the first filter circuit between the first path and the ground line. The power amplification system further comprises: a first switch connected between the first path and the first filter circuit; and The second switch is connected between the first path and the second filter circuit.

5. The power amplification system according to claim 1, wherein: The above-mentioned filtering circuit is a second filtering circuit, The power amplification system further comprises: a first filtering circuit connected to the first path; and The second power amplifier, The output switch circuit is further configured to selectively output at least one of the plurality of discrete voltages to the second power amplifier. The first filter circuit is further connected to a second path connecting the output switch circuit and the second power amplifier. The second filter circuit is further switchably connected to the second path. When the first power amplifier amplifies the first input signal, (i) when the second filter circuit is not connected to the first path, the digital predistortion circuit predistorts the first input signal using the first parameter set in the first mathematical model; (ii) when the second filter circuit is connected to the first path, the digital predistortion circuit predistorts the first input signal using the second parameter set in the second mathematical model; When the second power amplifier amplifies the second input signal, (iii) when the second filter circuit is connected to the second path, the digital predistortion circuit predistorts the second input signal using a third parameter set in a third mathematical model; The first to third parameter sets are at least partially different from each other.

6. The power amplification system according to claim 5, wherein: The first filter circuit is connected between the output switch circuit and the first power amplifier. The second filter circuit is connected between the output switch circuit and the second power amplifier. The power amplification system further includes a first switch connected between the output switching circuit and the second filter circuit.

7. The power amplification system according to claim 5, wherein: The first filter circuit is connected between the first path and the ground line. The second filter circuit is connected between the second path and the ground line. The power amplification system further includes a first switch connected between the second path and the second filter circuit.

8. The power amplification system according to claim 1, wherein: The above-mentioned filtering circuit is a second filtering circuit, The power amplification system further comprises: a first filtering circuit connected to the first path; a second power amplifier and a third power amplifier; and a third filter circuit switchably connected to the first path, switchably connected to the second path, and switchably connected to the third path, wherein the second path connects the output switch circuit and the second power amplifier, and the third path connects the output switch circuit and the third power amplifier. The output switch circuit is further configured to selectively output at least one of the plurality of discrete voltages to the second power amplifier and the third power amplifier. The first filter circuit is further connected to the second path and the third path. The second filter circuit is further switchably connected to the second path and switchably connected to the third path. When the first power amplifier amplifies the first input signal, (i) when the second filter circuit and the third filter circuit are not connected to the first path, the digital predistortion circuit predistorts the first input signal using the first parameter set in the first mathematical model; (ii) when the second filter circuit is connected to the first path and the third filter circuit is not connected to the first path, the digital predistortion circuit predistorts the first input signal using the second parameter set in the second mathematical model; (iii) when the second filter circuit is not connected to the first path and the third filter circuit is connected to the first path, the digital predistortion circuit predistorts the first input signal using a third parameter set in a third mathematical model; (iv) when the second filter circuit and the third filter circuit are connected to the first path, the digital predistortion circuit predistorts the first input signal using a fourth parameter set in a fourth mathematical model; When the second power amplifier amplifies the second input signal, (v) when the second filter circuit is connected to the second path and the third filter circuit is not connected to the second path, the digital predistortion circuit predistorts the second input signal using a fifth parameter set in a fifth mathematical model; (vi) when the second filter circuit and the third filter circuit are connected to the second path, the digital predistortion circuit predistorts the second input signal using a sixth parameter set in a sixth mathematical model; When the third power amplifier amplifies the third input signal, (vii) when the second filter circuit is not connected to the third path and the third filter circuit is connected to the third path, the digital predistortion circuit predistorts the third input signal using a seventh parameter set in a seventh mathematical model; (viii) when the second filter circuit and the third filter circuit are connected to the third path, the digital predistortion circuit predistorts the third input signal using an eighth parameter set in an eighth mathematical model; The first to eighth parameter sets are at least partially different from each other.

9. The power amplification system according to claim 8, wherein: The first filter circuit is connected between the output switch circuit and the first power amplifier. The second filter circuit is connected between the output switch circuit and the second power amplifier. The third filter circuit is connected between the output switch circuit and the third power amplifier. The power amplification system further comprises: A first switch connected between the output switch circuit and the second filter circuit; and The second switch is connected between the output switch circuit and the third filter circuit.

10. The power amplification system according to claim 8, wherein: The first filter circuit is connected between the first path and the ground line. The second filter circuit is connected between the second path and the ground line. The third filter circuit is connected between the third path and the ground line. The power amplification system further comprises: A first switch connected between the second path and the second filter circuit; and The second switch is connected between the third path and the third filter circuit.

11. The power amplification system according to claim 1, wherein: The filter circuit is connected between the output switch circuit and the first power amplifier. The power amplification system further comprises: A first switch connected between the output switch circuit and the filter circuit; and The second switch is connected between the output switch circuit and the first power amplifier without passing through the filter circuit.

12. A digital predistortion method, wherein: determining a mathematical model and a parameter set for digital predistortion based on an attenuation band of a variable filter circuit connected between an output switch circuit and a power amplifier, wherein the output switch circuit selectively supplies at least one of a plurality of discrete voltages to the power amplifier; The input signal of the power amplifier is predistorted using the determined parameter set in the determined mathematical model.

13. The digital predistortion method according to claim 12, wherein: In the above mathematical model and the determination of the above parameter set, In the case where the attenuation band of the variable filter circuit is wider than the threshold bandwidth, a first parameter set is determined. When the attenuation band of the variable filter circuit is not wider than the threshold bandwidth, a second parameter set having a smaller number of parameters than the first parameter set is determined.

14. A digital predistortion circuit, wherein: (i) a first path for selectively supplying at least one of a plurality of discrete voltages to a first power amplifier, wherein the digital predistortion circuit predistorts a first input signal of the first power amplifier using a first parameter set in a first mathematical model when the filter circuit switchably connected to the first path is not connected to the first path; (ii) when the filter circuit is connected to the first path, the digital predistortion circuit predistorts the first input signal using a second parameter set in a second mathematical model; The first parameter set and the second parameter set are at least partially different from each other.

15. The digital predistortion circuit according to claim 14, wherein: The above-mentioned filtering circuit is a second filtering circuit, (i) when a first filter circuit switchably connected to the first path is connected to the first path and the second filter circuit is not connected to the first path, the digital predistortion circuit predistorts the first input signal using the first parameter set in the first mathematical model; (ii) when the first filter circuit is connected to the first path and the second filter circuit is connected to the first path, the digital predistortion circuit predistorts the first input signal using the second parameter set in the second mathematical model; (iii) when the first filter circuit is not connected to the first path and the second filter circuit is connected to the first path, the digital predistortion circuit predistorts the first input signal using a third parameter set in a third mathematical model; The first to third parameter sets are at least partially different from each other.

16. The digital predistortion circuit according to claim 14, wherein: The above-mentioned filtering circuit is a second filtering circuit, The second filter circuit is further switchably connected to a second path, and the second path is used to selectively supply at least one of the plurality of discrete voltages to the second power amplifier. The first filter circuit is connected to the first path and the second path. When the first power amplifier amplifies the first input signal, (i) when the second filter circuit is not connected to the first path, the digital predistortion circuit predistorts the first input signal using the first parameter set in the first mathematical model; (ii) when the second filter circuit is connected to the first path, the digital predistortion circuit predistorts the first input signal using the second parameter set in the second mathematical model; When the second power amplifier amplifies the second input signal, (iii) when the second filter circuit is connected to the second path, the digital predistortion circuit predistorts the second input signal using a third parameter set in a third mathematical model; The first to third parameter sets are at least partially different from each other.

17. The digital predistortion circuit according to claim 14, wherein: The above-mentioned filtering circuit is a second filtering circuit, The second filter circuit is further switchably connected to a second path for selectively supplying at least one of the plurality of discrete voltages to a second power amplifier, and to a third path for selectively supplying at least one of the plurality of discrete voltages to a third power amplifier. The first filter circuit is connected to the first path, the second path, and the third path. The third filter circuit is switchably connected to the first path, the second path, and the third path. When the first power amplifier amplifies the first input signal, (i) when the second filter circuit and the third filter circuit are not connected to the first path, the digital predistortion circuit predistorts the first input signal using the first parameter set in the first mathematical model; (ii) when the second filter circuit is connected to the first path and the third filter circuit is not connected to the first path, the digital predistortion circuit predistorts the first input signal using the second parameter set in the second mathematical model; (iii) when the second filter circuit is not connected to the first path and the third filter circuit is connected to the first path, the digital predistortion circuit predistorts the first input signal using a third parameter set in a third mathematical model; (iv) when the second filter circuit and the third filter circuit are connected to the first path, the digital predistortion circuit predistorts the first input signal using a fourth parameter set in a fourth mathematical model; When the second power amplifier amplifies the second input signal, (v) when the second filter circuit is connected to the second path and the third filter circuit is not connected to the second path, the digital predistortion circuit predistorts the second input signal using a fifth parameter set in a fifth mathematical model; (vi) when the second filter circuit and the third filter circuit are connected to the second path, the digital predistortion circuit predistorts the second input signal using a sixth parameter set in a sixth mathematical model; When the third power amplifier amplifies the third input signal, (vii) when the second filter circuit is not connected to the third path and the third filter circuit is connected to the third path, the digital predistortion circuit predistorts the third input signal using a seventh parameter set in a seventh mathematical model; (viii) when the second filter circuit and the third filter circuit are connected to the third path, the digital predistortion circuit predistorts the third input signal using an eighth parameter set in an eighth mathematical model; The first to eighth parameter sets are at least partially different from each other.

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