N / P independent strained replacement metal gate (RMG) gate dicing for performance enhanced finfet

Abstract

The present disclosure describes a fin field effect transistor (FinFET). The FinFET includes a substrate and a shallow trench isolation (STI) region on the substrate. The FinFET also includes a first fin structure on the substrate and extending through the STI region. The FinFET also includes a second fin structure on the substrate and extending through the STI region. The FinFET also includes a metal gate on the STI region, on the first fin structure, and on the second fin structure. The metal gate includes a first sub-metal gate cut line filled with a first stressor material and a second sub-metal gate cut line filled with a second stressor material different from the first stressor material.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. patent application Ser. No. 18 / 098,633, filed on January 18, 2023, entitled “N / P-INDEPENDENTLY STRAINEDPOST-REPLACEMENT METAL GATE (RMG) GATE CUT FOR PERFORMANCE ENHANCED FINFET,” the disclosure of which is expressly incorporated herein by reference in its entirety. Technical Field

[0002] Aspects of the present disclosure relate to semiconductor devices, and more particularly to N / P independent strained post-replacement metal gate (RMG) gate cutting for performance enhanced fin-based field effect transistor (FinFET) technology. Background Art

[0003] As integrated circuit (IC) technology advances, device geometries decrease. Technological advances in IC materials and design have produced successive generations of integrated circuits, each with smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density has generally increased while geometric dimensions have decreased. This scaling down process has provided benefits by increasing production efficiency and reducing associated costs. However, this scaling down has also increased the complexity of IC processing and manufacturing. Furthermore, achieving these advances has involved similar developments in IC processing and manufacturing.

[0004] In some IC designs, as technology nodes shrink, one advancement is to replace polysilicon gate electrodes with metal gate electrodes to improve device performance by reducing feature sizes. Although existing methods for manufacturing IC devices are generally sufficient for their intended purposes, these methods are not completely satisfactory in all aspects. For example, fin-based devices are three-dimensional structures on the surface of a semiconductor substrate. Fin-based field effect transistors (FETs) can be referred to as FinFETs.

[0005] Advanced logic complementary metal oxide semiconductor (CMOS) scaling of FinFET technology has achieved higher performance power area (PPA) than previous process nodes. Unfortunately, further improvement of FinFET transistor mobility in process nodes below seven nanometers (nm) is difficult because conventional strain enhancers are reaching their limits. Therefore, a new strain enhancer is needed to continuously improve FinFET device performance. Summary of the Invention

[0006] A fin field-effect transistor (FinFET) is described. The FinFET includes a substrate and a shallow trench isolation (STI) region on the substrate. The FinFET also includes a first fin structure on the substrate and extending through the STI region. The FinFET further includes a second fin structure on the substrate and extending through the STI region. The FinFET also includes a metal gate on the STI region, the first fin structure, and the second fin structure. The metal gate includes a first sub-metal gate cut line filled with a first stressor material and a second sub-metal gate cut line filled with a second stressor material different from the first stressor material.

[0007] A method is described. The method includes replacing a dummy gate to form a metal gate on a shallow trench isolation (STI) region on a substrate and on a first fin structure and a second fin structure on the substrate. The method also includes applying a wire saw to separate the metal gate to form a first sub-metal gate cut line and a second sub-metal gate cut line. The method also includes filling the first sub-metal gate cut line with a first stressor material. The method also includes filling the second sub-metal gate cut line with a second stressor material different from the first stressor material.

[0008] A method is described. The method includes replacing a dummy gate to form a metal gate on a shallow trench isolation (STI) region on a substrate and on a first fin structure and a second fin structure on the substrate. The method also includes applying a wire cut to separate the metal gate to form a first sub-metal gate cut line and a second sub-metal gate cut line. The method also includes filling the first sub-metal gate cut line and the second sub-metal gate cut line with a first stressor material. The method also includes implanting ions into the first stressor material in the second sub-metal gate cut line to convert the first stressor material into a second stressor material different from the first stressor material.

[0009] This has been a fairly broad overview of the features and technical advantages of the present disclosure in order to better understand the detailed description below. Additional features and advantages of the present disclosure will be described below. It will be appreciated by those skilled in the art that the present disclosure can be easily used as a basis for modifying or designing other structures to achieve the same purpose of the present disclosure. It will also be appreciated by those skilled in the art that such equivalent constructions do not deviate from the teachings of the present disclosure as set forth in the appended claims. When considered in conjunction with the accompanying drawings, the novel features (including their construction and method of operation), and other objects and advantages that are considered to be characteristic of the present disclosure will be better understood from the following description. However, it will be clearly understood that each figure is provided for illustration and description purposes only and is not intended to be a limitation of the scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.

[0011] Figure 1 shows a perspective view of a semiconductor wafer;

[0012] Figure 2 A cross-sectional view of the die is shown;

[0013] Figure 3 shows a cross-sectional view of a metal oxide semiconductor field effect transistor (MOSFET) device;

[0014] Figure 4 A vertical fin field effect transistor (FinFET) is shown;

[0015] Figure 5A-5B is a schematic diagram illustrating an integrated circuit including a fin field effect transistor (FinFET) having independently strained N-type and P-type regions according to some aspects of the present disclosure;

[0016] Figure 6 illustrates a layout diagram of a fin field effect transistor (FinFET) with independently strained N-type and P-type regions according to aspects of the present disclosure;

[0017] Figure 7 is a flow chart illustrating a method of forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions according to some aspects of the present disclosure;

[0018] Figures 8A-8I is a schematic diagram illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions according to some aspects of the present disclosure;

[0019] Figures 9A-9G is a schematic diagram illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions using ion implantation according to some aspects of the present disclosure;

[0020] Figure 10 is a process flow diagram illustrating a method of fabricating a field effect transistor (FET) having independently strained N-type and P-type regions according to aspects of the present disclosure;

[0021] Figure 11 is a process flow diagram illustrating a method of fabricating a field effect transistor (FET) having independently strained N-type and P-type regions according to aspects of the present disclosure;

[0022] Figure 12is a block diagram illustrating an exemplary wireless communication system in which one aspect of the present disclosure may be advantageously employed; and

[0023] Figure 13 is a block diagram illustrating a design workstation for circuit, layout, and logic design of transistor structures according to one configuration. DETAILED DESCRIPTION

[0024] The detailed description presented below in conjunction with the accompanying drawings is intended to describe various configurations and is not intended to represent the only configuration in which the concepts described herein may be implemented. The detailed description includes specific details intended to provide a thorough understanding of the various concepts. However, it will be clear to those skilled in the art that these concepts may be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0025] As described herein, the use of the term "and / or" is intended to mean "open or", while the use of the term "or" is intended to mean "exclusive or". As described herein, the term "exemplary" as used throughout this specification means "serving as an example, instance, or illustration", and should not necessarily be interpreted as being preferred or advantageous over other exemplary configurations. As described herein, the term "coupled" as used in this specification means "connected directly or indirectly through an intervening connection (e.g., a switch), electrically, mechanically, or otherwise", and is not necessarily limited to physical connections. In addition, the connection can be such that the objects are permanently connected or releasably connected. The connection can be made by means of a switch. As described herein, the term "proximity" as used in this specification means "adjacent, very close, immediately adjacent, or close to". As described herein, the word "on..." as used in this specification means "directly on..." in some configurations and "indirectly on..." in other configurations.

[0026] As integrated circuit (IC) technology advances, device geometries decrease. Technological advances in IC materials and design have produced successive generations of integrated circuits, each with smaller and more complex circuits than the previous one. Throughout the evolution of ICs, functional density has generally increased while geometric dimensions have decreased. This scaling process has provided benefits by increasing production efficiency and reducing associated costs. However, this scaling has also increased the complexity of IC processing and manufacturing. Achieving these advances has involved similar developments in IC processing and manufacturing.

[0027] Fin-based devices represent a significant advancement in IC technology compared to planar-based devices. Fin-based devices are three-dimensional structures on the surface of a semiconductor substrate. A fin field-effect transistor (FinFET) is a type of fin-based metal-oxide-semiconductor field-effect transistor (MOSFET). Nanowire FETs also represent a significant advancement in IC technology. Gate-all-around (GAA) nanowire-based devices are another type of three-dimensional structure on the surface of a semiconductor substrate. Other fin-based devices include Ω-gate devices and π-gate devices. Fin-based field-effect transistors may be referred to as FinFET devices.

[0028] In some IC designs, as technology nodes shrink, one advancement is replacing polysilicon gate electrodes with metal gate electrodes to improve device performance by reducing feature sizes. While existing methods for manufacturing IC devices are generally adequate for their intended purpose, these methods are not entirely satisfactory in all respects. For example, fin-based devices can be implemented using replacement metal gate (RMG) technology.

[0029] Advanced logic complementary metal oxide semiconductor (CMOS) scaling of fin-based devices using RMG technology has achieved higher performance power area (PPA) than previous process nodes. Unfortunately, further improvement in fin-based transistor mobility at process nodes below seven nanometers (nm) is difficult because conventional strain enhancers are reaching their limits. Therefore, a new strain enhancer is needed to continuously improve the performance of fin-based transistors.

[0030] Various aspects of the present disclosure relate to independently strained N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS) regions of post-replacement metal gate (RMG) gate cut of fin-based devices for performance enhancement of fin-based field effect transistor (FinFET) technology. The process flow for manufacturing FinFET devices with independently strained NMOS and PMOS regions may include front-end of the line (FEOL) processes, middle of the line (MOL) processes, and back-end of the line (BEOL) processes. It should be understood that the term "layer" includes films and shall not be interpreted as indicating vertical or horizontal thickness unless otherwise specified. As described herein, the term "substrate" may refer to the substrate of a cut wafer, or may refer to the substrate of an uncut wafer. Likewise, the terms "wafer" and "die" may be used interchangeably unless such interchange would reduce credibility.

[0031] According to various aspects of the present disclosure, a fin field-effect transistor (FinFET) having independently strained N-type and P-type regions is described. The FinFET includes a substrate having a shallow trench isolation (STI) region on the substrate. The FinFET also includes a first fin structure on the substrate and extending through the STI region, and a second fin structure on the substrate and extending through the STI region. The FinFET also includes: a metal gate on the STI region, on the first fin structure, and on the second fin structure. In some aspects of the present disclosure, the metal gate is composed of a first sub-metal gate cut line filled with a first stressor material and a second sub-metal gate cut line filled with a second stressor material different from the first stressor material.

[0032] Figure 1 A perspective view of a semiconductor wafer according to various aspects of the present disclosure is shown, which can be used to manufacture FinFETs with independently strained N-type and P-type regions. Wafer 100 can be a semiconductor wafer, or can be a substrate material having one or more layers of semiconductor material on the surface of wafer 100. When wafer 100 is a semiconductor material, wafer 100 can be grown from a seed crystal using a Czochralski process, in which the seed crystal is immersed in a molten bath of semiconductor material and slowly rotated and removed from the bath. The molten material is then crystallized onto the seed crystal in a crystalline orientation.

[0033] Wafer 100 may be a single material (e.g., silicon (Si), germanium (Ge)), or a compound material (such as gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP)), a ternary material (such as indium gallium arsenide (InGaAs)), a quaternary material, or any material that can serve as a substrate material for other semiconductor materials. Although many materials can be crystalline in nature, polycrystalline or amorphous materials can also be used for wafer 100.

[0034] Wafer 100 or a layer coupled to wafer 100 may be provided with a material that makes wafer 100 more conductive. By way of example, and not limitation, a silicon wafer may have phosphorus or boron added to wafer 100 to allow charge to flow within wafer 100. These additives are called dopants and provide additional charge carriers (electrons or holes) within wafer 100 or portions of wafer 100. By selecting the areas in which the additional charge carriers are provided, which type of charge carriers are provided, and the amount (density) of the additional charge carriers within wafer 100, different types of electronic devices may be formed in or on wafer 100.

[0035] Wafer 100 has an orientation 102 indicating the crystallographic orientation of wafer 100. Orientation 102 may be, for example, Figure 1The wafer 100 is shown with a flat edge, or may be a notch or other marking to illustrate the crystal orientation of the wafer 100. The orientation 102 may indicate the Miller indices of the planes of the crystal lattice in the wafer 100.

[0036] Miller indices form a notation system for the planes in a lattice. A lattice plane can be represented by three integers h, k and (They are planes in the crystal Each index represents the relationship between the reciprocal lattice vector and the direction (h, k, ) are planes orthogonal to the direction h. These integers are usually written in their lowest terms (i.e., their greatest common divisor should be 1). A Miller index of 100 represents a plane orthogonal to the direction h; an index of 010 represents a plane orthogonal to the direction k, and an index of 001 represents a plane orthogonal to the direction k. For some crystals, negative numbers are used (written as bars above the index numbers), and for some crystals (such as gallium nitride), more than three numbers can be used to fully describe the different crystal planes.

[0037] Once wafer 100 has been processed as desired, wafer 100 is divided along scribe lines 104. Scribe lines 104 indicate where chips 100 will be singulated or separated into pieces. Scribe lines 104 may define the outlines of the various integrated circuits that have been fabricated on wafer 100.

[0038] Once scribe lines 104 are defined, wafer 100 may be sawn or otherwise separated into pieces to form die 106. Each of die 106 may be an integrated circuit having many devices, or may be a single electronic device. The physical size of die 106, which may also be referred to as a chip or semiconductor chip, depends at least in part on the ability to separate wafer 100 into specific sizes and the number of individual devices that die 106 is designed to include.

[0039] Once wafer 100 is separated into one or more die 106, die 106 may be mounted into a package to allow access to the devices and / or integrated circuits fabricated on die 106. The package may include a single-in-line package, a dual-in-line package, a motherboard package, a flip-chip package, an indium dot / bump package, or other types of devices that provide access to die 106. Die 106 may also be directly accessed via wire bonds, probes, or other connections without mounting die 106 in a separate package.

[0040] Figure 2 Shows aspects of the present disclosure Figure 1FIG2 is a cross-sectional view of a die 106 that can be used to fabricate a FinFET having independently strained N-type and P-type regions. In the die 106, there can be a substrate 200, which can be a semiconductor material and / or can serve as a mechanical support for the electronic device. The substrate 200 can be a doped semiconductor substrate having electrons (designated as N-channels) or holes (designated as P-channels) charge carriers distributed throughout the substrate 200. Subsequent doping of the substrate 200 with charge carrier ions / atoms can alter the charge carrying capacity of the substrate 200.

[0041] In a substrate 200 (e.g., a semiconductor substrate), wells 202 and 204 of a field effect transistor (FET) may be present, or the wells 202 and / or 204 may be fin structures of a fin-structured FET (FinFET). The wells 202 and / or 204 may also be other devices (e.g., resistors, capacitors, diodes, or other electronic devices), depending on the structure and other characteristics of the wells 202 and / or 204 and the surrounding structures of the substrate 200.

[0042] The semiconductor substrate may also have a well 206 and a well 208. The well 208 may be completely located within the well 206 and, in some cases, may form a bipolar junction transistor (BJT). The well 206 may also serve as an isolation well to isolate the well 208 from electric and / or magnetic fields within the die 106.

[0043] Layers (e.g., 210 to 214) may be added to die 106. Layer 210 may be, for example, an oxide or insulating layer that may isolate the wells (e.g., 202 to 208) from each other or from other devices on die 106. In this case, layer 210 may be silicon dioxide, a polymer, a dielectric, or another electrically insulating layer. Layer 210 may also be an interconnect layer, in which case it may include a conductive material such as copper, tungsten, aluminum, an alloy, or other conductive or metallic material.

[0044] Layer 212 may also be a dielectric layer or a conductive layer, depending on the desired device characteristics and / or the materials of the layers (e.g., 210 and 214). Layer 214 may be an encapsulation layer that protects layers (e.g., 210 and 212) as well as wells 202-208 and substrate 200 from external forces. By way of example, and not limitation, layer 214 may be a layer that protects die 106 from mechanical damage, or layer 214 may be a layer of material that protects die 106 from electromagnetic or radiation damage.

[0045] The electronic devices designed on the die 106 may include many features or structural components. For example, the die 106 may be exposed to a variety of methods to impart dopants into the substrate 200, the wells 202-208, and the layers (e.g., 210-214) (if desired). By way of example, and not limitation, the die 106 may be exposed to ion implantation, deposition of dopant atoms driven into the crystal lattice by a diffusion process, chemical vapor deposition, epitaxial growth, or other methods. By selective growth, material selection, and removal of portions of the layers (e.g., 210-214), as well as by selective removal, material selection, and dopant concentrations of the substrate 200 and wells 202-208, many different structures and electronic devices may be formed within the scope of the present disclosure.

[0046] Furthermore, substrate 200, wells 202-208, and layers (eg, 210-214) can be selectively removed or added by various processes. Chemical wet etching, chemical mechanical planarization (CMP), plasma etching, photoresist masking, damascene processes, and other methods can produce the structures and devices of the present disclosure.

[0047] Figure 3 A cross-sectional view of a metal oxide semiconductor field effect transistor (MOSFET) device 300 is shown. The MOSFET device 300 can have four input terminals. The four inputs are a source 302, a gate 304, a drain 306, and a body. The source 302 and drain 306 can be fabricated as wells 202 and 204 in a substrate 308, or can be fabricated as regions above the substrate 308, or can be fabricated as part of other layers on the die 106. Such other structures can be fins or other structures that protrude from the surface of the substrate 308. Furthermore, the substrate 308 can be the substrate 200 on the die 106, but the substrate 308 can also be one or more of the layers (e.g., 210-214) coupled to the substrate 200.

[0048] MOSFET device 300 is a unipolar device because current is generated by only one type of charge carrier (e.g., electrons or holes) depending on the type of MOSFET. MOSFET device 300 operates by controlling the amount of charge carriers in channel 310 between source 302 and drain 306. Voltage V 源极 312 is applied to the source 302, the voltage V 栅极 314 is applied to the gate 304, and the voltage V 漏极 316 is applied to the drain 306. A separate voltage V 基板 318 can also be applied to the substrate 308, although the voltage V 基板 318 can be coupled to a voltage V 源极 312, voltage V 栅极314 or voltage V 漏极 One of 316.

[0049] To control the charge carriers in the channel 310, when the gate 304 accumulates charge, the voltage V 栅极 314 generates an electric field in the channel 310. Charge opposite to the charge accumulated on the gate 304 begins to accumulate in the channel 310. The gate insulator 320 insulates the charge accumulated on the gate 304 from the source 302, the drain 306, and the channel 310. The gate 304 and the channel 310 (with the gate insulator 320 therebetween) create a capacitor, and as the voltage V 栅极 As the charge on the gate 304 increases, charge carriers on the gate 304 (acting as one plate of the capacitor) begin to accumulate. This accumulation of charge on the gate 304 attracts opposing charge carriers into the channel 310. Eventually, enough charge carriers accumulate in the channel 310 to provide a conductive path between the source 302 and the drain 306. This condition can be referred to as opening the channel of the FET.

[0050] By changing the voltage V 源极 312 and voltage V 漏极 316 and their relationship with voltage V 栅极 314, the amount of voltage applied to gate 304 to open channel 310 can vary. For example, voltage V 源极 312 usually has a voltage V 漏极 The potential of 316 is higher than the potential. 源极 312 and voltage V 漏极 A larger voltage difference between 316 will change the voltage V used to open channel 310. 栅极 314. In addition, a larger voltage difference will change the amount of electromotive force that moves charge carriers through channel 310, thereby generating a larger current through channel 310.

[0051] The gate insulator 320 material can be silicon oxide, or can be a dielectric or other material having a different dielectric constant (k) than silicon oxide. In addition, the gate insulator 320 can be a combination of materials or layers of different materials. For example, the gate insulator 320 can be aluminum oxide, hafnium oxide, hafnium oxide nitride, zirconium oxide, or a laminate and / or alloy of these materials. Other materials for the gate insulator 320 can be used without departing from the scope of the present disclosure.

[0052] By varying the material and thickness of gate insulator 320 (e.g., the distance between gate 304 and channel 310), the amount of charge on gate 304 that opens channel 310 can be varied. Also shown is symbol 322, which illustrates the terminals of MOSFET device 300. For an N-channel MOSFET (using electrons as charge carriers in channel 310), the substrate 308 terminal in symbol 322 is indicated with an arrow pointing away from the gate 304 terminal. For a P-type MOSFET (using holes as charge carriers in channel 310), the substrate 308 terminal in symbol 322 is indicated with an arrow pointing toward the gate 304 terminal.

[0053] In some MOSFET designs, a high-k material may be required for gate insulator 320, and in such designs, other conductive materials may be used. By way of example, and not limitation, a "high-k metal gate" design may employ a metal such as copper for gate 304. Although referred to as a "metal," polycrystalline materials, alloys, or other conductive materials are contemplated as suitable materials for gate 304, as described below.

[0054] Interconnect traces or layers are used to interconnect to MOSFET device 300, or to interconnect to other devices (e.g., semiconductors) in die 106. These interconnect traces may be in one or more layers (e.g., 210-214), or in other layers of die 106.

[0055] Figure 4 A vertical fin field effect transistor (FinFET) 400 is shown, which is similar to the Figure 3 The MOSFET device 300 operates in a similar manner. However, the fin 410 in the FinFET 400 is grown or otherwise coupled to Figure 3 The substrate 308 may be a semiconductor substrate or other similar supporting layer, for example, an oxide layer, a nitride layer, a metal oxide layer, or a silicon layer. The fin 410 includes a source 302 and a drain 306. The gate 304 is disposed on the fin 410 and the substrate 308 via a gate insulator 320. In the FinFET structure, the physical size of the FinFET 400 may be smaller than Figure 3 MOSFET device 300 structure is shown. This reduction in physical size allows for more devices per unit area on die 106.

[0056] FinFET 400 can be manufactured through a process including front-end of line (FEOL), middle of line (MOL), and back-end of line (BEOL). The MOL process includes gate and terminal contact formation. The MOL layer trench contacts the source and drain regions of FinFET 400 and is called a CA contact.

[0057] Fin-based devices, such as FinFET 400, represent a significant advancement in integrated circuit (IC) technology compared to planar-based devices. Fin-based devices are three-dimensional structures on the surface of a semiconductor substrate. A FinFET transistor is a type of fin-based metal oxide semiconductor field effect transistor (MOSFET). Nanowire FETs also represent a significant advancement in IC technology. Gate-all-around (GAA) nanowire-based devices are another type of three-dimensional structure on the surface of a semiconductor substrate. Other fin-based devices include Ω-gate devices and π-gate devices. Fin-based field effect transistors may be referred to as FinFET devices.

[0058] In some IC designs, as technology nodes shrink, one advancement is replacing polysilicon gate electrodes with metal gate electrodes to improve device performance by reducing feature sizes. While existing methods for manufacturing IC devices are generally adequate for their intended purpose, these methods are not entirely satisfactory in all respects. For example, fin-based devices can be implemented using replacement metal gate (RMG) technology.

[0059] Advanced logic complementary metal oxide semiconductor (CMOS) scaling of fin-based devices using RMG technology has achieved higher performance power area (PPA) than previous process nodes. Unfortunately, further improvement in fin-based transistor mobility at process nodes below seven nanometers (nm) is difficult because conventional strain enhancers are reaching their limits. Therefore, a new strain enhancer is needed to continue to improve the performance of fin-based transistors. Table I - Preferred strain types

[0060] For example, Table 1 lists the preferred strain types according to the X direction, Y direction and Z direction, such as Figure 4 As shown. In the X direction (e.g., the length direction from source 302 to drain 306), tensile (T) strain is preferred for NMOS electrons, while compressive (C) strain is preferred for PMOS holes. In the Y direction (e.g., the width direction), tensile (T) strain is preferred for both NMOS electrons and PMOS holes. In the Z direction (e.g., from the body to the gate 304), compressive (C) strain is preferred for NMOS electrons, while tensile (T) strain is preferred for PMOS holes. According to aspects of the present disclosure, for example, Figure 5A-5B FIG. 4 illustrates a FinFET with independently strained N-type and P-type regions formed during a replacement metal gate (RMG) gate cut process.

[0061] Figure 5A-5Bis a schematic diagram illustrating an integrated circuit including a fin field effect transistor (FinFET) 500 having independently strained N-type and P-type regions according to some aspects of the present disclosure. In this configuration, the FinFET 500 includes a substrate 502 having a shallow trench isolation (STI) region 504 on the substrate 502. In some aspects of the present disclosure, the FinFET 500 includes a first fin structure 510 (510-1, 510-2) on the substrate 502 and extending through the STI region 504, and a second fin structure 520 (520-1, 520-2) on the substrate 502 and extending through the STI region 504.

[0062] In this example, the first fin structure 510 (510-1, 510-2) corresponds to an N-type (e.g., N-type metal oxide semiconductor (NMOS)) region of the substrate 502. Similarly, the second fin structure 520 (520-1, 520-2) corresponds to a P-type (e.g., P-type metal oxide semiconductor (PMOS)) region of the substrate 502. In some aspects of the present disclosure, the NMOS channel of the substrate 502 may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium GaAs (InGaAs), gallium nitride (GaN), graphene, molybdenum disulfide (MoS2), and / or phosphorus. In these aspects of the present disclosure, the PMOS channel of the substrate 502 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), indium antimonide (InSb), graphene, molybdenum disulfide (MoS2), and / or phosphorus.

[0063] like Figure 5A As further shown, FinFET 500 includes a metal gate 530 over an STI region 504, a first fin structure 510 (510-1, 510-2), and a second fin structure 520 (520-1, 520-2). In some aspects of the present disclosure, metal gate 530 includes a first sub-metal gate cut line 540 filled with a first stressor material and a second sub-metal gate cut line 550 filled with a second stressor material different from the first stressor material. In this example, the first sub-metal gate cut line 540 and the second sub-metal gate cut line 550 pass through metal gate 530, through STI region 504, and extend into substrate 502.

[0064] like Figure 5AAs shown, the first sub-metal gate cut line 540 is coupled between the first N-type metal oxide semiconductor (NMOS) region (e.g., 510-1) and the second NMOS region (e.g., 510-2). Similarly, the second sub-metal gate cut line 550 is coupled between the first P-type metal oxide semiconductor (PMOS) region (e.g., 520-1) and the second PMOS region (e.g., 520-2). In some aspects of the present disclosure, the metal gate 530 includes tantalum (Ta), tantalum nitride (TaN), tantalum titanium (TaTi), titanium (Ti), titanium aluminide (TiAl), titanium aluminum nitride carbon (TiAl:C), tungsten nitride (W:N), platinum (Pt), and / or gold (Au).

[0065] In some aspects of the present disclosure, the first and second stressor materials are selected based on the type of region (e.g., NMOS / PMOS) and orientation (e.g., X / Y / Z) using Table 1. In some aspects of the present disclosure, the stressor materials used to fill the gate-cut trenches with tensile and / or compressive strain include, but are not limited to, silicon dioxide (SiO2), silicon dioxide-fluorine (SiO2:F), silicon dioxide-nitrogen (SiO2:N), silicon dioxide-germanium (SiO2:Ge), silicon oxynitride (SiON), silicon oxynitride-fluorine (SiON:F), silicon nitride-germanium (SiON:Ce), silicon nitride (SiN), silicon nitride-germanium (SiN:Ge), hafnium oxide (HfO2), hafnium zirconium oxide (HfZrO2), zirconium (ZrO2), hafnium lanthanum oxide (HfLaO), lanthanum oxide (LaO2), germanium oxide (GeOx), and / or silicon germanium oxide (SiGeOx). An inter-layer dielectric (ILD) layer 506 is provided on the metal gate 530 to support a signal track 508 coupled to the metal gate 530 through gate vias 532 and power rails (eg, VDD and VSS).

[0066] Figure 5B A FinFET 560 is shown having Figure 5A 500 and are described using similar symbols. FinFET 560 includes a substrate 502 having an STI region 504 on the substrate 502 and a first fin structure 510 (510-1, 510-2) on an N-type region of the substrate 502 and extending through the STI region 504. FinFET 560 also includes a second fin structure 520 (520-1, 520-2) on a P-type region of the substrate 502 and extending through the STI region 504.

[0067] FinFET 560 includes a metal gate 530 over an STI region 504, a first fin structure 510 (510-1, 510-2), and a second fin structure 520 (520-1, 520-2). In some aspects of the present disclosure, metal gate 530 includes a first sub-metal gate cut line 570 filled with a first stressor material and a second sub-metal gate cut line 580 filled with a second stressor material different from the first stressor material. In this example, the first sub-metal gate cut line 570 and the second sub-metal gate cut line 580 extend through metal gate 530 into STI region 504. In these aspects of the present disclosure, the first sub-metal gate cut line 570 and the second sub-metal gate cut line 580 do not extend through STI region 504 into substrate 502. FinFET 560 also includes an ILD layer 506 on the metal gate 530 for supporting a signal track 508 coupled to the metal gate 530 through a gate via 532 and power supply VDD and VSS rails.

[0068] Figure 6 A layout diagram of a FinFET 600 with independently strained N-type and P-type regions according to aspects of the present disclosure is shown. Figure 6 A FinFET 600 is shown having Figure 5A FinFET 500 and Figure 5B 560 in FIG. 1 and are described using similar symbols. In particular, Figure 5A The FinFET 500 shown and Figure 5B The illustrated FinFET 560 may be a cross-sectional view along cut line AA′ of the FinFET 600 .

[0069] like Figure 6As shown, FinFET 600 includes a substrate 502 having a first fin structure 510-1 on an NMOS region. FinFET 600 also includes a second fin structure 520-1 on the PMOS region of FinFET 600. FinFET 600 includes a plurality of metal gates 530 (530-1, 530-2, 530-3) on the first fin structure 510-1 and on the second fin structure 520-1. In some aspects of the present disclosure, the plurality of metal gates 530 (530-1, 530-2, 530-3) include first sub-metal gate cut lines 540 / 570 filled with a first stressor material and second sub-metal gate cut lines 550 / 580 filled with a second stressor material different from the first stressor material. The first sub-metal gate cut lines 540 / 570 and the second sub-metal gate cut lines 550 / 580 extend through the plurality of metal gates 530 (530-1, 530-2, 530-3). Also shown are gate vias 532, signal rail 508, and power supply VDD and VSS rails.

[0070] Figure 7 is a flow chart illustrating a method of forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions according to some aspects of the present disclosure. The method 700 begins at block 702 where fin / diffusion formation is performed. For example, Figure 5A As shown, the fin / diffusion formation process generates a first fin structure 510 ( 510 - 1 , 510 - 2 ) corresponding to the NMOS region of the substrate 502 . Similarly, the fin / diffusion formation process generates a second fin structure 520 ( 520 - 1 , 520 - 2 ) corresponding to the PMOS region of the substrate 502 .

[0071] At block 704, a dummy polysilicon formation process is performed to form a dummy gate. At block 706, a source / drain (S / D) epitaxial process is performed to form source and drain regions. For example, Figure 4 As shown, an S / D epitaxial process is performed to form the source 302 and drain 306 of the FinFET 400. At block 708, a replacement metal gate (RMG) process is performed to replace the dummy polysilicon gate with a metal gate. Figure 5A As shown, the FinFET 500 further includes a metal gate 530 on the STI region 504 , the first fin structure 510 ( 510 - 1 , 510 - 2 ), and the second fin structure 520 ( 520 - 1 , 520 - 2 ).

[0072] At block 710, a gate cutting process is performed after the replacement metal gate (RMG) process of block 708. At block 712, contacts are formed. For example, Figure 5AAs shown, the metal gate 530 includes a first sub-metal gate cut line 540 filled with a first stressor material and a second sub-metal gate cut line 550 filled with a second stressor material different from the first stressor material. In this example, the first sub-metal gate cut line 540 and the second sub-metal gate cut line 550 extend through the metal gate 530, through the STI region 504, and into the substrate 502. In some aspects of the present disclosure, strain is incorporated into the post-RMG gate cut (GC) dielectric material deposition. The strain can vary based on whether the region is an NMOS region or a PMOS region, for example, as Figures 8A-8I In some aspects of the present disclosure, strain is incorporated into post-RMG GC fill dielectric materials along with ion implantation, e.g., Figures 9A-9G shown.

[0073] Figures 8A-8I is a diagram illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions according to some aspects of the present disclosure.

[0074] Figure 8A FIG. 8 shows a first step 800 in forming a FinFET with independently strained N-type and P-type regions according to some aspects of the present disclosure. In this process, Figure 5A The initial stage of the FinFET 500 is shown after a replacement metal gate (RMG) process to form a metal gate 530 on the first fin structure 510 ( 510 - 1 , 510 - 2 ) and the second fin structure 520 ( 520 - 1 , 520 - 2 ).

[0075] Figure 8B The next step 810 in the process of forming a FinFET with independently strained N-type and P-type regions according to some aspects of the present disclosure is shown. At step 810, a hard mask (HM) 812 is deposited on the surface of the metal gate 530. Once the hard mask 812 is formed, a photoresist (PR) 814 is deposited on the hard mask 812. After the formation of the photoresist 814, the photoresist 814 and the hard mask 812 are patterned to form an opening 816 in preparation for performing the first gate cut in the PMOS region of the substrate 502.

[0076] Figure 8CThe next step 820 in forming a FinFET with independently strained N-type and P-type regions according to some aspects of the present disclosure is shown. At step 820, a gate cut trench etch is performed after the opening 816 in the hard mask 812 and the photoresist 814. The second sub-metal gate cut line 550 is formed by etching through the metal gate 530, the STI region 504, and in the PMOS region of the substrate 502. In addition, the photoresist 814 is stripped to expose the surface of the hard mask 812.

[0077] Figure 8D The next step 830 in forming a FinFET with independently strained N-type and P-type regions according to some aspects of the present disclosure is shown. At step 830, the second sub-metal gate cut line 550 is filled with a second stressor material 832, which is also deposited on the exposed surface of the hard mask 812. For example, Figure 5A and Figure 8D As shown, the second sub-metal gate cutting line 550 is filled with a second stressor material 832 (such as 830) through the metal gate 530, the STI region 504 in the PMOS region of the substrate 502 and on the surface of the hard mask 812. Figure 8D as shown), such as post-RMG GC filling with P-type dielectric material.

[0078] Figure 8E The next step 840 in forming a FinFET with independently strained N-type and P-type regions according to some aspects of the present disclosure is shown. At step 840, the second stressor material 832 and the hard mask 812 are stripped from the metal gate 530 using, for example, a chemical mechanical polishing (CMP) process. The CMP process of step 840 for stripping the second stressor material 832 and the hard mask 812 from the metal gate 530 completes the formation of the second sub-metal gate cut line 550 filled with the second stressor material 832.

[0079] Figure 8F The next step 850 in the process of forming a FinFET with independently strained N-type and P-type regions according to some aspects of the present disclosure is shown. At step 850, a hard mask 812 is deposited on the surface of the metal gate 530. Once the hard mask 812 is formed, a photoresist 814 is deposited on the hard mask 812. After forming the photoresist 814, the photoresist 814 and the hard mask 812 are patterned to form an opening 852 in preparation for performing a second gate cut in the NMOS region of the substrate 502.

[0080] Figure 8GThe next step 860 in forming a FinFET with independently strained N-type and P-type regions according to some aspects of the present disclosure is shown. At step 860, a gate cut trench etch is performed after the opening 852 in the hard mask 812 and the photoresist 814. The first sub-metal gate cut line 540 is formed in the NMOS region of the substrate 502 by etching through the metal gate 530 and the STI region 504. In addition, the photoresist 814 is stripped to expose the surface of the hard mask 812.

[0081] Figure 8H The next step 870 in forming a FinFET with independently strained N-type and P-type regions according to some aspects of the present disclosure is shown. At step 870, the first sub-metal gate cut line 540 is filled with a first stressor material 872, which is also deposited on the exposed surface of the hard mask 812. For example, Figure 5A and Figure 8H As shown, the first sub-metal gate cutting line 540 is filled with a first stressor material 872 (eg, Figure 8H ), such as a post-RMGGC fill N-type dielectric material. In this example, a first stressor material 872 is deposited in the first sub-metal gate cut line 540, through the metal gate 530, the STI region 504, in the PMOS region of the substrate 502, and on the surface of the hard mask 812.

[0082] Figure 8I The next step 880 in the process of forming a FinFET with independently strained N-type and P-type regions according to some aspects of the present disclosure is shown. At step 880, the first stressor material 872 and the hard mask 812 are stripped from the metal gate 530 using, for example, a second chemical mechanical polishing (CMP) process. The second CMP process of step 840 for stripping the first stressor material 872 and the hard mask 812 from the metal gate 530 completes the formation of the first sub-metal gate cut line 540 filled with the first stressor material 872. In this example, the first stressor material 872 exhibits a compressive strain orientation, while the second stressor material 832 exhibits a tensile strain orientation.

[0083] exist Figures 8A-8I5 , the first sub-metal gate cut line 540 is filled with a first stressor material 872, and the second sub-metal gate cut line 550 is filled with a second stressor material 832. In some aspects of the present disclosure, the second stressor material 832 comprises a post-RMG GC fill P-type dielectric material having a compressive stress to provide a tensile strain in the PMOS region of the FinFET 500 of FIG. 5 . In these aspects of the present disclosure, the first stressor material 872 comprises a post-RMG GC fill N-type dielectric material having a tensile stress to provide a compressive strain in the NMOS region of the FinFET 500. Figures 8A-8I The illustrated process includes two CMP processes for completing the formation of the first sub-metal gate cut line 540 and the second sub-metal gate cut line 550. Unfortunately, the application of these two CMP processes leads to potential concerns about the morphology of the metal gate 530 due to the different post-RMG GC fill dielectric materials used for the first stressor material 872 and the second stressor material 832.

[0084] Figures 9A-9G is a diagram illustrating a process for forming a fin field effect transistor (FinFET) having independently strained N-type and P-type regions using ion implantation, according to some aspects of the present disclosure. Figures 9A-9G The process is similar to Figures 8A-8I The processes shown are similar and are described using similar symbols.

[0085] Figure 9A 9 shows a first step in a process for forming a FinFET with independently strained N-type and P-type regions using ion implantation according to some aspects of the present disclosure. In this process, Figure 5A The initial stage of the FinFET 500 is shown after a replacement metal gate (RMG) process to form a metal gate 530 on the first fin structure 510 ( 510 - 1 , 510 - 2 ) and the second fin structure 520 ( 520 - 1 , 520 - 2 ).

[0086] Figure 9BThe next step 910 in a process for forming a FinFET with independently strained N-type and P-type regions using ion implantation according to some aspects of the present disclosure is shown. At step 910, a hard mask (HM) 812 is deposited on a surface of the metal gate 530. Once the hard mask 812 is formed, a photoresist (PR) 814 is deposited on the hard mask 812. After the formation of the photoresist 814, the photoresist 814 and the hard mask 812 are patterned to form a first opening 912 and a second opening 914. The first opening 912 and the second opening 914 are provided to prepare for etching of the first sub-metal gate cut line 540 in the NMOS region and the second sub-metal gate cut line 550 in the PMOS region of the substrate 502, as shown. Figure 9C shown.

[0087] Figure 9C The next step 920 in forming a FinFET with independently strained N-type and P-type regions according to some aspects of the present disclosure is shown. At step 920, a gate cut trench etch is performed after the first opening 912 and the second opening 914 in the hard mask 812 and the photoresist 814. The first sub-metal gate cut line 540 is formed in the NMOS region of the substrate 502 by etching through the metal gate 530 and the STI region 504 through the first opening 912. The second sub-metal gate cut line 550 is formed in the PMOS region of the substrate 502 by etching through the metal gate 530 and the STI region 504. In addition, the photoresist 814 is stripped to expose the surface of the hard mask 812.

[0088] Figure 9D The next step 930 in the process of forming a FinFET with independently strained N-type and P-type regions by ion implantation according to some aspects of the present disclosure is shown. At step 930, the first sub-metal gate cut line 540 and the second sub-metal gate cut line 550 are filled with the second stressor material 832 through the first opening 912 and the second opening 914. The second stressor material 832 is also deposited on the exposed surface of the hard mask 812. For example, Figure 5A and Figure 9D As shown, the first sub-metal gate cutting line 540 and the second sub-metal gate cutting line 550 are filled with the second stressor material 832 (eg, Figure 9D As shown) (eg, post-RMG GC filling with P-type dielectric material), the second stressor material 832 is also deposited on the surface of the hard mask 812 .

[0089] Figure 9EThe next step 940 in the process of forming a FinFET with independently strained N-type and P-type regions by ion implantation according to some aspects of the present disclosure is shown. At step 940, the second stressor material 832 and the hard mask 812 are stripped from the metal gate 530 using, for example, a chemical mechanical polishing (CMP) process. The CMP process of step 940 for stripping the second stressor material 832 and the hard mask 812 from the metal gate 530 completes the formation of the second sub-metal gate cut line 550 filled with the second stressor material 832; however, due to the presence of the second stressor material 832, the formation of the first sub-metal gate cut line 540 is incomplete.

[0090] Figure 9F The next step 950 in the process of forming a FinFET with independently strained N-type and P-type regions by ion implantation according to some aspects of the present disclosure is shown. At step 950, a photoresist 952 is deposited on the surface of the metal gate 530. After the photoresist 952 is formed, the photoresist 952 is patterned to form an opening 954. Once the opening 954 is formed, the first stressor material 872 in the first sub-metal gate cut line 540 is implanted with a substance having a larger lattice constant (e.g., germanium (Ge), argon (Ar)). Ion implantation 956 is performed to convert the second stressor material 832 into the first stressor material 872 in the NMOS region of the substrate 502. In some aspects of the present disclosure, the ion implanted substances include, but are not limited to, fluorine (F), nitrogen (N), silicon (Si), germanium (Ge), and argon (Ar).

[0091] Figure 9G The next step 960 in the process of forming a FinFET with independently strained N-type and P-type regions by ion implantation according to some aspects of the present disclosure is shown. At step 960, the photoresist 952 is stripped from the metal gate 530, and a low-temperature anneal is performed. The low-temperature annealing after stripping the photoresist 952 from the metal gate 530 completes the formation of the first sub-metal gate cut line 540 filled with the first stressor material 872. Figures 9A-9G The process shown utilizes a single chemical mechanical polishing (CMP) process by Figure 9E Using the same second stressor material 832 during the CMP process shown in step 940 avoids potential concerns about the topography of the metal gate 530 .

[0092] exist Figures 9A-9G In the example provided in , both the first sub-metal gate cutting line 540 and the second sub-metal gate cutting line 550 are filled with the second stressor material 832 . Figures 9A-9GThe illustrated process includes one CMP process for completing the planarization of the metal gate 530. Fortunately, by using the same post-RMG GC fill dielectric material (eg, second stressor material 832), the application of a single CMP process avoids potential issues with the topography of the metal gate 530.

[0093] Figure 10 1 is a process flow diagram illustrating a method 1000 for fabricating a field effect transistor (FET) having independently strained N-type and P-type regions according to aspects of the present disclosure. The method 1000 may begin at block 1002 where a dummy gate is replaced with a metal gate formed on a shallow trench isolation (STI) region on a substrate and on a first fin structure and a second fin structure on the substrate. For example, Figure 7 As shown, at block 708, a replacement metal gate (RMG) process is performed to replace the dummy polysilicon gate with a metal gate. Figure 5A As shown, the FinFET 500 includes a metal gate 530 on the STI region 504 , on the first fin structure 510 ( 510 - 1 , 510 - 2 ), and on the second fin structure 520 ( 520 - 1 , 520 - 2 ).

[0094] At block 1004, wire cutting is applied to separate the metal gate to form a first sub-metal gate cutting line and a second sub-metal gate cutting line. Figure 7 As shown, at block 710, a gate cutting process is performed after the RMG process of block 708. Figure 5A As shown, metal gate 530 includes a first sub-metal gate cutting line 540 and a second sub-metal gate cutting line 550. In this example, first sub-metal gate cutting line 540 and second sub-metal gate cutting line 550 extend through metal gate 530, through STI region 504, and into substrate 502. Metal gate 530 may be a high-K metal gate (HKMG).

[0095] At block 1006, the second sub-metal gate cut line is filled with a second stressor material. Figure 8D At step 830, the second sub-metal gate cut line 550 is filled with a second stressor material 832, which is also deposited on the exposed surface of the hard mask 812. Figure 5A and Figure 8D As shown, the second sub-metal gate cutting line 550 is filled with a second stressor material 832 (such as 830) through the metal gate 530, the STI region 504 in the PMOS region of the substrate 502 and on the surface of the hard mask 812. Figure 8D as shown), such as post-RMG GC filling with P-type dielectric material.

[0096] At block 1008, the first sub-metal gate cut line is filled with a first stressor material. Figure 8H As shown, the first sub-metal gate cut line 540 is filled with a first stressor material 872, which is also deposited on the exposed surface of the hard mask 812. Figure 5A and Figure 8D As shown, the first sub-metal gate cut line 540 is filled with a first stressor material 872, such as a post-RMG GC fill N-type dielectric material. In this example, the first stressor material 872 is deposited in the first sub-metal gate cut line 540 through the metal gate 530, the STI region 504 in the PMOS region of the substrate 502, and on the surface of the hard mask 812.

[0097] Figure 11 is a process flow diagram illustrating a method 1100 for fabricating a field effect transistor (FET) having independently strained N-type and P-type regions according to aspects of the present disclosure. Blocks 1102-1106 of the method 1100 correspond to Figure 10 The blocks 1002-1006 of the method 1000 are omitted and are not described in detail here. At block 1108, the first sub-metal gate cut line is filled with a second stressor material. For example, Figure 9D As shown, the first sub-metal gate cutting line 540 and the second sub-metal gate cutting line 550 are filled with the second stressor material 832 through the first opening 912 and the second opening 914. Figure 5A and Figure 9D As shown, the first sub-metal gate cutting line 540 and the second sub-metal gate cutting line 550 are filled with the second stressor material 832 (eg, Figure 9D As shown) (eg, post-RMG GC filling with P-type dielectric material), the second stressor material 832 is also deposited on the surface of the hard mask 812 .

[0098] At block 1110, ions are implanted into the second stressor material in the first sub-metal gate cut line to convert the second stressor material into a first stressor. Figure 9F As shown, the second stressor material 832 in the first sub-metal gate cut line 540 is implanted with a substance having a larger lattice constant (e.g., germanium (Ge), argon (Ar)). In this example, ion implantation 956 is performed to convert the second stressor material 832 into the first stressor material 872 in the NMOS region of the substrate 502. Figure 9G As shown, a low temperature annealing is performed. The low temperature annealing after stripping the photoresist 952 from the metal gate 530 completes the formation of the first sub-metal gate cut line 540 filled with the first stressor material 872 .

[0099] Figure 121 is a block diagram illustrating an exemplary wireless communication system 1200 in which one aspect of the present disclosure may be advantageously employed. Figure 12 Three remote units 1220, 1230, and 1250, and two base stations 1240 are shown. It will be appreciated that a wireless communication system may have more remote units and base stations. Remote units 1220, 1230, and 1250 include IC devices 1225A, 1225C, and 1225B that include the disclosed FinFETs. It will be appreciated that other devices may also include the disclosed FinFETs, such as base stations, switching equipment, and network equipment. Figure 12 Forward link signals 1280 from base station 1240 to remote units 1220, 1230, and 1250, and reverse link signals 1290 from remote units 1220, 1230, and 1250 to base station 1240 are shown.

[0100] exist Figure 12 , remote unit 1220 is shown as a mobile phone, remote unit 1230 is shown as a portable computer, and remote unit 1250 is shown as a fixed location remote unit in a wireless local loop system. For example, the remote unit may be a mobile phone, a handheld personal communication system (PCS) unit, a portable data unit such as a personal data assistant, a GPS-enabled device, a navigation device, a set-top box, a music player, a video player, an entertainment unit, a fixed location data unit such as a meter reading device, or other device that stores or retrieves data or computer instructions, or a combination thereof. Although Figure 12 Remote units according to aspects of the present disclosure are shown, but the present disclosure is not limited to these exemplary shown units.Aspects of the present disclosure may be suitably applied in many devices that include the disclosed FinFETs.

[0101] Figure 131 is a block diagram illustrating a design workstation for circuit, layout, and logic design of IC structures, such as the FinFETs disclosed above. Design workstation 1300 includes a hard disk 1301 that includes operating system software, support files, and design software, such as Cadence or OrCAD. Design workstation 1300 also includes a display 1302 for facilitating the design of a circuit 1310 or a fin structure 1312 including a FinFET. A storage medium 1304 is provided for tangibly storing the design of the circuit 1310 or fin structure 1312. The design of the circuit 1310 or fin structure 1312 can be saved on storage medium 1304 in a file format such as GDSII or GERBER. Storage medium 1304 can be a CD-ROM, DVD, hard disk, flash memory, or other suitable device. In addition, design workstation 1300 includes a drive 1303 for receiving input from storage medium 1304 or writing output to storage medium 1304.

[0102] The data recorded on storage medium 1304 may specify a logic circuit configuration, pattern data for a photolithography mask, or mask pattern data for a serial write tool (such as electron beam lithography). The data may also include logic verification data, such as timing diagrams or network circuits associated with logic simulations. Providing data on storage medium 1304 facilitates the design of circuit 1310 or fin structure 1312 by reducing the number of processes used to design a semiconductor wafer.

[0103] For firmware and / or software implementations, the methods can be implemented with modules (e.g., procedures, functions, etc.) that perform the functions described herein. A machine-readable medium tangibly embodying instructions can be used to implement the methods described herein. For example, software code can be stored in a memory and executed by a processor unit. The memory can be implemented within the processor unit or external to the processor unit. As used herein, the term "memory" refers to long-term, short-term, volatile, non-volatile, or other memory, and is not limited to a specific type of memory or a specific number of memories, or a type of medium that stores the memory.

[0104] If implemented in firmware and / or software, these functions may be stored as one or more instructions or codes on a computer-readable medium. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media include physical computer storage media. A storage medium may be a usable medium that can be accessed by a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other media that can be used to store the desired program code in the form of instructions or data structures and that can be accessed by a computer. Disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Optical discs, where magnetic disks typically reproduce data magnetically, while optical discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0105] In addition to being stored on a computer-readable medium, instructions and / or data may also be provided as signals on a transmission medium included in a communication device. For example, the communication device may include a transceiver that carries signals indicating the instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.

[0106] Implementation examples are described in the following numbered clauses: 1. A fin field-effect transistor (FinFET), comprising: substrate; a shallow trench isolation (STI) region located on the substrate; a first fin structure located on the substrate and extending through the STI region; a second fin structure located on the substrate and extending through the STI region; and a metal gate located in the STI region, on the first fin structure, and on the second fin structure, the metal gate including a first sub-metal gate cutting line filled with a first stressor material and a second sub-metal gate cutting line filled with a second stressor material different from the first stressor material. 2. The FinFET of clause 1, wherein the first stressor material comprises a compressive strain and the second stressor material comprises a tensile strain. 3. The FinFET of clause 2, wherein the first fin structure comprises a P-type metal oxide semiconductor (PMOS) region and the second fin structure comprises an N-type metal oxide semiconductor (NMOS) region. 4. The FinFET according to any one of clauses 1 to 3, wherein the first sub-metal gate cutting line and the second sub-metal gate cutting line extend through the metal gate to the STI region. 5. The FinFET of any one of clauses 1 to 3, wherein the first sub-metal gate cutting line and the second sub-metal gate cutting line extend through the metal gate, through the STI region, and into the substrate. 6. The FinFET of any one of clauses 1 to 5, wherein the metal gate comprises a high-K metal gate. 7. The FinFET of any one of clauses 1 to 6, wherein the first fin structure comprises: a first P-type metal oxide semiconductor (PMOS) region; and a second PMOS region, wherein the first sub-metal gate cutting line is coupled between the first PMOS region and the second PMOS region. 8. The FinFET of any one of clauses 1 to 7, wherein the second fin structure comprises: a first N-type metal oxide semiconductor (NMOS) region; and a second NMOS region, wherein the second sub-metal gate cutting line is coupled between the first NMOS region and the second NMOS region. 9. A FinFET as described in any of clauses 1 to 8, wherein the first stressor material and the second stressor material include silicon dioxide (SiO2), silicon dioxide-fluorine (SiO2:F), silicon dioxide-nitrogen (SiO2:N), silicon dioxide-germanium (SiO2:Ge), silicon oxynitride (SiON), silicon oxynitride-fluorine (SiON:F), silicon nitride-germanium (SiON:Ge), silicon nitride (SiN), silicon nitride-germanium (SiN:Ge), hafnium oxide (HfO2), hafnium zirconium oxide (HfZrO2), zirconium oxide (ZrO2), hafnium lanthanum oxide (HfLaO), lanthanum oxide (LaO2), germanium oxide (GeOx), and / or silicon germanium oxide (SiGeOx). 10. The FinFET of any of clauses 1 to 8, wherein the second stressor material comprises an ion-implanted species comprising fluorine (F), nitrogen (N), silicon (Si), germanium (Ge), and argon (Ar). 11. A method comprising: replacing the dummy gate to form a metal gate on a shallow trench isolation (STI) region on a substrate and on a first fin structure and a second fin structure on the substrate; Applying wire cutting to separate the metal gate to form a first sub-metal gate cutting line and a second sub-metal gate cutting line; filling the first sub-metal gate cut line with a first stressor material; and The second sub-metal gate cut line is filled with a second stressor material different from the first stressor material. 12. The method of clause 11, wherein applying the wire cutting comprises: depositing a hard mask on a surface of the metal gate; depositing a photoresist (PR) on the hard mask; patterning the photoresist and the hard mask to form an opening; etching through the opening in the photoresist and the hard mask to form the first sub-metal gate cutting line passing through the metal gate and the STI region in a P-type metal oxide semiconductor (PMOS) region of the substrate; and The photoresist is stripped to expose a surface of the hard mask. 13. The method of clause 12, wherein filling the first sub-metal gate cut line with the first stressor material comprises: depositing the first stressor material in the first sub-metal gate cut line; depositing the first stressor material on the exposed surface of the hard mask; and The first stressor material and the hard mask on the surface of the metal gate are polished. 14. The method of any one of clauses 11 to 13, wherein applying the wire cutting comprises: depositing a hard mask on a surface of the metal gate and on a portion of the first stressor material; depositing a photoresist (PR) on the hard mask; patterning the photoresist and the hard mask to form an opening; etching through the opening in the photoresist and the hard mask to form a second sub-metal gate cutting line passing through the metal gate and the STI region in an N-type metal oxide semiconductor (NMOS) region of the substrate; and The photoresist is stripped to expose a surface of the hard mask. 15. The method of clause 14, wherein filling the second sub-metal gate cut line with the second stressor material comprises: depositing the second stressor material in the second sub-metal gate cut line; depositing the second stressor material on the exposed surface of the hard mask; and The second stressor material and the hard mask on the surface of the metal gate are polished. 16. A method comprising: replacing the dummy gate to form a metal gate on a shallow trench isolation (STI) region on a substrate and on a first fin structure and a second fin structure on the substrate; Applying wire cutting to separate the metal gate to form a first sub-metal gate cutting line and a second sub-metal gate cutting line; filling the first sub-metal gate cutting line and the second sub-metal gate cutting line with a first stressor material; and Ions are implanted into the first stressor material in the second sub-metal gate cut line to convert the first stressor material into a second stressor material different from the first stressor material. 17. The method of clause 16, wherein applying the wire cutting comprises: depositing a hard mask on a surface of the metal gate; depositing a photoresist (PR) on the hard mask; patterning the photoresist and the hard mask to form a first opening and a second opening; etching through the photoresist and the first opening in the hard mask to form the first sub-metal gate cutting line passing through the metal gate and the STI region in a P-type metal oxide semiconductor (PMOS) region of the substrate; etching through the photoresist and the second opening in the hard mask to form the second sub-metal gate cutting line passing through the metal gate and the STI region in an N-type metal oxide semiconductor (NMOS) region of the substrate; and The photoresist is stripped to expose a surface of the hard mask. 18. The method of clause 17, wherein filling the first sub-metal gate cut line and the second sub-metal gate cut line with the first stressor material comprises: depositing the first stressor material in the first sub-metal gate cutting line and the second sub-metal gate cutting line; depositing the first stressor material on the exposed surface of the hard mask; and The first stressor material and the hard mask on the surface of the metal gate are polished. 19. The method of any one of clauses 16 to 18, wherein implanting ions comprises: depositing a photoresist (PR) on a surface of the metal gate and on a portion of the first stressor material; patterning the photoresist to form openings; and An ion implantation material is implanted through the opening in the photoresist to convert the first stressor material in the second sub-metal gate cut line into the second stressor material. 20. The method of clause 19, wherein the ion implantation species comprises fluorine (F), nitrogen (N), silicon (Si), germanium (Ge), and argon (Ar).

[0107] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and modifications can be made herein without departing from the technology of the present disclosure as defined by the appended claims. For example, relational terms such as "upper" and "lower" are used for substrates or electronic devices. Of course, if the substrate or electronic device is inverted, upper becomes lower, and vice versa. In addition, if facing sideways, upper and lower can refer to the sides of the substrate or electronic device. In addition, the scope of this application is not intended to be limited to the specific configurations of processes, machines, manufactures, and material compositions, means, methods and steps described in the specification. As will be readily understood by those skilled in the art from the disclosure, according to the present disclosure, processes, machines, manufactures, material compositions, means, methods or steps that currently exist or are to be developed later can be utilized to perform substantially the same functions as the corresponding configurations described herein or achieve substantially the same results as them. Accordingly, the appended claims are intended to include such processes, machines, manufactures, material compositions, means, methods or steps within their scope.

[0108] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the disclosure herein may be implemented as electronic hardware, computer software, or a combination of the two. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described generally in terms of their functions. Whether such functions are implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system. Those skilled in the art may implement the described functions in different ways for each specific application, but such implementation decisions should not be interpreted as causing a deviation from the scope of this disclosure.

[0109] The various illustrative logical blocks, modules, and circuits described in conjunction with the disclosure herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration).

[0110] The steps of the methods or algorithms described in conjunction with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may be located in RAM, flash memory, ROM, EPROM, EEPROM, cache, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative embodiment, the storage medium may be integral to the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In an alternative embodiment, the processor and storage medium may reside in a user terminal as discrete components.

[0111] In one or more exemplary designs, the functions described can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Computer-readable media include computer storage media and communication media, which include any media that facilitates the transfer of computer programs from one place to another. Storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. By way of example and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other media that can be used to carry or store a specified program code device in the form of an instruction or data structure and that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. In addition, any connection is properly referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies (such as infrared, radio, and microwave), the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies (such as infrared, radio, and microwave) are included in the definition of medium. Disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0112] The preceding description of the present disclosure is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A fin field-effect transistor (FinFET), comprising: substrate; a shallow trench isolation (STI) region located on the substrate; a first fin structure located on the substrate and extending through the STI region; a second fin structure located on the substrate and extending through the STI region; as well as a metal gate located on the STI region, on the first fin structure, and on the second fin structure, the metal gate including a first sub-metal gate cutting line filled with a first stressor material and a second sub-metal gate cutting line filled with a second stressor material different from the first stressor material.

2. The FinFET according to claim 1, wherein: The first stressor material includes a compressive strain, and the second stressor material includes a tensile strain.

3. The FinFET according to claim 2, wherein: The first fin structure includes a P-type metal oxide semiconductor (PMOS) region, and the second fin structure includes an N-type metal oxide semiconductor (NMOS) region.

4. The FinFET according to claim 1 , wherein: The first sub-metal gate cutting line and the second sub-metal gate cutting line extend through the metal gate to the STI region.

5. The FinFET according to claim 1 , wherein: The first sub-metal gate cutting line and the second sub-metal gate cutting line pass through the metal gate, pass through the STI region, and extend into the substrate.

6. The FinFET according to claim 1 , wherein: The metal gate includes a high-K metal gate.

7. The FinFET according to claim 1 , wherein: The first fin structure includes: a first P-type metal oxide semiconductor (PMOS) region; and a second PMOS region, wherein the first sub-metal gate cutting line is coupled between the first PMOS region and the second PMOS region.

8. The FinFET according to claim 1 , wherein: The second fin structure includes: a first N-type metal oxide semiconductor (NMOS) region; and a second NMOS region, wherein the second sub-metal gate cutting line is coupled between the first NMOS region and the second NMOS region.

9. The FinFET according to claim 1 , wherein: The first stressor material and the second stressor material include silicon dioxide (SiO2), silicon dioxide-fluorine (SiO2:F), silicon dioxide-nitrogen (SiO2:N), silicon dioxide-germanium (SiO2:Ge), silicon oxynitride (SiON), silicon oxynitride-fluorine (SiON:F), silicon nitride-germanium (SiON:Ge), silicon nitride (SiN), silicon nitride-germanium (SiN:Ge), hafnium oxide (HfO2), hafnium zirconium oxide (HfZrO2), zirconium oxide (ZrO2), hafnium lanthanum oxide (HfLaO), lanthanum oxide (LaO2), germanium oxide (GeOx), and / or silicon germanium oxide (SiGeOx).

10. The FinFET according to claim 1, wherein: The second stressor material includes ion implanted substances including fluorine (F), nitrogen (N), silicon (Si), germanium (Ge), and argon (Ar).

11. A method comprising: replacing the dummy gate to form a metal gate on a shallow trench isolation (STI) region on a substrate and on a first fin structure and a second fin structure on the substrate; Applying wire cutting to separate the metal gate to form a first sub-metal gate cutting line and a second sub-metal gate cutting line; filling the first sub-metal gate cut line with a first stressor material; as well as The second sub-metal gate cut line is filled with a second stressor material different from the first stressor material.

12. The method according to claim 11, wherein Applications of the wire cutting include: depositing a hard mask on a surface of the metal gate; depositing a photoresist (PR) on the hard mask; patterning the photoresist and the hard mask to form an opening; etching through the opening in the photoresist and the hard mask to form the first sub-metal gate cutting line passing through the metal gate and the STI region in a P-type metal oxide semiconductor (PMOS) region of the substrate; and The photoresist is stripped to expose a surface of the hard mask.

13. The method according to claim 12, wherein: Filling the first sub-metal gate cutting line with the first stressor material includes: depositing the first stressor material in the first sub-metal gate cut line; depositing the first stressor material on the exposed surface of the hard mask; and The first stressor material and the hard mask on the surface of the metal gate are polished.

14. The method according to claim 11, wherein Applications of the wire cutting include: depositing a hard mask on a surface of the metal gate and on a portion of the first stressor material; depositing a photoresist (PR) on the hard mask; patterning the photoresist and the hard mask to form an opening; etching through the opening in the photoresist and the hard mask to form a second sub-metal gate cutting line passing through the metal gate and the STI region in an N-type metal oxide semiconductor (NMOS) region of the substrate; and The photoresist is stripped to expose a surface of the hard mask.

15. The method according to claim 14, wherein Filling the second sub-metal gate cutting line with the second stressor material includes: depositing the second stressor material in the second sub-metal gate cut line; depositing the second stressor material on the exposed surface of the hard mask; and The second stressor material and the hard mask on the surface of the metal gate are polished.

16. A method comprising: replacing the dummy gate to form a metal gate on a shallow trench isolation (STI) region on a substrate and on a first fin structure and a second fin structure on the substrate; Applying wire cutting to separate the metal gate to form a first sub-metal gate cutting line and a second sub-metal gate cutting line; filling the first sub-metal gate cutting line and the second sub-metal gate cutting line with a first stressor material; as well as Ions are implanted into the first stressor material in the second sub-metal gate cut line to convert the first stressor material into a second stressor material different from the first stressor material.

17. The method according to claim 16, wherein Applications of the wire cutting include: depositing a hard mask on a surface of the metal gate; depositing a photoresist (PR) on the hard mask; patterning the photoresist and the hard mask to form a first opening and a second opening; etching through the photoresist and the first opening in the hard mask to form the first sub-metal gate cutting line passing through the metal gate and the STI region in a P-type metal oxide semiconductor (PMOS) region of the substrate; etching through the photoresist and the second opening in the hard mask to form the second sub-metal gate cutting line passing through the metal gate and the STI region in an N-type metal oxide semiconductor (NMOS) region of the substrate; and The photoresist is stripped to expose a surface of the hard mask.

18. The method according to claim 17, wherein Filling the first sub-metal gate cutting line and the second sub-metal gate cutting line with the first stressor material includes: depositing the first stressor material in the first sub-metal gate cutting line and the second sub-metal gate cutting line; depositing the first stressor material on the exposed surface of the hard mask; and The first stressor material and the hard mask on the surface of the metal gate are polished.

19. The method according to claim 16, wherein Implanted ions include: depositing a photoresist (PR) on a surface of the metal gate and on a portion of the first stressor material; patterning the photoresist to form openings; and An ion implantation material is implanted through the opening in the photoresist to convert the first stressor material in the second sub-metal gate cut line into the second stressor material.

20. The method according to claim 19, wherein The ion implantation materials include fluorine (F), nitrogen (N), silicon (Si), germanium (Ge), and argon (Ar).

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