Array substrate, display panel and display device

Abstract

The invention discloses an array substrate, a display panel and a display device, and the array substrate comprises a substrate which comprises a first region and a peripheral region surrounding the first region; the first electrode structure is positioned on one side of the substrate; the first electrode structure comprises a first electrode and a first electrode wire which is located on the side, away from the substrate, of the first electrode and electrically connected with the first electrode in a contact mode. The plurality of spacers are positioned on one side, deviating from the substrate, of the first electrode structure; the plurality of spacers comprise a plurality of first spacers; the orthographic projection of the first spacer on the substrate body and the orthographic projection of the first electrode wire on the substrate body are not overlapped, and the first electrode wire is disconnected in the area where the first spacer is arranged.

Description

Array substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] With the development of information technology, electronic devices are widely used in people's daily lives. Liquid crystal displays (LCDs), as the most widely used flat-panel displays, play an important role in display panels. With the continuous advancement of technology, users' requirements for display quality are also getting higher and higher.

[0003] To improve the stability of the common electrode voltage in high-refresh-rate products, common electrode traces are added to the panel, thereby improving the stability of the common electrode voltage. However, placing the common electrode traces on the same layer as the scan lines reduces the pixel aperture ratio, thereby affecting the transmittance of the display product and resulting in higher overall power consumption. Furthermore, because the common electrode traces are metal traces with reflective properties, they affect the monitoring and measurement of spacer production, affecting the spacer production yield.

[0004] Summary of the Invention

[0005] An embodiment of the present disclosure provides an array substrate, wherein the array substrate includes:

[0006] A substrate, comprising a first region and a peripheral region surrounding the first region;

[0007] A first electrode structure is located on one side of the substrate; the first electrode structure includes: a first electrode, and a first electrode line located on a side of the first electrode away from the substrate and electrically connected to the first electrode;

[0008] A plurality of spacers are located on a side of the first electrode structure away from the base substrate; the plurality of spacers include a plurality of first spacers; the orthographic projections of the first spacers on the base substrate do not overlap with the orthographic projections of the first electrode lines on the base substrate, and the first electrode lines are disconnected in the area where the first spacers are set.

[0009] In some embodiments, the first electrode line comprises:

[0010] a plurality of first sub-electrode lines extending along a first direction and arranged along a second direction, wherein the first direction intersects the second direction;

[0011] The first sub-electrode line is disconnected in the area where the first spacer is provided; the orthographic projection of the first spacer on the base substrate overlaps with the orthographic projection of the connecting line of the first sub-electrode line in the disconnected area on the base substrate.

[0012] In some embodiments, in the first direction, the distances between the orthographic projections of the first sub-electrode lines on both sides of the first spacer on the base substrate and the orthographic projections of the first spacer on the base substrate are substantially equal;

[0013] In the second direction, the orthographic projection of the first spacer on the base substrate includes portions located on both sides of the orthographic projection of the connection line of the first sub-electrode line in the disconnected area on the base substrate.

[0014] In some embodiments, a distance between an orthographic projection of the first spacer on the base substrate and an orthographic projection of the disconnected first sub-electrode line on the base substrate is greater than or equal to 4.5 micrometers.

[0015] In some embodiments, the array substrate further includes:

[0016] A plurality of scanning lines are located between the base substrate and the first electrode structure; the plurality of scanning lines extend along a first direction; the orthographic projection of the first sub-electrode line on the base substrate overlaps with the orthographic projection of the scanning line on the base substrate, and the orthographic projection of the spacer on the base substrate overlaps with the orthographic projection of the scanning line on the base substrate.

[0017] In some embodiments, the array substrate further includes:

[0018] A plurality of thin film transistors are located between the substrate and the first electrode structure; the thin film transistors include: a gate, a source and a drain; the gate is electrically connected to the scan line;

[0019] A plurality of second electrodes located on a side of the first electrode structure facing away from the substrate;

[0020] A plurality of first via holes; the second electrode and the drain electrode are electrically connected through the first via holes;

[0021] Orthographic projections of at least part of the first via holes on the base substrate fall into a wiring area between two adjacent rows of sub-pixel areas;

[0022] A distance between an orthographic projection of the first via hole on the base substrate and an orthographic projection of the first sub-electrode line on the base substrate is greater than or equal to 3 micrometers.

[0023] In some embodiments, the first electrode structure includes a plurality of first openings; and an orthographic projection of the first via on the base substrate falls within the orthographic projection of the first opening on the base substrate.

[0024] In some embodiments, the second electrode includes a plurality of slits; orthographic projections of the slits on the base substrate overlap with orthographic projections of the first opening on the base substrate.

[0025] In some embodiments, the array substrate further includes:

[0026] A plurality of data lines are located between the base substrate and the first electrode structure; an orthographic projection of the spacer on the base substrate overlaps with an orthographic projection of the data lines on the base substrate;

[0027] The first electrode line also includes:

[0028] A plurality of second sub-electrode lines extending in the same direction as the data lines;

[0029] The orthographic projection of the second sub-electrode line on the base substrate overlaps with the orthographic projection of the data line on the base substrate.

[0030] In some embodiments, the ratio of the number of data lines to the number of second sub-electrode lines is 3n, where n is a positive integer.

[0031] In some embodiments, the plurality of spacers further comprises a plurality of second spacers;

[0032] The orthographic projection of the second spacer on the base substrate overlaps with the orthographic projection of the first electrode line on the base substrate;

[0033] The first electrode line further includes: a plurality of first protrusions; the orthographic projections of the first protrusions on the base substrate overlap with the orthographic projections of the second spacers on the base substrate.

[0034] In some embodiments, the first electrode line includes a first sub-electrode line and a second sub-electrode line;

[0035] The first protrusion is electrically connected to the first sub-electrode line;

[0036] The orthographic projection of the second sub-electrode line on the base substrate overlaps with the orthographic projection of the second spacer on the base substrate.

[0037] In some embodiments, the number of the second sub-electrode lines is less than the number of the data lines, and the first electrode line further comprises: a plurality of first protrusions;

[0038] The orthographic projection of the first protrusion on the base substrate overlaps with the orthographic projection of the data line on the base substrate.

[0039] In some embodiments, an orthographic projection of the first protrusion on the base substrate overlaps with an orthographic projection of the gate of the thin film transistor on the base substrate.

[0040] In some embodiments, the array substrate includes a plurality of first vias; for the plurality of first vias and the plurality of first protrusions on one side of a sub-pixel area row, in the second direction, the orthographic projection of the first via on the base substrate and the orthographic projection of the first protrusion on the base substrate are located on the same side of the orthographic projection of the first sub-electrode line on the base substrate.

[0041] In some embodiments, the first electrode extends to the peripheral region;

[0042] The first electrode line also includes:

[0043] A first peripheral electrode line is located in the peripheral area;

[0044] The array substrate further includes:

[0045] The second peripheral electrode line is located between the substrate and the first electrode structure in the peripheral area; the second peripheral electrode line is electrically connected to the first peripheral electrode line.

[0046] In some embodiments, the array substrate includes a thin film transistor and a second electrode; the second peripheral electrode line is disposed in the same layer as the gate electrode of the thin film transistor;

[0047] The array substrate further includes:

[0048] a third peripheral electrode line, provided in the same layer as the second electrode;

[0049] The first peripheral electrode line and the second peripheral electrode line are electrically connected through a third peripheral electrode line.

[0050] In some embodiments, the first electrode structure includes:

[0051] A plurality of second openings are located in the peripheral area; the second openings penetrate the first electrode and the first peripheral electrode line;

[0052] The array substrate further includes:

[0053] A plurality of connection electrodes are provided in the peripheral region and in the same layer as the source electrode of the thin film transistor;

[0054] A plurality of second via holes are located in the peripheral area; the connecting electrode is electrically connected to the second peripheral electrode line through the second via holes;

[0055] a plurality of third via holes located in the peripheral area; an orthographic projection of the third via holes on the base substrate falls within an orthographic projection of the first peripheral electrode line on the base substrate, and the first peripheral electrode line and the third peripheral electrode line are electrically connected through the third via holes;

[0056] A plurality of fourth via holes are located in the peripheral area; the orthographic projections of the fourth via holes on the base substrate fall within the orthographic projections of the second opening on the base substrate, and the third peripheral electrode line is electrically connected to the connection electrode through the fourth via holes.

[0057] In some embodiments, the orthographic projection of the second via hole on the base substrate does not overlap with the orthographic projection of the third via hole on the base substrate and the orthographic projection of the fourth via hole on the base substrate.

[0058] In some embodiments, the peripheral region includes a fan-out region located on one side of the first region in the second direction;

[0059] The orthographic projections of the connecting electrode, the second opening, the second via hole, the third via hole, and the fourth via hole on the base substrate fall between the fan-out area and the first area.

[0060] In some embodiments, orthographic projections of the first peripheral electrode line, the second peripheral electrode line, and the third peripheral electrode line on the substrate surround the first region.

[0061] In some embodiments, the array substrate further includes:

[0062] a peripheral driving circuit located in a peripheral area on one side of the first area at least in the first direction;

[0063] The peripheral driving circuit includes: a plurality of cascaded driving units; the driving units include a first unit, a second unit, and a third unit arranged in sequence in a first direction; the first unit includes at least one first sub-unit, the second unit includes at least one second sub-unit, and the third unit includes at least one third sub-unit; the first sub-unit, the second sub-unit, and the third sub-unit each include a thin film transistor;

[0064] In the first direction, the width of the active area of ​​the thin film transistor included in the first subunit is smaller than the width of the active area of ​​the thin film transistor included in the second subunit, and the width of the active area of ​​the thin film transistor included in the second subunit is smaller than the width of the active area of ​​the thin film transistor included in the third subunit.

[0065] In some embodiments, in the first direction, the ratio of the width of the active area of ​​the thin film transistor included in the first subunit, the width of the active area of ​​the thin film transistor included in the second subunit, and the width of the active area of ​​the thin film transistor included in the third subunit is 1:2:4.

[0066] An embodiment of the present disclosure provides a display panel, the display panel comprising:

[0067] The array substrate provided by the embodiment of the present disclosure;

[0068] an opposite substrate, arranged opposite to the array substrate;

[0069] The liquid crystal layer is located between the array substrate and the opposite substrate.

[0070] An embodiment of the present disclosure provides a display device, which includes: a display panel provided by an embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0072] FIG1 is a schematic structural diagram of an array substrate provided by related art;

[0073] FIG2 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure;

[0074] FIG3 is a cross-sectional view along line AA′ in FIG2 provided by an embodiment of the present disclosure;

[0075] FIG4 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure;

[0076] FIG5 is a cross-sectional view along CC' in FIG4 provided by an embodiment of the present disclosure;

[0077] FIG6 is a cross-sectional view along line BB′ in FIG4 provided by an embodiment of the present disclosure;

[0078] FIG7 is an enlarged schematic diagram of the J region in FIG4 provided by an embodiment of the present disclosure;

[0079] FIG8 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure;

[0080] FIG9 is a schematic diagram of an enlarged structure of the E region in FIG8 according to an embodiment of the present disclosure;

[0081] FIG10 is a cross-sectional view along line FF′ in FIG9 provided by an embodiment of the present disclosure;

[0082] FIG11 is a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0083] FIG12 is a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0084] FIG13 is a schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0085] FIG14 is a schematic flow chart of a method for preparing an array substrate provided in an embodiment of the present disclosure;

[0086] FIG15 is a schematic flow chart of another method for preparing an array substrate provided in an embodiment of the present disclosure;

[0087] FIG16 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0088] FIG17 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0089] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0090] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0091] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0092] In the related art, as shown in FIG1 , the common electrode trace 19 is arranged on the same layer as the scan line 4. The common electrode trace 19 includes a first trace 1901 adjacent to the scan line 4. The arrangement of the first trace 1901 increases the size of the wiring area 1012 and reduces the size of the sub-pixel area 1011, resulting in a decrease in the sub-pixel aperture ratio, thereby affecting the transmittance of the display product and resulting in higher overall power consumption of the product. When the array substrate includes a spacer 3 and the spacer includes a first spacer, it is necessary to monitor and measure the size of the first spacer. Since the common electrode trace 19 is a metal trace with reflective properties, it affects the monitoring and measurement of the spacer 3 production, affects the production yield of the spacer 3, and further affects the production yield of the display product.

[0093] An embodiment of the present disclosure provides an array substrate, as shown in FIG2 and FIG3 , the array substrate includes:

[0094] The base substrate 1 includes a display area 101 and a peripheral area (not shown) surrounding the display area 101; the display area 101 includes: a plurality of sub-pixel areas 1011, and a wiring area 1012 located at least between adjacent sub-pixel areas 1011;

[0095] The first electrode structure 2 is located on one side of the base substrate 1. The first electrode structure 2 includes: a first electrode 201, and a first electrode line 202 located on a side of the first electrode 201 facing away from the base substrate 1 and electrically connected to the first electrode 201. The orthographic projection of the first electrode line 202 on the base substrate 1 falls within the wiring area 1012.

[0096] Multiple spacers 3 are located on the side of the first electrode structure 2 facing away from the base substrate 1; the orthographic projections of the multiple spacers 3 on the base substrate 1 fall into the wiring area 1012; the multiple spacers 3 include multiple first spacers 301; the orthographic projections of the first spacers 301 on the base substrate 1 do not overlap with the orthographic projections of the first electrode lines 202 on the base substrate 1, and the first electrode lines 202 are disconnected in the area where the first spacers 301 are set.

[0097] In the array substrate provided by the embodiment of the present disclosure, the first electrode line is electrically connected to the first electrode contact, which can reduce the resistance of the first electrode and improve the working stability of the first electrode structure. The first electrode line is electrically connected to the first electrode contact, that is, the first electrode line does not need to be set in the same layer as the scan line, which can avoid affecting the size of the sub-pixel area, can improve the sub-pixel aperture ratio, and thus reduce the power consumption of the display product. The orthographic projection of the first electrode line on the base substrate and the orthographic projection of the first spacer on the base substrate do not overlap with each other, and the first electrode line is disconnected in the area where the first spacer is set, which can avoid the reflection of the first electrode line affecting the data detection of the manufacturing process of the first spacer, can improve the manufacturing yield of the first spacer, and thus improve the manufacturing yield of the array substrate. In addition, since the first electrode line is electrically connected to the first electrode contact, when manufacturing the first electrode structure, a mask can be used to form the pattern of the first electrode line and the pattern of the first electrode through a half-tone mask process, which can save a mask, save process flow, and save cost.

[0098] It should be noted that FIG3 is a cross-sectional view along line AA′ in FIG2 . In FIG3 , film layers other than the base substrate 1 and the first electrode structure 2 are not shown.

[0099] In some embodiments, as shown in FIG4 , the array substrate further includes:

[0100] A plurality of scanning lines 4 are located between the base substrate 1 and the first electrode structure 2; the plurality of scanning lines 4 extend along a first direction X and are arranged along a second direction Y; the first direction X intersects the second direction Y; in FIG4 , the first direction X is perpendicular to the second direction Y; the orthographic projection of the spacer 3 on the base substrate 1 overlaps the orthographic projection of the scanning line 4 on the base substrate 1;

[0101] Multiple data lines 9 are located between the base substrate 1 and the first electrode structure 2; the multiple data lines 9 extend along the second direction Y and are arranged along the first direction X; the orthographic projection of the spacer 3 on the base substrate 1 overlaps with the orthographic projection of the data line 9 on the base substrate 1; the multiple scan lines 4 and the multiple data lines 9 are arranged to intersect with each other.

[0102] It should be noted that the data line extends along the second direction Y. As shown in FIG4 , the data line 9 may be bent and extended in the second direction Y. Alternatively, the data line may be extended in a straight line in the second direction Y.

[0103] It should be noted that the array substrate provided by the embodiment of the present disclosure can be applied to a liquid crystal display panel, and the liquid crystal display panel also includes a counter substrate arranged opposite to the array substrate. The first area includes: the area where the scan lines and data lines are located, and the area intersected by multiple scan lines and multiple data lines, that is, the first area corresponds to the display area of ​​the display panel; the area where the scan lines and data lines are located corresponds to the wiring area, that is, the orthographic projection of the scan lines on the substrate and the orthographic projection of the data lines on the substrate both fall into the wiring area; the sub-pixel area is located in the area intersected by multiple scan lines and multiple data lines. The counter substrate includes a black matrix, the black matrix has an opening area, the orthographic projection of the opening area on the substrate coincides with the sub-pixel area, and the orthographic projection of the black matrix on the substrate has an overlapping area with the wiring area located in the first area.

[0104] In a specific implementation, the first electrode is a common electrode, and the first electrode may be a planar electrode provided on the entire surface; that is, the orthographic projection of the first electrode on the base substrate overlaps with both the sub-pixel area and the wiring area.

[0105] In some embodiments, the first electrode is a transparent electrode to avoid affecting the light transmittance of the sub-pixel area; the first electrode comprises, for example, a transparent conductive material. The transparent conductive material is, for example, indium tin oxide;

[0106] The first electrode line is made of a metal material, such as molybdenum-niobium alloy (MoNb), copper (Cu), or molybdenum / niobium / titanium (Mo / Ni / Ti) alloy.

[0107] For example, the square resistance of the first electrode is approximately 40 ohms / square (Ω / □), and the square resistance of the first electrode line is approximately 0.065 Ω / □. The first electrode line is electrically connected to the first electrode, which is equivalent to the first electrode and the first electrode line being connected in parallel. This can significantly reduce the resistance of the first electrode and improve the operating stability of the first electrode. When the array substrate is used in a display panel, it can improve the display effect.

[0108] 2 , the orthographic projection of the first spacer 301 on the base substrate 1 overlaps the orthographic projection of the first electrode 201 on the base substrate 1. Since the first electrode is a transparent electrode, metal reflection will not affect the data monitoring of the first spacer.

[0109] In some embodiments, as shown in FIG. 2 , the plurality of sub-pixel regions 1011 include: a plurality of sub-pixel region rows 11 extending along a first direction X and arranged along a second direction Y, and a plurality of sub-pixel region columns 10 arranged along the first direction X and extending along a second direction Y; the wiring region 1012 includes: a plurality of wiring region rows 26 and a plurality of wiring region columns 27; at least a portion of the wiring region rows 26 is located between two adjacent rows of sub-pixel regions, and at least a portion of the wiring region columns 27 is located between two adjacent columns of sub-pixel regions;

[0110] The first electrode line 202 includes:

[0111] A plurality of first sub-electrode lines 2021 extend along a first direction X and are arranged along a second direction Y. As shown in FIG4 , the extending direction of the first sub-electrode lines 2021 is the same as the extending direction of the scan lines 4 . The orthographic projections of the first sub-electrode lines 2021 on the substrate 1 are located in the wiring area row 26 .

[0112] The orthographic projection of the first spacer 301 on the base substrate 1 overlaps with both the wiring area row 26 and the wiring area column 27;

[0113] The first sub-electrode line 2021 is disconnected in the area where the first spacer 301 is provided; the orthographic projection of the first spacer 301 on the base substrate 1 overlaps with the orthographic projection of the connecting line 45 of the first sub-electrode line 2021 in the disconnected area on the base substrate 1 .

[0114] It should be noted that the connection line of the first sub-electrode lines in the disconnected area refers to a connection line in the disconnected area and in the extending direction of the first sub-electrode lines.

[0115] In some embodiments, as shown in FIG. 2 , in the first direction X, a distance h1 between an orthographic projection of the first spacer 301 on the base substrate 1 and an orthographic projection of the disconnected first sub-electrode line 2021 on the base substrate 1 is greater than 0.

[0116] In the array substrate provided by the embodiment of the present disclosure, in the first direction X, the distance between the orthographic projection of the first spacer on the base substrate and the orthographic projection of the disconnected first sub-electrode line on the base substrate is greater than 0, thereby avoiding the situation where the orthographic projections of the first sub-electrode line on the base substrate are close and still affect the data detection during the production process of the first spacer, thereby improving the production yield of the first spacer.

[0117] In some embodiments, as shown in FIG. 2 , in the second direction Y, the orthographic projection of the first spacer 301 on the base substrate 1 includes portions on both sides of the orthographic projection of the connection line 45 of the first sub-electrode line 2021 in the disconnected area on the base substrate 1 .

[0118] In some embodiments, as shown in FIG. 2 , in the first direction X, the distances between the orthographic projections of the first sub-electrode lines 2021 on both sides of the first spacer 301 on the base substrate 1 and the orthographic projections of the first spacer 301 on the base substrate 1 are substantially equal.

[0119] It should be noted that the distances between the orthographic projections of the first sub-electrode lines respectively located on both sides of the first spacer on the base substrate and the orthographic projections of the first spacer on the base substrate being approximately equal means that: taking into account process errors, the difference between the distances between the orthographic projections of the first sub-electrode lines respectively located on both sides of the first spacer on the base substrate and the orthographic projections of the first spacer on the base substrate is less than the error, and it can be considered that the distances between the orthographic projections of the first sub-electrode lines respectively located on both sides of the first spacer on the base substrate and the orthographic projections of the first spacer on the base substrate are equal.

[0120] In the array substrate provided by the embodiment of the present disclosure, in the first direction, the distances between the orthographic projections of the first sub-electrode lines located on both sides of the first spacer on the base substrate and the orthographic projections of the first spacer on the base substrate are approximately equal, thereby avoiding the situation where the distance between the orthographic projections of the first sub-electrode lines on one side and the orthographic projections of the first spacer on the base substrate are too close to affect the data detection during the manufacturing process of the first spacer.

[0121] It should be noted that, as shown in Figure 2, in the first direction X, the distance h1 between the orthographic projection of the first spacer 301 on the base substrate 1 and the orthographic projection of the disconnected first sub-electrode line 2021 on the base substrate 1 is related to the position accuracy a1 when the first spacer 301 is manufactured and the spacer line width fluctuation a2, and needs to satisfy: h1≥a1+a2 / 2; wherein, a1 is approximately 2 microns to 3 microns, and a2 is approximately 2 microns to 4 microns.

[0122] That is, in specific implementation, h1 can be specifically set according to the width of the first spacer in the first direction to avoid the distance between the orthographic projection of the first sub-electrode line on the base substrate and the orthographic projection of the first spacer on the base substrate being too close to affect the data detection during the first spacer manufacturing process.

[0123] In some embodiments, as shown in FIG2 , the distance h1 between the orthographic projection of the first spacer 301 on the base substrate 1 and the orthographic projection of the disconnected first sub-electrode line 2021 on the base substrate 1 is greater than or equal to 4.5 microns. Furthermore, h1 can be set to be greater than or equal to 10 microns.

[0124] In some embodiments, as shown in FIG. 4 and FIG. 5 , the orthographic projection of the first sub-electrode line 2021 on the base substrate 1 overlaps with the orthographic projection of the scan line 4 on the base substrate 1 .

[0125] In the array substrate provided by the embodiment of the present disclosure, the first sub-electrode line and the scanning line have the same extension direction, and the orthographic projection of the first sub-electrode line on the base substrate overlaps with the orthographic projection of the scanning line on the base substrate, which can reduce the total width of the orthographic projections of the first sub-electrode line and the scanning line on the base substrate in the second direction, thereby reducing the width of the wiring area in the second direction and improving the sub-pixel aperture ratio.

[0126] It should be noted that FIG5 is a cross-sectional view along CC' in FIG4 .

[0127] In some embodiments, as shown in FIG4 , in the second direction Y, the line width of the scan line 4 is substantially equal to the line width of the first sub-electrode line 2021 ;

[0128] The orthographic projection of the first sub-electrode line 2021 on the base substrate 1 and the orthographic projection of the scanning line 4 on the base substrate 1 have a substantially overlapping area.

[0129] It should be noted that "the line width of the scan line is substantially equal to the line width of the first sub-electrode line" means that the difference between the line width of the scan line and the line width of the first sub-electrode line is less than the error, and the line width of the scan line is considered equal to the line width of the first sub-electrode line. "The orthographic projection of the first sub-electrode line on the substrate and the orthographic projection of the scan line on the substrate have a substantially overlapping area" means that, in the area where the orthographic projections of the first sub-electrode line and the orthographic projection of the scan line on the substrate overlap, the difference between the distances along the first direction between the edge of the orthographic projection of the first sub-electrode line on the substrate and the edge of the orthographic projection of the scan line on the substrate is less than the error, and the orthographic projection of the first sub-electrode line on the substrate and the orthographic projection of the scan line on the substrate have a substantially overlapping area.

[0130] In the array substrate provided by the embodiment of the present disclosure, the first sub-electrode line and the scanning line have the same extension direction, and the orthographic projection of the first sub-electrode line on the base substrate and the orthographic projection of the scanning line on the base substrate have a roughly overlapping area, which can further reduce the total width of the orthographic projection of the first sub-electrode line and the scanning line on the base substrate in the second direction, thereby reducing the width of the wiring area in the second direction and improving the sub-pixel aperture ratio.

[0131] In some embodiments, as shown in FIG. 4 and FIG. 6 , the first electrode structure 2 includes a plurality of first openings 25 ; the orthographic projections of the first openings 25 on the base substrate 1 fall within the wiring area 1012 ;

[0132] The array substrate further includes:

[0133] A plurality of thin film transistors 5 are located between the substrate 1 and the first electrode structure 2; the thin film transistors 5 include: a gate G, a source S and a drain D; the gate G is electrically connected to the scan line 4;

[0134] A plurality of second electrodes 6; located on the side of the first electrode structure 2 away from the base substrate 1; the orthographic projection of the second electrode 6 on the base substrate 1 overlaps with both the sub-pixel area 1011 and the wiring area 1012

[0135] The insulating layer 7 is located between the second electrode 6 and the drain electrode D, and includes a plurality of first via holes 8; the orthographic projections of the first via holes 8 on the base substrate 1 fall within the orthographic projections of the first opening 25 on the base substrate 1; the second electrode 6 and the drain electrode D are electrically connected through the first via holes 8;

[0136] The orthographic projection of at least part of the first via hole 8 on the base substrate 1 falls into the wiring area 1012 between two adjacent rows of sub-pixel areas 11 .

[0137] It should be noted that FIG6 is a cross-sectional view along line BB′ in FIG4 .

[0138] In the array substrate provided by the present disclosure, the second electrode is electrically connected to the drain electrode of the thin-film transistor through a first via. Because the second electrode is located on the side of the first electrode structure facing away from the base substrate, the first electrode structure includes a first opening that avoids the third via to facilitate electrical connection between the second electrode and the drain electrode.

[0139] In some embodiments, the second electrode is a pixel electrode; the pixel electrode is also a transparent electrode, and the material of the pixel electrode includes ITO.

[0140] In some embodiments, the first electrode or the second electrode further comprises a plurality of slits. In FIG4 , an example is given in which the first electrode 201 does not comprise slits and the second electrode 6 comprises slits 28 .

[0141] In some embodiments, as shown in FIG4 , the slits 28 extend along the second direction Y, and the orthographic projection of the slits 28 on the base substrate 1 overlaps with the orthographic projection of the first opening 25 on the base substrate 1. Therefore, when the array substrate provided by the embodiments of the present disclosure is applied to a liquid crystal display panel, the liquid crystal alignment liquid can better infiltrate the area corresponding to the first opening.

[0142] In some embodiments, as shown in FIG. 4 , the orthographic projection of the slit 28 on the base substrate 1 is in the form of a broken line, that is, the slit 28 bends and extends along the second direction Y.

[0143] Of course, in a specific implementation, the first electrode may include multiple slits while the second electrode may not include slits. When the first electrode includes slits, the slits are provided in a region of the first electrode outside the region where the first electrode lines are provided.

[0144] It should be noted that Figures 4 and 6 illustrate the example of the second electrode being located on the side of the first electrode structure facing away from the substrate. In practice, the first electrode structure may also be located on the side of the second electrode facing away from the substrate, thereby eliminating the need for the first electrode to have a first opening that avoids the second electrode. Alternatively, the first electrode may include multiple slits while the second electrode does not, or the second electrode may include multiple slits while the first electrode does not.

[0145] In some embodiments, as shown in FIG6 , a multi-layer insulating layer 7 is included between the second electrode 6 and the drain electrode D;

[0146] The multi-layer insulating layer 7 located between the second electrode 6 and the drain electrode D includes a first insulating layer 701 located between the first electrode structure 2 and the drain electrode D, and a second insulating layer 702 located between the first electrode structure 2 and the second electrode 6 .

[0147] In some embodiments, the thin film transistor has a bottom-gate structure, as shown in FIG6 , that is, the active layer 501 is located on the side of the gate G facing away from the base substrate 1 ; the array substrate further includes a third insulating layer 30 located between the active layer 501 and the gate G, and a buffer layer 31 located between the gate G and the base substrate 1 .

[0148] In some embodiments, as shown in FIG. 2 , FIG. 4 , and FIG. 6 , the first electrode 201 includes a plurality of first openings 25 .

[0149] That is, the first opening is formed in an area outside the pattern of the first electrode line to reduce the difficulty of manufacturing the first opening, avoid damaging the integrity of the first electrode line, avoid affecting the line width uniformity of the first electrode line, and avoid affecting the working stability of the first electrode structure.

[0150] In some embodiments, as shown in Figure 6, the first insulating layer 701 also includes a fifth via 32; the orthographic projection of the fifth via 32 on the substrate 1 falls within the orthographic projection of the first opening 25 on the substrate 1, the orthographic projection of the first via 8 on the substrate 1 falls within the orthographic projection of the fifth via 32 on the substrate 1, and the orthographic projection of the first via 8 on the substrate 1 and the orthographic projection of the fifth via 32 on the substrate 1 both fall within the orthographic projection of the drain D on the substrate 1.

[0151] In some embodiments, as shown in FIG4 and FIG7 , the distance h3 between the orthographic projection of the first via hole 8 on the base substrate 1 and the orthographic projection of the first sub-electrode line 2021 on the base substrate 1 is greater than or equal to 3 micrometers. This prevents process deviations during the fabrication of the first via hole from damaging the first sub-electrode line.

[0152] It should be noted that FIG7 is an enlarged view of the J region in FIG4 .

[0153] In some embodiments, a distance between an edge of an orthographic projection of the first via hole on the base substrate and an edge of an orthographic projection of the first opening on the base substrate is greater than 0, thereby preventing the second electrode from short-circuiting with the first electrode structure at the first via hole.

[0154] In some embodiments, the scan line and the gate are provided in the same layer and are electrically connected; specifically, the scan line and the gate are connected integrally.

[0155] It should be noted that in this disclosure, "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for producing a specific pattern, and then using the same mask through a single patterning process. That is, one patterning process corresponds to one mask. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or at different heights or have different thicknesses.

[0156] In some embodiments, as shown in FIG4 , the first electrode line 202 further includes:

[0157] A plurality of second sub-electrode lines 2022 extend in the same direction as the data lines 9 , that is, along the second direction Y;

[0158] The orthographic projection of the second sub-electrode line 2022 on the base substrate 1 and the orthographic projection of the data line 9 on the base substrate 1 fall into the wiring area 27 ; the orthographic projection of the second sub-electrode line 2022 on the base substrate 1 and the orthographic projection of the data line 9 on the base substrate 1 overlap.

[0159] In the array substrate provided by the embodiment of the present disclosure, the second sub-electrode line and the data line have the same extension direction, and the two are located in the wiring area column. The orthographic projection of the second sub-electrode line on the base substrate overlaps with the orthographic projection of the data line on the base substrate, which can reduce the total width of the orthographic projections of the second sub-electrode line and the data line on the base substrate in the first direction, thereby reducing the width of the wiring area in the first direction and improving the sub-pixel aperture ratio.

[0160] It should be noted that the second sub-electrode lines extend along the second direction Y. As shown in FIG4 , the second sub-electrode lines 2022 may be bent and extend in the second direction Y. Alternatively, the second sub-electrode lines may extend in a straight line in the second direction Y.

[0161] In some embodiments, the data line is provided in the same layer as the source and drain. In a specific implementation, the data line is integrally connected to the source.

[0162] In some embodiments, as shown in FIG4 , in the first direction X, the line width of the data line 9 is substantially equal to the line width of the second sub-electrode line 2022 ;

[0163] The orthographic projection of the second sub-electrode line 2022 on the base substrate 1 and the orthographic projection of the data line 9 on the base substrate 1 have a substantially overlapping area.

[0164] It should be noted that "the width of the data line is substantially equal to the width of the second sub-electrode line" means that the difference between the width of the data line and the width of the second sub-electrode line is less than the error, and the width of the data line is considered equal to the width of the second sub-electrode line. "The orthographic projection of the second sub-electrode line on the substrate and the orthographic projection of the data line on the substrate substantially overlap" means that, in the region where the orthographic projections of the second sub-electrode line and the orthographic projection of the data line on the substrate overlap, the difference between the distances along the second direction between the edge of the orthographic projection of the second sub-electrode line on the substrate and the edge of the orthographic projection of the data line on the substrate is less than the error, and the orthographic projection of the second sub-electrode line on the substrate and the orthographic projection of the data line on the substrate substantially overlap.

[0165] In the array substrate provided by the embodiment of the present disclosure, the second sub-electrode line and the data line have the same extension direction, and the orthographic projection of the second sub-electrode line on the base substrate and the orthographic projection of the data line on the base substrate have a roughly overlapping area, which can further reduce the total width of the orthographic projection of the second sub-electrode line and the data line on the base substrate in the first direction, thereby reducing the width of the wiring area in the first direction and improving the sub-pixel aperture ratio.

[0166] In some embodiments, as shown in FIG. 4 , the number of the second sub-electrode lines 2022 is less than the number of the data lines 9 .

[0167] It should be noted that in the related art, as shown in FIG1 , the common electrode trace 19 further includes longitudinally extending second traces 1902. The number of second traces 1902 is the same as the number of data lines (not shown), and the orthographic projections of the second traces 1902 and the data lines substantially coincide. If there is an alignment deviation between the second traces and the data lines, the size of the sub-pixel area 1011 in the first direction X will be affected, thereby affecting the sub-pixel aperture ratio.

[0168] In the array substrate provided by the embodiment of the present disclosure, the number of second sub-electrode lines is less than the number of data lines. Even if there is an alignment deviation between the second sub-electrode lines and the data lines, the impact on the sub-pixel aperture ratio can be reduced, thereby improving the display effect and enhancing the user experience.

[0169] In some embodiments, as shown in FIG. 4 , the number of data lines 9 spaced between any two adjacent second sub-electrode lines 2022 and their orthographic projections on the base substrate 1 is the same.

[0170] In the array substrate provided by the embodiment of the present disclosure, when the number of second sub-electrode lines is less than the number of data lines, the number of data lines spaced between any two adjacent second sub-electrode lines in the orthographic projection of the base substrate is the same, that is, the second sub-electrode lines are evenly distributed, which is beneficial to improving display uniformity.

[0171] In some embodiments, as shown in FIG4 , the ratio of the number of data lines 9 to the number of second sub-electrode lines 2022 is 3n, where n is a positive integer. The data lines are located in the first region and electrically connected to the thin film transistors, i.e., the data lines are required to transmit data signals.

[0172] Correspondingly, the orthographic projections of two adjacent second sub-electrode lines on the base substrate are spaced apart by 3n sub-pixel region columns.

[0173] In some embodiments, as shown in FIG4 , n=1. Two adjacent second sub-electrode lines 2022 are spaced apart by two data lines 9 and three sub-pixel area columns 10 on the orthographic projection of the base substrate 1 .

[0174] It should be noted that the multiple sub-pixels included in the array substrate are divided into multiple pixels; in some embodiments, each pixel includes three sub-pixels. When n = 1, that is, one pixel corresponds to one second sub-electrode line, this can reduce the impact on the sub-pixel aperture ratio while ensuring display uniformity.

[0175] In some embodiments, to ensure display uniformity, each pixel corresponds to at least one second sub-electrode line. That is, the ratio of the number of data lines to the number of second sub-electrode lines is m:k, where m is the number of sub-pixels included in the pixel, m is a positive integer greater than 1, and k is a positive integer not greater than m; the data line is a data line located in the first region and electrically connected to the thin film transistor, that is, the data line is a data line that needs to transmit a data signal. In a specific implementation, when m = 3, that is, each pixel includes 3 sub-pixels, then k = 1 or k = 2 or k = 3. When it is necessary to make the number of data lines greater than the number of second sub-electrode lines to reduce the impact on the sub-pixel aperture ratio, then k = 1 or k = 2.

[0176] In some embodiments, as shown in FIG. 4 , the orthographic projection of the first spacer 301 on the base substrate 1 and the orthographic projection of the second sub-electrode line 2022 on the base substrate 1 do not overlap with each other.

[0177] In some embodiments, as shown in FIG. 4 , when the number of the second sub-electrode lines 2022 is less than the number of the data lines 9 , no second sub-electrode lines 2022 are provided in the wiring area columns 27 corresponding to the first spacers 301 .

[0178] Alternatively, in some embodiments, if a first spacer needs to be set in the wiring area corresponding to the second sub-electrode line, the second sub-electrode line is disconnected in the area where the first spacer is set; in the second direction Y, the distance between the orthographic projection of the second sub-electrode line on the base substrate and the first spacer is greater than 0.

[0179] In the array substrate provided by the embodiment of the present disclosure, when the second sub-electrode line is disconnected in the area where the first spacer is set, in the second direction, the distance between the orthographic projection of the first spacer on the base substrate and the orthographic projection of the disconnected second sub-electrode line on the base substrate is greater than 0, thereby avoiding the situation where the orthographic projection of the second first electrode on the base substrate is close in distance and still affects the data detection of the first spacer manufacturing process, thereby improving the manufacturing yield of the first spacer.

[0180] In some embodiments, in the second direction, the distances between the orthographic projections of the second sub-electrode lines located on both sides of the first spacer on the base substrate and the orthographic projections of the first spacer on the base substrate are substantially equal.

[0181] It should be noted that the distances between the orthographic projections of the second sub-electrode lines located on both sides of the first spacer on the base substrate and the orthographic projections of the first spacer on the base substrate being approximately equal means that: taking into account process errors, the difference in the distances between the orthographic projections of the second sub-electrode lines located on both sides of the first spacer on the base substrate and the orthographic projections of the first spacer on the base substrate is less than the error, and it can be considered that the distances between the orthographic projections of the second sub-electrode lines located on both sides of the first spacer on the base substrate and the orthographic projections of the first spacer on the base substrate are equal.

[0182] In the array substrate provided by the embodiment of the present disclosure, in the second direction, the distances between the orthographic projections of the second sub-electrode lines located on both sides of the first spacer on the base substrate and the orthographic projections of the first spacer on the base substrate are approximately equal, thereby avoiding the situation where the distance between the orthographic projections of the second sub-electrode lines on one side and the orthographic projections of the first spacer on the base substrate are too close, which affects the data detection during the manufacturing process of the first spacer.

[0183] In some embodiments, when the second sub-electrode line is disconnected in the area where the first spacer is set, in the second direction, the distance h4 between the orthographic projection of the first spacer on the base substrate and the orthographic projection of the disconnected second sub-electrode line on the base substrate is related to the position accuracy a1 when the first spacer 301 is manufactured and the spacer line width fluctuation a2, and needs to satisfy: h4≥a1+a2 / 2; wherein a1 is approximately 2 microns to 3 microns, and a2 is approximately 2 microns to 4 microns.

[0184] That is, in specific implementation, h4 can be specifically set according to the width h5 of the first spacer in the second direction to avoid the distance between the orthographic projection of the second sub-electrode line on the base substrate and the orthographic projection of the first spacer on the base substrate being too close to affect the data detection of the first spacer manufacturing process.

[0185] In some embodiments, h5 is greater than or equal to 4.5 micrometers. Further, h5 can be set to be greater than or equal to 10 micrometers.

[0186] In some embodiments, as shown in FIG4 , the plurality of spacers 3 further include a plurality of second spacers 302 ; the thickness of the second spacers 302 is less than the thickness of the first spacers 301 ;

[0187] The orthographic projection of the second spacer 302 on the base substrate 1 overlaps with the orthographic projection of the first electrode line 202 on the base substrate 1 ;

[0188] The orthographic projection of the first sub-electrode line 2021 on the base substrate 1 and the orthographic projection of the second sub-electrode line 2022 on the base substrate 1 both overlap with the orthographic projection of the second spacer 302 on the base substrate 1 .

[0189] It should be noted that during the spacer fabrication process, data monitoring of the first spacer is more important. In the array substrate provided by the disclosed embodiments, the orthographic projection of the second spacer on the base substrate overlaps with the orthographic projection of the first electrode line on the base substrate. This ensures the electrical connection performance of the first electrode line and prevents disconnection of the first electrode line without affecting data monitoring of the first spacer.

[0190] 4 , the width of the second spacer 302 in the first direction X is smaller than the width of the first spacer 301 in the first direction X, and / or the width of the second spacer 302 in the second direction Y is smaller than the width of the first spacer 301 in the second direction Y.

[0191] In some embodiments, as shown in FIG4 , the number of the second sub-electrode lines 2022 is less than the number of the data lines 9 , and the first electrode line 202 further includes: a plurality of first protrusions 20211 ;

[0192] The first protrusion 20211 is electrically connected to the first sub-electrode line 2021 ; the orthographic projection of the first protrusion 20211 on the base substrate 1 is located in the wiring area 27 ; the first protrusion 20211 and the second sub-electrode line 2022 are located in different wiring areas 27 ;

[0193] The orthographic projection of the first protrusion 20211 on the base substrate 1 overlaps with the orthographic projection of the second spacer 302 on the base substrate 1 .

[0194] In the array substrate provided by the embodiment of the present disclosure, the first electrode line also includes an electrical connection with the first sub-electrode line, the orthographic projection of the first protrusion on the base substrate is located in a wiring area column, the first protrusion and the second sub-electrode line are located in different wiring areas, the orthographic projection of the first protrusion on the base substrate overlaps with the orthographic projection of the second spacer on the base substrate, so that the first electrode line is arranged under the second spacer, which can improve the height uniformity of the second spacer. When the array substrate is applied to a display panel, it can avoid the height difference of the second spacer at different positions affecting the performance of the display panel.

[0195] In some embodiments, as shown in FIG. 4 , the orthographic projection of the first protrusion 20211 on the base substrate 1 overlaps with the orthographic projection of the data line 9 on the base substrate 1 .

[0196] In some embodiments, as shown in FIG4 , in the first direction X, the line width of the data line 9 is substantially equal to the line width of the first protrusion 20211 ;

[0197] The orthographic projection of the first protrusion 20211 on the base substrate 1 and the orthographic projection of the data line 9 on the base substrate 1 have a substantially overlapping area.

[0198] It should be noted that the line width of the data line is substantially equal to the line width of the first raised portion line, which means that the difference between the line width of the data line and the line width of the first raised portion line is less than the error, and the line width of the data line is considered to be equal to the line width of the first raised portion line. The orthographic projection of the first raised portion line on the substrate and the orthographic projection of the data line on the substrate substantially overlap in an area where the orthographic projections of the first raised portion line overlap, which means that the difference between the distance between the edge of the orthographic projection of the first raised portion line on the substrate along the second direction and the edge of the orthographic projection of the data line on the substrate along the second direction in the area where the orthographic projections of the first raised portion line overlap is less than the error, and the orthographic projection of the first raised portion line on the substrate and the orthographic projection of the data line on the substrate substantially overlap.

[0199] In the array substrate provided by the embodiment of the present disclosure, the first raised portion line and the data line have the same extension direction, and the orthographic projection of the first raised portion line on the base substrate and the orthographic projection of the data line on the base substrate have a roughly overlapping area, which can further reduce the total width of the orthographic projection of the first raised portion line and the data line on the base substrate in the first direction, thereby reducing the width of the wiring area in the first direction and improving the sub-pixel aperture ratio.

[0200] In some embodiments, as shown in FIG. 4 , the orthographic projection of the first protrusion 20211 on the base substrate 1 overlaps with the orthographic projection of the gate G of the thin film transistor on the base substrate 1 .

[0201] In some embodiments, as shown in FIG. 4 , in the first direction X, the width of the first protrusion 20211 and the width of the second sub-electrode line 2022 are both smaller than the width of the second spacer 302 .

[0202] In some embodiments, as shown in FIG. 4 , the orthographic projection of the first protrusion 20211 on the base substrate 1 falls within the orthographic projection of the second spacer 302 on the base substrate 1 .

[0203] In some embodiments, as shown in Figure 4, the array substrate includes multiple first vias 8; for the multiple first vias 8 and the multiple first protrusions 20211 on one side of the sub-pixel area row 11, in the second direction Y, the orthographic projection of the first via 8 on the base substrate 1 and the orthographic projection of the first protrusion 20211 on the base substrate 1 are located on the same side of the orthographic projection of the first sub-electrode line 2021 on the base substrate 1.

[0204] In some embodiments, as shown in FIG8 , the first electrode (not shown) extends to the peripheral region 102 ;

[0205] The first electrode line 202 further includes:

[0206] The first peripheral electrode line 2023 is located in the peripheral area 102;

[0207] The array substrate further includes:

[0208] The second peripheral electrode line 12 is located between the base substrate 1 and the first electrode structure 2 in the peripheral area 102 ; the second peripheral electrode line 12 is electrically connected to the first peripheral electrode line 2023 .

[0209] The array substrate provided by the embodiment of the present disclosure also has a first peripheral electrode line and a second peripheral electrode line electrically connected to the first electrode in the peripheral area, thereby further reducing the resistance of the first electrode.

[0210] In some embodiments, the first sub-electrode line and the second sub-electrode line both extend to the peripheral region and are connected to the first peripheral electrode line.

[0211] In some embodiments, the orthographic projections of the first peripheral electrode line and the second peripheral electrode line on the base substrate surround the display area.

[0212] In some embodiments, as shown in Figure 8, in the first direction X, the width of the orthographic projection of the first peripheral electrode line 2023 on the substrate substrate 1 is smaller than the width of the orthographic projection of the second peripheral electrode line 12 on the substrate substrate 1, and in the second direction Y, the width of the orthographic projection of the first peripheral electrode line 2023 on the substrate substrate 1 is smaller than the width of the orthographic projection of the second peripheral electrode line 12 on the substrate substrate 1.

[0213] In some embodiments, as shown in FIG9 , the array substrate further includes:

[0214] The third peripheral electrode line 33 is provided in the same layer as the second electrode 6;

[0215] The first peripheral electrode line 2023 and the second peripheral electrode line 12 are electrically connected through the third peripheral electrode line 33 .

[0216] It should be noted that Figure 9 is an enlarged schematic diagram of region E in Figure 8. The pattern of the third peripheral electrode line and the conductive layer where it is located in the region corresponding to Figure 8 is shown in Figure 11.

[0217] In some embodiments, the second peripheral electrode line is disposed in the same layer as the gate of the thin film transistor.

[0218] In some embodiments, the second insulating layer also includes a plurality of third vias, and the third peripheral electrode line is electrically connected to the second peripheral electrode line through the third vias; the first electrode structure includes a plurality of second openings, and the second opening passes through the first electrode and the first peripheral electrode line; the array substrate also includes a seventh via passing through the first insulating layer and the third insulating layer, and the orthographic projection of the seventh via on the base substrate falls within the orthographic projection of the second opening on the base substrate, and the third peripheral electrode line is electrically connected to the second peripheral electrode line through the seventh via.

[0219] Alternatively, in some embodiments, as shown in FIG8 and FIG10 , the first electrode structure 2 includes:

[0220] A plurality of second openings 13 are located in the peripheral region 102 ; the second openings 13 pass through the first electrode 201 and the first peripheral electrode line 2023 ;

[0221] A plurality of connection electrodes 14 are provided in the peripheral region 102 and in the same layer as the source electrode (not shown) of the thin film transistor;

[0222] A plurality of second via holes 15 are located in the peripheral area 102 ; the connecting electrode 14 is electrically connected to the second peripheral electrode line 12 through the second via holes 15 ;

[0223] A plurality of third vias 16 are located in the peripheral area 102 ; the orthographic projections of the third vias 16 on the base substrate 1 fall within the orthographic projections of the first peripheral electrode lines 2023 on the base substrate 1 , and the first peripheral electrode lines 2023 are electrically connected to the third peripheral electrode lines 33 through the third vias 16 ;

[0224] A plurality of fourth vias 17 are located in the peripheral area 102 ; the orthographic projections of the fourth vias 17 on the base substrate 1 fall within the orthographic projections of the second openings 13 on the base substrate 1 , and the third peripheral electrode lines 33 are electrically connected to the connection electrodes 14 through the fourth vias 17 .

[0225] The array substrate provided by the embodiments of the present disclosure provides a connecting electrode, electrically connecting the connecting electrode to the second peripheral electrode line, and then electrically connecting the third peripheral electrode line to the connecting electrode and the second peripheral electrode line, thereby achieving electrical connection between the third peripheral electrode line, the first peripheral electrode line, the connecting electrode, and the second peripheral electrode line. The second, third, and fourth vias penetrate a relatively small number of insulating layers, thus avoiding overlap breakage caused by excessive via depth. This improves the manufacturing yield of the array substrate and reduces the difficulty of manufacturing the array substrate. The electrical connection between the first peripheral electrode line and the second peripheral electrode line by the third peripheral electrode line and the connecting electrode can also reduce the resistance of the electrode lines.

[0226] It should be noted that FIG10 is a cross-sectional view taken along line FF′ in FIG9 .

[0227] In some embodiments, as shown in Figure 10, the third insulating layer 30 includes a second via 15, that is, the second via 15 passes through the third insulating layer 30; the second insulating layer 702 includes a third via 16, that is, the third via 16 passes through the second insulating layer 702; the first insulating layer 701 also includes a sixth via 34, the orthographic projection of the sixth via 34 on the base substrate 1 falls within the orthographic projection of the second opening 13 on the base substrate 1, and the orthographic projection of the fourth via 17 on the base substrate 1 falls within the orthographic projection of the sixth via 34 on the base substrate 1; the fourth via 17 passes through the second insulating layer 702.

[0228] In some embodiments, as shown in FIG. 10 , the orthographic projection of the second via hole 15 on the base substrate 1 does not overlap with the orthographic projection of the third via hole 16 on the base substrate 1 and the orthographic projection of the fourth via hole 17 on the base substrate 1 .

[0229] In some embodiments, as shown in FIG8 , the peripheral area 102 includes a fan-out area 1021 located on one side of the display area 101 in the second direction Y;

[0230] The orthographic projections of the connecting electrode 14 , the second opening 13 , the second via hole (not shown), the third via hole (not shown), and the fourth via hole (not shown) on the base substrate 1 fall into the area between the display area 101 and the fan-out area 1021 .

[0231] In some embodiments, the orthographic projections of the first peripheral electrode line, the second peripheral electrode line, and the third peripheral electrode line on the base substrate surround the display area.

[0232] In some embodiments, as shown in FIG. 12 , the pattern of the second peripheral electrode line 12 and the conductive layer where it is located is shown in FIG. 12 , and the second peripheral electrode line 12 extends to the fan-out region 1021 .

[0233] Specifically, the fan-out region includes a first binding electrode electrically connected to the second peripheral electrode line. The first binding electrode can be used to bind to the driving element, so that the driving element provides a common voltage signal to the second peripheral electrode line and the first electrode structure through the first binding electrode.

[0234] In some embodiments, as shown in FIG13 , the array substrate further includes:

[0235] The peripheral driving circuit 18 is located in the peripheral area 102 on one side of the display area (not shown) at least in the first direction X;

[0236] The peripheral driving circuit 18 includes: a plurality of cascaded driving units 1801; each driving unit 1801 includes a first unit 1801-1, a second unit 1801-2, and a third unit 1801-3 arranged sequentially in a first direction X; the first unit 1801-1 includes at least one first sub-unit 18011, the second unit 1801-2 includes at least one second sub-unit 18012, and the third unit 1801-3 includes at least one third sub-unit 18013; the first sub-unit 18011, the second sub-unit 18012, and the third sub-unit 18013 include thin film transistors;

[0237] In the first direction X, the width of the thin film transistor active area included in the first subunit 18011 is smaller than the width of the thin film transistor active area included in the second subunit 18012 , and the width of the thin film transistor active area included in the second subunit 18012 is smaller than the width of the third subunit 18013 .

[0238] In the array substrate provided by the embodiment of the present disclosure, in the peripheral driving circuit, the widths of the active areas of different sub-units in the first direction are not exactly the same. The width of the active area can be set according to the specific structure of each sub-unit to avoid increasing the size of the peripheral area, which is conducive to achieving a narrow frame.

[0239] In some embodiments, in the first direction X, the ratio of the width of the thin film transistor active area included in the first subunit 18011, the width of the thin film transistor active area included in the second subunit 18012, and the width of the thin film transistor active area included in the third subunit 18013 is 1:2:4.

[0240] In some embodiments, in the second direction Y, the width of the thin film transistor active area included in the first subunit 18011, the width of the thin film transistor active area included in the second subunit 18012, and the width of the thin film transistor active area included in the third subunit 18013 are equal.

[0241] In some embodiments, a width of a thin film transistor active region included in the first sub-unit in the first direction is equal to a width of a thin film transistor active region included in the first sub-unit in the second direction.

[0242] In some embodiments, the width of the thin film transistor active area included in the first sub-unit in the first direction, the width of the thin film transistor active area included in the first sub-unit in the second direction, the width of the thin film transistor active area included in the second sub-unit in the second direction, and the width of the thin film transistor active area included in the third sub-unit in the second direction are all 5 microns; the width of the thin film transistor active area included in the second sub-unit in the first direction is 10 microns, and the width of the thin film transistor active area included in the third sub-unit in the first direction is 20 microns.

[0243] In some embodiments, the first unit, the second unit, and the third unit may further include a capacitor. The thin-film transistors included in the subunits are arranged as the smallest unit in the unit in which the subunit is located. As shown in FIG13 , the array substrate includes a first conductive layer 43, a second conductive layer 44 located on a side of the first conductive layer 43 facing away from the base substrate, and the first conductive layer 43.

[0244] Specifically, the first conductive layer includes: the gate of the thin film transistor located in the peripheral area and the display area, the first capacitor electrode of the capacitor of the peripheral driving circuit, the second peripheral electrode line and the scanning line; the second conductive layer includes: the source and drain of the thin film transistor located in the peripheral area and the display area, the second capacitor electrode of the capacitor of the peripheral driving circuit, the connecting electrode and the data line.

[0245] In some embodiments, as shown in FIG13 , the peripheral driving circuit 18 further includes a peripheral signal line 1802 . The first conductive layer 43 and the second conductive layer 44 both include the peripheral signal line 1802 .

[0246] In a specific implementation, the peripheral signal lines include, for example: high-level power lines, low-level power lines, output signal lines, frame start signal lines, clock signal lines, low-level signal lines, etc., to which each driving unit is electrically connected.

[0247] In a specific implementation, the peripheral driving circuit is, for example, a gate driving circuit. The peripheral driving unit is electrically connected to the scan line.

[0248] In a specific implementation, peripheral driving circuits can be provided on both sides of the display area in the first direction, wherein the peripheral driving circuit on one side is electrically connected to the odd-numbered scan lines, and the peripheral driving circuit on the other side is electrically connected to the even-numbered scan lines.

[0249] Based on the same inventive concept, an embodiment of the present disclosure further provides a method for preparing an array substrate, as shown in FIG14 , comprising:

[0250] S101, providing a base substrate; the base substrate includes a display area and a peripheral area surrounding the display area; the display area includes: a plurality of sub-pixel areas, and a wiring area located at least between adjacent sub-pixel areas;

[0251] S102, forming a first electrode layer and a first electrode line layer in sequence on one side of the base substrate;

[0252] S103, performing a patterning process on the first electrode layer and the first electrode line layer to form a pattern of a first electrode structure; the first electrode structure includes: a pattern of a first electrode formed by patterning the first electrode layer, and a pattern of a first electrode line formed by patterning the first electrode line layer; an orthographic projection of the first electrode line on the substrate falls within a wiring area;

[0253] S104, forming a plurality of spacers on a side of the first electrode line facing away from the base substrate; the orthographic projections of the plurality of spacers on the base substrate fall into the wiring area; the plurality of spacers include a plurality of first spacers; the orthographic projections of the first spacers on the base substrate do not overlap with the orthographic projections of the first electrode line on the base substrate, and the first electrode line is disconnected in the area where the first spacers are provided.

[0254] The method for preparing an array substrate provided by the embodiment of the present disclosure forms a first electrode line layer on the side of the first electrode layer facing away from the base substrate, and then performs a patterning process on the first electrode layer and the first electrode line layer to form a first electrode structure. A mask can be used to form the pattern of the first electrode line and the pattern of the first electrode through a half-tone mask process, which can save a mask, save process flow, and save costs. The first electrode line is electrically connected to the first electrode contact, which can reduce the resistance of the first electrode and improve the working stability of the first electrode structure. The first electrode line is electrically connected to the first electrode contact, that is, the first electrode line does not need to be set on the same layer as the scan line, which can avoid affecting the size of the sub-pixel area, can increase the sub-pixel aperture ratio, and thus reduce the power consumption of the display product. The orthographic projection of the first electrode line on the base substrate and the orthographic projection of the first spacer on the base substrate do not overlap with each other. The first electrode line is disconnected in the area where the first spacer is set, which can avoid the reflection of the first electrode line affecting the data detection in the manufacturing process of the first spacer, can improve the manufacturing yield of the first spacer, and thus improve the manufacturing yield of the array substrate.

[0255] In some embodiments, the first electrode includes a plurality of first openings; and before forming the first electrode layer, the method further includes:

[0256] forming a pattern of a gate electrode of a thin film transistor;

[0257] forming patterns of source and drain electrodes of thin film transistors;

[0258] forming a first insulating layer on a side of the source and drain electrodes facing away from the substrate, and patterning the first insulating layer to form a plurality of fifth via holes; wherein the orthographic projections of the fifth via holes on the substrate fall within the orthographic projections of the first opening on the substrate;

[0259] After forming the first electrode structure, the method further includes

[0260] forming a second insulating layer; the second insulating layer covers the first opening and the fifth via hole;

[0261] The second insulating layer is patterned to form a pattern of a plurality of first via holes; the orthographic projections of at least some of the first via holes on the base substrate fall within a wiring area between two adjacent rows of sub-pixel areas; the orthographic projections of the first via holes on the base substrate fall within the orthographic projections of the first opening on the base substrate, and the orthographic projections of the first via holes on the base substrate fall within the orthographic projections of the fifth via holes on the base substrate;

[0262] A pattern of a second electrode is formed; the second electrode is electrically connected to the drain electrode through the first via hole.

[0263] In specific implementation, when the second insulating layer is patterned to form a pattern of multiple first vias, it is necessary to meet the following requirements: the distance between the orthographic projection of the first via on the base substrate and the orthographic projection of the first sub-electrode line on the base substrate is greater than or equal to 3 microns, so as to avoid process deviations in the production process of the first via and cause damage to the first sub-electrode line.

[0264] In some embodiments, before forming the gate, the method further includes:

[0265] forming a buffer layer;

[0266] The gate is formed while:

[0267] forming a pattern of scan lines;

[0268] After forming the gate and before forming the source and drain, it also includes:

[0269] sequentially forming patterns of a third insulating layer and an active layer;

[0270] The source and drain electrodes are formed as well as:

[0271] A pattern of data lines is formed.

[0272] In some embodiments, the first electrode lines further include: a first peripheral electrode line located in the peripheral region;

[0273] While forming the pattern of the gate electrode of the thin film transistor, the method further includes:

[0274] forming a pattern of second peripheral electrode lines;

[0275] After forming the pattern of the gate electrode of the thin film transistor and before forming the pattern of the source electrode and the drain electrode of the thin film transistor, the method further includes:

[0276] forming a third insulating layer, and performing a patterning process on the third insulating layer to form a plurality of second via holes penetrating the third insulating layer;

[0277] While forming the pattern of the source and drain of the thin film transistor, it also includes:

[0278] forming a pattern of a plurality of connection electrodes; the connection electrodes are electrically connected to the second peripheral electrode lines through the second via holes;

[0279] After forming the first insulating layer, the method further includes:

[0280] Performing a patterning process on the first insulating layer to form a plurality of sixth via holes penetrating the first insulating layer;

[0281] While forming the first electrode structure, the method further includes:

[0282] forming a second opening penetrating the first peripheral electrode line and extending to the first electrode of the peripheral region; wherein the orthographic projection of the sixth via hole on the base substrate falls within the orthographic projection of the second opening on the base substrate, and the second insulating layer covers the second opening and the sixth via hole;

[0283] After forming the second insulating layer, the method further includes:

[0284] Performing a patterning process on the second insulating layer to form a plurality of third via holes and a plurality of fourth via holes; the orthographic projection of the third via holes on the base substrate falls within the orthographic projection of the first peripheral electrode line on the base substrate, the orthographic projection of the fourth via holes on the base substrate falls within the second opening, and the orthographic projection of the sixth via holes on the base substrate;

[0285] While forming the pattern of the second electrode, the method further comprises:

[0286] A pattern of a third peripheral electrode line is formed; the third peripheral electrode line is electrically connected to the first peripheral electrode line through the third via hole, and the third peripheral electrode line is electrically connected to the connection electrode through the fourth via hole.

[0287] In some embodiments, a patterning process is performed on the first electrode layer and the first electrode line layer to form a pattern of the first electrode structure, as shown in FIG15 , specifically including:

[0288] S1031 , coating a photoresist layer 37 on a side of the first electrode line layer 35 facing away from the substrate 1 ;

[0289] S1032, exposing the photoresist layer 37 using a half-tone mask process to remove the photoresist layer 37 in the first removal area Q1, and thinning the photoresist layer in the second removal area Q2;

[0290] S1033, removing the first electrode line layer 36 in the first removal area Q1 by an etching process;

[0291] S1034, removing the photoresist layer 37 in the second removal area Q2;

[0292] S1035 , removing the first electrode layer 35 in the first removal area Q1 by an etching process to form a pattern of the first electrode 201 ;

[0293] S1036 , removing the first electrode line layer 36 in the second removal area Q2 by an etching process to form a pattern of the first electrode line 202 ;

[0294] S1037 , removing the photoresist layer 37 on the side of the pattern of the first electrode line 202 facing away from the base substrate 1 .

[0295] During specific implementation, for example, an ashing process is used to remove the photoresist layer of the second removal area Q2. The first removal area corresponds to the area where both the first electrode layer and the first electrode line layer need to be removed, and the second removal area corresponds to the area outside the first removal area where only the first electrode line layer needs to be removed. The first removal area, for example, includes areas corresponding to the first opening and the second opening. If the first electrode layer of the first removal area is first removed by a process, and then the photoresist of the second removal area is removed by an ashing process, the side wall of the second insulating layer exposed in the first removal area will be etched, thereby causing the first electrode to be in a suspended state. The method for preparing the array substrate provided by the embodiment of the present disclosure, after removing the first electrode line in the first removal area, first removes the photoresist layer of the second removal area, and then removes the first electrode layer of the first removal area, so that the second insulating layer under the first electrode will not be etched.

[0296] In some embodiments, it further includes:

[0297] A peripheral driving circuit is formed in a peripheral area located on one side of the display area in a first direction; the peripheral driving circuit includes: a plurality of cascaded driving units; the driving unit includes a first subunit, a second subunit and a third subunit; in the first direction, the width of the thin film transistor active area included in the first subunit is smaller than the width of the thin film transistor active area included in the second subunit, and the width of the thin film transistor active area included in the second subunit is smaller than the width of the thin film transistor active area included in the third subunit.

[0298] In a specific implementation, while forming the gate, the following steps are also included:

[0299] forming a gate of a thin film transistor included in a driving unit and at least a portion of a peripheral signal line;

[0300] While forming the active layer, it also includes:

[0301] forming an active layer of a thin film transistor included in the driving unit;

[0302] While forming the source and drain, it also includes:

[0303] The source and drain of the thin film transistor included in the driving unit and at least a portion of the peripheral signal line are formed.

[0304] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, as shown in FIG16 , comprising:

[0305] The array substrate 38 provided in the embodiment of the present disclosure;

[0306] The opposite substrate 39 is arranged opposite to the array substrate 38;

[0307] The liquid crystal layer 40 is located between the array substrate 38 and the opposite substrate 39 .

[0308] The display panel provided by the embodiment of the present disclosure includes the above-mentioned array substrate provided by the present disclosure, and the first electrode line is electrically connected to the first electrode contact, which can reduce the resistance of the first electrode and improve the working stability of the first electrode structure. The first electrode line is electrically connected to the first electrode contact, that is, the first electrode line does not need to be arranged on the same layer as the scan line, which can avoid affecting the size of the sub-pixel area, can improve the sub-pixel aperture ratio, and thus reduce the power consumption of the display product. The orthographic projection of the first electrode line on the base substrate and the orthographic projection of the first spacer on the base substrate do not overlap with each other, and the first electrode line is disconnected in the area where the first spacer is set, which can avoid the reflection of the first electrode line affecting the data detection during the manufacturing process of the first spacer, can improve the manufacturing yield of the first spacer, and thus improve the manufacturing yield of the array substrate. In addition, since the first electrode line is electrically connected to the first electrode contact, when manufacturing the first electrode structure, a mask can be used to form the pattern of the first electrode line and the pattern of the first electrode through a half-tone mask process, which can save a mask, save process flow, and save costs.

[0309] In some embodiments, the opposing substrate also includes a base substrate. For ease of distinction, the disclosed embodiment refers to the base substrate included in the array substrate as the first base substrate, and the base substrate included in the opposing substrate as the second base substrate. The opposing substrate also includes a black matrix and color resist on the side of the second base substrate facing the liquid crystal layer. The black matrix has an opening area, and the color resist is located in the opening area; the spacer is located on the side of the black matrix facing the liquid crystal layer. In the display area, the orthographic projection of the black matrix on the base substrate coincides with the wiring area, and the orthographic projection of the opening area on the base substrate coincides with the sub-pixel area.

[0310] In a specific implementation, the orthographic projection of the color resist on the array substrate falls within the sub-pixel area. The color resist includes a red color resist corresponding to the red sub-pixel area, a blue color resist corresponding to the blue sub-pixel area, and a green color resist corresponding to the green sub-pixel area.

[0311] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device. As shown in FIG17 , the display device includes: a display panel 41 provided in an embodiment of the present disclosure.

[0312] In some embodiments, the display device provided in the embodiments of the present disclosure may further include a backlight module 42 located on the light incident side of the array substrate 38, as shown in FIG17 . The backlight module may be a direct-lit backlight module or an edge-lit backlight module.

[0313] In a specific implementation, the side-entry backlight module may include a light bar, a stacked reflective sheet, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet stacked on the light-emitting side of the matrix light source, a diffuser, and a brightening film, etc. The reflective sheet includes an opening arranged directly opposite the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source can be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.). Submillimeter or even micron-scale micro light-emitting diodes are self-luminous devices like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, it has a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because inorganic light-emitting diodes emit light based on metal semiconductors with more stable properties and lower resistance, they have the advantages of lower power consumption, better resistance to high and low temperatures, and longer service life compared to organic light-emitting diodes that emit light based on organic matter. Moreover, when micro-light-emitting diodes are used as backlight sources, more sophisticated dynamic backlight effects can be achieved. While effectively improving screen brightness and contrast, it can also solve the glare phenomenon caused by traditional dynamic backlighting between bright and dark areas of the screen, thereby optimizing the visual experience.

[0314] The display device provided in the embodiments of the present disclosure is any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. Other essential components of the display device are readily understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure. The implementation of the display device can be referenced to the aforementioned embodiments of the array substrate and display panel, and any repetitive details will not be repeated.

[0315] In summary, the array substrate and its preparation method, display panel, and display device provided by the embodiments of the present disclosure, wherein the first electrode line is electrically connected to the first electrode contact, can reduce the resistance of the first electrode and improve the working stability of the first electrode structure. The first electrode line is electrically connected to the first electrode contact, that is, the first electrode line does not need to be set on the same layer as the scan line, which can avoid affecting the size of the sub-pixel area, can improve the sub-pixel aperture ratio, and thus reduce the power consumption of the display product. The orthographic projection of the first electrode line on the base substrate and the orthographic projection of the first spacer on the base substrate do not overlap with each other, and the first electrode line is disconnected in the area where the first spacer is set, which can avoid the reflection of the first electrode line affecting the data detection of the first spacer manufacturing process, can improve the manufacturing yield of the first spacer, and thus improve the manufacturing yield of the array substrate. Moreover, since the first electrode line is electrically connected to the first electrode contact, when manufacturing the first electrode structure, a mask can be used to form the pattern of the first electrode line and the pattern of the first electrode through a half-tone mask process, which can save a mask, save process flow, and save costs.

[0316] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0317] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein, The array substrate comprises: A substrate, comprising a first region and a peripheral region surrounding the first region; A first electrode structure is located on one side of the substrate; the first electrode structure comprises: a first electrode, and a first electrode line located on a side of the first electrode away from the substrate and in contact and electrically connected with the first electrode; A plurality of spacers are located on a side of the first electrode structure away from the base substrate; the plurality of spacers include a plurality of first spacers; the orthographic projection of the first spacer on the base substrate and the orthographic projection of the first electrode line on the base substrate do not overlap each other, and the first electrode line is disconnected in the area where the first spacer is set.

2. The array substrate according to claim 1, wherein The first electrode line comprises: A plurality of first sub-electrode lines extending along a first direction and arranged along a second direction, wherein the first direction intersects with the second direction; The first sub-electrode line is disconnected in the area where the first spacer is provided; the orthographic projection of the first spacer on the base substrate overlaps with the orthographic projection of the connecting line of the first sub-electrode line in the disconnected area on the base substrate.

3. The array substrate according to claim 2, wherein In the first direction, the distances between the orthographic projections of the first sub-electrode lines respectively located on both sides of the first spacer on the base substrate and the orthographic projections of the first spacer on the base substrate are substantially equal; In the second direction, the orthographic projection of the first spacer on the base substrate includes portions located on both sides of the orthographic projection of the connection line of the first sub-electrode line in the disconnected area on the base substrate.

4. The array substrate according to claim 2, wherein, A distance between an orthographic projection of the first spacer on the base substrate and an orthographic projection of the disconnected first sub-electrode line on the base substrate is greater than or equal to 4.5 micrometers.

5. The array substrate according to any one of claims 2 to 4, wherein, The array substrate further includes: A plurality of scanning lines are located between the base substrate and the first electrode structure; the plurality of scanning lines extend along the first direction; the orthographic projection of the first sub-electrode line on the base substrate overlaps with the orthographic projection of the scanning line on the base substrate, and the orthographic projection of the spacer on the base substrate overlaps with the orthographic projection of the scanning line on the base substrate.

6. The array substrate according to any one of claims 2 to 5, wherein, The array substrate further includes: A plurality of thin film transistors are located between the substrate and the first electrode structure; the thin film transistors include: a gate, a source and a drain; the gate is electrically connected to the scan line; A plurality of second electrodes; located on a side of the first electrode structure away from the substrate; A plurality of first via holes; the second electrode is electrically connected to the drain electrode through the first via holes; A distance between an orthographic projection of the first via hole on the base substrate and an orthographic projection of the first sub-electrode line on the base substrate is greater than or equal to 3 micrometers.

7. The array substrate according to claim 6, wherein, The first electrode structure includes a plurality of first openings; an orthographic projection of the first via hole on the base substrate falls within an orthographic projection of the first opening on the base substrate.

8. The array substrate according to claim 7, wherein, The second electrode includes a plurality of slits; an orthographic projection of the slits on the base substrate overlaps with an orthographic projection of the first opening on the base substrate.

9. The array substrate according to any one of claims 2 to 8, wherein, The array substrate further includes: Multiple data lines, located between the substrate and the first electrode structure; the spacer overlaps with the data line in the orthographic projection on the substrate; The first electrode line further includes: Multiple second sub-electrode lines, consistent with the extending direction of the data line; The orthographic projection of the second sub-electrode line on the substrate overlaps with the orthographic projection of the data line on the substrate.

10. The array substrate according to claim 9, wherein, The ratio of the number of the data lines to the number of the second sub-electrode lines is 3n; where n is a positive integer.

11. The array substrate according to any one of claims 1 to 10, wherein, The multiple spacers further include multiple second spacers; The orthographic projection of the second spacer on the substrate overlaps with the orthographic projection of the first electrode line on the substrate; The first electrode line further includes: multiple first protrusions; The orthographic projection of the first protrusion on the substrate overlaps with the orthographic projection of the second spacer on the substrate.

12. The array substrate according to claim 11, wherein, The first electrode line includes a first sub-electrode line and a second sub-electrode line; The first protrusion is electrically connected to the first sub-electrode line; The orthographic projection of the second sub-electrode line on the substrate overlaps with the orthographic projection of the second spacer on the substrate.

13. The array substrate according to claim 12, wherein, The number of the second sub-electrode lines is less than the number of the data lines; The orthographic projection of the first protrusion on the substrate overlaps with the orthographic projection of the data line on the substrate.

14. The array substrate according to any one of claims 11 to 13, wherein, The orthographic projection of the first protrusion on the substrate overlaps with the orthographic projection of the gate of the thin film transistor on the substrate.

15. The array substrate according to any one of claims 11 to 14, wherein, The array substrate includes multiple first vias; for the multiple first vias and the multiple first protrusions on one side of the row in the sub-pixel region, in the second direction, the orthographic projection of the first via on the substrate and the orthographic projection of the first protrusion on the substrate are located on the same side of the orthographic projection of the first sub-electrode line on the substrate.

16. The array substrate according to any one of claims 1 to 15, wherein, The first electrode extends to the peripheral region; The first electrode line further includes: A first peripheral electrode line, located in the peripheral region; The array substrate further includes: A second peripheral electrode line, located between the substrate and the first electrode structure in the peripheral region; the second peripheral electrode line is electrically connected to the first peripheral electrode line.

17. The array substrate according to claim 16, wherein, The array substrate includes a thin film transistor and a second electrode; The second peripheral electrode line is arranged on the same layer as the gate of the thin film transistor; The array substrate further includes: A third peripheral electrode line, arranged on the same layer as the second electrode; The first peripheral electrode line is electrically connected to the second peripheral electrode line through the third peripheral electrode line.

18. The array substrate according to claim 17, wherein, The first electrode structure includes: Multiple second openings, located in the peripheral region; the second openings penetrate through the first electrode and the first peripheral electrode line; The array substrate further includes: Multiple connection electrodes, arranged on the same layer as the source of the thin film transistor in the peripheral region; Multiple second vias, located in the peripheral region; the connection electrode is electrically connected to the second peripheral electrode line through the second via; A plurality of third vias, located in the peripheral region; a positive projection of the third vias on the substrate falls within a positive projection of the first peripheral electrode line on the substrate, and the first peripheral electrode line and the third peripheral electrode line are electrically connected through the third vias; A plurality of fourth vias, located in the peripheral region; a positive projection of the fourth vias on the substrate falls within a positive projection of the second opening on the substrate, and the third peripheral electrode line and the connection electrode are electrically connected through the fourth vias.

19. The array substrate according to claim 18, wherein, A positive projection of the second via on the substrate, a positive projection of the third via on the substrate, and a positive projection of the fourth via on the substrate do not overlap with each other.

20. The array substrate according to claim 18 or 19, wherein The peripheral region includes a fan-out region located on one side of the first region in the second direction; Positive projections of the connection electrode, the second opening, the second via, the third via, and the fourth via on the substrate fall between the fan-out region and the first region.

21. The array substrate according to any one of claims 16 to 20, wherein, Positive projections of the first peripheral electrode line, the second peripheral electrode line, and the third peripheral electrode line on the substrate surround the first region.

22. The array substrate according to any one of claims 1 to 21, wherein, The array substrate further includes: A peripheral driving circuit, at least in the peripheral region on one side of the first region in the first direction; The peripheral driving circuit includes: a plurality of cascaded driving units; the driving unit includes a first unit, a second unit, and a third unit arranged in sequence in the first direction; the first unit includes at least one first sub-unit, the second unit includes at least one second sub-unit, and the third unit includes at least one third sub-unit; the first sub-unit, the second sub-unit, and the third sub-unit all include thin film transistors; In the first direction, a width of an active region of the thin film transistor included in the first sub-unit is smaller than a width of an active region of the thin film transistor included in the second sub-unit, and the width of the active region of the thin film transistor included in the second sub-unit is smaller than a width of an active region of the thin film transistor included in the third sub-unit.

23. The array substrate according to claim 22, wherein, In the first direction, a ratio of the width of the active region of the thin film transistor included in the first sub-unit, the width of the active region of the thin film transistor included in the second sub-unit, and the width of the active region of the thin film transistor included in the third sub-unit is 1:2:

4.

24. A display panel, wherein, The display panel includes: The array substrate according to any one of claims 1 to 23; A counter substrate, disposed opposite to the array substrate; A liquid crystal layer, located between the array substrate and the counter substrate.

25. A display device, wherein, The display device includes: the display panel according to claim 24.

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