Display device, display panel and manufacturing method thereof

Abstract

The invention discloses a display device, a display panel and a manufacturing method thereof. The display panel comprises a display area (10) with a cathode layer (900), wherein the display area (10) comprises a plurality of pixel areas (11); the plurality of pixel areas (11) comprise a first pixel area (111) with a first color light-emitting unit, a second pixel area (112) with a second color light-emitting unit and a third pixel area (113) with a third color light-emitting unit; the cathode layer (900) comprises a first cathode region (910) and a second cathode region (920); the first cathode region (910) is connected with a first VSS signal end with a first voltage, and the first cathode region (910) covers the first pixel region (111); the second cathode region (920) is connected with a second VSS signal end with a second voltage, and the second cathode region (920) covers the second pixel region (112) and / or the third pixel region (113). The display panel further comprises an auxiliary VSS layer (310), the auxiliary VSS layer (310) comprises a first auxiliary VSS signal line (311) and a second auxiliary VSS signal line (312), the first auxiliary VSS signal line (311) is connected with the first VSS signal end through a via hole located in the non-pixel area (12), and the second auxiliary VSS signal line (312) is connected with the second VSS signal end through a via hole located in the non-display area (20).

Description

Display device, display panel and manufacturing method thereof Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display device, a display panel and a manufacturing method thereof. Background Art

[0002] Organic electroluminescent display (OLED) panels have gradually become the mainstream in the display field due to their excellent performance such as low power consumption, high color saturation, wide viewing angle, thin thickness, and flexibility. They can be widely used in terminal products such as smartphones, tablets, and TVs.

[0003] With the advancement of OLED display technology and the continuous optimization of product performance, reducing overall screen power consumption is currently a key development direction for OLEDs. Traditional OLED screens often feature a cathode layer that spans the entire surface and is connected to the VSS signal terminal, meaning there's only a single VSS voltage within the screen. However, due to the characteristics of OLED pixel devices, the current flowing through the RGB components at the same brightness varies. Because the current flowing through the B (blue) pixel is greater than that flowing through the R / G (red / green) pixels, the saturation margin voltage of the R / G pixels is higher than that of the B pixels, even if the VDD and VSS voltages across the RGB pixels remain unchanged. This results in wasted energy.

[0004] Summary of the Invention

[0005] The purpose of this application is to provide a display device with low energy consumption, a display panel and a manufacturing method thereof.

[0006] The present application discloses a display panel, comprising:

[0007] A display area, the display area including a plurality of pixel areas;

[0008] The plurality of pixel regions include:

[0009] a first pixel region, the first pixel region including a first color light emitting unit;

[0010] a second pixel region, the second pixel region including a second color light emitting unit;

[0011] a third pixel region, the third pixel region including a third color light emitting unit;

[0012] a cathode layer, the cathode layer comprising:

[0013] a first cathode region, the first cathode region being connected to a first VSS signal terminal, the first VSS signal terminal having a first voltage, and the first cathode region covering the first pixel region;

[0014] The second cathode region is connected to the second VSS signal terminal, the second VSS signal terminal has a second voltage, and the second cathode region covers the second pixel region and / or the third pixel region.

[0015] Optionally, the second cathode region covers the second pixel region;

[0016] The cathode layer further includes a third cathode region, the third cathode region is connected to a third VSS signal terminal, the third VSS signal terminal has a third voltage, and the third cathode region covers the third pixel region.

[0017] Optionally, the first color is one of green, red or blue; the second color is another of green, red or blue; and the third color is the last of green, red or blue.

[0018] Optionally, the display panel further includes an auxiliary VSS layer; the auxiliary VSS layer includes a first auxiliary VSS signal line; the first auxiliary VSS signal line is connected to the first VSS signal terminal; and the first auxiliary VSS signal line is connected to the first cathode region.

[0019] Optionally, the auxiliary VSS layer further includes a second auxiliary VSS signal line; the second auxiliary VSS signal line is connected to the second VSS signal terminal; and the second auxiliary VSS signal line is connected to the second cathode region.

[0020] Optionally, the auxiliary VSS layer further includes a third auxiliary VSS signal line; the third auxiliary VSS signal line is connected to the third VSS signal terminal; and the third auxiliary VSS signal line is connected to the third cathode region.

[0021] Optionally, the display panel further includes:

[0022] substrate;

[0023] a driving structure layer, the driving structure layer being arranged on one side of the substrate;

[0024] a first source / drain metal layer, wherein the first source / drain metal layer is disposed on a side of the driving structure layer away from the substrate;

[0025] A first flat layer; the first flat layer is arranged on a side of the first source / drain metal layer away from the driving structure layer;

[0026] a second source-drain metal layer, the second source-drain metal layer being disposed on a side of the first planar layer away from the first source-drain metal layer;

[0027] a second planarization layer, the second planarization layer being arranged on a side of the second source / drain metal layer away from the first planarization layer;

[0028] an anode layer, the anode layer being arranged on a side of the second planar layer away from the second source / drain metal layer;

[0029] a light-emitting structure layer, the light-emitting structure layer including the light-emitting unit, the light-emitting structure layer being arranged on a side of the anode layer away from the second planar layer;

[0030] The cathode layer is arranged on a side of the light emitting structure layer away from the anode layer;

[0031] A pixel defining layer is disposed on the second planar layer and away from the second source / drain metal layer.

[0032] Optionally, the auxiliary VSS layer is provided on any layer between the anode layer and the driving structure layer, or the auxiliary VSS layer is provided between any two adjacent layers between the anode layer and the driving structure layer.

[0033] Optionally, the display panel further includes:

[0034] A non-display area, the non-display area includes multiple first vias, the first cathode area is connected to the first auxiliary VSS signal line through the first via, the second cathode area is connected to the second auxiliary VSS signal line through the first via, and the third cathode area is connected to the third auxiliary VSS signal line through the first via.

[0035] Optionally, the display area includes multiple second vias, the first cathode area is connected to the first auxiliary VSS signal line through the second vias, the second cathode area is connected to the second auxiliary VSS signal line through the second vias, and the third cathode area is connected to the third auxiliary VSS signal line through the second vias.

[0036] Optionally, an orthographic projection of the second via hole onto the substrate has no overlapping area with an orthographic projection of the pixel area onto the substrate.

[0037] Optionally, the display panel further includes:

[0038] substrate;

[0039] a driving structure layer, the driving structure layer being arranged on one side of the substrate;

[0040] a first source / drain metal layer, wherein the first source / drain metal layer is disposed on a side of the driving structure layer away from the substrate;

[0041] A first flat layer; the first flat layer is arranged on a side of the first source / drain metal layer away from the driving structure layer;

[0042] a second source-drain metal layer, the second source-drain metal layer being disposed on a side of the first planar layer away from the first source-drain metal layer;

[0043] a second planarization layer, the second planarization layer being arranged on a side of the second source / drain metal layer away from the first planarization layer;

[0044] The cathode layer is arranged on a side of the second planar layer away from the second source / drain metal layer;

[0045] a light-emitting structure layer, the light-emitting structure layer including the light-emitting unit, the light-emitting structure layer being arranged on a side of the anode layer away from the second planar layer;

[0046] an anode layer, the anode layer being arranged on a side of the light-emitting structure layer away from the cathode layer;

[0047] A pixel defining layer is disposed on the second planar layer and away from the second source / drain metal layer.

[0048] Optionally, the auxiliary VSS layer is provided in any layer between the cathode layer and the driving structure layer.

[0049] The present application also discloses a method for manufacturing a display panel, wherein the display panel comprises:

[0050] A display area, the display area including a plurality of pixel areas;

[0051] The plurality of pixel regions include:

[0052] a first pixel region, the first pixel region including a first color light emitting unit;

[0053] a second pixel region, the second pixel region including a second color light emitting unit;

[0054] a third pixel region, the third pixel region including a third color light emitting unit;

[0055] The method includes forming a cathode layer, and the forming of the cathode layer includes:

[0056] Manufacturing a first cathode region, wherein the first cathode region is connected to a first VSS signal terminal, the first VSS signal terminal has a first voltage, and the first cathode region covers the first pixel region;

[0057] A second cathode region is manufactured, wherein the second cathode region is connected to a second VSS signal terminal, the second VSS signal terminal has a second voltage, and the second cathode region covers the second pixel region and / or the third pixel region.

[0058] Optionally, forming the cathode layer includes:

[0059] The first cathode region and the second cathode region are formed on the cathode layer by fine metal mask evaporation technology.

[0060] Optionally, forming the cathode layer includes:

[0061] An isolation column is preset in the cathode layer, and then filled to form the first cathode region and the second cathode region.

[0062] The present application also discloses a display device, which includes the above-mentioned display panel.

[0063] Compared with the related art, the cathode layer of the present invention includes a first cathode region and a second cathode region. The first cathode region is connected to the first VSS signal terminal and the first pixel region, and the second cathode region is connected to the second VSS signal terminal and the second pixel region and / or the third pixel region, so that the cross-voltage of each pixel region can be controlled individually, thereby reducing the energy consumption of the display panel.

[0064] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0066] FIG1 is a schematic top view of the display panel of the present application.

[0067] FIG2 is a schematic diagram of pixel distribution in area A in FIG1 .

[0068] FIG3 is a schematic diagram of cathode layer distribution in area A in FIG1 .

[0069] FIG4 is a schematic diagram of cathode layer distribution in area B in FIG1 .

[0070] FIG5 is a schematic cross-sectional view of an embodiment of a display panel of the present application along line EE in FIG3 .

[0071] FIG6 is a schematic cross-sectional view of another embodiment of the display panel of the present application along line HH in FIG4 .

[0072] FIG7 is a schematic cross-sectional view of another embodiment of the display panel of the present application along line EE in FIG3 .

[0073] FIG8 is a schematic cross-sectional view of another embodiment of the display panel of the present application along line DD in FIG3 .

[0074] FIG9 is a schematic cross-sectional view of another embodiment of the display panel of the present application along line FF in FIG4 .

[0075] FIG10 is a schematic cross-sectional view of another embodiment of the display panel of the present application along line DD in FIG3 .

[0076] FIG11 is a schematic cross-sectional view of another embodiment of the display panel of the present application along line CC in FIG3 .

[0077] FIG12 is a schematic cross-sectional view of another embodiment of the display panel of the present application along line GG in FIG4 .

[0078] FIG13 is a schematic cross-sectional view of another embodiment of the display panel of the present application along line CC in FIG3 . DETAILED DESCRIPTION

[0079] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of this specification, as detailed in the appended claims.

[0080] The terminology used in this application is for the purpose of describing specific embodiments only and is not intended to limit the present disclosure. Unless otherwise defined, technical or scientific terms used in this specification should have the same ordinary meaning as those having ordinary skill in the art to which this application belongs. The terms "first," "second," and similar terms used in this specification and claims do not denote any order, quantity, or importance, but are simply used to distinguish different components. Similarly, terms such as "a" or "an" do not denote a limitation of quantity, but rather indicate the presence of one. "Multiple" or "several" means two or more. Unless otherwise indicated, terms such as "front," "rear," "lower," and / or "upper" are used for convenience only and are not intended to limit the scope of the present disclosure to a specific location or spatial orientation. Terms such as "include" or "comprising" mean that the elements or objects listed before "include" or "comprising" include the elements or objects listed after "include" or "comprising" and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect.

[0081] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used in this specification and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0082] In related art, the cathode layer of a display panel is designed to be uniform across the entire surface, with its voltage being the same as the voltage at the VSS signal terminal. However, due to the characteristics of OLED pixel devices, the current flowing through the RGB devices at the same brightness is not uniform. The current flowing through the blue pixel is greater than that flowing through the red and green pixels. Therefore, when the voltage across the pixel VDD and VSS remains unchanged, the power consumption of the red and green pixels is greater than that of the blue pixel. This results in energy waste.

[0083] As shown in FIG? , to solve the above problem, the present application provides a display panel, which includes:

[0084] A display area 10, wherein the display area 10 includes a plurality of pixel areas 11;

[0085] The plurality of pixel regions 11 include:

[0086] A first pixel area 111, wherein the first pixel area 111 includes a first color light emitting unit;

[0087] A second pixel area 112, wherein the second pixel area 112 includes a second color light emitting unit;

[0088] A third pixel area 113, wherein the third pixel area 113 includes a third color light emitting unit;

[0089] The cathode layer 900 includes:

[0090] A first cathode region 910 , wherein the first cathode region 910 is connected to a first VSS signal terminal, the first VSS signal terminal has a first voltage U1 , and the first cathode region 910 covers the first pixel region 111 ;

[0091] The second cathode region 920 is connected to the second VSS signal terminal, the second VSS signal terminal has a second voltage U2 , and the second cathode region 920 covers the second pixel region 112 and / or the third pixel region 113 .

[0092] In order to solve the above technical problems, the present application further provides a method for manufacturing a display panel.

[0093] In order to solve the above technical problems, the present application also provides a display device, which includes the above display panel.

[0094] The cathode layer 900 of the present application includes a first cathode region 910 and a second cathode region 920. The first cathode region 910 is connected to the first VSS signal terminal and the first pixel region 111, and the second cathode region 920 is connected to the second VSS signal terminal and the second pixel region 112 and / or the third pixel region 113, so that the cross-voltage of each pixel region can be controlled individually, thereby reducing the energy consumption of the display panel.

[0095] The following will describe in detail the various embodiments of the present application that are consistent with the above-mentioned creative concepts.

[0096] As shown in Figures 1 to 5 , the present application provides a display panel comprising a display area 10 and a non-display area 20 . The non-display area 20 is located at the edge of the display area 10 and surrounds at least a portion of the display area 10 .

[0097] The display area 10 includes a pixel area 11 and a non-pixel area 12. A plurality of pixel areas 11 are arranged in an array in the display area 10 of the display panel. Each pixel area 11 is separated by a non-pixel area 12. The plurality of pixel areas 11 include a first pixel area 111, a second pixel area 112 and a third pixel area 113. The first pixel area 111 includes a first color light-emitting unit, the second pixel area 112 includes a second color light-emitting unit, and the third pixel area 113 includes a third color light-emitting unit. The first color is one of green, red or blue, the second color is another of green, red or blue, and the third color is the last of green, red or blue. For example, the first color is green, the second color is blue, and the third color is red, or the first color is blue, the second color is red, and the third color is green, etc. Of course, the first color, the second color and the third color can also be colors other than red, green and blue, as long as the combination of the first color, the second color and the third color can meet the light output requirements of the display panel. The first pixel region 111 , the second pixel region 112 and the third pixel region 113 are each arranged in an array in the display region 10 of the display panel.

[0098] The non-display area 20 includes a VSS signal line. Optionally, the VSS signal line includes a first VSS signal line 22 connected to the first VSS signal terminal, and a second VSS signal line 23 connected to the second VSS signal terminal. Or the VSS signal line includes a first VSS signal line 22 connected to the first VSS signal terminal, a second VSS signal line 23 connected to the second VSS signal terminal, and a third VSS signal line 24 connected to the third VSS signal terminal. The first VSS signal terminal has a first voltage U1, the second VSS signal terminal has a second voltage U2, and the third VSS signal terminal has a third voltage U3. The first voltage U1, the second voltage U2, and the third voltage U3 can be adjusted independently as needed. Optionally, the non-display area 20 may also include GOA (gate drive circuit, Gate Drive on Array), VDD signal lines, and other wiring or structures (not shown).

[0099] As shown in FIG5 , the display panel includes a substrate 100, which may be a rigid substrate. The rigid substrate may be a glass substrate or a PMMA (polymethyl methacrylate) substrate. Alternatively, the substrate 100 may be a flexible substrate. The flexible substrate may be a PET (polyethylene terephthalate) substrate, a PEN (polyethylene naphthalate diformic acid glycol ester) substrate, or a PI (polyimide) substrate.

[0100] A driving structure layer 200 is provided on one side of the substrate 100. The driving structure layer 200 includes a driving circuit structure of the pixel. The driving circuit structure of the pixel can be a circuit structure such as 2T1C (2 TFTs plus 1 capacitor) (TFT: Thin Film Transistor), 3T1C, 7T1C, 12T1C or 16T3C. The driving structure layer 200 may include an active area, several gate insulating layers, the gate of the transistor, the source of the transistor, the drain of the transistor, etc. (not shown). A first source-drain metal layer 300 is provided on the side of the driving structure layer 200 away from the substrate 100, and the gate of the transistor and the source of the transistor are connected to the first source-drain metal layer 300. A first flat layer 400 is provided on the side of the first source-drain metal layer 300 away from the driving structure layer 200. Optionally, a second source-drain metal layer 500 is provided on the side of the first flat layer 400 away from the first source-drain metal layer 300. A second flat layer 600 is provided on the side of the second source / drain metal layer 500 away from the first flat layer 400. A pixel defining layer 700 is provided on the side of the second flat layer 600 away from the second source / drain metal layer 500. The pixel defining layer 700 includes a plurality of pixel openings, and the pixel defining layer 700 defines a pixel area 11 through the pixel openings. That is, the area corresponding to the pixel openings in the pixel defining layer 700 is the pixel area 11, and the area corresponding to the non-pixel openings is the non-pixel area 12. An anode layer 800, a cathode layer 900, and a light-emitting structure layer 810 located between the anode layer 800 and the cathode layer 900 are provided on the side of the second flat layer 600 away from the second source / drain metal layer 500. Among them, the light-emitting structure layer 810 may include a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting unit, a hole blocking layer, an electron transport layer, an electron injection layer, etc. (not shown) from the anode to the cathode. The light-emitting unit may be a red light-emitting unit, a green light-emitting unit, or a blue light-emitting unit, etc. The light emitting structure layer 810 is disposed at the pixel opening position in the pixel defining layer 700 , that is, the light emitting structure layer 810 is disposed in the pixel region 11 .

[0101] As shown in Figures 5, 6, 8, and 9, in an optional embodiment, an anode layer 800 is disposed on a side of the second planar layer 600 away from the second source / drain metal layer 500. A light-emitting structure layer 810 is disposed on a side of the anode layer 800 away from the second planar layer 600. A cathode layer 900 is disposed on a side of the light-emitting structure layer 810 away from the anode layer 800. Cathode layer 900 includes a first cathode region 910 and a second cathode region 920. The first cathode region 910 is connected to a first VSS signal terminal. Specifically, the first cathode region 910 can be connected to the first VSS signal terminal via a first VSS signal line 22. The first VSS signal terminal has a first voltage U1, and the first cathode region 910 covers the first pixel region 111. The second cathode region 920 is connected to a second VSS signal terminal. Specifically, the second cathode region 920 can be connected to the second VSS signal terminal via a second VSS signal line 23. The second VSS signal terminal has a second voltage U2, and the second cathode region 920 covers the second pixel region 112 and the third pixel region 113. That is, the first cathode region 910 provides a first VSS signal terminal voltage U1 to the cathode of the light emitting structure layer 810 in the first pixel region 111, and the second cathode region 920 provides a second VSS signal terminal voltage U2 to the cathode of the light emitting structure layer 810 in the second pixel region 112 and the third pixel region 113. The first VSS signal terminal voltage U1 and the second VSS signal terminal voltage U2 can be independently controlled.

[0102] Take, for example, a 7T1C pixel circuit, with the first color being blue, the second color being red, and the third color being green. In related art, the voltage ΔU between the VDD signal terminal and the VSS signal terminal is fixed. When the first pixel region 111, the second pixel region 112, and the third pixel region 113 reach the same brightness, the saturation region margin voltage of the first pixel region 111 is approximately 10%-15% of ΔU, the saturation region margin voltage of the second pixel region 112 is approximately 17%-23% of ΔU, and the saturation region margin voltage of the third pixel region 113 is approximately 25%-30% of ΔU. The present application allows for independent regulation of the voltage U1 of the first VSS signal terminal and the voltage U2 of the second VSS signal terminal. By regulating the voltage U2 of the second VSS signal terminal, the saturation region margin voltages of the second pixel region 112 and the third pixel region 113 can be reduced. The pixel circuit operates in the saturation region, so the operating current of the second pixel region 112 and the third pixel region 113 remains unchanged. According to the formula power consumption (P) = voltage (U) * current (I), reducing the saturation region margin voltage of the second pixel region 112 and the third pixel region 113 will reduce the power consumption of the display panel.

[0103] Optionally, the display panel further includes an auxiliary VSS layer 310. The auxiliary VSS layer 310 can be provided on the same layer as any layer between the anode layer 800 and the driving structure layer 200. For example, the auxiliary VSS layer 310 can be provided on the same layer as the first source / drain metal layer 300, the auxiliary VSS layer 310 can also be provided on the same layer as the second source / drain metal layer 500, or the auxiliary VSS layer 310 can also be provided on the same layer as the second source / drain metal layer 500, etc. The auxiliary VSS layer 310 can be provided between any two adjacent layers between the anode layer 800 and the driving structure layer 200. For example, the auxiliary VSS layer 310 can be provided between the first source / drain metal layer 300 and the first planarizing layer 400, the auxiliary VSS layer 310 can also be provided between the second source / drain metal layer 500 and the first planarizing layer 400, or the auxiliary VSS layer 310 can also be provided between the second source / drain metal layer 500 and the second planarizing layer 600, etc.

[0104] As shown in Figures 5 and 6, the auxiliary VSS layer 310 optionally includes a first auxiliary VSS signal line 311. The first auxiliary VSS signal line 311 is connected to the first VSS signal terminal. Specifically, the first auxiliary VSS signal line 311 can be connected to the first VSS signal terminal through the first VSS signal line 22. The first auxiliary VSS signal line 311 is connected to the first cathode area 910. Optionally, the non-display area 20 includes a plurality of first vias 21, and the first cathode area 910 is connected to the first auxiliary VSS signal line 311 through the first vias 21. Specifically, the first vias 21 penetrate the pixel defining layer 700, so that the first cathode area 910 is connected to the conductive structure 820 located in the anode layer 800. The conductive structure 820 is connected to the first auxiliary VSS signal line 311 through the third via 610, thereby achieving the connection between the first cathode area 910 and the first auxiliary VSS signal line 311. Optionally, the non-pixel region 12 in the display region 10 includes a plurality of second vias 121, through which the first cathode region 910 is connected to the first auxiliary VSS signal line 311. Specifically, the second vias 121 penetrate the pixel defining layer 700, connecting the first cathode region 910 to the conductive structure 820 located in the anode layer 800. The conductive structure 820 is connected to the first auxiliary VSS signal line 311 via the third via 610, thereby connecting the first cathode region 910 to the first auxiliary VSS signal line 311. The first auxiliary VSS signal line 311 can effectively reduce the load on the first cathode region 910.

[0105] As shown in Figures 8 and 9, the auxiliary VSS layer 310 optionally includes a second auxiliary VSS signal line 312. The second auxiliary VSS signal line 312 is connected to the second VSS signal terminal. Specifically, the second auxiliary VSS signal line 312 can be connected to the second VSS signal terminal via the second VSS signal line 23. The second auxiliary VSS signal line 312 is connected to the second cathode region 920. Optionally, the non-display area 20 includes a plurality of first vias 21, and the second cathode region 920 is connected to the second auxiliary VSS signal line 312 via the first vias 21. Specifically, the first vias 21 penetrate the pixel defining layer 700, so that the second cathode region 920 is connected to the conductive structure 820 located in the anode layer 800. The conductive structure 820 is connected to the second auxiliary VSS signal line 312 via the third via 610, thereby achieving the connection between the second cathode region 920 and the second auxiliary VSS signal line 312. Optionally, the non-pixel region 12 in the display region 10 includes a plurality of second vias 121, through which the second cathode region 920 is connected to the second auxiliary VSS signal line 312. Specifically, the second vias 121 penetrate the pixel defining layer 700, connecting the second cathode region 920 to the conductive structure 820 located in the anode layer 800. The conductive structure 820 is connected to the second auxiliary VSS signal line 312 via the third via 610, thereby connecting the second cathode region 920 to the second auxiliary VSS signal line 312. The second auxiliary VSS signal line 312 can effectively reduce the load on the second cathode region 920.

[0106] As shown in Figures 5, 6, 8, 9, 11, and 12, in an optional embodiment, the anode layer 800 is disposed on a side of the second planar layer 600 away from the second source / drain metal layer 500. The light-emitting structure layer 810 is disposed on a side of the anode layer 800 away from the second planar layer 600. The cathode layer 900 is disposed on a side of the light-emitting structure layer 810 away from the anode layer 800. The cathode layer 900 includes a first cathode region 910, a second cathode region 920, and a third cathode region 930. The first cathode region 910 is connected to a first VSS signal terminal. Specifically, the first cathode region 910 can be connected to the first VSS signal terminal via a first VSS signal line 22. The first VSS signal terminal has a first voltage U1, and the first cathode region 910 covers the first pixel region 111. The second cathode region 920 is connected to a second VSS signal terminal. Specifically, the second cathode region 920 can be connected to the second VSS signal terminal via a second VSS signal line 23. The second VSS signal terminal has a second voltage U2, and the second cathode region 920 covers the second pixel region 112. The third cathode region 930 is connected to the third VSS signal terminal. Specifically, the third cathode region 930 can be connected to the third VSS signal terminal via the third VSS signal line 24. The third VSS signal terminal has a third voltage U3, and the third cathode region 930 covers the third pixel region 113. That is, the first cathode region 910 provides the voltage U1 of the first VSS signal terminal to the cathode of the light-emitting structure layer 810 of the first pixel region 111, and the second cathode region 920 provides the voltage U2 of the second VSS signal terminal to the cathode of the light-emitting structure layer 810 of the second pixel region 112. The third cathode region 930 provides the voltage U3 of the third VSS signal terminal to the cathode of the light-emitting structure layer 810 of the third pixel region 113. The voltage U1 of the first VSS signal terminal, the voltage U2 of the second VSS signal terminal, and the voltage U3 of the third VSS signal terminal can be independently controlled.

[0107] Take, for example, a 7T1C pixel circuit, with the first color being blue, the second color being red, and the third color being green. In related art, the voltage across the VDD signal terminal and the VSS signal terminal, ΔU, is fixed. When the first pixel region 111, the second pixel region 112, and the third pixel region 113 reach the same brightness, the saturation region margin voltage of the first pixel region 111 is approximately 10%-15% of ΔU, the saturation region margin voltage of the second pixel region 112 is approximately 17%-23% of ΔU, and the saturation region margin voltage of the third pixel region 113 is approximately 25%-30% of ΔU. The present application can independently adjust the voltage U1 of the first VSS signal terminal, the voltage U2 of the second VSS signal terminal, and the voltage U3 of the third VSS signal terminal. By regulating the voltage U2 at the second VSS signal terminal and the voltage U3 at the third VSS signal terminal, the saturation region margin voltages of the second pixel region 112 and the third pixel region 113 can be reduced to the same value as the saturation region margin voltage of the first pixel region 111, which is approximately 10%-15% of ΔU. Furthermore, since the pixel circuit operates in the saturation region, the operating currents of the second pixel region 112 and the third pixel region 113 remain unchanged. As can be seen from the equation power consumption (P) = voltage (U) * current (I), reducing the saturation region margin voltages of the second pixel region 112 and the third pixel region 113 reduces the power consumption of the display panel, ultimately reducing power consumption by 5%-7%.

[0108] Optionally, the display panel further includes an auxiliary VSS layer 310. The auxiliary VSS layer 310 can be provided on the same layer as any layer between the anode layer 800 and the driving structure layer 200. For example, the auxiliary VSS layer 310 can be provided on the same layer as the first source / drain metal layer 300, the auxiliary VSS layer 310 can also be provided on the same layer as the second source / drain metal layer 500, or the auxiliary VSS layer 310 can also be provided on the same layer as the second source / drain metal layer 500, etc. The auxiliary VSS layer 310 can be provided between any two adjacent layers between the anode layer 800 and the driving structure layer 200. For example, the auxiliary VSS layer 310 can be provided between the first source / drain metal layer 300 and the first planarizing layer 400, the auxiliary VSS layer 310 can also be provided between the second source / drain metal layer 500 and the first planarizing layer 400, or the auxiliary VSS layer 310 can also be provided between the second source / drain metal layer 500 and the second planarizing layer 600, etc.

[0109] As shown in Figures 5 and 6, the auxiliary VSS layer 310 optionally includes a first auxiliary VSS signal line 311. The first auxiliary VSS signal line 311 is connected to the first VSS signal terminal. Specifically, the first auxiliary VSS signal line 311 can be connected to the first VSS signal terminal through the first VSS signal line 22. The first auxiliary VSS signal line 311 is connected to the first cathode area 910. Optionally, the non-display area 20 includes a plurality of first vias 21, and the first cathode area 910 is connected to the first auxiliary VSS signal line 311 through the first vias 21. Specifically, the first vias 21 penetrate the pixel defining layer 700, so that the first cathode area 910 is connected to the conductive structure 820 located in the anode layer 800. The conductive structure 820 is connected to the first auxiliary VSS signal line 311 through the third via 610, thereby achieving the connection between the first cathode area 910 and the first auxiliary VSS signal line 311. Optionally, the non-pixel region 12 in the display region 10 includes a plurality of second vias 121, through which the first cathode region 910 is connected to the first auxiliary VSS signal line 311. Specifically, the second vias 121 penetrate the pixel defining layer 700, connecting the first cathode region 910 to the conductive structure 820 located in the anode layer 800. The conductive structure 820 is connected to the first auxiliary VSS signal line 311 via the third via 610, thereby connecting the first cathode region 910 to the first auxiliary VSS signal line 311. The first auxiliary VSS signal line 311 can effectively reduce the load on the first cathode region 910.

[0110] As shown in Figures 8 and 9, the auxiliary VSS layer 310 optionally includes a second auxiliary VSS signal line 312. The second auxiliary VSS signal line 312 is connected to the second VSS signal terminal. Specifically, the second auxiliary VSS signal line 312 can be connected to the second VSS signal terminal via the second VSS signal line 23. The second auxiliary VSS signal line 312 is connected to the second cathode region 920. Optionally, the non-display area 20 includes a plurality of first vias 21, and the second cathode region 920 is connected to the second auxiliary VSS signal line 312 via the first vias 21. Specifically, the first vias 21 penetrate the pixel defining layer 700, so that the second cathode region 920 is connected to the conductive structure 820 located in the anode layer 800. The conductive structure 820 is connected to the second auxiliary VSS signal line 312 via the third via 610, thereby achieving the connection between the second cathode region 920 and the second auxiliary VSS signal line 312. Optionally, the non-pixel region 12 in the display region 10 includes a plurality of second vias 121, through which the second cathode region 920 is connected to the second auxiliary VSS signal line 312. Specifically, the second vias 121 penetrate the pixel defining layer 700, connecting the second cathode region 920 to the conductive structure 820 located in the anode layer 800. The conductive structure 820 is connected to the second auxiliary VSS signal line 312 via the third via 610, thereby connecting the second cathode region 920 to the second auxiliary VSS signal line 312. The second auxiliary VSS signal line 312 can effectively reduce the load on the second cathode region 920.

[0111] As shown in Figures 11 and 12, the auxiliary VSS layer 310 optionally includes a third auxiliary VSS signal line 313. The third auxiliary VSS signal line 313 is connected to the third VSS signal terminal. Specifically, the third auxiliary VSS signal line 313 can be connected to the third VSS signal terminal via the third VSS signal line 24. The third auxiliary VSS signal line 313 is connected to the third cathode region 930. Optionally, the non-display area 20 includes a plurality of first vias 21, and the third cathode region 930 is connected to the third auxiliary VSS signal line 313 via the first vias 21. Specifically, the first vias 21 penetrate the pixel defining layer 700, connecting the third cathode region 930 to the conductive structure 820 located in the anode layer 800. The conductive structure 820 is connected to the third auxiliary VSS signal line 313 via the third via 610, thereby connecting the third cathode region 930 to the third auxiliary VSS signal line 313. Optionally, the non-pixel region 12 in the display area 10 includes a plurality of second vias 121, and the third cathode region 930 is connected to the third auxiliary VSS signal line 313 via the second vias 121. Specifically, the second vias 121 penetrate the pixel defining layer 700, connecting the third cathode region 930 to the conductive structure 820 located in the anode layer 800. The conductive structure 820 is connected to the third auxiliary VSS signal line 313 via the third via 610, thereby connecting the third cathode region 930 to the third auxiliary VSS signal line 313. The third auxiliary VSS signal line 313 can effectively reduce the load on the third cathode region 930.

[0112] As shown in Figures 7 and 10, in an optional embodiment, a cathode layer 900 is disposed on a side of the second planar layer 600 away from the second source / drain metal layer 500. A light-emitting structure layer 810 is disposed on a side of the cathode layer 900 away from the second planar layer 600. An anode layer 800 is disposed on a side of the light-emitting structure layer 810 away from the cathode layer 900. The cathode layer 900 includes a first cathode region 910 and a second cathode region 920. The first cathode region 910 is connected to a first VSS signal terminal. Specifically, the first cathode region 910 can be connected to the first VSS signal terminal via a first VSS signal line 22. The first VSS signal terminal has a first voltage U1, and the first cathode region 910 covers the first pixel region 111. The second cathode region 920 is connected to a second VSS signal terminal. Specifically, the second cathode region 920 can be connected to the second VSS signal terminal via a second VSS signal line 23. The second VSS signal terminal has a second voltage U2, and the second cathode region 920 covers the second pixel region 112 and the third pixel region 113. That is, the first cathode region 910 provides a first VSS signal terminal voltage U1 to the cathode of the light emitting structure layer 810 in the first pixel region 111, and the second cathode region 920 provides a second VSS signal terminal voltage U2 to the cathode of the light emitting structure layer 810 in the second pixel region 112 and the third pixel region 113. The first VSS signal terminal voltage U1 and the second VSS signal terminal voltage U2 can be independently controlled.

[0113] Optionally, the display panel further includes an auxiliary VSS layer 310. The auxiliary VSS layer 310 can be provided on the same layer as any layer between the anode layer 800 and the driving structure layer 200. For example, the auxiliary VSS layer 310 can be provided on the same layer as the first source / drain metal layer 300, the auxiliary VSS layer 310 can also be provided on the same layer as the second source / drain metal layer 500, or the auxiliary VSS layer 310 can also be provided on the same layer as the second source / drain metal layer 500, etc. The auxiliary VSS layer 310 can be provided between any two adjacent layers between the anode layer 800 and the driving structure layer 200. For example, the auxiliary VSS layer 310 can be provided between the first source / drain metal layer 300 and the first planarizing layer 400, the auxiliary VSS layer 310 can also be provided between the second source / drain metal layer 500 and the first planarizing layer 400, or the auxiliary VSS layer 310 can also be provided between the second source / drain metal layer 500 and the second planarizing layer 600, etc.

[0114] As shown in Figure 7, the auxiliary VSS layer 310 optionally includes a first auxiliary VSS signal line 311. The first auxiliary VSS signal line 311 is connected to the first VSS signal terminal. Specifically, the first auxiliary VSS signal line 311 can be connected to the first VSS signal terminal through the first VSS signal line 22. The first auxiliary VSS signal line 311 is connected to the first cathode region 910. Specifically, the first cathode region 910 is connected to the first auxiliary VSS signal line 311 through the third via 610, and then the first auxiliary VSS signal line 311 is connected to the first VSS signal terminal through the driving structure layer 200. The first auxiliary VSS signal line 311 can effectively reduce the load of the first cathode region 910.

[0115] As shown in FIG10 , the auxiliary VSS layer 310 optionally includes a second auxiliary VSS signal line 312. The second auxiliary VSS signal line 312 is connected to the second VSS signal terminal. Specifically, the second auxiliary VSS signal line 312 can be connected to the second VSS signal terminal via the second VSS signal line 23. The second auxiliary VSS signal line 312 is connected to the second cathode region 920. Specifically, the second cathode region 920 is connected to the second auxiliary VSS signal line 312 via the third via 610, and then the second auxiliary VSS signal line 312 is connected to the second VSS signal terminal via the driving structure layer 200. The second auxiliary VSS signal line 312 can effectively reduce the load on the second cathode region 920.

[0116] As shown in Figures 7, 10, and 13, in an optional embodiment, a cathode layer 900 is disposed on a side of the second planar layer 600 away from the second source / drain metal layer 500. A light-emitting structure layer 810 is disposed on a side of the cathode layer 900 away from the second planar layer 600. An anode layer 800 is disposed on a side of the light-emitting structure layer 810 away from the cathode layer 900. The cathode layer 900 includes a first cathode region 910, a second cathode region 920, and a third cathode region 930. The first cathode region 910 is connected to a first VSS signal terminal. Specifically, the first cathode region 910 can be connected to the first VSS signal terminal via a first VSS signal line 22. The first VSS signal terminal has a first voltage U1, and the first cathode region 910 covers the first pixel region 111. The second cathode region 920 is connected to a second VSS signal terminal. Specifically, the second cathode region 920 can be connected to the second VSS signal terminal via a second VSS signal line 23. The second VSS signal terminal has a second voltage U2, and the second cathode region 920 covers the second pixel region 112. The third cathode region 930 is connected to the third VSS signal terminal. Specifically, the third cathode region 930 can be connected to the third VSS signal terminal through the third VSS signal line 24. The third VSS signal terminal has a third voltage U3, and the third cathode region 930 covers the third pixel region 113. That is, the first cathode region 910 provides the voltage U1 of the first VSS signal terminal to the cathode of the light-emitting structure layer 810 of the first pixel region 111, and the second cathode region 920 provides the voltage U2 of the second VSS signal terminal to the cathode of the light-emitting structure layer 810 of the second pixel region 112. The third cathode region 930 provides the voltage U3 of the third VSS signal terminal to the cathode of the light-emitting structure layer 810 of the third pixel region 113. Among them, the voltage U1 of the first VSS signal terminal, the voltage U2 of the second VSS signal terminal, and the voltage U3 of the third VSS signal terminal can be regulated independently of each other.

[0117] Optionally, the display panel further includes an auxiliary VSS layer 310. The auxiliary VSS layer 310 can be provided on the same layer as any layer between the anode layer 800 and the driving structure layer 200. For example, the auxiliary VSS layer 310 can be provided on the same layer as the first source / drain metal layer 300, the auxiliary VSS layer 310 can also be provided on the same layer as the second source / drain metal layer 500, or the auxiliary VSS layer 310 can also be provided on the same layer as the second source / drain metal layer 500, etc. The auxiliary VSS layer 310 can be provided between any two adjacent layers between the anode layer 800 and the driving structure layer 200. For example, the auxiliary VSS layer 310 can be provided between the first source / drain metal layer 300 and the first planarizing layer 400, the auxiliary VSS layer 310 can also be provided between the second source / drain metal layer 500 and the first planarizing layer 400, or the auxiliary VSS layer 310 can also be provided between the second source / drain metal layer 500 and the second planarizing layer 600, etc.

[0118] As shown in Figure 7, the auxiliary VSS layer 310 optionally includes a first auxiliary VSS signal line 311. The first auxiliary VSS signal line 311 is connected to the first VSS signal terminal. Specifically, the first auxiliary VSS signal line 311 can be connected to the first VSS signal terminal through the first VSS signal line 22. The first auxiliary VSS signal line 311 is connected to the first cathode region 910. Specifically, the first cathode region 910 is connected to the first auxiliary VSS signal line 311 through the third via 610, and then the first auxiliary VSS signal line 311 is connected to the first VSS signal terminal through the driving structure layer 200. The first auxiliary VSS signal line 311 can effectively reduce the load of the first cathode region 910.

[0119] As shown in FIG10 , the auxiliary VSS layer 310 optionally includes a second auxiliary VSS signal line 312. The second auxiliary VSS signal line 312 is connected to the second VSS signal terminal. Specifically, the second auxiliary VSS signal line 312 can be connected to the second VSS signal terminal via the second VSS signal line 23. The second auxiliary VSS signal line 312 is connected to the second cathode region 920. Specifically, the second cathode region 920 is connected to the second auxiliary VSS signal line 312 via the third via 610, and then the second auxiliary VSS signal line 312 is connected to the second VSS signal terminal via the driving structure layer 200. The second auxiliary VSS signal line 312 can effectively reduce the load on the second cathode region 920.

[0120] As shown in FIG13 , the auxiliary VSS layer 310 optionally includes a third auxiliary VSS signal line 313. The third auxiliary VSS signal line 313 is connected to the third VSS signal terminal. Specifically, the third auxiliary VSS signal line 313 can be connected to the third VSS signal terminal via the third VSS signal line 24. The third auxiliary VSS signal line 313 is connected to the third cathode region 930. Specifically, the third cathode region 930 is connected to the third auxiliary VSS signal line 313 via the third via 610, thereby achieving a connection between the third cathode region 930 and the third auxiliary VSS signal line 313. The third auxiliary VSS signal line 313 is then connected to the third VSS signal terminal via the driving structure layer 200. The third auxiliary VSS signal line 313 can effectively reduce the load on the third cathode region 930.

[0121] The present application also discloses a method for manufacturing a display panel, which includes manufacturing a cathode layer 900 .

[0122] Fabricating the cathode layer 900 includes:

[0123] A first cathode region 910 is formed. The first cathode region 910 is connected to a first VSS signal terminal. The first VSS signal terminal has a first voltage U17. The first cathode region 910 covers the first pixel region 111.

[0124] A second cathode region 920 is fabricated. The second cathode region 920 is connected to a second VSS signal terminal having a second voltage U2. The second cathode region 920 covers the second pixel region 112 and / or the third pixel region 113. Optionally, fabricating the cathode layer further includes forming a first cathode region 910 and a second cathode region 920 on the cathode layer 900 using a fine metal mask evaporation technique. Optionally, fabricating the cathode layer 900 further includes pre-setting isolation columns in the cathode layer 900, and then filling the gaps between the isolation columns to form the first cathode region 910 and the second cathode region 920.

[0125] The cathode layer of the present invention includes a first cathode area and a second cathode area. The first cathode area is connected to the first VSS signal end and the first pixel area, and the second cathode area is connected to the second VSS signal end and the second pixel area and / or the third pixel area, so that the cross-voltage of each pixel area can be controlled individually, reducing the energy consumption of the display panel.

[0126] Other embodiments of the present invention will readily occur to those skilled in the art upon consideration of the present invention and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present invention being indicated by the following claims.

[0127] It should be understood that the present description is not limited to the exact structure that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.

[0128] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

Claims

1. A display panel, characterized in that, Comprising: A display area, the display area including a plurality of pixel areas; The plurality of pixel areas include: A first pixel area, the first pixel area including a first color light-emitting unit; A second pixel area, the second pixel area including a second color light-emitting unit; A third pixel area, the third pixel area including a third color light-emitting unit; A cathode layer, the cathode layer including: A first cathode area, the first cathode area being connected to a first VSS signal terminal, the first VSS signal terminal having a first voltage, and the first cathode area covering the first pixel area; A second cathode area, the second cathode area being connected to a second VSS signal terminal, the second VSS signal terminal having a second voltage, and the second cathode area covering the second pixel area and / or the third pixel area.

2. The display panel according to claim 1, wherein The second cathode area covers the second pixel area; The cathode layer further includes a third cathode area, the third cathode area being connected to a third VSS signal terminal, the third VSS signal terminal having a third voltage, and the third cathode area covering the third pixel area.

3. The display panel according to claim 1 or 2, characterized in that, The first color is one of green, red, or blue; the second color is another of green, red, or blue; and the third color is the last of green, red, or blue.

4. The display panel according to claim 3, wherein The display panel further includes an auxiliary VSS layer; the auxiliary VSS layer includes a first auxiliary VSS signal line; the first auxiliary VSS signal line is connected to the first VSS signal terminal; and the first auxiliary VSS signal line is connected to the first cathode area.

5. The display panel according to claim 4, wherein The auxiliary VSS layer further includes a second auxiliary VSS signal line; the second auxiliary VSS signal line is connected to the second VSS signal terminal; and the second auxiliary VSS signal line is connected to the second cathode area.

6. The display panel according to claim 5, wherein The auxiliary VSS layer further includes a third auxiliary VSS signal line; the third auxiliary VSS signal line is connected to the third VSS signal terminal; and the third auxiliary VSS signal line is connected to the third cathode area.

7. The display panel according to claim 6, wherein The display panel further includes: A substrate; A driving structure layer, the driving structure layer being disposed on one side of the substrate; A first source-drain metal layer, the first source-drain metal layer being disposed on the side of the driving structure layer away from the substrate; A first planarization layer; the first planarization layer being disposed on the side of the first source-drain metal layer away from the driving structure layer; A second source-drain metal layer, the second source-drain metal layer being disposed on the side of the first planarization layer away from the first source-drain metal layer; A second planarization layer, the second planarization layer being disposed on the side of the second source-drain metal layer away from the first planarization layer; An anode layer, the anode layer being disposed on the side of the second planarization layer away from the second source-drain metal layer; A light-emitting structure layer, the light-emitting structure layer including the light-emitting unit, the light-emitting structure layer being disposed on the side of the anode layer away from the second planarization layer; The cathode layer is disposed on the side of the light-emitting structure layer away from the anode layer; A pixel definition layer, the pixel definition layer being disposed on the side of the second planarization layer away from the second source-drain metal layer.

8. The display panel according to claim 7, wherein The auxiliary VSS layer is provided on any layer between the anode layer and the driving structure layer, or the auxiliary VSS layer is provided between any two adjacent layers between the anode layer and the driving structure layer.

9. The display panel according to claim 8, wherein The display panel further includes: A non-display area, the non-display area includes a plurality of first vias, the first cathode area is connected to the first auxiliary VSS signal line through the first via, the second cathode area is connected to the second auxiliary VSS signal line through the first via, and the third cathode area is connected to the third auxiliary VSS signal line through the first via.

10. The display panel according to claim 8, wherein, The display area includes a plurality of second vias, the first cathode area is connected to the first auxiliary VSS signal line through the second via, the second cathode area is connected to the second auxiliary VSS signal line through the second via, and the third cathode area is connected to the third auxiliary VSS signal line through the second via.

11. The display panel according to claim 10, wherein, The positive projection of the second via on the substrate has no overlapping area with the positive projection of the pixel area on the substrate.

12. The display panel according to claim 6, wherein The display panel further includes: A substrate; A driving structure layer, the driving structure layer is provided on one side of the substrate; A first source-drain metal layer, the first source-drain metal layer is provided on the side of the driving structure layer away from the substrate; A first planarization layer; the first planarization layer is provided on the side of the first source-drain metal layer away from the driving structure layer; A second source-drain metal layer, the second source-drain metal layer is provided on the side of the first planarization layer away from the first source-drain metal layer; A second planarization layer, the second planarization layer is provided on the side of the second source-drain metal layer away from the first planarization layer; The cathode layer is provided on the side of the second planarization layer away from the second source-drain metal layer; A light-emitting structure layer, the light-emitting structure layer includes the light-emitting unit, the light-emitting structure layer is provided on the side of the cathode layer away from the second planarization layer; An anode layer, the anode layer is provided on the side of the light-emitting structure layer away from the cathode layer; A pixel defining layer, the pixel defining layer is provided on the side of the second planarization layer away from the second source-drain metal layer.

13. The display panel according to claim 11, wherein The auxiliary VSS layer is provided on any layer between the cathode layer and the driving structure layer.

14. A manufacturing method of a display panel, characterized in that, The display panel includes: A display area, the display area includes a plurality of pixel areas; The plurality of pixel areas include: A first pixel area, the first pixel area includes a first-color light-emitting unit; A second pixel area, the second pixel area includes a second-color light-emitting unit; A third pixel area, the third pixel area includes a third-color light-emitting unit; The method includes fabricating a cathode layer, and the fabricating the cathode layer includes: Fabricating a first cathode area, the first cathode area is connected to a first VSS signal terminal, the first VSS signal terminal has a first voltage, and the first cathode area covers the first pixel area; Fabricating a second cathode area, the second cathode area is connected to a second VSS signal terminal, the second VSS signal terminal has a second voltage, and the second cathode area covers the second pixel area and / or the third pixel area.

15. The manufacturing method of the display panel according to claim 14, characterized in that, The fabricating the cathode layer includes: The first cathode region and the second cathode region are formed in the cathode layer by a fine metal mask evaporation technique.

16. The manufacturing method of the display panel according to claim 14, wherein The manufacturing of the cathode layer includes: Presetting isolation columns in the cathode layer and then filling them to form the first cathode region and the second cathode region.

17. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1-13.

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