Wafer testing device

Abstract

The invention provides a wafer testing device which does not increase leakage current and can perform inspection at high temperature. The wafer testing apparatus according to the present disclosure includes an inspection table on which a wafer having a plurality of semiconductor chips is mounted, and a probe card for inspecting the plurality of semiconductor chips, the inspection table having a temperature adjustment mechanism capable of adjusting the temperature of a portion of the wafer, the temperature adjustment mechanism including a plurality of first heaters that are separated from each other and are independently controlled.

Description

Technical Field

[0001] The present disclosure relates to a wafer testing device for testing semiconductor devices in a wafer state. Background Art

[0002] When testing whether semiconductor chips meet product specifications, accelerated tests are often performed by increasing the temperature of the semiconductor chips to shorten the test time. For example, power semiconductor devices are often tested at 25°C to 200°C.

[0003] Patent Document 1 discloses a semiconductor device inspection apparatus that can locally adjust the wafer temperature by irradiating light onto a semiconductor device in a wafer state to perform an accelerated test. Prior art literature Patent Literature

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 2022-030909 Summary of the Invention Technical problem to be solved by the invention

[0005] Patent Document 1 describes increasing the temperature of a portion of a semiconductor device in wafer form by irradiating the desired temperature region with light. However, using light irradiation for characteristic testing of power semiconductor devices not only raises leakage current due to light energy but also hinders the ability to achieve temperatures as high as 200°C.

[0006] The present disclosure is proposed to solve the above-mentioned problem, and its object is to provide a wafer testing device that does not increase leakage current and can perform inspections at high temperatures. Technical means for solving technical problems

[0007] The wafer testing device disclosed herein includes: an inspection table carrying a wafer having a plurality of semiconductor chips, and a probe card for inspecting the plurality of semiconductor chips, wherein the inspection table has a temperature regulating mechanism capable of regulating the temperature of a portion of the wafer, and the temperature regulating mechanism includes a plurality of first heaters that are separated from each other and independently controlled. Effects of the Invention

[0008] The wafer testing apparatus disclosed herein can centrally heat the semiconductor chips under test using multiple first heaters. This eliminates the increased leakage current caused by light energy, as occurs with temperature increase through light irradiation, and allows for rapid temperature increase to a high temperature of 200°C, thereby shortening inspection time. Furthermore, by centrally heating the semiconductor chips under test, prolonged high temperatures are avoided, preventing Ni from precipitating from the electrodes of the stacked structure and enabling accelerated testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a plan view illustrating the structure of an inspection table of the wafer testing device according to the first embodiment of the present disclosure. Figure 2 It is a cross-sectional view illustrating the structure of an inspection table of the wafer testing device according to the first embodiment of the present disclosure. Figure 3 It is a top view showing the inspection table before a wafer is mounted. Figure 4 This is a plan view schematically showing a state in which the semiconductor chips to be measured are intensively heated in the inspection stage of the wafer testing apparatus according to the first embodiment of the present disclosure. Figure 5 This is a cross-sectional view schematically showing a state in which the semiconductor chips to be measured are intensively heated in the inspection stage of the wafer testing apparatus according to the first embodiment of the present disclosure. Figure 6 This is a plan view schematically showing the function of a temperature adjustment mechanism in an inspection stage of a wafer testing device according to a second embodiment of the present disclosure. Figure 7 This is a plan view schematically showing the function of a temperature adjustment mechanism in an inspection stage of a wafer testing device according to a second embodiment of the present disclosure. Figure 8 It is a cross-sectional view illustrating the structure of a wafer testing device according to a third embodiment of the present disclosure. Figure 9 It is a cross-sectional view illustrating the structure of a wafer testing device according to a third embodiment of the present disclosure. Figure 10 It is a cross-sectional view illustrating the structure of a wafer testing device according to a fourth embodiment of the present disclosure. Figure 11 This is a bottom view of the probe card of the wafer testing device according to the fourth embodiment of the present disclosure as viewed from the bottom surface side. Figure 12 It is a cross-sectional view illustrating the structure of a wafer testing device according to a fifth embodiment of the present disclosure. Figure 13It is a cross-sectional view illustrating the structure of a wafer testing device according to a fifth embodiment of the present disclosure. Figure 14 This is a bottom view of the probe card of the wafer testing device according to the fifth embodiment of the present disclosure as viewed from the bottom surface side. Figure 15 It is a plan view illustrating the structure of a wafer testing device according to a sixth embodiment of the present disclosure. Figure 16 This is a cross-sectional view illustrating the structure of a wafer testing device according to a sixth embodiment of the present disclosure. Figure 17 This is a diagram showing a wafer test using a wafer testing device according to Embodiment 6 of the present disclosure. Figure 18 This is a diagram showing a wafer test using a wafer testing device according to Embodiment 6 of the present disclosure. DETAILED DESCRIPTION

[0010] <Preface> The drawings are schematic. The sizes and positions of the images shown in different drawings are not necessarily accurate and may be modified as appropriate. In the following description, identical components are denoted by the same reference numerals, and their names and functions are assumed to be the same. Therefore, detailed descriptions of these components may be omitted.

[0011] In addition, in the following description, terms such as "upper", "lower", "side", "surface" and "back" are sometimes used to indicate specific positions and directions, but these terms are used to facilitate understanding of the contents of the implementation method and have nothing to do with the direction during actual implementation.

[0012] <Implementation Method 1> use Figures 1 to 5 A wafer testing device according to the first embodiment of the present disclosure will be described.

[0013] Figure 1 1 is a plan view illustrating the structure of the inspection table 2 of the wafer testing apparatus 100 according to the first embodiment. Figure 2 yes Figure 1 Cross-sectional view along line AA.

[0014] like Figure 1 As shown in FIG. 1 , a wafer 1 on which a plurality of semiconductor chips 3 are prepared is placed on an inspection table 2. Figure 2 As shown, a temperature control mechanism 11 is provided inside the inspection table 2. The temperature control mechanism 11 is composed of, for example, a plurality of heaters 11a (first heaters), which are separated from each other and independently controlled so as to be able to heat only an arbitrarily selected portion rather than the entire wafer 1. Figure 1 and Figure 2 In the figure, a probe card having probes for testing the semiconductor chip 3 is omitted from the figure, but a conventional cantilever type probe card or vertical type probe card can be used as the probe card.

[0015] Figure 3 FIG. 2 is a top view showing the inspection table 2 and the wafer 1 before the wafer 1 is mounted. In the inspection table 2 on the lower side, the area where the wafer 1 is mounted is omitted for convenience. Figure 3 As shown, the heating surfaces of the plurality of heaters 11a are arranged facing the back surface of the wafer 1, so that each heater 11a can be turned on and off independently. As a result, by focusing on heating the semiconductor chip 3 to be measured rather than the entire wafer 1, the time it takes for the semiconductor chip 3 to reach a high temperature can be shortened. Figure 3 2 shows a structure in which the plurality of heaters 11 a are arranged so as to divide a circular area, but the present invention is not limited thereto, and the plurality of heaters 11 a may be provided so as to divide a quadrilateral.

[0016] The heater 11 a is provided inside the inspection table 2 and has no portion in direct contact with the wafer 1 . Therefore, a metal heater such as a nichrome wire heater can be used.

[0017] Figure 4 and Figure 5 1 is a diagram schematically showing a state in which the semiconductor chip 3 to be measured is centrally heated in the inspection station 2 according to the first embodiment. Figure 4 is with Figure 1 The corresponding top view, Figure 5 is with Figure 2 Corresponding cross-sectional view. Figure 4 The region RM indicated by the middle dotted line represents a temperature rising region and is a region including the three semiconductor chips 3 . Figure 5 The shaded area indicates the heating state of the heaters 11a within the region RM. The three heaters 11a generate heat, raising the temperature of the three semiconductor chips 3 thereon. After the three semiconductor chips 3 to be measured are heated and measurement using the probe card is completed, the temperature of the next three semiconductor chips 3 to be measured begins. This operation is repeated to measure all the semiconductor chips 3 included in the wafer 1.

[0018] exist Figure 5 , the number of heaters 11a to be controlled is not limited thereto, as long as at least one heater 11a can be controlled. If fewer heaters 11a are used, the thermal influence on the surrounding semiconductor chips 3 can be reduced.

[0019] Power semiconductor devices are sometimes screened for quality assurance by subjecting the semiconductor chips to higher temperatures than those encountered during actual use, thereby shortening the inspection time. However, prolonged exposure to high temperatures can cause nickel (Ni) to precipitate from the gold (Au) layer on the chip surface, potentially leading to bonding failures during package assembly.

[0020] Specifically, in SiC chips using silicon carbide (SiC) substrates, the electrodes and other components employ a stacked structure consisting of, for example, a titanium (Ti) barrier metal, an aluminum silicon (AlSi) layer, a nickel phosphorus (NiP) layer, and an Au layer stacked on the SiC substrate. However, when the SiC chip is exposed to high temperatures for extended periods, nickel (NiP) may precipitate from the NiP layer onto the surface of the Au layer. If this precipitated Ni oxidizes to form an oxide film, this can cause bonding failures when wire bonding the Au layer, for example.

[0021] In particular, wafer testing requires a longer time for individual chips to remain in a high-temperature state than in chip testing, limiting temperature conditions and increasing inspection time. For example, if a test on a single chip requires 10 seconds, the chip test only requires 10 seconds of high-temperature state due to the temperature rise of the individual chips. However, in wafer testing, the entire wafer heats up, so the time spent in a high-temperature state is 10 times the number of chips on each wafer (seconds). Therefore, if a wafer contains 100 chips, the time spent in a high-temperature state on a single chip in wafer testing is 100 times that of chip testing.

[0022] If the wafer temperature is high, accelerated testing can be performed, thus shortening the test time. However, the higher the temperature, the more likely Ni is to precipitate. Therefore, the high temperature state in wafer testing is longer than that in chip testing. As a result, the temperature of the measurement conditions cannot be increased, and the inspection time is extended.

[0023] On the other hand, in the inspection station 2 of embodiment 1, since the semiconductor chip 3 to be measured is heated centrally, it is possible to implement an accelerated test while preventing Ni precipitation, thereby shortening the inspection time. In particular, SiC chips have many crystal defects and require a large number of screening items, which tends to take longer inspection times. Therefore, high-temperature accelerated tests are effective. Here, high temperature refers to a temperature higher than room temperature (25°C). For example, when the guaranteed temperature of the chip is 150°C, performing a screening test at 150°C can shorten the test time the most. In addition, since the temperature is increased by the heater 11a, the target temperature can be reached in a shorter time.

[0024] <Implementation Method 2> use Figure 6 and Figure 7 A wafer testing device according to a second embodiment of the present disclosure will be described. Figure 6 and Figure 7 This is a plan view schematically showing the function of the temperature adjustment mechanism in the inspection stage 2 of the wafer testing apparatus 200 according to the second embodiment.

[0025] In the inspection stage 2 of the wafer testing apparatus 100 of the first embodiment, the temperature control mechanism 11 is configured with multiple heaters 11a that are separated and independently controlled. This allows heating of only a portion of the wafer 1, thereby concentrating the temperature of the semiconductor chip 3 to be measured. After the temperature of the semiconductor chip 3 to be measured is raised and the measurement by the probe card is completed, the temperature of the next semiconductor chip 3 to be measured is started. By repeating this operation, all semiconductor chips 3 included in the wafer 1 are measured.

[0026] In contrast, in the inspection stage 2 of the wafer testing apparatus 200 of the second embodiment, the inspection order of the semiconductor chips 3 to be inspected is set, and the temperature adjustment mechanism 11 is controlled to adjust the temperature of the portion of the wafer 1 corresponding to the set inspection order.

[0027] For example, in Figure 6 In FIG. 1 , an example of controlling the on / off of the heater 11a is shown, and the temperature of the semiconductor chip 3 to be measured is increased in units of one or more semiconductor chips along the inspection path indicated by the arrows from left to right, from top to bottom, and from right to left. Figure 6 In the example shown in FIG, the inspection paths in the left and right direction arrows are separated by a space of one semiconductor chip 3, and the temperature rise of one inspection path along the arrow direction does not affect the surrounding chips.

[0028] In addition, Figure 7 In FIG. 1 , an example is shown in which the temperature of the semiconductor chip 3 to be measured is increased in units of one or more to control the on / off of the heater 11a along the inspection path indicated by the arrow from the upper left to the lower right. Figure 7 In the example, the four inspection paths indicated by arrows are marked with A to D, which is a mode of heating the semiconductor chip 3 to be measured in the order of inspection paths A, B, C, and D. The order of heating is set to be spaced apart by one inspection path along the direction of the arrow, and the heating of one inspection path along the direction of the arrow will not affect the surrounding chips.

[0029] That is, even if the multiple heaters 11a are separated and controlled independently to locally increase the temperature of the inspection table 2, the inspection table 2 itself is connected, so the chips around the semiconductor chip 3 to be measured will also increase in temperature due to heat conduction. Therefore, there are semiconductor chips 3 that continue to increase in temperature while still affecting the temperature increase of the semiconductor chip 3 to be measured. However, if Figure 6 and Figure 7As shown, by setting the inspection order of the semiconductor chips 3 to be inspected and adjusting the temperature of the portion of the wafer 1 corresponding to the set order, the time during which the semiconductor chips 3 continue to be at a high temperature can be reduced to some extent.

[0030] <Implementation Method 3> use Figure 8 and Figure 9 A wafer testing device according to a third embodiment of the present disclosure will be described. Figure 8 and Figure 9 1 is a cross-sectional view illustrating the structure of a wafer testing apparatus 300 according to a third embodiment.

[0031] exist Figure 8 In FIG. 1 , a probe card 6 is arranged above the wafer 1 mounted on the inspection table 2, and the probe card 6 is a cross-sectional view. Figure 2 The inspection table 2 shown is the same as that shown in the figure, but includes a temperature adjustment mechanism 11 in which a plurality of heaters 11 a are separated from each other and independently controlled.

[0032] The probe card 6 is a probe card having cantilever-type probes 4, but may also be a spring-type probe. A plurality of heater holes 62 for accommodating heaters 5 (second heaters) are provided on the outer wall 61 outside the area where the probes 4 are arranged. The heater holes 62 are arranged to extend in the height direction (vertical direction) from the bottom surface of the outer wall 61, and are internally provided with elastic wiring 63 that is connected to the heater 5 to provide power for heating the heater 5 and suspends the heater 5 from the bottom of the hole. The wiring 63 has elasticity that applies force to the heater 5 in the vertical direction, such as Figure 8 As shown, in a state where the probe card 6 is arranged above the wafer 1 , the heater 5 is suspended on the wiring 63 , and the wiring 63 is in a stretched state.

[0033] Figure 9 This figure shows a state where probes 4 of probe card 6 are in contact with wafer 1 and the end face of heater 5 is also in contact with wafer 1. In this state, a portion of heater 5 is housed within heater hole 62, wiring 63 is compressed between heater 5 and the bottom of the hole, and the end face of heater 5 is firmly pressed against wafer 1 by the repulsive force of wiring 63.

[0034] exist Figure 8 and Figure 9 In the figure, for convenience, only a part of the probe card, that is, the housing portion that accommodates the probes 4, is shown. In fact, the housing portion includes a probe card substrate including wiring, etc., but is omitted from the illustration.

[0035] When the probes 4 of the probe card 6 are in contact with the wafer 1 and the end surface of the heater 5 is pressed against the wafer 1, the heater 5 is energized. Figure 9As shown in FIG. 1 , the temperature of the semiconductor chip 3 to be measured is increased from the upper surface side by the heat generated by the heater 5. In addition, the temperature is increased from the lower surface side of the semiconductor chip 3 by the temperature control mechanism 11 in the inspection table 2. Figure 9 In FIG. 1 , the region where the temperature of the semiconductor chip 3 rises is indicated by hatching.

[0036] Thus, the temperature of the semiconductor chip 3 is increased not only from the bottom surface side but also from the top surface side, thereby shortening the heating time. Raising the temperature of the semiconductor chip 3 means that the heater 5 can also be called a temperature control mechanism.

[0037] Furthermore, by preheating the probe 4 using the heater 5 , the work involved in the preheating can be simplified.

[0038] Preheating the probe 4 is a process that preheats the probe 4 before high-temperature measurement. The probe 4 is typically made of metal, which undergoes thermal expansion. If an unpreheated probe 4 is placed in contact with a high-temperature semiconductor chip 3 during measurement, heat will be transferred to the probe 4 during the characteristic measurement, and thermal expansion could cause the probe 4's needle to become embedded in the semiconductor chip 3.

[0039] In the past, before measuring electrical characteristics, the probe was brought close to a platform heated to a high temperature and preheated for a certain period of time. However, in the chip testing device 300 of embodiment 3, the probe 4 is preheated using the heater 5 provided on the probe card 6, and then the semiconductor chip 3 is heated by using the temperature control mechanism 11 in the inspection table 2, which can simplify the operations associated with preheating.

[0040] The number of heaters 5 to be arranged is not particularly limited, but the more the better from the viewpoint of uniformly increasing the temperature of the semiconductor chip 3 . As an example, 4 to 8 heaters can be arranged.

[0041] <Implementation Method 4> use Figure 10 and Figure 11 A wafer testing device according to a fourth embodiment of the present disclosure will be described. Figure 10 It is a cross-sectional view illustrating the structure of a wafer testing apparatus 400 according to the fourth embodiment, and shows a state in which a probe card 6A is placed on a wafer 1 mounted on an inspection table 2 . Figure 11 This is a bottom view of the probe card 6A as viewed from the bottom surface side. Figure 11 The cross section of line BB in the figure is equivalent to Figure 10 A cross-sectional view of the . Figure 10 In the probe card 6A, Figure 8 The same components of the probe card 6 are denoted by the same reference numerals, and redundant descriptions are omitted.

[0042] Figure 10The probe card 6A shown has a sensor hole 64 for accommodating a temperature sensor 7 such as a resistance temperature measuring element or a thermocouple, in addition to a plurality of heater holes 62 for accommodating heaters 5 on an outer wall 61 outside the region where the probes 4 are arranged.

[0043] As an example of a temperature-measuring resistor, a platinum temperature-measuring resistor can be used, which utilizes the fact that the resistivity of platinum changes with temperature and measures the temperature by measuring the resistivity of platinum.

[0044] The sensor hole 64 is provided to extend in the height direction (vertical direction) from the bottom surface of the outer wall 61, and is provided with a flexible wiring 65 connected to the sensor 7 to detect the output signal of the sensor 7 and suspending the sensor 7 from the bottom of the hole. The wiring 65 has elasticity to apply force to the sensor 7 in the vertical direction, such as Figure 10 As shown, when the probes 4 of the probe card 6A are placed in contact with the wafer 1, the end surface of the sensor 7 also comes into contact with the wafer 1. In this state, a portion of the sensor 7 is accommodated in the sensor hole 64, and the wiring 65 is compressed between the sensor 7 and the bottom of the hole. The end surface of the sensor 7 is firmly pressed against the wafer 1 by the repulsive force of the wiring 65.

[0045] like Figure 11 As shown, sensors 7 are provided at four locations outside the arrangement area of ​​the probes 4. In addition, heaters 5 are provided at four locations in the area where the probes 4 are not arranged. Thus, the probe card 6A includes sensors 7. When inspecting the semiconductor chip 3 to be measured, the sensors 7 are in contact with the semiconductor chip 3, and thus the temperature of the semiconductor chip 3 can be directly measured.

[0046] Conventionally, wafer-level testing often uses the platform temperature as the measured chip temperature, rather than directly measuring the temperature of the chip being tested. However, because the platform temperature exhibits an in-plane temperature distribution, with temperatures at the edges being lower than in the center, monitoring the platform temperature can prevent accurate measurement of the chip temperature.

[0047] However, in the wafer testing apparatus 400 of the fourth embodiment, the temperature of the semiconductor chip 3 can be directly measured and an accurate temperature can be obtained, so that the characteristic values ​​of the semiconductor chip 3 can be temperature-corrected, thereby obtaining the characteristics of the semiconductor chip 3 in more detail.

[0048] Furthermore, by using a temperature measuring resistor, a thermocouple, or the like as the temperature sensor 7 , the temperature sensor 7 can have a relatively simple structure.

[0049] <Implementation Method 5> use Figures 12 to 14 A wafer testing device according to a fifth embodiment of the present disclosure will be described. Figure 12 and Figure 13 is a cross-sectional view illustrating the structure of a wafer testing apparatus 500 according to a fifth embodiment. Figure 14 This is a bottom view of the probe card 6B as viewed from the bottom surface side. Figure 14 The cross section of the CC line in is equivalent to Figure 12 and Figure 13 sectional view of .

[0050] exist Figure 12 , a state where a probe card 6B is arranged above a wafer 1 mounted on an inspection table 2 is shown, and the probe card 6B is a cross-sectional view. Figure 12 In the probe card 6B, Figure 8 The same components of the probe card 6 are denoted by the same reference numerals, and redundant descriptions are omitted.

[0051] Figure 12 The probe card 6B shown is provided with a nozzle 9 of an air blowing device (not shown) for blowing hot air and cold air onto the semiconductor chip 3, in addition to a heater 5 provided on the outer wall 61 outside the area where the probes 4 are arranged. In addition, it also includes a pressurized wall 8 that seals the space between the probe card 6B and the semiconductor chip 3 to be measured. The pressurized wall 8 is provided in a manner that surrounds the outer wall 61 of the probe card 6B and is fixed to the outer wall 61 of the probe card 6B. The pressurized wall 8 can be formed of the same material as the outer wall 61 or a different material. In the case of being formed of the same material as the outer wall 61, it can also form an integral structure with the outer wall 61.

[0052] like Figure 14 As shown, nozzles 9 are provided at four locations outside the area where probes 4 are arranged. Furthermore, heaters 5 are provided at four locations in areas where probes 4 are not arranged. The number of nozzles 9 provided is not particularly limited, but from the perspective of uniformly increasing or decreasing the temperature of semiconductor chip 3, the more nozzles 9 provided, the better. As an example, two to four nozzles may be provided.

[0053] Figure 13 The diagram shows a state where probes 4 of probe card 6B are in contact with wafer 1 and the end face of heater 5 is also in contact with wafer 1. In this state, a portion of heater 5 is housed within heater hole 62, and wiring 63 is compressed between heater 5 and the bottom of the hole. The end face of heater 5 is firmly pressed against wafer 1 by the repulsive force of wiring 63. Furthermore, pressurizing wall 8 is in contact with wafer 1, sealing the space between probe card 6B and semiconductor chip 3 to be measured.

[0054] When the heater 5 is energized in this state, the temperature of the semiconductor chip 3 to be measured is increased from the upper surface side due to the heat generated by the heater 5. In addition, the temperature is increased from the lower surface side of the semiconductor chip 3 by the temperature control mechanism 11 in the inspection table 2. In addition, by operating the air blower to release hot air from the nozzle 9, the temperature of the semiconductor chip 3 can be rapidly increased from the upper surface side.

[0055] As a result, the semiconductor chip 3 is heated not only from the lower surface side but also from the upper surface side, thereby shortening the heating time. Heating the semiconductor chip 3 means that the air blowing device including the nozzle 9 can also be called a temperature regulating mechanism. In this case, the hot air is a temperature higher than the room temperature (25°C) and is set to the temperature when the semiconductor chip 3 of the measurement object is inspected. The gas blown out is not limited to air, and inert gases such as nitrogen, argon, and neon can be used. However, if the Paschen law described later is used, the discharge suppression effect varies depending on the type of gas blown out, so the gas used is set in consideration of this point.

[0056] In addition, by making the temperature of the blown gas cold air, that is, lower than room temperature (25°C), the temperature of the semiconductor chip 3 can be rapidly reduced, the temperature of the semiconductor chip 3 can be controlled, and the time that the semiconductor chip 3 is in a high temperature state can be shortened.

[0057] Furthermore, by blowing gas toward the semiconductor chip 3 in the space sealed by the pressurized wall 8 , the space is pressurized, thereby preventing discharge.

[0058] Specifically, according to Paschen's law, the voltage that triggers spark discharge increases as the pressure approaches a vacuum or increases. Therefore, discharge in power semiconductor devices with a withstand voltage of 1200V to 6500V can be suppressed by a pressure of approximately 200kPa (approximately 2 atmospheres) to 500kPa (approximately 5 atmospheres). Therefore, by filling the space sealed by pressurized wall 8 with gas at this pressure, discharge during testing can be prevented.

[0059] <Implementation Method 6> use Figures 15 to 18 A wafer testing device according to a sixth embodiment of the present disclosure will be described. Figure 15 1 is a plan view illustrating the structure of the inspection table 2 of the wafer testing apparatus 600 according to the sixth embodiment. Figure 16 yes Figure 15 Cross-sectional view of line DD in FIG.

[0060] like Figure 15 As shown in FIG. 1 , a wafer 1 on which a plurality of semiconductor chips 3 are prepared is placed on an inspection table 2. Figure 16As shown, a movable stage 10 is provided inside the inspection table 2. The movable stage 10 has a heater 11a inside. The heater 11a contacts at least the back surface of the semiconductor chip 3 to be inspected of the wafer 1 mounted on the wafer mounting table 21 of the inspection table 2, thereby heating at least the semiconductor chip 3 to be measured. Figure 15 and Figure 16 In FIG. 1 , the semiconductor chips 3 to be measured are enclosed by dotted lines. In this example, three semiconductor chips 3 are to be measured, but the number of the measurement targets is not limited thereto.

[0061] When conducting a test on the semiconductor chip 3, the movable platform 10 moves to the bottom of the semiconductor chip 3 to be measured and contacts the back side of the semiconductor chip 3 to be measured, thereby concentrating on heating the semiconductor chip 3 to be measured rather than the entire chip 1. Therefore, compared with the inspection table 2 of embodiment 1 in which the inspection table 2 contacts the entire chip 1, heat is not easily diffused in the inspection table 2, and the heating time can be shortened.

[0062] A movable mechanism (not shown) of the movable stage 10 is provided under the wafer mounting table 21 so that the movable stage 10 can cover the entire wafer 1 , thereby increasing the temperature of the semiconductor chip 3 located at the end of the wafer 1 .

[0063] Figure 17 and Figure 18 FIG. 1 is a diagram showing a wafer test using a wafer testing apparatus 600. Figure 17 This shows an example of testing three semiconductor chips 3 at the same time. Figure 18 An example of testing the semiconductor chips 3 one by one is shown.

[0064] exist Figure 17 In the example shown, the movable platform 10 heats up three semiconductor chips 3, and the probes 4 extending from the three test circuits TB1, TB2 and TB3 of the probe card 6 respectively contact the three semiconductor chips 3 to be measured and test them simultaneously. When the test of the three semiconductor chips 3 is completed, the movable platform 10 moves to the bottom of the next semiconductor chip 3 to be measured.

[0065] exist Figure 18The example shown shows a state where the movable stage 10 heats three semiconductor chips 3A, 3B, and 3C, and probes 4 extending from test circuit TB1 of probe card 6 contact the semiconductor chip 3A to be tested. When the test of semiconductor chip 3A is completed, the probe card 6 moves, and the probes 4 extending from test circuit TB1 contact the semiconductor chip 3B to perform the test. When the test of semiconductor chip 3B is completed, the probe card 6 moves, and the probes 4 extending from test circuit TB1 contact the semiconductor chip 3C to perform the test. When the test of semiconductor chips 3A to 3C is completed, the movable stage 10 moves to the bottom of the next semiconductor chip 3 to be tested.

[0066] The present disclosure can freely combine the various embodiments within the scope of the disclosure, or can appropriately modify or omit the various embodiments.

[0067] The present disclosure described above is summarized as a supplementary note.

[0068] (Supplementary Note 1) A wafer testing device comprising: an inspection stage carrying a wafer having a plurality of semiconductor chips; and a probe card for inspecting the plurality of semiconductor chips, The inspection stage has a temperature adjustment mechanism capable of adjusting the temperature of a portion of the wafer. The temperature adjustment mechanism includes a plurality of first heaters that are separated from each other and independently controlled.

[0069] (Supplementary Note 2) The wafer testing device as described in Supplementary Note 1, The temperature adjustment mechanism controls the plurality of first heaters to increase the temperature of at least one semiconductor chip among the plurality of semiconductor chips.

[0070] (Supplementary Note 3) The wafer testing device as described in Supplementary Note 1, The plurality of first heaters are provided inside the inspection table.

[0071] (Supplementary Note 4) The wafer testing device as described in Supplementary Note 1, The temperature adjustment mechanism controls the plurality of first heaters to increase the temperature of corresponding portions of the wafer in accordance with a predetermined inspection order of the plurality of semiconductor chips.

[0072] (Supplementary Note 5) The wafer testing device as described in Supplementary Note 4, The inspection order of the plurality of semiconductor chips is set to have a plurality of inspection paths according to the arrangement of the plurality of semiconductor chips. The plurality of inspection paths are set to be spaced apart from at least one semiconductor chip.

[0073] (Supplementary Note 6) The wafer testing device as described in Supplementary Note 1, The probe card is arranged above the inspection table, The second heater is provided so as to contact a semiconductor chip to be measured among the plurality of semiconductor chips via a probe and thereby contact a surface of the semiconductor chip to be measured.

[0074] (Supplementary Note 7) The wafer testing device as described in Supplementary Note 6, The probe card further includes a temperature sensor that contacts the surface of the semiconductor chip to be measured by the probes contacting the semiconductor chip to be measured.

[0075] (Supplementary Note 8) The wafer testing device as described in Supplementary Note 7, The temperature sensor is composed of a temperature measuring resistor or a thermocouple.

[0076] (Supplementary Note 9) The wafer testing device as described in Supplementary Note 6, The probe card further includes a nozzle of an air blowing device for blowing hot air or cold air toward the semiconductor chip to be measured while the probe is in contact with the semiconductor chip to be measured.

[0077] (Supplementary Note 10) The wafer testing device as described in Supplementary Note 9, The probe card includes a pressurizing wall that seals a space between the probe and the semiconductor chip to be measured when the probe contacts the semiconductor chip to be measured.

[0078] (Supplementary Note 11) The wafer testing device as described in Supplementary Note 1, The inspection table is a movable platform that partially contacts the wafer when the wafer is mounted thereon. The movable stage is controlled to come into contact with a surface of a semiconductor chip to be measured among the plurality of semiconductor chips, to increase the temperature of the semiconductor chip to be measured, and to move when measurement of the semiconductor chip to be measured is completed.

Claims

1. A wafer testing device, characterized in that: include: an inspection stage carrying a wafer having a plurality of semiconductor chips; as well as a probe card for inspecting the plurality of semiconductor chips, The inspection stage includes a temperature adjustment mechanism capable of adjusting the temperature of a portion of the wafer, the temperature adjustment mechanism including a plurality of first heaters that are separated from each other and independently controlled.

2. The wafer testing device according to claim 1, wherein: The temperature adjustment mechanism controls the plurality of first heaters to increase the temperature of at least one semiconductor chip among the plurality of semiconductor chips.

3. The wafer testing device according to claim 1, wherein: The plurality of first heaters are provided inside the inspection table.

4. The wafer testing device according to any one of claims 1 to 3, wherein: The temperature adjustment mechanism controls the plurality of first heaters to increase the temperature of corresponding portions of the wafer in accordance with a predetermined inspection order of the plurality of semiconductor chips.

5. The wafer testing device according to claim 4, wherein: The inspection order of the plurality of semiconductor chips is set to have a plurality of inspection paths according to the arrangement of the plurality of semiconductor chips. The plurality of inspection paths are set to be spaced apart from at least one semiconductor chip.

6. The wafer testing device according to claim 1, wherein: The probe card is arranged above the inspection table, The device further includes a second heater that contacts a surface of a semiconductor chip to be measured among the plurality of semiconductor chips by bringing a probe into contact with the semiconductor chip to be measured.

7. The wafer testing device according to claim 6, wherein: The probe card further includes a temperature sensor that comes into contact with a surface of the semiconductor chip to be measured by bringing the probe into contact with the semiconductor chip to be measured.

8. The wafer testing device according to claim 7, wherein: The temperature sensor is composed of a temperature measuring resistor or a thermocouple.

9. The wafer testing device according to claim 6, wherein: The probe card further includes a nozzle of an air blowing device for blowing hot air or cold air toward the semiconductor chip to be measured while the probe is in contact with the semiconductor chip to be measured.

10. The wafer testing device according to claim 9, wherein: The probe card includes a pressurizing wall that seals a space between the probe and the semiconductor chip to be measured when the probe contacts the semiconductor chip to be measured.

11. The wafer testing device according to claim 1, wherein: The inspection table is a movable platform that partially contacts the wafer when the wafer is mounted thereon. The movable stage is controlled to come into contact with a surface of a semiconductor chip to be measured among the plurality of semiconductor chips, to increase the temperature of the semiconductor chip to be measured, and to move when measurement of the semiconductor chip to be measured is completed.

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