A class-ab output stage biasing circuit and method which follows changes in load current

Abstract

The application relates to the technical field of integrated circuit design, and particularly discloses a class-AB output stage bias circuit and method capable of following changes in load current, which comprises an IBOOSTP filling current source, the two ends of which are connected in parallel with the source-drain electrode of a PMOS tube connected with a power supply in a gate bias circuit for determining the static current of an output NMOS tube of a class-AB, and the size of the IBOOSTP filling current source is proportional to the current flowing through the output PMOS tube of the class-AB; and an IBOOSTN pulling current source, the two ends of which are connected in parallel with the source-drain electrode of an NMOS tube connected with the ground in the gate bias circuit for determining the static current of an output PMOS tube of a class-AB, and the size of the IBOOSTN pulling current source is proportional to the current flowing through the output NMOS tube of the class-AB. The IBOOSTP filling current source and the IBOOSTN pulling current source are set to have sizes proportional to the current flowing through the output PMOS tube and the output NMOS tube of the class-AB respectively, so that the overall gain of the class-AB is increased and the output error is reduced under large load current.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and particularly relates to a class-AB output stage bias circuit and method following changes in load current. BACKGROUND

[0002] Figure 1 For a traditional class AB output operational amplifier, a floating current source bias circuit is used to support bidirectional load current output of source / sink. The floating current source bias circuit realizes accurate control of the static current of the class-AB output stage through the following formula.

[0003] The P side (Pside) formula is:

[0004] ;

[0005] ;

[0006] The N side (Nside) formula is:

[0007] ;

[0008] ;

[0009] Under the no-load condition, the currents iMPOUT=iMNOUT of MPOUT / MNOUT are equal, and the currents of MP9 / MP11 are set to be the same as the width-length ratio proportion, so that:

[0010] ;

[0011] The currents of MPOUT / MP10 are set to be the same as the width-length ratio proportion, so that:

[0012] ;

[0013] , and ;

[0014] Similarly, the currents of MN9 / MN11 are set to be the same as the width-length ratio proportion, so that:

[0015] ;

[0016] The currents of MNOUT / MN10 are set to be the same as the width-length ratio proportion, so that:

[0017] ;

[0018] , and ;

[0019] The total current of MN9 and MP9 is a fixed current 2 i0;

[0020] When the output needs to support a large source current, the current of MN9 increases, the current of MP9 decreases, decreases in absolute value, increases in absolute value so that the output MPOUT can provide sufficient sink current; similarly, when the output needs to support a large sink current, the current of MP9 increases, the current of MN9 decreases, decreases, increases so that the output MNOUT can provide sufficient source current.

[0021] The problems of the conventional class AB output operational amplifier are:

[0022] When the output stage needs to drive a large load current, assuming that the load current flows to the ground (sink current mode), the absolute value of VGS of MPOUT is large, the absolute value of VGS of MP9 is small, and MP9 is turned off. The current flows through MN9 entirely, and the increase of VGS of MN9 causes the voltage of VG_NOUT to decrease, and the too low VG_NOUT causes the Vds of the cascode tube MN8 to decrease, and MN8 enters the linear region, causing the gain of the first stage of the operational amplifier to decrease greatly, thereby the overall gain of the operational amplifier decreases, and the output error becomes large.

[0023] Similarly, in the case of large current load in the sink current output, MP8 entering the linear region will also cause the overall gain of the operational amplifier to decrease, and the output error becomes large.

[0024] Based on this technical background, the present application studies a class-AB output stage bias circuit and method following the change of load current. SUMMARY

[0025] In view of the deficiencies of the prior art, the present application provides a class-AB output stage bias circuit and method following the change of load current, which sets the sizes of IBOOSTP sink current source and IBOOSTN sink current source to be proportional to the currents flowing through the output PMOS tube and the output NMOS tube of the class-AB, respectively, and then increases the overall gain of the class-AB under large load current.

[0026] In order to achieve the above purpose, the first aspect of the present application provides a class-AB output stage bias circuit following the change of load current, comprising:

[0027] IBOOSTP pumping current source, connected in parallel with the source-drain of the PMOS transistor in the gate bias circuit that determines the quiescent current of the class-AB output NMOS transistor, the size of which is proportional to the current flowing through the class-AB output PMOS transistor;

[0028] IBOOSTN pulling current source, connected in parallel with the source-drain of the NMOS transistor in the gate bias circuit that determines the quiescent current of the class-AB output PMOS transistor, the size of which is proportional to the current flowing through the class-AB output NMOS transistor;

[0029] The IBOOSTP pumping current source and the IBOOSTN pulling current source are used to increase the overall gain of the class-AB under large load current, thereby reducing the output error.

[0030] The second aspect of the present application provides a class-AB output stage biasing method that follows the changes in load current in the above-mentioned circuit, comprising:

[0031] Connecting the source-drain of the PMOS transistor in the gate bias circuit that determines the quiescent current of the class-AB output NMOS transistor in parallel with the IBOOSTP pumping current source;

[0032] Connecting the source-drain of the NMOS transistor in the gate bias circuit that determines the quiescent current of the class-AB output PMOS transistor in parallel with the IBOOSTN pulling current source;

[0033] By setting the size of the IBOOSTP pumping current source and the IBOOSTN pulling current source to be proportional to the current flowing through the class-AB output PMOS transistor and the class-AB output NMOS transistor respectively, the overall gain of the class-AB is increased under large load current.

[0034] The beneficial effects of the present application include:

[0035] (1) The class-AB output stage biasing circuit that follows the changes in load current proposed by the present application increases the overall gain of the class-AB under large load current by setting the size of the IBOOSTP pumping current source and the IBOOSTN pulling current source to be proportional to the current flowing through the class-AB output PMOS transistor and the class-AB output NMOS transistor respectively.

[0036] (2) The class-AB output stage bias circuit following the change of load current can still keep the operational amplifier to output with high gain under the condition of large current load, and supports the pull current / source current mode; accurately copies the output tube gate-source voltage / drain-source voltage, and then realizes the accurate load current mirror; under the condition of output no load, the IBOOSTP source current and the IBOOSTN pull current source are both 0, and the static current is not increased; the open loop control is adopted, and the stability of the amplifier itself is not affected, and the area is very small.

[0037] Other features and advantages of the present application will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0038] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which like reference characters refer to like parts throughout the figures, and in which:

[0039] Figure 1 It is a structure schematic diagram of the traditional class AB output operational amplifier.

[0040] Figure 2 It is a simplified structure schematic diagram of the class-AB output stage bias circuit following the change of load current proposed by the present application.

[0041] Figure 3 It is a structure schematic diagram of one specific embodiment of the class-AB output stage bias circuit following the change of load current proposed by the present application.

[0042] BRIEF DESCRIPTION OF DRAWINGS

[0043] MN18 - first NMOS input transistor, MN17 - second NMOS input transistor, MN16 - first NMOS bias transistor, MN14 - second NMOS bias transistor, Rl - first load resistor, MP16 - first PMOS load transistor, MP14 - second PMOS load transistor, MP17 - first PMOS source transistor, MP OUT COPY - second PMOS source transistor, MP19 - first PMOS input transistor, MP20 - second PMOS input transistor, MP18 - first PMOS bias transistor, MP15 - second PMOS bias transistor, R2 - second load resistor, MN19 - first NMOS load transistor, MN15 - second NMOS load transistor, MN20 - first NMOS source transistor, MN OUT COPY - second NMOS source transistor, MP OUT - output PMOS transistor, MN OUT - output NMOS transistor, MP9 - PMOS current mirror transistor, MN9 - NMOS current mirror transistor, MN4 - PMOS differential input transistor adjacent load NMOS transistor, MN3 - PMOS differential input transistor non-adjacent load NMOS transistor, MP4 - NMOS differential input transistor adjacent load PMOS transistor, MP3 - NMOS differential input transistor non-adjacent load PMOS transistor, MP13 - PMOS transistor in gate bias circuit connected to power supply, MN12 - NMOS transistor in gate bias circuit connected to ground;

[0044] VDD - power supply, VSS - ground, Vnb - second NMOS bias voltage, Vncas - first NMOS bias voltage, Vpb - second PMOS bias voltage, Vpcas - first PMOS bias voltage, VOUT - class-AB output voltage, IL - load current, iMPOUT - current through output PMOS transistor, iMN OUT - current through output NMOS transistor, VOUT TRACKP - first output voltage follower voltage, TRACKP N - second output voltage follower voltage, K - ratio, il - current through PMOS current mirror transistor, i2 - current through NMOS current mirror transistor, i0 - total current through PMOS current mirror transistor and NMOS current mirror transistor, VG NB - gate voltage of NMOS current mirror transistor, VG NOUT - gate voltage of output NMOS transistor, VG PB - gate voltage of PMOS current mirror transistor, VG POUT - gate voltage of output PMOS transistor, Track Pside - follower P side, Track Nside - follower N side, VG PCAS - bias voltage, VD MPOUT COPY - source voltage of first PMOS source transistor, VD MN OUT COPY - source voltage of first NMOS source transistor. DETAILED DESCRIPTION

[0045] Preferred embodiments of the present application will be described in more detail below. Although the preferred embodiments of the present application are described below, it is understood that the present application can be practiced with modifications within the scope of the present application, which are not to be interpreted as being limited to the embodiments set forth herein.

[0046] In the present application, the orientation words such as "upper", "lower", "inner", "outer" are used in the context of the device in the normal use state, unless otherwise specified. In addition, the terms "first", "second", "third" are used only for the purpose of description, and should not be construed as indicating or implying relative importance or implying the number of the technical features indicated. Therefore, the features defined as "first", "second", "third" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0047] The present application provides a class-AB output stage bias circuit following the load current change, as shown in Figures 2-3 comprising:

[0048] IBOOSTP pumping current source, both ends of which are connected in parallel with the source-drain of PMOS MP13 in the gate bias circuit for determining the static current of the output NMOS MNOUT of the class-AB, and the size is proportional to the current flowing through the output PMOS MPOUT of the class-AB;

[0049] IBOOSTN pumping current source, both ends of which are connected in parallel with the source-drain of NMOS MN12 in the gate bias circuit for determining the static current of the output PMOS MPOUT of the class-AB, and the size is proportional to the current flowing through the output NMOS MNOUT of the class-AB;

[0050] IBOOSTP pumping current source and IBOOSTN pumping current source are used to increase the overall gain of the class-AB under large load current IL, thereby reducing the output error.

[0051] According to the present application, the IBOOSTP pumping current source comprises a first output voltage follower circuit and a PMOS source-out circuit;

[0052] The first output voltage follower circuit is used to follow the output voltage VOUT of the class-AB, and provide a bias voltage for the PMOS source-out circuit;

[0053] The drain of the PMOS source-out circuit is electrically connected with the drain of the PMOS MP13 in the gate bias circuit for determining the static current of the output NMOS MNOUT of the class-AB.

[0054] According to the application, the IBOOSTN pull current source comprises a second output voltage follower circuit and an NMOS pull-in circuit;

[0055] The second output voltage follower circuit is used for following the output voltage VOUT of the class-AB and providing a bias voltage for the NMOS pull-in circuit;

[0056] The source end of the NMOS pull-in circuit is electrically connected with the drain of the NMOS tube MN12 connected with the ground VSS in the gate bias circuit for determining the static current of the output PMOS tube MPOUT of the class-AB.

[0057] According to the application, the first output voltage follower circuit comprises:

[0058] A first NMOS input tube MN18, the gate of which is electrically connected with the output voltage VOUT of the class-AB;

[0059] A second NMOS input tube MN17, the source of which is electrically connected with the source of the first NMOS input tube MN18;

[0060] A first NMOS bias tube MN16, the drain of which is electrically connected with the source of the first NMOS input tube MN18, and the gate of which is electrically connected with the first NMOS bias Vncas of the class-AB;

[0061] A second NMOS bias tube MN14, the drain of which is electrically connected with the source of the first NMOS bias tube MN16, the source of which is electrically connected with the ground VSS, and the gate of which is electrically connected with the second NMOS bias Vnb of the class-AB;

[0062] A first load resistor R1, one end of which is electrically connected with the power supply VDD, and the other end of which is electrically connected with the drain of the first NMOS input tube MN18;

[0063] A first PMOS load tube MP16, the drain of which is electrically connected with the drain of the second NMOS input tube MN17, and the gate of which is electrically connected with the drain thereof;

[0064] A second PMOS load tube MP14, the drain of which is electrically connected with the gate of the second NMOS input tube MN17 and the source of the first PMOS load tube MP16, the source of which is electrically connected with the power supply VDD, and the gate of which is electrically connected with the second PMOS bias Vpb of the class-AB;

[0065] The PMOS pull-out circuit comprises:

[0066] The first PMOS source-out tube MP17 has its drain electrically connected to the drain of the PMOS tube MP13 in the gate bias circuit for determining the static current of the output NMOS tube MNOUT of the class-AB, and its gate electrically connected to the gate of the first PMOS load tube MP16.

[0067] The second PMOS source-out tube MPOUT_COPY has its drain electrically connected to the source of the first PMOS source-out tube MP17, its source electrically connected to the power supply VDD, and its gate electrically connected to the gate of the output PMOS of the class-AB.

[0068] According to the present application, the second output voltage follower circuit comprises:

[0069] The first PMOS input tube MP19 has its gate electrically connected to the output voltage VOUT of the class-AB.

[0070] The second PMOS input tube MP20 has its source electrically connected to the source of the first PMOS input tube MP19.

[0071] The first PMOS bias tube MP18 has its drain electrically connected to the source of the first PMOS input tube MP19, and its gate electrically connected to the first PMOS bias Vpcas of the class-AB.

[0072] The second PMOS bias tube MP15 has its drain electrically connected to the source of the first PMOS bias tube MP18, its source electrically connected to the power supply VDD, and its gate electrically connected to the second PMOS bias Vpb of the input stage of the class-AB.

[0073] The second load resistor R2 has one end electrically connected to the ground VSS, and the other end electrically connected to the drain of the first PMOS input tube MP19.

[0074] The first NMOS load tube MN19 has its drain electrically connected to the drain of the second PMOS input tube MP20, and its gate electrically connected to its own drain.

[0075] The second NMOS load tube MN15 has its drain electrically connected to the gate of the second PMOS input tube MP20 and the source of the first NMOS load tube MN19, its source electrically connected to the power supply VDD, and its gate electrically connected to the second NMOS bias Vnb of the class-AB.

[0076] The NMOS source-in circuit comprises:

[0077] The first NMOS source-in tube MN20 is electrically connected with the drain of the NMOS tube MN12 in the gate bias circuit for determining the static current of the output PMOS tube MPOUT of the class-AB, and the gate is electrically connected with the gate of the first NMOS load tube MN19;

[0078] The second NMOS source-in tube MNOUT_COPY is electrically connected with the source of the first NMOS source-in tube, and the source is electrically connected with the ground VSS, and the gate is electrically connected with the gate of the output NMOS of the class-AB.

[0079] According to the application, the first NMOS bias Vncas is the gate bias of the load NMOS tube MN4 adjacent to the PMOS differential input tube of the class-AB;

[0080] The second NMOS bias Vnb is the gate bias of the load NMOS tube MN3 non-adjacent to the PMOS differential input tube of the class-AB;

[0081] The first PMOS bias Vpcas is the gate bias of the load PMOS tube MP4 adjacent to the NMOS differential input tube of the class-AB;

[0082] The second PMOS bias Vpb is the gate bias of the load PMOS tube MP3 non-adjacent to the NMOS differential input tube of the class-AB.

[0083] According to the application, the first NMOS input tube MN18 and the second NMOS input tube MN17 are of the same size;

[0084] The first PMOS input tube MP19 and the second PMOS input tube MP20 are of the same size;

[0085] The size ratio of the second PMOS source-in tube MPOUT_COPY and the output PMOS of the class-AB, the size ratio of the second NMOS source-in tube and the output NMOS of the class-AB, the ratio of the IBOOSTP current source and the current flowing through the output PMOS tube MPOUT of the class-AB, and the ratio of the IBOOSTN current source and the current flowing through the output NMOS tube MNOUT of the class-AB are all the same, and the value of the ratio is much smaller than 1.

[0086] According to the application, the input stage of the class-AB adopts a rail-to-rail folded cascode structure.

[0087] The application also provides a method performed in the above bias circuit, comprising:

[0088] The source-drain of the PMOS MP13 connected with the power supply VDD in the gate bias circuit for determining the static current of the class-AB output NMOS MNOUT is connected in parallel with the IBOOSTP pumping current source;

[0089] The source-drain of the NMOS MN12 connected with the ground VSS in the gate bias circuit for determining the static current of the class-AB output PMOS MPOUT is connected in parallel with the IBOOSTN pumping current source;

[0090] By setting the sizes of the IBOOSTP pumping current source and the IBOOSTN pumping current source to be proportional to the currents flowing through the class-AB output PMOS MPOUT and the class-AB output NMOS MNOUT respectively, the overall gain of the class-AB is increased under a large load current IL.

[0091] According to the present application, it further comprises:

[0092] The sizes of the first NMOS input tube MN18 and the second NMOS input tube MN17 in the IBOOSTP pumping current source are set to be the same, and the sizes of the first PMOS input tube MP19 and the second PMOS input tube MP20 in the IBOOSTN pumping current source are set to be the same;

[0093] The sizes of the second PMOS output tube MPOUT_COPY and the class-AB output PMOS, the sizes of the second NMOS output tube and the class-AB output NMOS, the ratio of the IBOOSTP pumping current source and the current flowing through the class-AB output PMOS MPOUT, and the ratio of the IBOOSTN pumping current source and the current flowing through the class-AB output NMOS MNOUT are all the same, and the value of the ratio is much smaller than 1. When the accurate load current IL mirroring is achieved, the static current of the class-AB is not increased, the gate voltage VG_POUT of the class-AB output PMOS MPOUT, and the gate voltage VG_NOUT of the class-AB output NMOS MNOUT are ensured.

[0094] The present application will be described in more detail through specific embodiments.

[0095] Embodiment 1

[0096] As shown in the figure, the present embodiment provides a class-AB output stage bias circuit following the change of the load current, which comprises: Figures 2-3

[0097] ​IBOOSTP pumping current source, both ends of which are connected in parallel with the source-drain of PMOS MP13 connected to power supply VDD in the gate bias circuit for determining the quiescent current of the class-AB output NMOS MNOUT, and the size of which is proportional to the current flowing through the class-AB output PMOS MPOUT;

[0098] IBOOSTN pulling current source, both ends of which are connected in parallel with the source-drain of NMOS MN12 connected to ground VSS in the gate bias circuit for determining the quiescent current of the class-AB output PMOS MPOUT, and the size of which is proportional to the current flowing through the class-AB output NMOS MNOUT;

[0099] The IBOOSTP pumping current source comprises a first output voltage follower circuit and a PMOS source-out circuit;

[0100] The first output voltage follower circuit is configured to follow the class-AB output voltage VOUT and provide a bias voltage for the PMOS source-out circuit;

[0101] The PMOS source-out circuit is electrically connected to the drain of PMOS MP13 connected to power supply VDD in the gate bias circuit for determining the quiescent current of the class-AB output NMOS MNOUT;

[0102] The IBOOSTN pulling current source comprises a second output voltage follower circuit and an NMOS source-in circuit;

[0103] The second output voltage follower circuit is configured to follow the class-AB output voltage VOUT and provide a bias voltage for the NMOS source-in circuit;

[0104] The NMOS source-in circuit is electrically connected to the drain of NMOS MN12 connected to ground VSS in the gate bias circuit for determining the quiescent current of the class-AB output PMOS MPOUT;

[0105] The first output voltage follower circuit comprises:

[0106] A first NMOS input tube MN18, the gate of which is electrically connected to the class-AB output voltage VOUT;

[0107] A second NMOS input tube MN17, the source of which is electrically connected to the source of the first NMOS input tube MN18;

[0108] A first NMOS bias tube MN16, the drain of which is electrically connected to the source of the first NMOS input tube MN18, and the gate of which is electrically connected to the class-AB first NMOS bias Vncas;

[0109] The second NMOS biasing tube MN14 has its drain electrically connected to the source of the first NMOS biasing tube MN16, its source electrically connected to the ground VSS, and its gate electrically connected to the second NMOS bias voltage Vnb of the class-AB;

[0110] The first load resistor R1 has one end electrically connected to the power supply VDD and the other end electrically connected to the drain of the first NMOS input tube MN18;

[0111] The first PMOS load tube MP16 has its drain electrically connected to the drain of the second NMOS input tube MN17 and its gate electrically connected to its drain.

[0112] The second PMOS load tube MP14 has its drain electrically connected to the gate of the second NMOS input tube MN17 and the source of the first PMOS load tube MP16, its source electrically connected to the power supply VDD, and its gate electrically connected to the second PMOS bias voltage Vpb of the class-AB;

[0113] The PMOS source output circuit comprises:

[0114] The first PMOS source output tube MP17 has its drain electrically connected to the drain of the PMOS tube MP13 in the gate biasing circuit for determining the static current of the output NMOS tube MNOUT of the class-AB, and its gate electrically connected to the gate of the first PMOS load tube MP16.

[0115] The second PMOS source output tube MPOUT_COPY has its drain electrically connected to the source of the first PMOS source output tube MP17, its source electrically connected to the power supply VDD, and its gate electrically connected to the gate of the output PMOS of the class-AB;

[0116] The second output voltage follower circuit comprises:

[0117] The first PMOS input tube MP19 has its gate electrically connected to the output voltage VOUT of the class-AB.

[0118] The second PMOS input tube MP20 has its source electrically connected to the source of the first PMOS input tube MP19.

[0119] The first PMOS biasing tube MP18 has its drain electrically connected to the source of the first PMOS input tube MP19, and its gate electrically connected to the first PMOS bias voltage Vpcas of the class-AB.

[0120] The second PMOS biasing tube MP15 has its drain electrically connected to the source of the first PMOS biasing tube MP18, its source electrically connected to the power supply VDD, and its gate electrically connected to the second PMOS bias voltage Vpb of the input stage of the class-AB.

[0121] A second load resistor R2 has one end electrically connected to the ground VSS and the other end electrically connected to the drain of a first PMOS input transistor MP19;

[0122] A first NMOS load transistor MN19 has its drain electrically connected to the drain of a second PMOS input transistor MP20 and its gate electrically connected to its drain;

[0123] A second NMOS load transistor MN15 has its drain electrically connected to the gate of the second PMOS input transistor MP20 and the source of the first NMOS load transistor MN19, its source electrically connected to the power supply VDD, and its gate electrically connected to a second NMOS bias voltage Vnb of the class-AB;

[0124] The NMOS source follower circuit comprises:

[0125] A first NMOS source follower transistor MN20 has its drain electrically connected to the drain of an NMOS transistor MN12 in a gate bias circuit for determining the static current of an output PMOS transistor MPOUT of the class-AB, its gate electrically connected to the gate of the first NMOS load transistor MN19;

[0126] A second NMOS source follower transistor MNOUT_COPY has its drain electrically connected to the source of the first NMOS source follower transistor, its source electrically connected to the ground VSS, and its gate electrically connected to the gate of an output NMOS transistor of the class-AB;

[0127] In the embodiment, a first NMOS bias voltage Vncas is a gate bias voltage of a load NMOS transistor MN4 adjacent to a PMOS differential input transistor of the class-AB;

[0128] A second NMOS bias voltage Vnb is a gate bias voltage of a load NMOS transistor MN3 non-adjacent to a PMOS differential input transistor of the class-AB;

[0129] A first PMOS bias voltage Vpcas is a gate bias voltage of a load PMOS transistor MP4 adjacent to an NMOS differential input transistor of the class-AB;

[0130] A second PMOS bias voltage Vpb is a gate bias voltage of a load PMOS transistor MP3 non-adjacent to an NMOS differential input transistor of the class-AB;

[0131] In the embodiment, the first NMOS input transistor MN18 and the second NMOS input transistor MN17 have the same size;

[0132] The first PMOS input transistor MP19 and the second PMOS input transistor MP20 have the same size;

[0133] The ratio of the size of the second PMOS source transistor MPOUT_COPY to the size of the output PMOS transistor of class-AB, the ratio of the size of the second NMOS source transistor to the size of the output NMOS transistor of class-AB, the ratio of the current flowing through the IBOOSTP sink current source and the current flowing through the output PMOS transistor MPOUT of class-AB, and the ratio of the current flowing through the IBOOSTN pull current source and the current flowing through the output NMOS transistor MNOUT of class-AB are all the same, and the value of this ratio is much less than 1.

[0134] In this embodiment, the input stage of class-AB adopts the existing rail-to-rail folded cascode structure.

[0135] The working principle of the class-AB output stage bias circuit that follows load current changes proposed in this invention is as follows:

[0136] like Figure 2 As shown, in the existing class-AB structure, a current IBOOSTP / IBOOSTN proportional to the current iMPOUT / iMNOUT of the output PMOS / NMOS transistors is added;

[0137] Taking the pull-out output current as an example, assuming that as the load current IL increases, iMPOUT increases, and IBOOSTP increases proportionally; the VGS of MN10 / MN11 in the gate bias circuit of the NMOS regulated transistor MN9 increases, and the gate voltage VG_NB of the NMOS regulated transistor MN9 becomes higher; even if MP9 is completely turned off, 2 The current i0 (the total current flowing through the PMOS and NMOS transistors) flows entirely through the NMOS transistor MN9. Because the gate voltage VG_NB of the NMOS transistor MN9 increases, the gate voltage VG_NOUT of the output NMOS transistor increases, which in turn increases the Vds of the NMOS transistor MN8, allowing it to operate in the saturation region. Under high load current, the overall gain of the op-amp is higher than that of the traditional structure, and the output absolute error is smaller.

[0138] The sink current output is similar to the source current mode. As the load current IL increases, IBOOSTN increases proportionally, resulting in a lower gate voltage of the PMOS current regulating transistor / gate voltage of the output PMOS transistor VG_PB / VG_POUT. The absolute value of Vds of the PMOS transistor MP8 increases, allowing it to operate in the saturation region. Under a large load current IL, the overall gain of the op-amp is higher than that of the traditional gain, and the absolute output error is smaller.

[0139] Under low current load or no-load conditions, IBOOSTP / IBOOSTN are very small, and compared with traditional structures, the static current remains unchanged and the gain is similar.

[0140] The specific working principle of the class-AB output stage bias circuit following the load current change is as follows:

[0141] As shown in the figure, taking the P-side Track Pside as an example, the P-side Track Nside is the same: Figure 3

[0142] The output voltage VOUT of the class-AB is connected to the gate of the first NMOS input tube MN18 of the first output voltage follower circuit of the P-side Track Pside. The second NMOS input tube MN17 / the first NMOS input tube / MN18 has the same size, and the current of the second NMOS bias tube MN14 is twice the current of the second PMOS load tube MP14, so that the current flowing through the second NMOS input tube MN17 / the first NMOS input tube / MN18 is equal, Therefore, the voltage of the first output voltage follower circuit following the voltage VOUT_TRACKP is approximately equal to the output voltage VOUT of the class-AB;

[0143] The current flowing through the diode-connected first PMOS load tube MP16 MP16 generates a bias voltage VG_PCAS to bias the first PMOS source output tube MP17. The source voltage VD_MPOUT_COPY of the first PMOS source output tube MP17 is approximately equal to the voltage VOUT_TRACKP (the output voltage VOUT of the class-AB) followed by the first output voltage follower circuit;

[0144] The gate voltage VG_POUT of the output PMOS tube MPOUT of the class-AB is connected to the source voltage MPOUT_COPY of the first PMOS source output tube MP17. The VGS voltage of the output PMOS tube MPOUT of the class-AB MPOUT / the second PMOS source output tube MPOUT_COPY is equal, and the VDS voltage is also approximately equal. Therefore, by setting the size of the second PMOS source output tube MPOUT_COPY to be K times the size of the output PMOS tube MPOUT of the class-AB, the K times current is:

[0145] IBOOSTP=K iMPOUT; (usually set K << 1);

[0146] Similarly, the same principle is used for the P-side Track Nside:

[0147] IBOOSTN=K iMNOUT.

[0148] ​The class-AB output stage bias circuit which follows the change of the load current can still make the operational amplifier keep high-gain output under large current load condition, and supports pull current / source current mode; accurately copies the output tube gate-source voltage / drain-source voltage, and then realizes accurate load current mirroring; under the condition of output no load, IBOOSTP source current and IBOOSTN pull current source are 0, and the static current is not increased; open-loop control is adopted, which does not affect the stability of the amplifier itself, and the area is very small.

[0149] The above has described the embodiments of the present application, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A class-AB output stage biasing circuit which follows changes in load current, characterized by, The application relates to a class-AB amplifier, comprising: IBOOSTP pumping current source, both ends of which are connected in parallel with the source-drain of a PMOS tube connected with a power supply in a gate bias circuit for determining the static current of an output NMOS tube of the class-AB, and the size of the IBOOSTP pumping current source is proportional to the current flowing through the output PMOS tube of the class-AB; IBOOSTN pumping current source, both ends of which are connected in parallel with the source-drain of an NMOS tube connected with the ground in a gate bias circuit for determining the static current of the output PMOS tube of the class-AB, and the size of the IBOOSTN pumping current source is proportional to the current flowing through the output NMOS tube of the class-AB; The IBOOSTP pumping current source and the IBOOSTN pumping current source are used for increasing the overall gain of the class-AB under large load current, thereby reducing output error; The IBOOSTP pumping current source comprises a first output voltage follower circuit and a PMOS source-out circuit; The first output voltage follower circuit is used for following the output voltage of the class-AB and providing a bias voltage for the PMOS source-out circuit; The drain of the PMOS source-out circuit is electrically connected with the drain of a PMOS tube connected with a power supply in a gate bias circuit for determining the static current of an output NMOS tube of the class-AB; The IBOOSTN pumping current source comprises a second output voltage follower circuit and an NMOS source-in circuit; The second output voltage follower circuit is used for following the output voltage of the class-AB and providing a bias voltage for the NMOS source-in circuit; The drain of the NMOS source-in circuit is electrically connected with the drain of an NMOS tube connected with the ground in a gate bias circuit for determining the static current of the output PMOS tube of the class-AB.

2. The biasing circuit of claim 1, wherein, The first output voltage follower circuit comprises: A first NMOS input tube, the gate of which is electrically connected with the output voltage of the class-AB; A second NMOS input tube, the source of which is electrically connected with the source of the first NMOS input tube; A first NMOS bias tube, the drain of which is electrically connected with the source of the first NMOS input tube, and the gate of which is electrically connected with the first NMOS bias voltage of the class-AB; A second NMOS bias tube, the drain of which is electrically connected with the source of the first NMOS bias tube, the source of which is electrically connected with the ground, and the gate of which is electrically connected with the second NMOS bias voltage of the class-AB; A first load resistor, one end of which is electrically connected with the power supply, and the other end of which is electrically connected with the drain of the first NMOS input tube; A first PMOS load tube, the drain of which is electrically connected with the drain of the second NMOS input tube, and the gate of which is electrically connected with the drain of the first PMOS load tube; A second PMOS load tube, the drain of which is electrically connected with the gate of the second NMOS input tube and the source of the first PMOS load tube, the source of which is electrically connected with the power supply, and the gate of which is electrically connected with the second PMOS bias voltage of the class-AB; The PMOS source-out circuit comprises: a first PMOS source-out tube, whose drain is electrically connected to the drain of a PMOS tube for connecting power supply in a gate bias circuit for determining the static current of the output NMOS tube of the class-AB, and whose gate is electrically connected to the gate of the first PMOS load tube; a second PMOS source-out tube, whose drain is electrically connected to the source of the first PMOS source-out tube, whose source is electrically connected to the power supply, and whose gate is electrically connected to the gate of the output PMOS tube of the class-AB.

3. The biasing circuit of claim 1, wherein, The second output voltage follower circuit comprises: a first PMOS input tube, whose gate is electrically connected to the output voltage of the class-AB; a second PMOS input tube, whose source is electrically connected to the source of the first PMOS input tube; a first PMOS bias tube, whose drain is electrically connected to the source of the first PMOS input tube, and whose gate is electrically connected to the first PMOS bias voltage of the class-AB; a second PMOS bias tube, whose drain is electrically connected to the source of the first PMOS bias tube, whose source is electrically connected to the power supply, and whose gate is electrically connected to the second PMOS bias voltage of the input stage of the class-AB; a second load resistor, one end of which is electrically connected to the ground, and the other end of which is electrically connected to the drain of the first PMOS input tube; a first NMOS load tube, whose drain is electrically connected to the drain of the second PMOS input tube, and whose gate is electrically connected to its own drain; a second NMOS load tube, whose drain is electrically connected to the gate of the second PMOS input tube and the source of the first NMOS load tube, whose source is electrically connected to the power supply, and whose gate is electrically connected to the second NMOS bias voltage of the class-AB. The NMOS source-in circuit comprises: a first NMOS source-in tube, whose drain is electrically connected to the drain of an NMOS tube for connecting the ground in a gate bias circuit for determining the static current of the output PMOS tube of the class-AB, and whose gate is electrically connected to the gate of the first NMOS load tube; a second NMOS source-in tube, whose drain is electrically connected to the source of the first NMOS source-out tube, whose source is electrically connected to the ground, and whose gate is electrically connected to the gate of the output NMOS tube of the class-AB.

4. Biasing circuit according to claim 2 or 3, characterized in that, The first NMOS bias voltage is the gate bias voltage of the load NMOS tube adjacent to the PMOS differential input tube of the class-AB; The second NMOS bias voltage is the gate bias voltage of the load NMOS tube non-adjacent to the PMOS differential input tube of the class-AB; The first PMOS bias voltage is the gate bias voltage of the load PMOS tube adjacent to the NMOS differential input tube of the class-AB; The second PMOS bias voltage is the gate bias voltage of the load PMOS tube non-adjacent to the NMOS differential input tube of the class-AB.

5. The biasing circuit of claim 2 or 3, wherein, The sizes of the first NMOS input tube and the second NMOS input tube are the same; The sizes of the first PMOS input tube and the second PMOS input tube are the same; The ratio of the size of the second PMOS source-out tube to the size of the output PMOS tube of the class-AB, the ratio of the size of the second NMOS source-out tube to the size of the output NMOS tube of the class-AB, the ratio of the IBOOSTP current source to the current flowing through the output PMOS tube of the class-AB, and the ratio of the IBOOSTN current source to the current flowing through the output NMOS tube of the class-AB are all the same, and the value of the ratio is much less than 1.

6. The biasing circuit of claim 1, wherein, The input stage of the class-AB adopts a rail-to-rail folded cascode structure.

7. A class-AB output stage biasing method for following changes in load current in a bias circuit as claimed in any one of claims 1 to 6, characterised in that, Comprise: The source-drain of the PMOS tube connected to the power supply in the gate bias circuit for determining the static current of the output NMOS tube of the class-AB is connected in parallel with the IBOOSTP current source; The source-drain of the NMOS tube connected to the ground in the gate bias circuit for determining the static current of the output PMOS tube of the class-AB is connected in parallel with the IBOOSTN current source; By setting the sizes of the IBOOSTP current source and the IBOOSTN current source to be proportional to the currents flowing through the output PMOS tube and the output NMOS tube of the class-AB respectively, the overall gain of the class-AB is increased under large load current.

8. The method of claim 7, wherein, Also comprise: The sizes of the first NMOS input tube and the second NMOS input tube in the IBOOSTP current source are set to be the same, and the sizes of the first PMOS input tube and the second PMOS input tube in the IBOOSTN current source are set to be the same; The ratio of the size of the second PMOS source-out tube to the size of the output PMOS tube of the class-AB, the ratio of the size of the second NMOS source-out tube to the size of the output NMOS tube of the class-AB, the ratio of the IBOOSTP current source to the current flowing through the output PMOS tube of the class-AB, and the ratio of the IBOOSTN current source to the current flowing through the output NMOS tube of the class-AB are all the same, and the value of the ratio is much less than 1, which ensures that there is no increase in the static current of the class-AB under the condition of output no-load while achieving accurate load current mirroring.

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