A read-write multiplexing circuit for RRAM storage and computing array and RRAM storage and computing system

Abstract

The present invention belongs to the technical field related to in-memory computing, and discloses a read-write multiplexing circuit and an RRAM memory computing system applied to an RRAM memory computing array. The read-write multiplexing circuit includes a bit line control module and a signal line control module. In the bit line control module, the bit line drive selection circuit starts the required bit line drive circuit, the demultiplexer connects the corresponding bit line drive circuit to the target bit line, and the bit line digital signal is converted into an analog voltage and loaded onto the target bit line; in the signal line control module, the signal line drive selection circuit starts the required signal line drive circuit, the multiplexer connects the target signal line to the corresponding signal line drive circuit, and the signal line digital signal converter converts it into an analog voltage signal and loads it onto the target signal line. Based on the above read-write multiplexing circuit, circuit multiplexing of the read and write process can be realized, which reduces the area overhead of the peripheral circuit, and can also realize the parallel operation of the write process, thereby improving the efficiency of the weight mapping process.

Description

Technical Field

[0001] The present invention belongs to the technical field related to in-memory computing, and more specifically, relates to a read-write multiplexing circuit applied to a RRAM memory computing array and an RRAM memory computing system. Background Art

[0002] The rapid development of technologies like big data and artificial intelligence has accelerated research on existing scientific problems, particularly in areas such as weather forecasting, aerospace technology, and earthquake prediction. These applications involve a large number of matrix operations, placing higher demands on the performance and reliability of existing computing platforms. To meet the growing demand for scientific computing, current computing platforms must achieve both high precision and high speed while maintaining sufficient energy efficiency. Memristor-based computing-in-memory (CIM) technology, exemplified by resistive random access memory (RRAM), has become a key area of ​​research in computing architecture due to its significant low-latency advantages.

[0003] Compared to the traditional von Neumann architecture, the memristor array-based CIM architecture effectively avoids the interconnect bus overhead caused by separating storage and computing units by performing computations directly within the memory cells. Parasitic effects such as latency and passive losses within the interconnect bus are key bottlenecks that restrict the speed and energy efficiency of the von Neumann architecture. Therefore, the CIM architecture is more capable of meeting future computing power and energy efficiency trends. Among them, RRAM-based memristors, thanks to their multi-value storage and high density, are promising for large-scale storage and computing arrays, making them a key storage and computing medium in current CIM architecture research.

[0004] Currently, on-chip write circuits for large-scale RRAM arrays generally use a pre-charged write method to avoid the impact of a large amount of passive parasitic capacitance and parasitic resistance in the array on signal integrity during high-speed reading and writing. However, the current method can only write to a single RRAM device and cannot meet the demand for efficient writing to large-scale arrays. Secondly, the separation of write and calculation circuits also brings additional area and power consumption overhead. Currently, there is a lack of an efficient on-chip read-write peripheral circuit to perform weight writing and data calculation on memristor arrays represented by RRAM. Therefore, how to design a read-write peripheral circuit for large-scale RRAM arrays that can achieve efficient weight writing to the RRAM array and data calculation has become one of the key issues in promoting the maturity of high-efficiency storage and computing chips based on RRAM memristors. Summary of the Invention

[0005] In response to the above-mentioned defects or improvement needs of the prior art, the present invention provides a read-write multiplexing circuit and an RRAM storage and computing system applied to an RRAM storage and computing array, the purpose of which is to realize parallel writing of weights, improve the efficiency of weight writing, and reuse the same circuit in the write mode and the computing mode, thereby reducing the chip area overhead.

[0006] To achieve the above object, according to one aspect of the present invention, a read-write multiplexing circuit applied to an RRAM storage and computing array is provided, which includes: a bit line control module and a signal line control module;

[0007] The bit line control module includes a bit line drive selection circuit and M bit line clamp drive circuits. Each bit line clamp drive circuit includes a bit line digital-to-analog converter, a bit line drive circuit, and a demultiplexer connected in sequence. The bit line drive selection circuit is controlled by a bit line drive selection signal to activate the desired bit line drive circuit. The demultiplexer is a single-input multi-output selector, and its different output terminals are used to connect to different bit lines in the storage and computing array. The demultiplexer is controlled by the bit line selection signal to connect the corresponding bit line drive circuit to the target bit line. The bit line clamp drive circuit is used to receive an external bit line digital signal. The bit line digital signal is converted into an analog voltage by the bit line digital-to-analog converter in the corresponding bit line clamp drive circuit, and then loaded onto the target bit line through the bit line drive circuit and the demultiplexer.

[0008] The signal line control module includes a signal line drive selection circuit and K signal line clamping drive circuits. Each of the signal line clamping drive circuits includes a signal line digital-to-analog converter, a multiplexer, and a signal line drive circuit. The multiplexer and the signal line drive circuit are connected in a one-to-one correspondence. The signal line drive selection circuit is controlled by a signal line drive selection signal to start the required signal line drive circuit. The multiplexer is a multi-input single-output selector and its different input ends are used to connect to different signal lines in the storage and computing array. The multiplexer is controlled by the signal line selection signal to connect the target signal line to the corresponding signal line drive circuit. The signal line digital-to-analog converter is used to receive an external input signal line digital signal and convert it into an analog voltage signal, which is then loaded onto the target signal line through the signal line drive circuit and the multiplexer. The current of each target signal line is input into the corresponding signal line drive circuit through the multiplexer and converted into an output voltage.

[0009] Wherein, M and K are both positive integers greater than 1.

[0010] Optionally, K signal line clamp driving circuits share one signal line digital-to-analog converter, and analog voltage signals output by the signal line digital-to-analog converter are respectively connected to the K signal line driving circuits.

[0011] Optionally, the bit line selection signal and the signal line selection signal are both multi-bit digital signals, the demultiplexer decodes the received bit line selection signal and connects it to the target bit line according to the decoding result; the multiplexer decodes the received signal line selection signal and connects it to the target signal line according to the decoding result.

[0012] Optionally, the bit line drive selection signal is an m_1-bit digital signal, and the signal line drive selection signal is an m_2-bit digital signal, where m_1 and m_2 are both positive integers greater than 0;

[0013] The bit line drive selection circuit includes a decoder and an OR gate, wherein: the decoder is used to decode the received m_1 bit bit line drive selection signal, and the 2 m_1 Different output terminals are connected to 2 m_1 Different OR gate inputs, 2 m_1 Different OR gates and 2 m_1 The bit line drive circuits of each group correspond to each other one by one. The output result of each OR gate controls the start of the corresponding bit line drive circuit. Each bit line drive circuit contains M / 2 m_1 a bit line driver circuit;

[0014] The signal line drive selection circuit includes a decoder and an OR gate, wherein: the decoder is used to decode the received m_2 bit signal line drive selection signal, and the 2 m_2 Different output terminals are connected to 2 m_2 Different OR gate inputs, 2 m_2 Different OR gates and 2 m_2 The signal line drive circuits of each group correspond to each other one by one. The output result of each OR gate controls the start of the corresponding signal line drive circuit. Each group of bit line drive circuits contains K / 2 m_2 a signal line driver circuit;

[0015] The other input end of all OR gates in the bit line drive selection circuit and the signal line drive selection circuit is used to access the mode selection level. When the weight write mode is selected, the mode selection level is a low level, and when the calculation mode is selected, the mode selection level is a high level.

[0016] Optionally, the bit line driver selection circuit starts the corresponding bit line driver circuit by controlling access to a bias current.

[0017] Optionally, both the bit line digital signal and the signal line digital signal are 8-bit digital signals, and the 8-bit digital signals are converted into analog voltages within a range of 0-1.5V by corresponding digital-to-analog converters.

[0018] Optionally, the bit line driving circuit and the signal line driving circuit both include an operational amplifier, the output end of each digital-to-analog converter is connected to the positive input end of the corresponding operational amplifier, the reverse input end of the operational amplifier in the bit line driving circuit is connected to its output end, and the reverse input end of the operational amplifier in the signal line driving circuit is connected to its output end through a resistor.

[0019] Optionally, the operational amplifier is a class AB complementary output operational amplifier.

[0020] Optionally, the operational amplifier includes MOS transistors M1 to M24 and current sources P1 to P6, wherein: M1, M3, M6, M7, M9, M12, M13, M16, M21, M22, M23, and M24 are all NMOS transistors, and the rest are PMOS transistors. The current of each current source is proportional to the external input bias current, P1 and P3 are the same, and P2 and P4 are the same.

[0021] M1 and M2 are connected in series between the voltage source interface and the ground in sequence;

[0022] M5, M4, M3 and P1 are connected in series between the voltage source interface and the ground in sequence, with the gate and drain of M5 short-circuited, the gate and drain of M4 short-circuited, and P2 connected between the drain of M3 and the ground;

[0023] P3, M8, M7 and M6 are connected in series between the voltage source interface and the ground in sequence, with the gate and drain of M7 short-circuited, the gate and drain of M6 short-circuited, and P4 connected between the voltage source interface and the drain of M8;

[0024] M17, M19, M10, M21 and M23 are connected in series between the voltage source interface and the ground in sequence, the gate of M17 is short-circuited with the drain of M19, the gate of M23 is short-circuited with the drain of M21, the drain of M9 is short-circuited with the source of M10, and the source of M9 is short-circuited with the drain of M10;

[0025] M18, M20, M12, M22 and M24 are connected in series between the voltage source interface and the ground in sequence, the gate of M18 is short-circuited with the gate of M17, the gate of M20 is short-circuited with the gate of M19, the gate of M22 is short-circuited with the gate of M21, the gate of M24 is short-circuited with the gate of M23, the drain of M11 is short-circuited with the source of M12, the source of M11 is short-circuited with the drain of M12, the gate of M11, the gate of M10 and the drain of M4 are short-circuited, and the gate of M12, the gate of M9 and the drain of M8 are short-circuited;

[0026] M13 and P5 are connected in series between the drain of M18 and the ground in sequence, the drain of M16 is short-circuited with the drain of M17, and the source of M16 is short-circuited with the source of M13;

[0027] P6 and M14 are connected in series between the voltage source interface and the source of M22 in sequence, the source of M15 is short-circuited with the source of M14, and the drain of M15 is short-circuited with the drain of M23;

[0028] Among them, the voltage source interface is used to access the voltage VDD, the gates of M13 and M14 are short-circuited and serve as the positive input terminal of the op amp, the gates of M15 and M16 are short-circuited and serve as the reverse input terminal of the op amp, the drain of M1 serves as the output terminal of the op amp, the gate of M8 is used to access the mode selection level, and the gate of M3 is used to access the inversion of the mode selection level. When the weight write mode is selected, the mode selection level is low, and when the calculation mode is selected, the mode selection level is high.

[0029] According to a second aspect of the present invention, there is provided an RRAM storage and computing system, comprising:

[0030] RRAM storage and computing array;

[0031] A read-write multiplexing circuit applied to an RRAM storage and computing array as described in any one of the above items; and

[0032] A controller is provided for controlling a bit line control module and a signal line control module according to a current mode; controlling the bit line control module includes: applying a bit line drive selection signal to a bit line drive selection circuit to start the bit line drive circuit required for the current mode, applying a bit line selection signal to a demultiplexer to connect the corresponding bit line drive circuit to a target bit line; applying a bit line digital signal to a bit line clamp drive circuit, converting the bit line digital signal into an analog voltage via the bit line digital-to-analog converter in the corresponding bit line clamp drive circuit, and then loading the bit line to the target bit line via the bit line drive circuit and the demultiplexer; controlling the signal line control module includes: applying a signal line drive selection signal to a signal line drive selection circuit to start the signal line drive circuit required for the current mode, applying a signal line selection signal to a multiplexer to connect the target signal line to the corresponding signal line drive circuit, applying a signal line digital signal to a signal line digital-to-analog converter, converting the signal line digital signal into an analog voltage signal via the signal line digital-to-analog converter, and then loading the target signal line via the signal line drive circuit and the multiplexer.

[0033] In general, the above technical solutions conceived by the present invention have the following beneficial effects compared with the prior art:

[0034] The read / write multiplexing circuit provided by the present invention is designed for a bit line control module and a signal line control module: in the bit line control module, a bit line drive selection circuit selects a number of bit line clamp drive circuits from M bit line clamp drive circuits to enter operation, and each bit line clamp drive circuit is connected to a different bit line through a demultiplexer, and the demultiplexer selects and connects a target bit line. By combining the bit line drive selection circuit and the demultiplexer, voltage can be applied to the required number of target bit lines at the same time; in the signal line control module, a number of bit line clamp drive circuits are selected from K signal line clamp drive circuits to enter operation through the signal line drive selection circuit, and Each signal line clamp driver circuit is connected to a different signal line through a multiplexer. The multiplexer selects the target signal line to be connected. Combined with the signal line driver selection circuit and the multiplexer, it is possible to simultaneously apply voltage to the required number of target signal lines. Based on the above multiplexing circuit, when writing weights, by selecting a target bit line and a target signal line, it is possible to write weights to a single RRAM. By selecting multiple target bit lines or target signal lines, it is possible to simultaneously write weights to multiple RRAMs. When performing matrix calculations, by selecting multiple target bit lines and target signal lines, the RRAM array can perform calculations. Therefore, based on the above read-write multiplexing circuit, circuit multiplexing of the read and write process can be realized, reducing the area overhead of the peripheral circuit, and also realizing parallel operation of the write process, improving the efficiency of the weight mapping process. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 FIG. 1 is a curve of electrical characteristic parameters of an RRAM in an embodiment.

[0036] Figure 2 2 is a schematic structural diagram of a read-write multiplexing circuit in an embodiment of the present invention.

[0037] Figure 3 1 is a schematic structural diagram of a bit line driver selection circuit in one embodiment of the present invention.

[0038] Figure 4 1 is a schematic structural diagram of a class AB complementary output operational amplifier in one embodiment of the present invention.

[0039] Figure 5 1 is a transient curve of the voltage across different target RRAMs in a parallel reset process in an embodiment of the present invention.

[0040] Figure 6 1 is a transient curve of the voltage across the RRAM in a parallel Set process in one embodiment of the present invention.

[0041] Figure 7 1 is a transient curve of differential output current with different weights in a calculation mode in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0043] The RRAM storage array is a 1T1R array used to implement matrix multiplication operations, which includes RRAM devices and NMOS switches. The RRAM device is used to store the weights corresponding to the algorithm in the form of conductance. Figure 1 The figure shows the electrical characteristic parameter curves of an RRAM in one embodiment. When the operating voltage is 0.8 V and -0.9 V, respectively, the RRAM resistance changes, enabling Set and Reset write operations, i.e., the corresponding weight write process. When the voltage across the RRAM is between -0.9 V and 0.8 V, the RRAM resistance remains unchanged, and the operating voltage across it can be linearly converted into current, i.e., the read calculation process for a single device. NMOS switches control whether the branch containing the target RRAM is open. The array comprises a bit line (BL), a signal line (SL), and a word line (WL). Typically, the WL is parallel to the SL, and the BL is perpendicular to both the WL and SL. A voltage is applied to the corresponding BL via a BL clamp driver circuit, and a voltage is applied to the corresponding SL via an SL clamp driver circuit. The WL controls the on / off of the RRAM branch. According to Kirchhoff's law I = G·V, the voltage difference between the BL and SL clamp driver circuits is converted into a calculated analog current vector, which is input into the SL clamp driver circuit to produce an output voltage representing the calculated result.

[0044] In a first aspect, the present invention provides a read-write multiplexing circuit applied to a RRAM storage array, such as Figure 2 FIG2 is a schematic structural diagram of a read / write multiplexing circuit in an embodiment of the present invention, which includes a bit line control module and a signal line control module;

[0045] The bit line control module includes a bit line drive selection circuit and M bit line clamp drive circuits. Each bit line clamp drive circuit includes a bit line digital-to-analog converter, a bit line drive circuit, and a demultiplexer connected in sequence. The bit line drive selection circuit is controlled by a bit line drive selection signal to activate the desired bit line drive circuit. The demultiplexer is a single-input multi-output selector, and its different output terminals are used to connect to different bit lines in the storage and computing array. The demultiplexer is controlled by the bit line selection signal to connect the corresponding bit line drive circuit to the target bit line. The bit line clamp drive circuit is used to receive an external bit line digital signal. The bit line digital signal is converted into an analog voltage by the bit line digital-to-analog converter in the corresponding bit line clamp drive circuit, and then loaded to the target bit line through the bit line drive circuit and the demultiplexer.

[0046] The signal line control module includes a signal line drive selection circuit and K signal line clamping drive circuits. Each signal line clamping drive circuit includes a signal line digital-to-analog converter, a multiplexer and a signal line drive circuit. The multiplexer and the signal line drive circuit are connected one-to-one. The signal line drive selection circuit is controlled by the signal line drive selection signal to start the required signal line drive circuit. The multiplexer is a multi-input single-output selector and its different input ends are used to connect to different signal lines in the storage and computing array. The multiplexer is controlled by the signal line selection signal to connect the target signal line to the corresponding signal line drive circuit. The signal line digital-to-analog converter is used to receive the external input signal line digital signal and convert it into an analog voltage signal and then load it to the target signal line through the signal line drive circuit. The current of each target signal line is input into the corresponding signal line drive circuit through the multiplexer and converted into an output voltage.

[0047] Specifically, the bit line clamp driver circuit is used to convert the digital signal into an analog voltage and load it to the lower electrode of the target RRAM device. The signal line clamp driver circuit is used to convert the digital signal into an analog voltage and load it to the upper electrode of the target RRAM device. This creates a voltage difference in the target RRAM device, enabling operations or weight writing.

[0048] The above read-write multiplexing circuit is used to design the bit line control module and the signal line control module: in the bit line control module, a number of bit line clamp drive circuits are selected from M bit line clamp drive circuits through the bit line drive selection circuit to enter operation, and each bit line clamp drive circuit is connected to a different bit line through a demultiplexer, and the target bit line is selected and connected through the demultiplexer. By combining the bit line drive selection circuit and the demultiplexer, it is possible to simultaneously load voltage to the required number of target bit lines; in the signal line control module, a number of bit line clamp drive circuits are selected from K signal line clamp drive circuits through the signal line drive selection circuit to enter operation, and each bit line clamp drive circuit is connected to a different bit line through a demultiplexer. The signal line clamp drive circuit is connected to different signal lines through a multiplexer. The multiplexer selects the target signal line to be connected. Combined with the signal line drive selection circuit and the multiplexer, it is possible to simultaneously apply voltage to the required number of target signal lines. Based on the above multiplexing circuit, when writing weights, by selecting a target bit line and a target signal line, it is possible to write weights to a single RRAM. By selecting multiple target bit lines or target signal lines, it is possible to simultaneously write weights to multiple RRAMs. When performing matrix calculations, by selecting multiple target bit lines and target signal lines, the RRAM array can perform calculations. Therefore, based on the above read-write multiplexing circuit, circuit multiplexing of the read and write process can be realized, reducing the area overhead of the peripheral circuit, and it can also realize parallel operation of the write process, improving the efficiency of the weight mapping process.

[0049] In one embodiment, both the bit line digital signal and the signal line digital signal are 8-bit digital signals, and the 8-bit digital signals are converted into analog voltages within a range of 0-1.5V by corresponding digital-to-analog converters.

[0050] In one embodiment, K signal line clamp driver circuits share a single signal line digital-to-analog converter. That is, the signal line control module includes only one signal line digital-to-analog converter, and the analog voltage signals output by the signal line digital-to-analog converter are connected to the K signal line driver circuits. In this way, a single digital signal can be input to provide driving voltages for the K signal line driver circuits.

[0051] In one embodiment, the bit line selection signal and the signal line selection signal are both multi-bit digital signals. The demultiplexer decodes the received bit line selection signal and connects it to the target bit line according to the decoding result; the multiplexer decodes the received signal line selection signal and connects it to the target signal line according to the decoding result.

[0052] For example, let the bit line selection signal be SEL_sub_BL and the signal line selection signal be SEL_sub_SL. Assuming that SEL_sub_BL is an n_1-bit digital signal and SEL_sub_SL is an n_2-bit digital signal, and n_1 and n_2 are both positive integers greater than 1, the demultiplexer can have 2n_1 A decoding result, a complex decoder can be connected to 2 n_1 Different bit lines, different decoding results correspond to the selection of different bit lines. Similarly, the multiplexer can also have 2 n_2 decoding results, one decoder can be connected to 2 n_2 Different signal lines are selected according to different decoding results. The present invention has M bit line clamping drive circuits and K signal line clamping drive circuits. Therefore, the size of the RRAM memory array that can be controlled is (M×2 n_1 )×(K×2 n_2 ), different modes of operating voltages are loaded onto BL and SL, and then write or calculation operations are performed through the pulse start signal loaded on the target WL.

[0053] In one embodiment, the bit line drive selection signal is an m_1-bit digital signal, and the signal line drive selection signal is an m_2-bit digital signal, where m_1 and m_2 are both positive integers greater than 0; for example, the bit line drive selection signal is recorded as SEL_top_BL, and the signal line drive selection signal is recorded as SEL_top_SL;

[0054] The bit line drive selection circuit includes a decoder and an OR gate, wherein: the decoder is used to decode the received m_1 bit bit line drive selection signal SEL_top_BL, and the 2 m_1 Different output terminals are connected to 2 m_1 Different OR gate inputs, 2 m_1 Different OR gates and 2 m_1 The bit line drive circuits of each group correspond to each other one by one. The output result of each OR gate controls the start of the corresponding bit line drive circuit. Each bit line drive circuit contains M / 2 m_1 a bit line driver circuit;

[0055] The signal line drive selection circuit includes a decoder and an OR gate, wherein: the decoder is used to decode the received m_2 bit signal line drive selection signal SEL_top_SL, and the 2 m_2 Different output terminals are connected to 2 m_2 Different OR gate inputs, 2 m_2 Different OR gates and 2 m_2 The signal line drive circuits of each group correspond to each other one by one. The output result of each OR gate controls the start of the corresponding signal line drive circuit. Each group of bit line drive circuits contains K / 2 m_2 a signal line driver circuit;

[0056] The other input end of all OR gates in the bit line driver selection circuit and the signal line driver selection circuit is used to access the mode selection level. When the weight write mode is selected, the mode selection level is low, and when the calculation mode is selected, the mode selection level is high.

[0057] like Figure 3 The figure shows a schematic diagram of the structure of a bit line driver selection circuit in one embodiment of the present invention. For example, assuming M = 32 and m_1 = 4, the decoder is a 4-line to 16-line decoder with 16 output terminals, each of which is connected to a corresponding OR gate. The other input terminal of the OR gate is used to access the mode selection level EN_Cal. The 32 bit line driver circuits can be divided into 16 groups, each with two bit line driver circuits. Different OR gates control the activation of different groups of bit line driver circuits. If the OR gate outputs a high level, the bit line driver circuit of the corresponding group is activated. If the OR gate outputs a low level, the bit line driver circuit of the corresponding group cannot be activated. Specifically, the bit line driver selection circuit applies a bias current lb to the corresponding first to Mth bit line driver circuits. <1> ~lb <m>, and controls the on / off switching of the bias current access branch, thereby selecting the corresponding bit line driver circuit to receive the bias current. The bit line driver circuit that receives the bias current is activated; otherwise, it is disabled. For example, a 5uA current is generated by an internal reference current source and applied to each driver by a current mirror. By controlling the on / off switching of the current mirror branch through a decoder and an OR gate, different numbers of active BL drivers can be achieved in calculation and write modes, avoiding the additional area overhead of using separate decoders and switches for each mode.

[0058] In the above embodiment, by combining the decoder and the OR gate and using one of the input terminals of the OR gate to access the mode selection level, when weight selection is required, it is only necessary to set the mode selection level to a low level. At this time, the corresponding driving circuit will be started according to the driving selection signal received by the decoder, and then the target RRAM write weight will be selected. When matrix operation is required, it is only necessary to set the mode selection level to a high level. At this time, the output of the OR gate is not affected by the driving selection signal, and directly outputs a high level to start all driving circuits, thereby realizing the matrix operation.

[0059] In one embodiment, the bit line driving circuit and the signal line driving circuit both include an operational amplifier, the output end of each digital-to-analog converter is connected to the positive input end of the corresponding operational amplifier, the negative input end of the operational amplifier in the bit line driving circuit is connected to its output end, and the negative input end of the operational amplifier in the signal line driving circuit is connected to its output end through a resistor.

[0060] In this embodiment, in the bit line clamp driving circuit, the output end of the bit line digital-to-analog converter is connected to the positive input end of the bit line driving circuit, and the reverse input end of the bit line driving circuit is connected to its output end. The above bit line driving circuit can load the analog voltage output by the bit line digital-to-analog converter to the target RRAM and provide sufficient driving current for the RRAM, thereby avoiding the output voltage deviation caused by insufficient driving capability of the direct digital-to-analog converter; in the signal line clamp driving circuit, the output end of the signal line digital-to-analog converter is connected to the positive input end of the signal line driving circuit, and the reverse input end of the signal line driving circuit is connected to its output end through a resistor. The above signal line driving circuit can load the analog voltage output by the signal line digital-to-analog converter to the target RRAM and convert the analog current output by the signal line into an analog voltage output.

[0061] In one embodiment, the operational amplifiers are all class AB complementary output operational amplifiers, thereby reducing waveform distortion.

[0062] In one embodiment, the operational amplifier has different current drive requirements in weight write mode and matrix operation mode. For example, when in a low-resistance state of 1kΩ, a reset operation on the RRAM requires applying an operating voltage of 0.9V, resulting in a current of 0.9mA flowing through the RRAM. When performing matrix calculations, the maximum voltage difference across the RRAM is 0.3V, resulting in a maximum current of 0.3mA flowing through the RRAM. To ensure that the operational amplifier has different drive capabilities in different modes, this embodiment also designs a Class AB complementary output operational amplifier.

[0063] like Figure 4 FIG2 is a schematic diagram of the structure of a class AB complementary output operational amplifier in an embodiment of the present invention, which includes MOS transistors M1 to M24 and current sources P1 to P6. Among them, M1, M3, M6, M7, M9, M12, M13, M15, M21, M22, M23, and M24 are all NMOS transistors, and the rest are PMOS transistors. The current of each current source is proportional to the bias current. P1 and P3 are the same, and P2 and P4 are the same.

[0064] M1 and M2 are connected in series between the voltage source interface and the ground in sequence;

[0065] M5, M4, M3 and P1 are connected in series between the voltage source interface and the ground in sequence, with the gate and drain of M5 short-circuited, the gate and drain of M4 short-circuited, and P2 connected between the drain of M3 and the ground;

[0066] P3, M8, M7 and M6 are connected in series between the voltage source interface and the ground in sequence, with the gate and drain of M7 short-circuited, the gate and drain of M6 short-circuited, and P4 connected between the voltage source interface and the drain of M8;

[0067] M17, M19, M10, M21 and M23 are connected in series between the voltage source interface and the ground in sequence, the gate of M17 is short-circuited with the drain of M19, the gate of M23 is short-circuited with the drain of M21, the drain of M9 is short-circuited with the source of M10, and the source of M9 is short-circuited with the drain of M10;

[0068] M18, M20, M12, M22 and M24 are connected in series between the voltage source interface and the ground in sequence, the gate of M18 is short-circuited with the gate of M17, the gate of M20 is short-circuited with the gate of M19, the gate of M22 is short-circuited with the gate of M21, the gate of M24 is short-circuited with the gate of M23, the drain of M11 is short-circuited with the source of M12, the source of M11 is short-circuited with the drain of M12, the gate of M11, the gate of M10 and the drain of M4 are short-circuited, and the gate of M12, the gate of M9 and the drain of M8 are short-circuited;

[0069] M13 and P5 are connected in series between the drain of M18 and the ground in sequence, the drain of M16 is short-circuited with the drain of M17, and the source of M16 is short-circuited with the source of M13;

[0070] P6 and M14 are connected in series between the voltage source interface and the source of M22 in sequence, the source of M15 is short-circuited with the source of M14, and the drain of M15 is short-circuited with the drain of M23;

[0071] Among them, the voltage source interface is used to access the voltage VDD, the gates of M13 and M14 are short-circuited and serve as the positive input terminal of the op amp, the gates of M15 and M16 are short-circuited and serve as the reverse input terminal of the op amp, the drain of M1 serves as the output terminal of the op amp, the gate of M8 is used to access the mode selection level, and the gate of M3 is used to access the inversion of the mode selection level. When the weight write mode is selected, the mode selection level is low, and when the calculation mode is selected, the mode selection level is high.

[0072] In conventional op amps, the current driving capability is mainly determined by M1 and M2. For each MOS transistor in M1 and M2, when in normal operation, the MOS transistor is in the saturation region. Without considering the channel length modulation effect, the output current satisfies the following formula:

[0073] ;

[0074] Where, I D is the drain current flowing through the MOS (regardless of direction), μ is the mobility of MOS carriers, C ox is the gate oxide capacitance of MOS, V GS is the gate-source voltage of MOS, V TH is the threshold voltage of MOS, W and L are the channel width and length respectively. That is, the greater the gate-source voltage of M1 and M2, the stronger the current drive that can be achieved. However, when there is no current output, , the excessive driving capability leads to a large static current between M1 and M2, which means the deterioration of power consumption and energy efficiency, which is a huge bottleneck for the application of RRAM storage and computing arrays in large-scale and efficient matrix operations.

[0075] In this embodiment, M3 and M8 are introduced to adjust the current driving capability of the operational amplifier in the weight writing mode and the matrix operation mode respectively.

[0076] For M1-M12, the voltage relationship is as follows:

[0077] ;

[0078] ;

[0079] Right now:

[0080] ;

[0081] ;

[0082] Where V Bp is the drain voltage of M3, V Bn is the drain voltage of M7, VGS k is the gate-source voltage of the Kth MOS tube.

[0083] The current flowing through M4-M7 is I, which satisfies:

[0084] ;

[0085] ;

[0086] Where μ p is the PMOS carrier mobility, μ n is the mobility of NMOS carriers.

[0087] Therefore, adjusting the current of M4-M7 can adjust the gate-source voltage of M1 and M2, and as the current I increases, the gate-source voltage V GS1 、V GS2 Increase, add M3 and M8 as the switch MOS tube of the auxiliary current source branch, and are controlled by the mode selection level EN_Cal signal and its inverted signal EN_Cal_n. When the weight write mode is selected, EN_Cal is low, EN_Cal_n is high, M3 and M8 are turned on, I=I0+I1, and the gate-source voltage of M1 and M2 is V GS1 、V GS2 The larger the current drive of the op amp, the stronger it is. When the calculation mode is selected, EN_Cal is high, EN_Cal_n is low, M3 and M8 are turned off, I=I0, and the gate-source voltage of M1 and M2 is V GS1 、V GS2 As the value becomes smaller, the current drive of the op amp becomes smaller, so the required drive current can be adjusted according to different modes.

[0088] In a second aspect, the present invention provides an RRAM storage and computing system, comprising:

[0089] RRAM storage and computing array;

[0090] The read-write multiplexing circuit applied to the RRAM storage array as described in the first aspect; and

[0091] A controller is used to control the bit line control module and the signal line control module according to the current mode; controlling the bit line control module includes: applying a bit line drive selection signal to the bit line drive selection circuit to start the bit line drive circuit required for the current mode, applying a bit line selection signal to the demultiplexer to connect the corresponding bit line drive circuit to the target bit line; applying a bit line digital signal to the bit line clamp drive circuit, the bit line digital signal is converted into an analog voltage by the bit line digital-to-analog converter in the corresponding bit line clamp drive circuit, and then loaded to the target bit line through the bit line drive circuit and the demultiplexer; controlling the signal line control module includes: applying a signal line drive selection signal to the signal line drive selection circuit to start the signal line drive circuit required for the current mode, applying a signal line selection signal to the multiplexer to connect the target signal line to the corresponding signal line drive circuit, applying a signal line digital signal to the signal line digital-to-analog converter, the signal line digital signal is converted into an analog voltage signal by the signal line digital-to-analog converter, and then loaded to the target signal line through the signal line drive circuit and the multiplexer.

[0092] The working process of the read-write multiplexing circuit in the present invention is described below with reference to a specific example.

[0093] M=32, n_1= n_2=n=5, K=32, the RRAM array size is 1024×1024, and the read-write multiplexing circuit includes 32 BL driving circuits and demultiplexers DEMUX and 32 SL driving circuits and multiplexers MUX.

[0094] Assuming m_1 = 2, the decoder in the bit line control module can correspond to four decoding results. Therefore, the 32 bit line driver circuits are divided into four groups, each containing eight BL driver circuits. The first group is numbered [1:8], the second group is numbered [9:16], the third group is numbered [17:24], and the fourth group is numbered [25:32]. The bit line control module activates the required BL driver circuit group.

[0095] Assume that m_2=5, each group of signal line driver circuits contains only one signal line driver circuit, that is, each of the 32 signal line driver circuits is independently controlled;

[0096] Since M=32, 1024 BLs can be divided into 32 groups. Each group of BLs has 32 BLs. 32 BL driving circuits are connected to the 32 groups of BLs through 32 demultiplexers DEMUX. Each BL driving circuit is connected to one of the 32 BLs in the corresponding group through the demultiplexer DEMUX. The i-th BL driving circuit corresponds to the i-th group of BLs. The j-th BL in the i-th group of BLs is numbered as BL.<j+32(i-1)> ;

[0097] Since K=32, 1024 SLs can be divided into 32 groups. Each group of SLs has 32 SLs. 32 SL driving circuits are connected to the 32 groups of SLs through 32 multiplexers MUX. Each BL driving circuit is connected to one of the 32 SLs in the corresponding group through the multiplexer MUX. The i-th SL driving circuit corresponds to the i-th group of SLs. The j-th SL in the i-th group of SLs is numbered as SL.<j+32(i-1)> .

[0098] When weight writing mode is selected:

[0099] When EN_Cal is low and SEL_top_BL is a 2-bit digital vector of 00, the bit line driver selection circuit applies a bias reference current only to the first group of BL driver circuits, that is, to the BL driver circuits numbered [1:8], enabling them. The remaining BL drivers are not biased and are off. When SEL_sub_BL is a 5-bit digital vector of 00001, the driving voltage output by the eight BL driver circuits numbered [1:8] is applied only to the second BL in its corresponding group of BLs, that is, to the target BLs numbered BL<2+32(i-1)> (i=1,2,3,4,5,6,7,8).

[0100] Similarly, the SL clamp driver adopts the same operation logic. Assuming that SEL_top_SL is a 5-bit digital vector 11111, the selected number is <32> SL driving circuit, assuming that SEL_sub_BL is a 5-bit digital vector 00001, the number is <32> The SL drive circuit is numbered SL <994> Apply voltage to the target SL;

[0101] By determining the target BL and target SL, the target RRAM can be determined;

[0102] When a reset operation is required for the target RRAM, an 8-bit digital signal 10111111 is input to the bit line DACs corresponding to the eight BL driver circuits numbered [1:8], which are converted into an analog voltage of 1.35V and loaded to the target BL<2+32(i-1)> (i=1,2,3,4,5,6,7,8) determined above through the bit line driver circuit and the demultiplexer; ... <32> The 8-bit digital signal 01000000 is input to the signal line digital-to-analog converter corresponding to the SL driving circuit, and is converted into an analog voltage of 0.45 V and loaded into the target SL determined above through the signal line driving circuit and the multiplexer. <994> , applying an on pulse to the target WL, a voltage difference of 1.35V -0.45V = 0.9V can be applied to the eight RRAMs in the target column to achieve a parallel reset operation, increasing the resistance of the RRAMs; Figure 5 The figure shows the transient curve of the voltage across the RRAM during the parallel reset process.<x,y> Representative BL <x>SL <y>Corresponding RRAM;

[0103] When a Set operation is required for the target RRAM, the 8-bit digital signal 01000000 is input to the bit line DACs corresponding to the 8 BL driver circuits numbered [1:8], converted into an analog voltage of 0.45V and loaded to the target BL<2+32(i-1)> (i=1,2,3,4,5,6,7,8) determined above through the bit line driver circuit and the demultiplexer. <32> The signal line digital-to-analog converter corresponding to the SL driving circuit inputs the 8-bit digital signal 10110001, which is converted into an analog voltage of 1.25 V and loaded into the target SL determined above through the signal line driving circuit and the multiplexer. <994> By applying an on pulse to the target WL, a voltage difference of 1.25V -0.45V = 0.8V can be applied to the eight RRAMs in the target column to achieve a parallel Set operation, reducing the resistance of the RRAM. Figure 6 The figure shows the transient curve of the voltage across the RRAM during the parallel Set process.

[0104] When weight writing mode is selected:

[0105] EN_Cal is at a high level. Regardless of how the SEL_top_BL digital vector changes, the bit line driver selection circuit applies a bias reference current to all BL driver circuit numbers [1:32]. All BL drivers are in the on state, and the DAC provides a reference voltage in the range of 0.3V-0.6V as the voltage vector input. When the input SEL_sub_BL digital signal vector is 00001, the voltage output by the BL driver end will only be loaded to BL<2+32(i-1)> (i=1:32). Similarly, the SL end will turn on all SL clamp op amps in the matrix operation mode, and provide a reference voltage of 0.3V through the DAC. The input voltage difference vector is converted into a current vector through Kirchhoff's current law KCL to realize vector-matrix multiplication. For example Figure 7 The figure shows the transient curves of the differential output current for different weights in the calculation mode. Specifically, it shows the calculated current difference between the signal line with an RRAM resistance distribution of R1 and the signal line with an RRAM resistance distribution of R2. Different weights correspond to different differential output currents.

[0106] The technical features of the above embodiments may be combined in any manner. To simplify the description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there are no conflicts in the combination of these technical features, they should be considered to be within the scope of this specification. It should be noted that the phrases "in one embodiment," "for example," and "another example" are intended to illustrate the present invention and are not intended to limit the present invention.

[0107] The above embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, and all such variations and improvements fall within the scope of protection of the present invention.< / y> < / x> < / m>

Claims

1. A read-write multiplexing circuit applied to an RRAM storage and computing array, characterized in that: include: A bit line control module and a signal line control module; The bit line control module includes a bit line drive selection circuit and M bit line clamp drive circuits. Each bit line clamp drive circuit includes a bit line digital-to-analog converter, a bit line drive circuit, and a demultiplexer connected in sequence. The bit line drive selection circuit is controlled by a bit line drive selection signal to activate the desired bit line drive circuit. The demultiplexer is a single-input multi-output selector, and its different output terminals are used to connect to different bit lines in the storage and computing array. The demultiplexer is controlled by the bit line selection signal to connect the corresponding bit line drive circuit to the target bit line. The bit line clamp drive circuit is used to receive an external bit line digital signal. The bit line digital signal is converted into an analog voltage by the bit line digital-to-analog converter in the corresponding bit line clamp drive circuit, and then loaded onto the target bit line through the bit line drive circuit and the demultiplexer. The signal line control module includes a signal line drive selection circuit and K signal line clamping drive circuits. Each of the signal line clamping drive circuits includes a signal line digital-to-analog converter, a multiplexer, and a signal line drive circuit. The multiplexer and the signal line drive circuit are connected in a one-to-one correspondence. The signal line drive selection circuit is controlled by a signal line drive selection signal to start the required signal line drive circuit. The multiplexer is a multi-input single-output selector and its different input ends are used to connect to different signal lines in the storage and computing array. The multiplexer is controlled by the signal line selection signal to connect the target signal line to the corresponding signal line drive circuit. The signal line digital-to-analog converter is used to receive an external input signal line digital signal and convert it into an analog voltage signal, which is then loaded onto the target signal line through the signal line drive circuit and the multiplexer. The current of each target signal line is input into the corresponding signal line drive circuit through the multiplexer and converted into an output voltage. Wherein, M and K are both positive integers greater than 1.

2. The read-write multiplexing circuit according to claim 1, wherein: K signal line clamp driving circuits share one signal line digital-to-analog converter, and the analog voltage signals output by the signal line digital-to-analog converter are respectively connected to the K signal line driving circuits.

3. The read-write multiplexing circuit according to claim 1, wherein: The bit line selection signal and the signal line selection signal are both multi-bit digital signals. The demultiplexer decodes the received bit line selection signal and connects it to the target bit line according to the decoding result; the multiplexer decodes the received signal line selection signal and connects it to the target signal line according to the decoding result.

4. The read-write multiplexing circuit according to claim 1, wherein: The bit line drive selection signal is an m_1-bit digital signal, and the signal line drive selection signal is an m_2-bit digital signal, where m_1 and m_2 are both positive integers greater than 0; The bit line drive selection circuit includes a decoder and an OR gate, wherein: the decoder is used to decode the received m_1 bit bit line drive selection signal, and the 2 m_1 Different output terminals are connected to 2 m_1 Different OR gate inputs, 2 m_1 Different OR gates and 2 m_1 The bit line drive circuits of each group correspond to each other one by one. The output result of each OR gate controls the start of the corresponding bit line drive circuit. Each bit line drive circuit contains M / 2 m_1 a bit line driver circuit; The signal line drive selection circuit includes a decoder and an OR gate, wherein: the decoder is used to decode the received m_2 bit signal line drive selection signal, and the 2 m_2 Different output terminals are connected to 2 m_2 Different OR gate inputs, 2 m_2 Different OR gates and 2 m_2 The signal line drive circuits of each group correspond to each other one by one. The output result of each OR gate controls the start of the corresponding signal line drive circuit. Each group of bit line drive circuits contains K / 2 m_2 a signal line driver circuit; The other input end of all OR gates in the bit line drive selection circuit and the signal line drive selection circuit is used to access the mode selection level. When the weight write mode is selected, the mode selection level is a low level, and when the calculation mode is selected, the mode selection level is a high level.

5. The read-write multiplexing circuit according to claim 1, wherein: The bit line driver selection circuit starts the corresponding bit line driver circuit by controlling the access of the bias current.

6. The read-write multiplexing circuit according to claim 1, wherein: The bit line digital signal and the signal line digital signal are both 8-bit digital signals, and the 8-bit digital signals are converted into analog voltages within a range of 0-1.5V by corresponding digital-to-analog converters.

7. The read-write multiplexing circuit according to claim 1, wherein: The bit line driving circuit and the signal line driving circuit both include an operational amplifier, the output end of each digital-to-analog converter is connected to the positive input end of the corresponding operational amplifier, the reverse input end of the operational amplifier in the bit line driving circuit is connected to its output end, and the reverse input end of the operational amplifier in the signal line driving circuit is connected to its output end through a resistor.

8. The read-write multiplexing circuit according to claim 7, wherein: The operational amplifier is a class AB complementary output operational amplifier.

9. The read-write multiplexing circuit according to claim 8, wherein: The operational amplifier includes MOS transistors M1 to M24 and current sources P1 to P6, wherein: M1, M3, M6, M7, M9, M12, M13, M16, M21, M22, M23, and M24 are all NMOS transistors, and the rest are PMOS transistors. The current of each current source is proportional to the external input bias current. P1 and P3 are the same, and P2 and P4 are the same. M1 and M2 are connected in series between the voltage source interface and the ground in sequence; M5, M4, M3 and P1 are connected in series between the voltage source interface and the ground in sequence, with the gate and drain of M5 short-circuited, the gate and drain of M4 short-circuited, and P2 connected between the drain of M3 and the ground; P3, M8, M7 and M6 are connected in series between the voltage source interface and the ground in sequence, with the gate and drain of M7 short-circuited, the gate and drain of M6 short-circuited, and P4 connected between the voltage source interface and the drain of M8; M17, M19, M10, M21 and M23 are connected in series between the voltage source interface and the ground in sequence, the gate of M17 is short-circuited with the drain of M19, the gate of M23 is short-circuited with the drain of M21, the drain of M9 is short-circuited with the source of M10, and the source of M9 is short-circuited with the drain of M10; M18, M20, M12, M22 and M24 are connected in series between the voltage source interface and the ground in sequence, the gate of M18 is short-circuited with the gate of M17, the gate of M20 is short-circuited with the gate of M19, the gate of M22 is short-circuited with the gate of M21, the gate of M24 is short-circuited with the gate of M23, the drain of M11 is short-circuited with the source of M12, the source of M11 is short-circuited with the drain of M12, the gate of M11, the gate of M10 and the drain of M4 are short-circuited, and the gate of M12, the gate of M9 and the drain of M8 are short-circuited; M13 and P5 are connected in series between the drain of M18 and the ground in sequence, the drain of M16 is short-circuited with the drain of M17, and the source of M16 is short-circuited with the source of M13; P6 and M14 are connected in series between the voltage source interface and the source of M22 in sequence, the source of M15 is short-circuited with the source of M14, and the drain of M15 is short-circuited with the drain of M23; Among them, the voltage source interface is used to access the voltage VDD, the gates of M13 and M14 are short-circuited and serve as the positive input terminal of the op amp, the gates of M15 and M16 are short-circuited and serve as the reverse input terminal of the op amp, the drain of M1 serves as the output terminal of the op amp, the gate of M8 is used to access the mode selection level, and the gate of M3 is used to access the inversion of the mode selection level. When the weight write mode is selected, the mode selection level is low, and when the calculation mode is selected, the mode selection level is high.

10. A RRAM storage and computing system, characterized in that: include: RRAM storage and computing array; The read-write multiplexing circuit applied to the RRAM storage and computing array according to any one of claims 1 to 9; as well as, A controller, configured to control the bit line control module and the signal line control module according to a current mode; The control of the bit line control module includes: applying a bit line drive selection signal to the bit line drive selection circuit to start the bit line drive circuit required for the current mode, applying a bit line selection signal to the demultiplexer to connect the corresponding bit line drive circuit to the target bit line; applying a bit line digital signal to the bit line clamp drive circuit, the bit line digital signal is converted into an analog voltage by the bit line digital-to-analog converter in the corresponding bit line clamp drive circuit, and then loaded to the target bit line through the bit line drive circuit and the demultiplexer; the control of the signal line control module includes: applying a signal line drive selection signal to the signal line drive selection circuit to start the signal line drive circuit required for the current mode, applying a signal line selection signal to the multiplexer to connect the target signal line to the corresponding signal line drive circuit, applying a signal line digital signal to the signal line digital-to-analog converter, the signal line digital signal is converted into an analog voltage signal by the signal line digital-to-analog converter, and then loaded to the target signal line through the signal line drive circuit and the multiplexer.

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