Chip parallel packaging method and parallel packaging structure

Abstract

According to the chip parallel packaging method and the parallel packaging structure provided by the embodiment of the invention, the two MOS chips are packaged back to back, so that the packaging size of a product is reduced, and the electrical performance of the product is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor packaging technology, and in particular to a chip parallel packaging method and a parallel packaging structure. Background Art

[0002] As the application scope of MOS power devices gradually expands in various industries, the demand for miniaturization of package size gradually increases while the performance of products is improved. The improvement of product performance is accompanied by an increase in chip area, which cannot meet product requirements.

[0003] In the prior art, MOS chip packaging is performed by spacing each chip and connecting it to the pins. This packaging method results in a large package size for the overall product and cannot achieve miniaturization. Therefore, a new packaging method is needed to solve the problems in the prior art. Summary of the Invention

[0004] In order to solve or alleviate the problems in the prior art, an embodiment of the present application provides a chip parallel packaging method, the method comprising:

[0005] The first electrode lead layer is arranged on the front surface of the first MOS chip by a ball planting process, and the second electrode lead layer is arranged on the front surface of the second MOS chip by a ball planting process;

[0006] fixing the second MOS chip on the carrier board;

[0007] The second MOS chip and the second electrode lead layer are covered with the first plastic package;

[0008] Grinding and exposing the second electrode lead layer through a grinding process;

[0009] Electroplating the second electrode lead layer onto the pin;

[0010] Plastic-encapsulate all the pins with a second plastic encapsulation body;

[0011] removing the carrier board to expose the back side of the second MOS chip;

[0012] connecting the back side of the second MOS chip to the back side of the first MOS chip through the first conductive layer;

[0013] Plastic-sealing the first MOS chip and the first electrode lead layer with a third plastic-sealing body;

[0014] Grinding and exposing the first electrode lead layer through a grinding process;

[0015] Electroplating the wiring layer onto the first electrode lead-out layer, and connecting the wiring layer to the pins through the second conductive layer to form a conducting circuit;

[0016] Encapsulating the entire device with a third plastic package;

[0017] The plastic-encapsulated devices are cut into individual chips based on each chip.

[0018] As a preferred embodiment of the present application, both the first conductive layer and the second conductive layer are metal.

[0019] In a second aspect, an embodiment of the present application further provides a chip parallel packaging method, which is prepared by the method described in the first aspect.

[0020] Compared with the prior art, the embodiments of the present application provide a chip parallel packaging method and a parallel packaging structure, which reduce the packaging size of the product and increase the electrical performance of the product by packaging two MOS chips back to back. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. Some specific embodiments of the present application will be described in detail in an illustrative and non-restrictive manner with reference to the drawings. The same reference numerals in the drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the drawings:

[0022] Figure 1 This is a flow chart of a chip parallel packaging method provided by the present application;

[0023] Figures 2 to 11 This is a schematic structural diagram corresponding to each step of a chip parallel packaging method provided in this application. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0025] like Figure 1 As shown, an embodiment of the present application provides a chip parallel packaging method, the method comprising:

[0026] Step S01, disposing a first electrode lead layer on the front surface of a first MOS chip by a ball planting process, and disposing a second electrode lead layer on the front surface of a second MOS chip by a ball planting process;

[0027] It should be noted that the ball implantation process is a relatively common process for those skilled in the art to arrange an electrode lead layer in the semiconductor field, and will not be described in detail here.

[0028] Step S02, as Figure 2 As shown, the second MOS chip is fixed on the carrier board;

[0029] It should be noted that the second MOS chip 1 is fixed on the carrier board 3 , which mainly plays a supporting role. The carrier board 3 can be made of metal or other materials, which is not limited here.

[0030] Step S03, as Figure 3 As shown, the second MOS chip and the second electrode lead layer are covered with a first plastic package;

[0031] It should be noted that the second MOS chip 1 and the second electrode lead-out layer 2 are encapsulated by covering the second MOS chip 1 and the second electrode lead-out layer 2 with the first plastic package body 4 .

[0032] Step S04, as Figure 4 As shown, the second electrode lead layer 2 is exposed by grinding through a grinding process;

[0033] It should be noted that the grinding process is a process well known to those skilled in the art in the semiconductor field. The second electrode lead-out layer 2 is exposed by the grinding process to facilitate the arrangement of pins on the second electrode lead-out layer 2 .

[0034] Step S05, as Figure 5 As shown, the second electrode lead layer 2 is electroplated onto the pin 5;

[0035] It should be noted that the pins are provided to facilitate the extraction of the gate or source.

[0036] Step S06, reference Figure 6 , using a second plastic packaging body 6 to plastic-encapsulate all the pins 5;

[0037] Step S07: removing the carrier board to expose the back side of the second MOS chip;

[0038] It should be noted that the carrier board is removed mainly for connecting the second MOS transistor and the first MOS transistor back to back.

[0039] Step S08, reference Figure 7 As shown, the back side of the second MOS chip 1 is connected to the back side of the first MOS chip 8 through the first conductive layer 7;

[0040] It should be noted that because the second MOS transistor 1 and the first MOS transistor 8 are connected back-to-back, a first conductive layer 7 is provided to lead out the drains of the second MOS transistor 1 and the first MOS transistor 8. The drains of the second MOS transistor 1 and the first MOS transistor 8 can be led out through the first conductive layer 7. In the embodiment of the present application, the first conductive layer 7 is metal.

[0041] Step S09, reference Figure 8 As shown, the first MOS chip 8 and the first electrode lead layer 10 are plastic-sealed with a third plastic sealing body 9;

[0042] Step S10, reference Figure 9 As shown, the first electrode lead-out layer 10 is exposed by grinding through a grinding process;

[0043] It should be noted that exposing the first electrode lead-out layer 10 can facilitate the arrangement of a wiring layer on the first electrode lead-out layer 10 . In the embodiment of the present application, the wiring layer is metal.

[0044] Step S11, reference Figure 10 As shown, the wiring layer 11 is electroplated onto the first electrode lead layer 10, and the wiring layer 11 is connected to the pin 5 through the second conductive layer 12 to form a conductive circuit;

[0045] It should be noted that the second conductive layer 12 is provided in the first plastic package 4 and the second plastic package 6 , and the gates of the first MOS transistor 8 and the second MOS transistor 1 are connected via the second conductive layer 12 , wherein the second conductive layer 12 is metal.

[0046] Step S12, as Figure 11 As shown, the entire device is covered with a fourth plastic package 13;

[0047] Step S13, as Figure 11 As shown, the device after plastic encapsulation is cut into individual chips along the dotted lines in 11, taking each chip as a unit.

[0048] In a second aspect, an embodiment of the present application provides a chip parallel packaging structure, which is prepared by the method described in the first aspect.

[0049] Compared with the prior art, the embodiments of the present application provide a chip parallel packaging method and a parallel packaging structure, which reduce the packaging size of the product and increase the electrical performance of the product by packaging two MOS chips back to back.

[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip parallel packaging method, characterized in that: The method comprises: The first electrode lead layer is arranged on the front surface of the first MOS chip by a ball planting process, and the second electrode lead layer is arranged on the front surface of the second MOS chip by a ball planting process; fixing the second MOS chip on the carrier board; The second MOS chip and the second electrode lead layer are covered with the first plastic package; Grinding and exposing the second electrode lead layer through a grinding process; Electroplating the second electrode lead layer onto the pin; Plastic-encapsulate all the pins with a second plastic encapsulation body; removing the carrier board to expose the back side of the second MOS chip; connecting the back side of the second MOS chip to the back side of the first MOS chip through the first conductive layer; Plastic-sealing the first MOS chip and the first electrode lead layer with a third plastic-sealing body; Grinding and exposing the first electrode lead layer through a grinding process; Electroplating the wiring layer onto the first electrode lead-out layer, and connecting the wiring layer to the pins through the second conductive layer to form a conducting circuit; Encapsulating the entire device with a third plastic package; The plastic-encapsulated devices are cut into individual chips based on each chip.

2. The method according to claim 1, wherein The first conductive layer and the second conductive layer are both metal.

3. A chip parallel packaging structure, characterized in that: Prepared by the method according to claim 1 or 2.

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