Manufacturing method of metal-insulator-metal capacitor
By alternately forming odd and even electrode layers and forming vias in the interlayer dielectric layer during the manufacturing process of metal-insulator-metal capacitors, the problem of poor via hole etching consistency is solved, and higher etching consistency and device reliability are achieved.
Patent Information
- Application Number
- CN202410264613.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-08
- Publication Date
- 2025-09-09
AI Technical Summary
During the manufacturing process of metal-insulator-metal capacitors, the etching consistency of the vias is poor, resulting in a smaller etching process window, slower etching rate, more severe polymer etching, metal line depressions, and an increased risk of metal chip contamination, affecting device reliability.
By forming the first electrode layer and the dielectric layer on the insulating layer, odd and even electrode layers are alternately formed, and via holes are formed in the interlayer dielectric layer, the structural consistency of each film layer is ensured, and the same etching process is used to form the via holes, avoiding problems caused by differences in film layer structure and thickness.
The etching consistency of the via holes is improved, the etching process window, etching rate and etching effect are guaranteed, the metal wires are prevented from being etched into depressions, the risk of metal chip contamination is reduced, and the device reliability is improved.
Smart Images
Figure CN120613307A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a method for manufacturing a metal-insulator-metal capacitor. Background Art
[0002] With the continuous development of semiconductor technology, the application of Metal-Insulator-Metal (MIM) capacitors integrated between back-end metal layers is becoming more and more widespread.
[0003] like Figure 1 As shown, in the related art, a substrate 10' includes multiple electrode layers 12' and dielectric layers 13' stacked in sequence to form a multi-layer MIM capacitor, and the multi-layer MIM capacitor is covered with an interlayer dielectric layer 14'. Different conductive holes can usually be used to connect the odd-numbered electrode layers to each other and the even-numbered electrode layers to each other to increase the capacitance per unit area. However, since the above-mentioned vias connecting the odd-numbered electrode layers and the metal wires 11' (first type of vias 15'), the vias connecting the even-numbered electrode layer metal wires 11' (second type of vias 16'), and the vias of the metal wires 11' of other non-MIM capacitors (third type of vias 17') are located at different positions and have different film layer structures, when etching the above-mentioned vias, the three types of vias cannot stop on the barrier layer at the same time (the etching consistency is poor). When the barrier layer is removed according to the normal process recipe, barrier layer residue will appear. Therefore, it is necessary to increase the energy, time and other parameters for removing the barrier layer, which further leads to the following problems: the etching process window is reduced; the barrier layer etching rate is slow, affecting production capacity; the etching of the polymer is aggravated, and it is difficult to remove it later; the metal wire below the via hole is etched into a depression, affecting device reliability and increasing the risk of metal contamination of the machine; the roughness of the dielectric layer above the electrode layer will increase, which is not conducive to subsequent processes, etc. Summary of the Invention
[0004] The object of the present invention is to provide a method for manufacturing a metal-insulator-metal capacitor, so as to improve the uniformity of etching of a via hole of the metal-insulator-metal capacitor.
[0005] To solve the above technical problems, the present invention provides a method for manufacturing a metal-insulator-metal capacitor, comprising:
[0006] Providing a substrate, wherein first to third types of metal wires arranged in the same layer and an insulating layer covering the first to third types of metal wires are formed on the substrate, wherein the first to third types of metal wires are respectively located in first to third regions of the substrate, wherein a capacitor region is provided between the first region and the second region;
[0007] forming a first electrode layer on the insulating layer, wherein the first electrode layer extends from above the first region to above the capacitor region, and the first electrode layer has a first opening above the first type of metal line to expose the surface of the insulating layer;
[0008] forming a dielectric layer conformally covering the first electrode layer and the insulating layer, and forming a second electrode layer on the dielectric layer, wherein the second electrode layer extends from above the second region to above the capacitor region to cover at least a portion of the dielectric layer on the first electrode layer, and the second electrode layer has a second opening above the second type of metal line to expose a surface of the dielectric layer;
[0009] Alternatingly forming dielectric layers and electrode layers, wherein the odd-numbered electrode layers are sequentially located above the first electrode layer and have openings located above the first openings to expose the dielectric layers thereunder, and the even-numbered electrode layers are sequentially located above the second electrode layer and have openings located above the second openings to expose the dielectric layers thereunder;
[0010] forming an interlayer dielectric layer to cover the dielectric layer and the electrode layer, and forming a first type of via hole penetrating the first opening and the openings of each odd-numbered electrode layer thereon, and a second type of via hole penetrating the second opening and the openings of each even-numbered electrode layer thereon in the interlayer dielectric layer and the dielectric layer, wherein the bottom of the first type of via hole exposes the surface of the first type of metal wire and the sidewall thereof exposes the corresponding electrode layer, the bottom of the second type of via hole exposes the surface of the second type of metal wire and the sidewall thereof exposes the corresponding electrode layer, and forming a third type of via hole exposing the surface of the third type of metal wire;
[0011] Conductive material layers are formed in the first to third types of conductive holes to electrically lead out the first to third types of metal wires, and electrically connect the odd-numbered electrode layers with the first type of metal wires and electrically connect the even-numbered electrode layers with the second type of metal wires.
[0012] Optionally, the first opening, the second opening and the openings in each of the electrode layers all have a first aperture.
[0013] Optionally, the first to third types of conducting holes all have a second aperture, and the second aperture is larger than the first aperture.
[0014] Optionally, the difference between the second aperture and the first aperture is greater than or equal to the overlay accuracy of the corresponding photolithography process.
[0015] Optionally, the electrode layer in the capacitor region is in a planar shape to form a planar capacitor, and / or the electrode layer in the capacitor region is located in a trench to form a trench capacitor.
[0016] Optionally, the step of forming each electrode layer includes:
[0017] forming an electrode material layer to cover the corresponding surface;
[0018] The electrode material layer is subjected to corresponding photolithography and etching processes to form corresponding electrode layers, wherein each electrode layer not only forms a corresponding electrode pattern, but also simultaneously forms the opening in the electrode pattern in advance to form a corresponding conductive hole.
[0019] Optionally, a first mask is used to perform corresponding photolithography and etching processes to form the first electrode layer and the electrode layers of the odd-numbered layers thereon, and a second mask is used to perform corresponding photolithography and etching processes to form the second electrode layer and the electrode layers of the even-numbered layers thereon.
[0020] Optionally, after forming each dielectric layer, a third mask is used to perform a patterning process on the dielectric layer to remove the dielectric layer outside the capacitor region and the first to third regions.
[0021] Optionally, after forming each electrode layer and each dielectric layer, a patterning process is further performed on all dielectric layers.
[0022] Optionally, the steps of forming the first to third types of vias include:
[0023] forming a patterned mask on the interlayer dielectric layer, wherein the patterned mask has a plurality of openings, and the openings are respectively located above the first opening, the second opening, and the third type of metal line;
[0024] An etching process is performed to remove the interlayer dielectric layer, the dielectric layer, and the insulating layer below the opening of the patterned mask to expose the surfaces of the first to third types of metal lines respectively.
[0025] In summary, the present invention forms a first electrode on the insulating layer on the first type of metal wire and its periphery, the first electrode layer has a first opening above the first type of metal wire to expose the surface of the insulating layer, and a dielectric layer is formed to conformally cover the first electrode layer and the insulating layer. Then, a second electrode layer is formed on at least a portion of the dielectric layer above the second type of metal wire and the first electrode layer, and the second electrode layer has a second opening above the second type of metal wire to expose the surface of the dielectric layer. Then, the remaining dielectric layers and electrode layers are formed alternately in the same manner, wherein the odd-numbered electrode layers in the remaining electrode layers are sequentially located above the first electrode layer and have an opening located above the first opening and expose the dielectric layer thereunder, and the even-numbered electrode layers in the remaining electrode layers are sequentially located above the second electrode layer. The present invention relates to a method for forming a first type of conductive hole through the first opening and the opening of the odd-numbered electrode layer above the first opening, and a second type of conductive hole through the second opening and the opening of the even-numbered electrode layer above the first opening, and a second type of conductive hole through the second opening and the opening of the even-numbered electrode layer above the first opening, and a second type of conductive hole through the second opening and the opening of the even-numbered electrode layer above the first opening, and a third type of conductive hole through the surface of the third type of metal wire, and a conductive material layer is formed in the first to third types of conductive holes to electrically lead out the first to third types of metal wires, respectively. In the etching process for forming the first to third types of vias, the film structures etched are essentially the same, i.e., they are all interlayer dielectric layers, dielectric layers, and insulating layers in sequence, and the thicknesses of the etched film layers are also essentially the same, ensuring better etching consistency when etching each via, avoiding a series of problems caused by different film layer structures or thicknesses, thereby ensuring that the etching process window, etching rate, and etching effect of each via are in a relatively ideal state. Furthermore, it is also beneficial to simultaneously stop etching and the surface of each metal wire, preventing the metal wire from being etched into a depression, affecting device reliability, and increasing the risk of metal shavings contamination. Furthermore, the present invention can simultaneously form the above-mentioned openings when patterning each electrode material layer, which is simple and easy to implement, making it more operable. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.
[0027] Figure 1 Schematic diagram of via hole etching of a multilayer MIM capacitor in the related art;
[0028] Figure 2 is a flow chart of a method for manufacturing a metal-insulator-metal capacitor provided in Example 1;
[0029] Figure 3a-3j This is a schematic structural diagram corresponding to the corresponding steps of the method for manufacturing the metal-insulator-metal capacitor provided in Example 1.
[0030] Figure 1 Middle: 10'-substrate; 11'-metal line; 12'-electrode layer; 13'-dielectric layer; 14'-interlayer dielectric layer; 15'-first type of via; 16'-second type of via; 17'-third type of via.
[0031] Figure 3a ˉ Figure 3j In the figure: 10-substrate; 11-first type of metal wire; 12-second type of metal wire; 13-third type of metal wire; 14-insulating layer; AA-capacitor area; BB-first region; CC-second region; DD-third region; 21a-first electrode layer; 21b-third electrode layer; 21c-fifth electrode layer; 23a-first opening; 23b-third opening; 23c-fifth opening; 24a-first dielectric layer; 24b-second dielectric layer; 24c-third dielectric layer; 24d-fourth dielectric layer; 25a-second electrode layer; 25b-fourth electrode layer; 26a-second opening; 26b-fourth opening; 31-interlayer dielectric layer; 32-patterned mask layer; 33-first type of via hole; 34-second type of via hole; 35-third type of via hole; 36-first through-hole lead-out structure; 37-second through-hole lead-out structure; 38-third through-hole lead-out structure. DETAILED DESCRIPTION
[0032] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.
[0033] As used in the present invention, the singular forms "a", "an", and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features specified as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.
[0034] Example 1
[0035] Embodiment 1 provides a method for manufacturing a metal-insulator-metal capacitor.
[0036] Figure 2 This is a flow chart of a method for manufacturing a metal-insulator-metal capacitor provided in Example 1.
[0037] like Figure 2 As shown, the manufacturing method of the metal-insulator-metal capacitor provided in this embodiment includes:
[0038] S01: Providing a substrate, wherein first to third types of metal wires arranged in the same layer and an insulating layer covering the first to third types of metal wires are formed on the substrate, wherein the first to third types of metal wires are respectively located in first to third regions of the substrate, wherein a capacitor region is provided between the first region and the second region;
[0039] S02: forming a first electrode layer on the insulating layer, wherein the first electrode layer extends from above the first region to above the capacitor region, and the first electrode layer has a first opening above the first type of metal line to expose a surface of the insulating layer;
[0040] S03: forming a dielectric layer conformally covering the first electrode layer and the insulating layer, and forming a second electrode layer on the dielectric layer, wherein the second electrode layer extends from above the second region to above the capacitor region to cover at least a portion of the dielectric layer on the first electrode layer, and the second electrode layer has a second opening above the second type of metal line to expose the surface of the dielectric layer accordingly;
[0041] S04: Alternately forming dielectric layers and electrode layers in sequence, wherein the odd-numbered electrode layers are sequentially located above the first electrode layer and have openings located above the first openings to expose the dielectric layers thereunder; and the even-numbered electrode layers are sequentially located above the second electrode layer and have openings located above the second openings to expose the dielectric layers thereunder;
[0042] S05: forming an interlayer dielectric layer to cover the dielectric layer and the electrode layer, and forming a first type of via hole penetrating the first opening and the openings of each odd-numbered electrode layer thereon, and a second type of via hole penetrating the second opening and the openings of each even-numbered electrode layer thereon, in the interlayer dielectric layer and the dielectric layer, wherein the bottom of the first type of via hole exposes the surface of the first type of metal wire and the sidewall thereof exposes the corresponding electrode layer, the bottom of the second type of via hole exposes the surface of the second type of metal wire and the sidewall thereof exposes the corresponding electrode layer, and a third type of via hole is formed to expose the surface of the third type of metal wire;
[0043] S06: forming a conductive material layer in the first to third types of conductive vias to electrically lead out the first to third types of metal wires, respectively, and electrically connect the odd-numbered electrode layers with the first type of metal wires and electrically connect the even-numbered electrode layers with the second type of metal wires.
[0044] Figure 3a ˉ Figure 3j The structural diagram corresponding to the corresponding steps of the manufacturing method of the metal-insulator-metal capacitor provided in this embodiment is shown in FIG. Figure 3a ˉ Figure 3j A method for manufacturing the metal-insulator-metal capacitor will be described in detail.
[0045] First, please refer to Figure 3a , performing step S01, providing a substrate 10, wherein first to third types of metal wires (11ˉ13) arranged in the same layer and an insulating layer 14 covering the first to third types of metal wires (11ˉ13) are formed in the substrate 10, and the first to third types of metal wires (11ˉ13) are respectively located in first to third regions (BBˉDD) of the substrate 10, wherein a capacitor area AA is provided between the first region BB and the second region CC.
[0046] The substrate 10 may be any suitable base material known to those skilled in the art, and may be, for example, at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SiOI), silicon-germanium-on-insulator (SiGe), silicon-germanium-on-insulator (SiGe), germanium-on-insulator (GeO), and silicon carbide. In this embodiment, the material of the substrate 10 is described using silicon (silicon substrate) as an example.
[0047] A device layer and an interconnection layer electrically connected to the device layer are formed in the substrate 10. The interconnection layer is located above the device layer and can be formed using a damascene process. The first to third types of metal wires (11-13) can be metal wiring arranged at intervals of the Nth layer (N is greater than or equal to 1) in the interconnection layer. The first type of metal wire 11 is located in the first region BB, and the second type of metal wire 12 is located in the second region CC. A capacitor region AA is provided between the first region BB and the second region CC. The first type of metal wire 11 and the second type of metal wire 12 are used to connect the electrodes of the capacitor. The third type of metal wire 13 is located in the third region DD. It is the remaining metal wire in the interconnection layer to be electrically led out except for the first type of metal wire 11 and the second type of metal wire 12. The materials of the three can include, for example, copper, aluminum, etc. In this embodiment, the first to third types of metal wires (11-13) can be top-layer metal wiring arranged sequentially and adjacently. The substrate 10 in the capacitor region AA can be flat, so that multiple layers of planar electrodes can be formed thereon to form a multi-layer planar capacitor. In practice, the boundaries between the first region BB, the second region CC, and the third region DD and the capacitor area AA are not absolute, and the capacitor may partially extend outside the capacitor area AA, for example, partially extend to the first to third regions BBˉDD.
[0048] An insulating layer 14 is covered on the first to third types of metal wires (11ˉ13). The insulating layer 14 may include a blocking dielectric layer and an etch stop layer formed in sequence. The blocking dielectric layer is used to block the escape of metal ions. Its material may include, for example, silicon nitride or silicon carbonitride. The etch stop layer is used to stop etching. Its material is different from that of the blocking dielectric layer. It may include, for example, silicon nitride or silicon oxynitride.
[0049] In addition, in other examples of this embodiment, as needed, multiple (at least two) first-class metal wires 11, multiple second-class metal wires 12 and multiple third-class metal wires 13 may be provided, that is, multiple first regions BB, multiple second regions CC and multiple third regions DD. The first-class metal wires 11 and the second-class metal wires 12 are respectively used to connect to the electrode layers of the odd-numbered layers and the electrode layers of the even-numbered layers of the metal-insulator-metal capacitor to be formed. The third-class metal wires 13 may be metal wires other than the first-class metal wires 11 and the second-class metal wires 12 in the Nth layer of the interconnection layer.
[0050] Next, please refer to Figure 3b, step S02 is performed to form a first electrode layer 21a on the insulating layer 14. The first electrode layer 21a extends from above the first region BB to above the capacitor region AA, and the first electrode layer 21a has a first opening 23a above the first type of metal line 11 to expose the surface of the insulating layer 14. Specifically, a first electrode material layer can be first formed to cover the surface of the insulating layer 14, and then the first electrode material layer is patterned (photolithography and etching processes) to use the remaining first electrode material layer as the first electrode layer 21a. Any suitable process can be used to form a thin film conductive layer as the first electrode material layer, which can include one or more thin film conductive layers. The material can, for example, include one or more of titanium, titanium nitride, tantalum, or tantalum nitride. The formation process can include physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The first electrode material layer can have a relatively thin thickness to form a multilayer capacitor. The thickness can, for example, be 100 angstroms to 400 angstroms.
[0051] It should be noted that the above-mentioned photolithography and etching processes not only form the electrode pattern of the first electrode layer 21a, but also simultaneously form a first opening 23a in the electrode pattern in advance, exposing the insulating layer 14 (through the first electrode layer 21a) above the first area BB. The first electrode layer 21a extends from above the first area BB to above the capacitor area AA for the subsequent formation of corresponding vias and metal-insulator-metal capacitors. The first opening 23a may have a first aperture, which may be slightly smaller than the aperture of the subsequent via that passes through the first opening 23a and connects to the first type of metal line 11. This allows the via to pass through the first opening 23a while exposing the first electrode layer 21a on its sidewalls, thereby electrically connecting the first type of metal line 11 and the first electrode layer 21a. The difference between the first aperture and the aperture of the corresponding via can be greater than or equal to the overlay accuracy of the photolithography. In a preferred example, the difference between the first aperture and the aperture of the corresponding via can be, for example, between one overlay accuracy and two overlay accuracy.
[0052] Next, step S03 is performed to form a dielectric layer that conformally covers the first electrode layer 21a and the insulating layer 14, and to form a second electrode layer 25a on the dielectric layer. The second electrode layer 25a extends from above the second area CC to above the capacitor area AA to cover at least a portion of the dielectric layer on the first electrode layer 21a, and the second electrode layer 25a has a second opening 26a above the second type of metal line 12 to expose the surface of the dielectric layer accordingly.
[0053] For details, please refer to Figure 3cFirst, a first dielectric layer 24a can be formed to conformally cover the first electrode layer 21a and the insulating layer 14 (including the first to third regions BB-DD and the capacitor region AA). The first dielectric layer 24a can be made of a dielectric material with a relatively high dielectric constant, such as greater than or equal to 3.9. The material can be, for example, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or rhodium oxide. The thickness of the first dielectric layer 24a can be, for example, 50 angstroms to 300 angstroms.
[0054] Please refer to Figure 3d A second electrode layer 25a is formed to cover the second-type metal line 12 and at least a portion of the first dielectric layer 24a above the first electrode layer 21a. The second electrode layer 25a has a second opening 26a above the second-type metal line 12 to expose the surface of the first dielectric layer 24a. This process may include, for example, forming a second electrode material layer to cover the surface of the first dielectric layer 24a, then patterning the second electrode material layer (photolithography and etching processes), leaving the remaining second electrode material layer as the second electrode layer 25a. The material and thickness of the second electrode material layer may refer to the first electrode material layer.
[0055] During the photolithography and etching process of the second electrode layer 25a, not only is the electrode pattern of the second electrode layer 25a formed, but a second opening 26a is also simultaneously formed in the electrode pattern to expose the first dielectric layer 24a (through the second electrode layer 25a) on the second region CC. The second electrode layer 25a extends from above the second region CC to above the capacitor area AA for the subsequent formation of corresponding vias and metal-insulator-metal capacitors. The second opening 26a may have a third aperture, which may be slightly smaller than the aperture of the subsequent via that passes through the second opening 26a and connects to the second type of metal line 12 to prevent overlay deviation during photolithography. In a preferred example, the second opening 26a may have the same aperture as the first opening 23a and adopt a similar configuration as the first aperture, so as to form a via that passes through the first opening 23a while exposing the first electrode layer 21a on its sidewall, thereby electrically connecting the first type of metal line 11 and the first electrode layer 21a.
[0056] Next, step S04 is performed to alternately form dielectric layers and electrode layers in sequence, wherein the odd-numbered electrode layers are sequentially located above the first electrode layer 21a and have openings located above the first opening 23a to correspondingly expose the dielectric layer thereunder, and the even-numbered electrode layers are sequentially located above the second electrode layer 25a and have openings located above the second opening 26a to correspondingly expose the dielectric layer thereunder.
[0057] In this embodiment, the metal-insulator-metal capacitor may include, for example, a total of five electrode layers. In addition to the aforementioned electrode layers and dielectric layers, there are three remaining electrode layers and three remaining dielectric layers. Specifically, the odd-numbered electrode layers may include a third electrode layer 21b and a fifth electrode layer 21c, and the even-numbered electrode layers may include a fourth electrode layer 25b. The remaining three dielectric layers may be second to fourth dielectric layers 24b-24d. The materials and thicknesses of the third to fifth electrode layers 21b, 21c, and 25b may refer to those of the first electrode layer 21a, and the materials and thicknesses of the second to fourth dielectric layers 24b-24d may refer to those of the first dielectric layer 24a.
[0058] For details, please refer to Figure 3e A second dielectric layer 24b is formed to conformally cover the second electrode layer 25a and the first dielectric layer 24a, and a third electrode material layer is formed to cover the surface of the second dielectric layer 24b. The third electrode material layer is then patterned (photolithography and etching processes), with the remaining third electrode material layer serving as the third electrode layer 21b. Similar to the formation of the first electrode layer 21a, during the photolithography and etching processes for the third electrode layer 21b, not only is the electrode pattern of the third electrode layer 21b formed, but a third opening 23b is also pre-formed within the electrode pattern, located above the first region BB, exposing the second dielectric layer 24b (through the third electrode layer 21b). The third electrode layer 21b extends from above the first region BB to above the capacitor area AA for the subsequent formation of corresponding vias and metal-insulator-metal capacitors. The third electrode layer 21b (its electrode pattern) can overlap with the first electrode layer 21a as much as possible. The third opening 23b is located in the first region BB, directly above the first opening 23a, and has the same aperture as the first opening 23a. In a preferred example, the third electrode layer 21 b and the first electrode layer 21 a can be formed by performing photolithography and etching processes using the same mask (eg, the first mask).
[0059] Please refer to Figure 3fA third dielectric layer 24c is formed conformally covering the third electrode layer 21b and the second dielectric layer 24b. A fourth electrode material layer is formed covering the surface of the third dielectric layer 24c. The fourth electrode material layer is then patterned (photolithography and etching processes), with the remaining fourth electrode material layer serving as the fourth electrode layer 25b. Similar to the formation of the second electrode layer 25a, during the photolithography and etching processes for the fourth electrode layer 25b, not only is the electrode pattern of the fourth electrode layer 25b formed, but a fourth opening 26b is also pre-formed within the electrode pattern in the second region CC, exposing the third dielectric layer 24c (through the fourth electrode layer 25b). The fourth electrode layer 25b extends from above the second region CC to above the capacitor area AA, facilitating the subsequent formation of corresponding vias and metal-insulator-metal capacitors. The fourth electrode layer 25b (and its electrode pattern) can overlap as much as possible with the second electrode layer 25a. The fourth opening 26b is located in the second region CC, directly above the second opening 26a, and has the same aperture as the second opening 26a. In a preferred example, the fourth electrode layer 25 b and the second electrode layer 25 a can be formed by performing photolithography and etching processes using the same mask (eg, the second mask).
[0060] Please refer to Figure 3g A fourth dielectric layer 24d is formed conformally overlying the fourth electrode layer 25b and the third dielectric layer 24c. A fifth electrode material layer is then formed overlying the surface of the fourth dielectric layer 24d. The fifth electrode material layer is then patterned (photolithography and etching processes), leaving the remaining fifth electrode material layer as the fifth electrode layer 21c. Similar to the formation of the first electrode layer 21a, the photolithography and etching processes for the fifth electrode layer 21c not only form the electrode pattern of the fifth electrode layer 21c but also simultaneously form a fifth opening 23c in the electrode pattern above the first area BB, exposing the fourth dielectric layer 24d (and penetrating the fifth electrode layer 21c). The fifth electrode layer 21c extends from above the first area BB to above the capacitor area AA, facilitating the subsequent formation of a corresponding via-type metal-insulator-metal capacitor. The fifth electrode layer 21c (and its electrode pattern) can overlap as much as possible with the first electrode layer 21a. The fifth opening 23c is located in the first area BB, directly above the first opening 23a, and has the same aperture as the first opening 23a. In a preferred example, the fifth electrode layer 21 c and the first electrode layer 21 a can be formed by performing photolithography and etching processes using the same mask (eg, the first mask).
[0061] It should be noted that in other examples, the number of electrode layers of the metal-insulator-metal capacitor can be other values and can be prepared using similar methods as described above. After forming each electrode layer, all dielectric layers (e.g., the first to fourth dielectric layers 24a-24d) can be patterned using a third mask to remove the dielectric layers except those above the capacitor area AA, the first region BB, the second region CC, and the third region DD. Of course, in some examples, it is also feasible to use a third mask to perform corresponding patterning after forming each dielectric layer.
[0062] Next, step S05 is performed to form an interlayer dielectric layer 31 covering the dielectric layers and electrode layers. A first-type via 33 is formed in the interlayer dielectric layer 31 and the dielectric layers (e.g., the first to fourth dielectric layers 24a-24d), penetrating the first opening 23a and the openings of the odd-numbered electrode layers above it, and a second-type via 34 is formed in the interlayer dielectric layer 31 and the dielectric layers (e.g., the first to fourth dielectric layers 24a-24d), penetrating the first opening 23a and the openings of the odd-numbered electrode layers above it. The bottom of the first-type via 33 exposes the surface of the first-type metal line 11, and its sidewalls expose the corresponding electrode layers (the first electrode layer 21a, the third electrode layer 21b, and the fifth electrode layer 21c). The bottom of the second-type via 34 exposes the surface of the second-type metal line 12, and its sidewalls expose the corresponding electrode layers (the second electrode layer 25a and the fourth electrode layer 25b). Furthermore, a third-type via 35 is formed, exposing the surface of the third-type metal line 13. A metal-insulator-metal capacitor is located between the first-type via 33 and the second-type via 34.
[0063] For details, please refer to Figure 3h An interlayer dielectric layer 31 is formed to cover the top electrode layer and dielectric layer, filling the top portion thereof to form a flat surface suitable for photolithography. Next, a patterned mask layer 32 is formed on the surface of the interlayer dielectric layer 31. The patterned mask layer 32 has a plurality of openings, some of which are located above the first opening 23a (including the third opening 23b and the fifth opening 23c), some of which are located above the second opening 26a (including the fourth opening 26b), and other openings are located above the third type of metal line 13, for forming corresponding vias to lead out the corresponding metal lines. The opening size of the patterned mask layer 32, i.e., the aperture of the via (e.g., the second aperture), can be slightly larger than the aperture of the first opening 23a or the second opening 26a. The specific configuration can be as described above.
[0064] Please refer to Figure 3iUsing the patterned mask layer 32, an etching process is performed to form first to third types of vias 33-35. The first type of via 33 penetrates the interlayer dielectric layer 31, the odd-numbered electrode layers, the dielectric layers, and the insulating layer 14, and exposes the surface of the first type of metal line 11 at its bottom (bottom wall) and the side surfaces of the odd-numbered electrode layers at its side (sidewall). The second type of via 34 penetrates the interlayer dielectric layer 31, the even-numbered electrode layers, the dielectric layers, and the insulating layer 14, and exposes the surface of the second type of metal line 12 at its bottom (bottom wall) and the side surfaces of the even-numbered electrode layers at its side (sidewall). The third type of via 35 penetrates the interlayer dielectric layer 31, the dielectric layers, and the insulating layer 14, and exposes the surface of the third type of metal line 13 at its bottom (bottom wall). The first to third types of vias 33-35 may have the same aperture (e.g., the second aperture).
[0065] In particular, in the above-mentioned etching process for forming the first to third types of via holes 33ˉ35, the film layer structure below the opening of each patterned mask layer 32 is consistent, that is, they are all interlayer dielectric layer 31, dielectric layer and insulating layer 14 in sequence, and the thickness of each film layer is basically the same, ensuring better etching consistency when etching each via hole, avoiding a series of problems caused by different film layer structures or different film layer thicknesses, thereby ensuring that the etching process window, etching rate and etching effect of each via hole are in a relatively ideal state, and it is also beneficial to simultaneously stop etching and the surface of each metal wire, preventing the metal wire from being etched into a depression, affecting the reliability of the device and increasing the risk of metal chip contamination.
[0066] Next, please refer to Figure 3j , execute step S06 to form a conductive material layer in the first to third types of conductive holes 33ˉ35 to electrically lead out the first to third types of metal wires 11ˉ13, respectively, and electrically connect the electrode layer of the odd layers with the first type of metal wire 11 and electrically connect the electrode layer of the even layers with the second type of metal wire 12.
[0067] Specifically, the patterned mask layer 32 can be first removed, and then a conductive material layer can be formed to cover the surface of the interlayer dielectric layer 31, filling the first to third types of vias 33-35 to the top thereof. Then, the conductive material layer on the surface of the interlayer dielectric layer 31 can be removed, and the remaining conductive material layer in the first to third types of vias 33-35 can be used as the first to third through-hole lead-out structures 36-38, respectively. The conductive material layer can be a metal material layer and can be formed using any suitable process, such as CVD, PVD, or chemical plating. The first through-hole lead-out structure 36 leads out the first type of metal wire 11 and electrically connects the odd-numbered electrode layers of the metal-insulator-metal capacitor. The second through-hole lead-out structure 37 leads out the second type of metal wire 12 and electrically connects the even-numbered electrode layers of the metal-insulator-metal capacitor. The third through-hole lead-out structure 38 leads out the third type of metal wire 13.
[0068] Example 2
[0069] Embodiment 2 provides a method for manufacturing a metal-insulator-metal capacitor.
[0070] Figure 2 This is a flow chart of a method for manufacturing a metal-insulator-metal capacitor provided in Example 1.
[0071] like Figure 2 As shown, the manufacturing method of the metal-insulator-metal capacitor provided in this embodiment includes:
[0072] S01: Providing a substrate, wherein first to third types of metal wires arranged in the same layer and an insulating layer covering the first to third types of metal wires are formed on the substrate, wherein the first to third types of metal wires are respectively located in first to third regions of the substrate, wherein a capacitor region is provided between the first region and the second region;
[0073] S02: forming a first electrode layer on the insulating layer, wherein the first electrode layer extends from above the first region to above the capacitor region, and the first electrode layer has a first opening above the first type of metal line to expose a surface of the insulating layer;
[0074] S03: forming a dielectric layer conformally covering the first electrode layer and the insulating layer, and forming a second electrode layer on the dielectric layer, wherein the second electrode layer extends from above the second region to above the capacitor region to cover at least a portion of the dielectric layer on the first electrode layer, and the second electrode layer has a second opening above the second type of metal line to expose the surface of the dielectric layer accordingly;
[0075] S04: Alternately forming dielectric layers and electrode layers in sequence, wherein the odd-numbered electrode layers are sequentially located above the first electrode layer and have openings located above the first openings to expose the dielectric layers thereunder; and the even-numbered electrode layers are sequentially located above the second electrode layer and have openings located above the second openings to expose the dielectric layers thereunder;
[0076] S05: forming an interlayer dielectric layer to cover the dielectric layer and the electrode layer, and forming a first type of via hole penetrating the first opening and the openings of each odd-numbered electrode layer thereon, and a second type of via hole penetrating the second opening and the openings of each even-numbered electrode layer thereon, in the interlayer dielectric layer and the dielectric layer, wherein the bottom of the first type of via hole exposes the surface of the first type of metal wire and the sidewall thereof exposes the corresponding electrode layer, the bottom of the second type of via hole exposes the surface of the second type of metal wire and the sidewall thereof exposes the corresponding electrode layer, and a third type of via hole is formed to expose the surface of the third type of metal wire;
[0077] S06: forming a conductive material layer in the first to third types of conductive vias to electrically lead out the first to third types of metal wires, respectively, and electrically connect the odd-numbered electrode layers with the first type of metal wires and electrically connect the even-numbered electrode layers with the second type of metal wires.
[0078] The manufacturing method of the metal-insulator-metal capacitor provided in Example 2 is the same as that provided in Example 1, with the only difference being that a plurality of grooves are further formed in the substrate between the first type of metal wire and the second type of metal wire, the insulating layer conformally covers the substrate surface and the sidewalls of the groove, and a multi-layer electrode layer and a multi-layer dielectric layer are formed on the surface of the substrate and the inner wall of the groove using the method of Example 1, and openings penetrating the electrode layer are simultaneously formed during the process to facilitate the formation of a via hole of the metal-insulator-metal capacitor. In other words, the aforementioned plurality of grooves are provided in the capacitor region in Example 1, and the odd-numbered electrode layers and the even-numbered electrode layers overlap in sequence in the groove and the surrounding area to form a trench capacitor. Of course, the groove may also partially extend to the area outside the area between the first type of metal wire and the second type of metal wire.
[0079] In summary, the present invention forms a first electrode on the insulating layer on the first type of metal wire and its periphery, the first electrode layer has a first opening above the first type of metal wire to expose the surface of the insulating layer, and a dielectric layer is formed to conformally cover the first electrode layer and the insulating layer. Then, a second electrode layer is formed on at least a portion of the dielectric layer above the second type of metal wire and the first electrode layer, and the second electrode layer has a second opening above the second type of metal wire to expose the surface of the dielectric layer. Then, the remaining dielectric layers and electrode layers are formed alternately in the same manner, wherein the odd-numbered electrode layers in the remaining electrode layers are sequentially located above the first electrode layer and have an opening located above the first opening and expose the dielectric layer thereunder, and the even-numbered electrode layers in the remaining electrode layers are sequentially located above the second electrode layer. The present invention relates to a method for forming a first type of conductive hole through the first opening and the opening of the odd-numbered electrode layer above the first opening, and a second type of conductive hole through the second opening and the opening of the even-numbered electrode layer above the first opening, and a second type of conductive hole through the second opening and the opening of the even-numbered electrode layer above the first opening, and a second type of conductive hole through the second opening and the opening of the even-numbered electrode layer above the first opening, and a third type of conductive hole through the surface of the third type of metal wire, and a conductive material layer is formed in the first to third types of conductive holes to electrically lead out the first to third types of metal wires, respectively. In the etching process for forming the first to third types of vias, the film structures etched are essentially the same, i.e., they are all interlayer dielectric layers, dielectric layers, and insulating layers in sequence, and the thicknesses of the etched film layers are also essentially the same, ensuring better etching consistency when etching each via, avoiding a series of problems caused by different film layer structures or thicknesses, thereby ensuring that the etching process window, etching rate, and etching effect of each via are in a relatively ideal state. Furthermore, it is also beneficial to simultaneously stop etching and the surface of each metal wire, preventing the metal wire from being etched into a depression, affecting device reliability, and increasing the risk of metal shavings contamination. Furthermore, the present invention can simultaneously form the above-mentioned openings when patterning each electrode material layer, which is simple and easy to implement, making it more operable.
[0080] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for manufacturing a metal-insulator-metal capacitor, characterized in that: include: Providing a substrate, wherein first to third types of metal wires arranged in the same layer and an insulating layer covering the first to third types of metal wires are formed on the substrate, wherein the first to third types of metal wires are respectively located in first to third regions of the substrate, wherein a capacitor region is provided between the first region and the second region; forming a first electrode layer on the insulating layer, wherein the first electrode layer extends from above the first region to above the capacitor region, and the first electrode layer has a first opening above the first type of metal line to expose the surface of the insulating layer; forming a dielectric layer conformally covering the first electrode layer and the insulating layer, and forming a second electrode layer on the dielectric layer, wherein the second electrode layer extends from above the second region to above the capacitor region to cover at least a portion of the dielectric layer on the first electrode layer, and the second electrode layer has a second opening above the second type of metal line to expose a surface of the dielectric layer; Alternatingly forming dielectric layers and electrode layers, wherein the odd-numbered electrode layers are sequentially located above the first electrode layer and have openings located above the first openings to expose the dielectric layers thereunder, and the even-numbered electrode layers are sequentially located above the second electrode layer and have openings located above the second openings to expose the dielectric layers thereunder; forming an interlayer dielectric layer to cover the dielectric layer and the electrode layer, and forming a first type of via hole penetrating the first opening and the openings of each odd-numbered electrode layer thereon, and a second type of via hole penetrating the second opening and the openings of each even-numbered electrode layer thereon in the interlayer dielectric layer and the dielectric layer, wherein the bottom of the first type of via hole exposes the surface of the first type of metal wire and the sidewall thereof exposes the corresponding electrode layer, the bottom of the second type of via hole exposes the surface of the second type of metal wire and the sidewall thereof exposes the corresponding electrode layer, and forming a third type of via hole exposing the surface of the third type of metal wire; Conductive material layers are formed in the first to third types of conductive holes to electrically lead out the first to third types of metal wires, and electrically connect the odd-numbered electrode layers with the first type of metal wires and electrically connect the even-numbered electrode layers with the second type of metal wires.
2. The method for manufacturing a metal-insulator-metal capacitor according to claim 1, wherein: The first opening, the second opening and the openings in each of the electrode layers all have a first aperture.
3. The method for manufacturing a metal-insulator-metal capacitor according to claim 2, wherein: The first to third types of conducting holes all have a second aperture, and the second aperture is larger than the first aperture.
4. The method for manufacturing a metal-insulator-metal capacitor according to claim 3, wherein: A difference between the second aperture and the first aperture is greater than or equal to an overlay accuracy of a corresponding photolithography process.
5. The method for manufacturing a metal-insulator-metal capacitor according to claim 1, wherein: The electrode layer in the capacitor region is in a flat plate shape to form a flat plate capacitor, and / or the electrode layer in the capacitor region is located in a trench to form a trench capacitor.
6. The method for manufacturing a metal-insulator-metal capacitor according to claim 1, wherein: The steps of forming each of the electrode layers include: forming an electrode material layer to cover the corresponding surface; The electrode material layer is subjected to corresponding photolithography and etching processes to form corresponding electrode layers, wherein each electrode layer not only forms a corresponding electrode pattern, but also simultaneously forms the opening in the electrode pattern in advance to form a corresponding conductive hole.
7. The method for manufacturing a metal-insulator-metal capacitor according to claim 6, wherein: A first mask is used to perform corresponding photolithography and etching processes to form the first electrode layer and the electrode layers of each odd-numbered layer thereon, and a second mask is used to perform corresponding photolithography and etching processes to form the second electrode layer and the electrode layers of each even-numbered layer thereon.
8. The method for manufacturing a metal-insulator-metal capacitor according to claim 6, wherein: After forming each dielectric layer, a third mask is used to perform a patterning process on the dielectric layer to remove the dielectric layer outside the capacitor region and the first to third regions.
9. The method for manufacturing a metal-insulator-metal capacitor according to claim 6, wherein: After forming each electrode layer and each dielectric layer, a patterning process is performed on all dielectric layers.
10. The method for manufacturing a metal-insulator-metal capacitor according to claim 1, wherein: The steps of forming the first to third types of vias include: forming a patterned mask on the interlayer dielectric layer, wherein the patterned mask has a plurality of openings, and the openings are respectively located above the first opening, the second opening, and the third type of metal line; An etching process is performed to remove the interlayer dielectric layer, the dielectric layer, and the insulating layer below the opening of the patterned mask to expose the surfaces of the first to third types of metal lines respectively.