Interposer substrate and semiconductor package including same

Abstract

The present disclosure provides an interposer substrate and a semiconductor package including the interposer substrate. The interposer substrate includes: a core including a first surface and a second surface opposite to each other in a first direction, including a via hole penetrating from the first surface to the second surface, and including glass; and a conductive member disposed only in a portion of the via hole. The through hole includes: a first portion penetrating a portion of the core from the first surface; and a second portion penetrating another portion of the core from the second surface to be connected to the first portion, and the conductive member is disposed at the second portion.

Description

Technical Field

[0001] The present disclosure relates to an interposer substrate and a semiconductor package including the interposer substrate. Background Art

[0002] As electronic components are required to be highly functional, lightweight, thin, short, and compact, the circuit substrates (or circuit boards) installed within them are also required to be highly functional, lightweight, thin, short, and compact. To achieve this, the circuit patterns of these circuit substrates are meticulously designed, and semiconductor elements that perform various functions are incorporated within them to achieve this high functionality.

[0003] Multiple printed circuit boards, each with a chip mounted thereon, can be stacked vertically to form a semiconductor package such as a stacked package or a package-on-package (POP). A stacked package is a stacked structure in which a certain distance is maintained between the upper and lower packages due to the thickness of the chips, and this certain distance can be maintained using structures such as metal pillars.

[0004] Meanwhile, the interposer market is growing due to the adoption of high-spec boards and high-bandwidth memory (HBM). Currently, organic materials are the mainstream interposer material based on conventional substrate manufacturing methods, but methods using glass as an interposer are also being developed.

[0005] High-speed HBM requires the formation of small, densely packed vias. Glass substrates are known to offer superior warpage resistance and flatness compared to organic substrates, resulting in fewer issues during internal processing and facilitating line-width and space (L / S) reduction. Therefore, the development of interposer substrates using glass is necessary. Summary of the Invention

[0006] An aspect of the present disclosure is to provide an interposer substrate and a semiconductor package including the same, which can reduce the occurrence of warpage defects, increase thermal stability and signal count, reduce the height of the semiconductor package, and improve heat dissipation characteristics.

[0007] However, the problems to be solved by the present disclosure are not limited to the above-mentioned problems, and can be variously extended within the scope of the technical concept included in the present disclosure.

[0008] An interposer substrate according to an embodiment includes: a core portion including a first surface and a second surface opposing each other in a first direction, including a via hole penetrating from the first surface to the second surface and comprising glass; and a conductive member disposed only in a portion of the via hole. The via hole includes a first portion penetrating a portion of the core portion from the first surface; and a second portion penetrating another portion of the core portion from the second surface to connect to the first portion, with the conductive member disposed at the second portion.

[0009] The core may include a cavity on the second surface, and the via hole may be provided in plural around the cavity.

[0010] The conductive member may also be provided in a portion of the first portion.

[0011] The interposer substrate may further include a heat dissipation portion penetrating the core from the first surface and extending to the cavity.

[0012] The heat dissipation portion may be provided in plurality, and the plurality of heat dissipation portions may be provided to be spaced apart from each other.

[0013] The heat dissipation portion may have a plate shape extending in a plane perpendicular to the first direction.

[0014] The interposer substrate may further include a protection portion covering a bottom surface of the cavity in the first direction and a side surface of the cavity in a direction perpendicular to the first direction.

[0015] In the first portion and / or the second portion, a width of one outer end of the core may be greater than a width of one inner end of the core opposite to the one outer end in the first direction.

[0016] The first portion and the second portion may have symmetrical shapes with respect to a reference surface perpendicular to the first direction.

[0017] Among the first portion and the second portion, the conductive member may be provided only in the second portion.

[0018] An interposer substrate according to another embodiment includes: a core including a first surface and a second surface facing each other in a first direction, including a via hole penetrating from the first surface to the second surface, including a cavity located on the second surface, and comprising glass; a conductive member disposed in a portion of the via hole; and a heat dissipation portion penetrating the core from the first surface and extending to the cavity. The via hole includes a first portion penetrating a portion of the core from the first surface; and a second portion penetrating another portion of the core from the second surface to connect to the first portion, with the conductive member disposed at the second portion.

[0019] The via hole may be provided in plural numbers around the cavity.

[0020] The conductive member may also be provided in a portion of the first portion.

[0021] The heat dissipation portion may be provided in plurality, and the plurality of heat dissipation portions may be provided to be spaced apart from each other.

[0022] The heat dissipation portion may extend in a direction perpendicular to the first direction.

[0023] In the first portion and / or the second portion, a width of one outer end of the core may be greater than a width of one inner end of the core opposite to the one outer end in the first direction.

[0024] The first portion and the second portion may have symmetrical shapes with respect to a reference surface perpendicular to the first direction.

[0025] A semiconductor package according to an embodiment includes: an interposer substrate; an upper package disposed on one side of the interposer substrate and including a first circuit substrate including an insulating layer and a conductive layer; and a connecting member partially disposed in the interposer substrate to connect the upper package and the interposer substrate. The interposer substrate includes: a core portion including a first surface and a second surface opposing each other in a first direction, including a via hole penetrating from the first surface to the second surface, and including glass; and a conductive member disposed in a portion of the via hole. The via hole includes: a first portion penetrating a portion of the core portion from the first surface and providing a space in which the connecting member is disposed; and a second portion penetrating another portion of the core portion from the second surface to connect to the first portion, with the conductive member disposed at the second portion.

[0026] The semiconductor package may further include a lower package disposed on the other side of the interposer substrate and including a second circuit substrate including an insulating layer and a conductive layer.

[0027] The core may have a cavity on the second surface, and the semiconductor package may further include a heat dissipation portion penetrating the core from the first surface and extending to the cavity.

[0028] According to the interposer substrate and semiconductor package based on the embodiment, the occurrence of warpage defects can be reduced, thermal stability and signal number can be increased, power transmission characteristics can be improved, the height of the entire semiconductor package can be reduced, and heat generated from electronic components can be effectively transferred and dispersed to the outside of the interposer substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a cross-sectional view of a semiconductor package according to an embodiment.

[0030] Figure 2 is a cross-sectional view illustrating a portion of a semiconductor package according to an embodiment.

[0031] Figure 3 is a perspective view of an interposer substrate according to an embodiment.

[0032] Figure 4 is a cross-sectional view illustrating a portion of a semiconductor package according to another embodiment.

[0033] Figure 5 is a perspective view of an interposer substrate according to another embodiment.

[0034] Figure 6 is a cross-sectional view illustrating a portion of a semiconductor package according to another embodiment.

[0035] Figure 7 is a perspective view of an interposer substrate according to another embodiment.

[0036] Figure 8 is a cross-sectional view illustrating a portion of a semiconductor package according to another embodiment.

[0037] Figure 9 is a cross-sectional view of a semiconductor package according to another embodiment.

[0038] Figures 10 to 15 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment.

[0039] Figures 16 to 20 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to another embodiment. DETAILED DESCRIPTION

[0040] Hereinafter, embodiments of the present disclosure will be described more fully with reference to the accompanying drawings so that those skilled in the art can easily implement the embodiments of the present disclosure. In order to clearly describe the present disclosure, parts or portions not related to the description are omitted, and throughout this specification, the same or similar constituent elements are represented by the same reference numerals. In the drawings, some elements are enlarged, omitted, or schematically shown, and the size of each element does not accurately reflect its actual size.

[0041] The drawings are only for easy understanding of the embodiments disclosed in this specification, and the technical concepts disclosed in this specification are not limited to the drawings, and this disclosure should be understood to include all modifications, equivalents, and replacements included in the spirit and technical scope of this disclosure.

[0042] Terms including ordinal numbers such as "first," "second," etc. may be used to describe various elements, but the elements are not limited by the terms. The terms are used only for the purpose of distinguishing one element from another.

[0043] It will be understood that when an element, such as a layer, film, region, or substrate, is referred to as being "on" or "over" another element, the element may be directly on the other element, or intervening elements may be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. Furthermore, throughout this specification, the phrases "on" or "over" a target element will be understood to mean disposed above or below the target element, and will not necessarily be understood to mean disposed "at the upper side of the target element" based on a direction opposite to the direction of gravity.

[0044] Throughout the specification, terms such as "include" and "have" are intended to indicate the presence of the features, quantities, steps, operations, components, or combinations thereof described in the specification, and should be understood as not excluding the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, or combinations thereof. Therefore, unless explicitly described to the contrary, the word "include" and variations such as "comprises" and "have" will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements.

[0045] In addition, throughout the specification, the phrase "on a plane" means observing a target portion from the top, and the phrase "on a cross section" means observing a cross section formed by vertically cutting a target portion from the side.

[0046] Throughout the specification, when it is described that a component is “coupled” to another component, the component may be “directly connected or physically connected” to the other component, or may be “indirectly connected or connected without contact” to the other component with a third component located therebetween.

[0047] Throughout the specification, "connected" not only means that two or more elements are directly connected, but also means that two or more elements are indirectly connected through another element, or that two or more elements are physically or electrically connected, or may include the following situation: although two or more elements are called different names according to position or function, they are basically integrated.

[0048] Figure 1 is a cross-sectional view of a semiconductor package according to an embodiment, Figure 2 is a cross-sectional view showing a portion of a semiconductor package according to an embodiment, and Figure 3 is a perspective view of an interposer substrate according to an embodiment.

[0049] Reference Figures 1 to 3 According to an embodiment, a semiconductor package 10 may include: an interposer substrate 100; an upper package 200, which is disposed at one side of the interposer substrate 100; a lower package 300, which is disposed at the other side of the interposer substrate 100; a first electronic component 400, which is connected to the lower package 300 and is disposed in a cavity 102 of the interposer substrate 100; a first connecting member 11, which is partially disposed in the interposer substrate 100 to connect the interposer substrate 100 and the upper package 200; a second connecting member 12, which connects the interposer substrate 100 and the lower package 300; and a third connecting member 13, which connects the lower package 300 to the outside.

[0050] An interposer substrate 100 according to an embodiment may include a core 101 having at least one via hole 110 penetrating the interposer substrate 100 and a conductive member 120 filled in a portion of the via hole 110. One surface of the core 101 may have a cavity 102.

[0051] The upper package 200 may include a first circuit substrate (or first circuit board) 201 and a second electronic component 202 mounted on the first circuit substrate 201. Figure 1 , but the first circuit substrate 201 may include an insulating layer, a conductive layer, and a via layer. The insulating layer of the first circuit substrate 201 may be formed using at least one selected from epoxy resin, polyimide (PI) resin, bismaleimide triazine (BT) resin, liquid crystal polymer (LCP), etc. Specifically, the insulating layer of the first circuit substrate 201 may include prepreg (PPG), Ajinomoto built-up film (ABF), etc. In addition, the insulating layer of the first circuit substrate 201 may include glass fiber, filler, etc. On the other hand, although not shown in Figure 1 , but the insulating layer of the first circuit substrate 201 may be formed using a plurality of layers, and the number of layers is not limited.

[0052] The conductive layer constituting the circuit may be provided on or within the insulating layer of the first circuit substrate 201. The conductive layer of the first circuit substrate 201 may provide a path for transmitting electrical signals and may be formed using at least one of copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), and platinum (Pt).

[0053] As an example, the first circuit substrate 201 may not include a cavity. In this case, the second electronic component 202 may be mounted on the upper surface of the first circuit substrate 201. For example, the second electronic component 202 may be mounted on the upper surface of the first circuit substrate 201 using a wire bonding method, a flip-chip mounting method, or the like.

[0054] The second electronic component 202 may be at least one of an active component, a passive component, and an integrated circuit. The upper package 200 may be connected to the interposer substrate 100 through a first connection member 11. The first connection member 11 may be a solder ball or the like.

[0055] The lower package 300 may include a second circuit substrate (or second circuit board) 301. The second circuit substrate 301 may include an insulating layer, a conductive layer, and a via layer. The insulating layer of the second circuit substrate 301 may be formed using at least one selected from epoxy resin, polyimide (PI) resin, bismaleimide triazine (BT) resin, liquid crystal polymer (LCP), etc. Specifically, the insulating layer of the second circuit substrate 301 may include prepreg (PPG), Ajinomoto build-up film (ABF), etc. In addition, the insulating layer of the second circuit substrate 301 may include glass fiber, filler, etc. On the other hand, although not in Figure 1 , but the insulating layer of the second circuit substrate 301 may be formed using a plurality of layers, and the number of layers is not limited.

[0056] The conductive layer constituting the circuit may be provided in or on the insulating layer of the second circuit substrate 301. The conductive layer of the second circuit substrate 301 may provide a path for transmitting electrical signals and may be formed using at least one of copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), and platinum (Pt).

[0057] The lower package 300 may be connected to the interposer substrate 100 through the second connection members 12. The lower package 300 may be connected to the first electronic component 400 through the second connection members 12. The second connection members 12 may be solder balls, etc. The first electronic component 400 may be at least one of an active component, a passive component, and an integrated circuit.

[0058] If necessary, a conductive film 401 may be provided between the first electronic component 400 and the core 101. The conductive film 401 may bond the first electronic component 400 to the core 101. A molding material 402 may be provided in a space of the cavity 102 where the first electronic component 400 and the conductive film 401 are not provided. The molding material 402 may fix the first electronic component 400.

[0059] In the following, reference will be made to Figure 2 and Figure 3 The interposer substrate 100 is described in detail.

[0060] Reference Figure 2 and Figure 3 , the core 101 may be a glass substrate. The core 101 may have a first surface and a second surface opposite to each other in a first direction. The first direction may be a direction along which the upper package 200, the interposer substrate 100, and the lower package 300 are stacked. As an example, the upper package 200 may be disposed above the interposer substrate 100 along the first direction. The lower package 300 may be disposed below the interposer substrate 100 along the first direction. The first surface may be a surface of the core 101 that faces the upper package 200 of the semiconductor package 10. For example, the first surface may be an upper surface of the core 101 in the first direction, and the second surface may be a lower surface of the core 101 in the first direction.

[0061] The passage hole 110 may penetrate from the first surface of the core 101 to the second surface of the core 101. The passage hole 110 may be provided in plurality. The cavity 102 may be provided on the second surface of the core 101. The cavity 102 may have a shape that is recessed from the second surface toward the first surface along the first direction. The passage hole 110 may be provided at one side of the cavity 102. As an example, a plurality of passage holes 110 may be provided at the periphery of the cavity 102 along the periphery of the cavity 102. A plurality of passage holes 110 may be provided along the edge area of ​​the cavity 102. The passage hole 110 may include: a first portion 111 that penetrates a portion of the core 101 from the first surface; and a second portion 112 that penetrates the remaining portion of the core 101 from the second surface to connect to the first portion 111.

[0062] The first portion 111 may have an opening on the first surface. In the first portion 111, the width of an outer end of the core 101 may be greater than the width of an inner end of the core 101 opposite to the outer end in the first direction. The first portion 111 may have a shape in which the width of the first portion 111 increases as the first portion 111 moves toward the outside of the core 101. The first portion 111 may have a shape in which the width of the first portion 111 increases as the first portion 111 approaches the first surface along the first direction.

[0063] The second portion 112 may have an opening on the second surface. In the second portion 112, the width of one outer end of the core 101 may be greater than the width of an inner end of the core 101 opposite to the one outer end in the first direction. The second portion 112 may have a shape in which the width of the second portion 112 increases as the second portion 112 moves toward the outside of the core 101. The second portion 112 may have a shape in which the width of the second portion 112 increases as the second portion 112 approaches the second surface along the first direction.

[0064] In other words, in the first portion 111 and / or the second portion 112 , the width of one outer end of the core 101 may be greater than the width of one inner end of the core 101 opposite to the one outer end in the first direction.

[0065] The first portion 111 and the second portion 112 may form a symmetrical shape with respect to a reference surface P perpendicular to the first direction. However, the present disclosure is not limited thereto, and the heights (or thicknesses) of the first portion 111 and the second portion 112 may be different.

[0066] A portion of the via hole 110 may be filled with the conductive member 120. At least a portion of the second portion 112 may be filled with the conductive member 120. The conductive member 120 may be provided at the second portion 112. Thus, the first portion 111 may form an inner wall, the conductive member 120 may form a bottom surface, and a groove portion having an opening may be formed on the first surface. Figure 2 and Figure 3 , the conductive member 120 is shown as being filled in the entire second portion 112, but the present disclosure is not limited thereto, and the conductive member 120 may be provided to be filled in only a portion of the second portion 112. In addition, the conductive member 120 may be additionally filled in a portion of the first portion 111. As an example, the conductive member 120 may include copper (Cu).

[0067] The interior of the first portion 111 may provide a space in which the first connecting member 11 is disposed. The first connecting member 11 may be disposed inside the first portion 111. In other words, at least a portion of the first connecting member 11 may be accommodated in a groove space formed by the first portion 111 of the via hole 110 of the core 101. The first connecting member 11 may be disposed to be connected to the conductive member 120. Figure 1 As shown in FIG, the first connection member 11 may be provided inside the first portion 111 to contact the conductive member 120. The first connection member 11 may be provided to contact one surface of the conductive member 120 exposed upward in the first direction. The first connection member 11 may connect the upper package 200 and the interposer substrate 100.

[0068] The second connection member 12 may be disposed to be connected to the conductive member 120 . The second connection member 12 may be disposed to contact the other surface of the conductive member 120 exposed downward in the first direction. The second connection member 12 may connect the lower package 300 and the interposer substrate 100 .

[0069] According to the interposer substrate and semiconductor package according to the above-described embodiments, the glass core disposed between the upper and lower packages can reduce the occurrence of warpage defects. The via holes disposed within the glass core can increase thermal stability and signal count. Furthermore, the interposer substrate and semiconductor package according to the above-described embodiments can improve power transmission characteristics. Furthermore, the connection member disposed within the via holes can reduce the height of the entire semiconductor package.

[0070] In the following, reference will be made to Figure 4 and Figure 5 An interposer substrate 100 and a semiconductor package 10 according to another embodiment are described.

[0071] Figure 4 is a cross-sectional view showing a portion of a semiconductor package according to another embodiment, and Figure 5 is a perspective view of an interposer substrate according to another embodiment.

[0072] Reference Figure 4 and Figure 5 The interposer substrate 100 according to this embodiment and the Figure 2 and Figure 3 Detailed descriptions of the same components are omitted.

[0073] Reference Figure 4 and Figure 5 ,and Figure 2 and Figure 3 Compared to the interposer substrate 100 of the embodiment shown in , the interposer substrate 100 according to this embodiment may further include a heat dissipation portion 130 connected to the cavity 102. The heat dissipation portion 130 may penetrate the core 101 from the first surface thereof and extend to the cavity 102. The heat dissipation portion 130 may contact the first electronic component 400 disposed in the cavity 102 (if the conductive film 401 is disposed between the first electronic component 400 and the core 101, the heat dissipation portion 130 may contact the conductive film 401).

[0074] A plurality of heat dissipating portions 130 may be provided. The heat dissipating portions 130 may be provided on one side of the cavity 102 in the first direction. For example, the plurality of heat dissipating portions 130 may be provided in regions of the core 101 corresponding to the cavity 102. The plurality of heat dissipating portions 130 may be arranged along a single direction (e.g., perpendicular to the first direction). The plurality of heat dissipating portions 130 may be spaced apart from one another.

[0075] The heat dissipation part 130 may include at least one of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof.

[0076] According to the interposer substrate and the semiconductor package according to the above-described another embodiment, heat generated from the electronic component disposed in the cavity can be effectively transferred and dispersed to the outside of the interposer substrate through the heat dissipation portion.

[0077] In the following, reference will be made to Figure 6 and Figure 7 An interposer substrate 100 and a semiconductor package 10 according to another embodiment are described.

[0078] Figure 6 is a cross-sectional view showing a portion of a semiconductor package according to another embodiment, and Figure 7 is a perspective view of an interposer substrate according to another embodiment.

[0079] Reference Figure 6 and Figure 7 The interposer substrate 100 according to this embodiment and the Figure 4 and Figure 5 Detailed descriptions of the same components are omitted.

[0080] Reference Figure 6 and Figure 7 ,and Figure 4 and Figure 5 Compared to the interposer substrate 100 of another embodiment shown in , the interposer substrate 100 according to this embodiment may include a heat dissipation portion 130 having a large planar surface area. The heat dissipation portion 130 may be provided so as to penetrate the core 101 from the first surface thereof and extend into the cavity 102. The heat dissipation portion 130 may contact the first electronic component 400 disposed in the cavity 102 (or, if the conductive film 401 is disposed between the first electronic component 400 and the core 101, the heat dissipation portion 130 may contact the conductive film 401). The heat dissipation portion 130 may have a plate shape that extends to an area corresponding to the interior area of ​​the cavity 102. The heat dissipation portion 130 may extend in a direction perpendicular to the first direction. As an example, the heat dissipation portion 130 may have a plate shape that extends in a plane perpendicular to the first direction.

[0081] The heat dissipation part 130 may include at least one of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof.

[0082] According to the interposer substrate and the semiconductor package according to another embodiment described above, a heat dissipation portion having a large planar area can be formed to increase the surface area of ​​the heat dissipation portion facing the electronic component (eg, the first electronic component 400 ), thereby improving heat dissipation efficiency.

[0083] In the following, reference will be made to Figure 8 An interposer substrate 100 according to another embodiment is described.

[0084] Figure 8 is a cross-sectional view illustrating a portion of a semiconductor package according to another embodiment.

[0085] Reference Figure 8 The interposer substrate 100 according to this embodiment and the Figure 2 and Figure 3 Detailed descriptions of the same components are omitted.

[0086] Reference Figure 8 ,and Figure 2 and Figure 3 Compared to the interposer substrate 100 of the embodiment shown in , the interposer substrate 100 according to this embodiment may further include a protection portion 140 covering a surface of the cavity 102. The protection portion 140 may be configured to shield electromagnetic interference (EMI) by covering a bottom surface of the cavity 102 in a first direction and side surfaces of the cavity 102 in a direction perpendicular to the first direction. The protection portion 140 may include at least one of a magnetic material and a metal material.

[0087] The interposer substrate and the semiconductor package according to another embodiment described above may facilitate shielding of electromagnetic waves.

[0088] In the following, reference will be made to Figure 9 A semiconductor package 10 according to another embodiment is described.

[0089] Figure 9 is a cross-sectional view of a semiconductor package according to another embodiment.

[0090] Reference Figure 9 The semiconductor package 10 according to this embodiment is different from the semiconductor package 10 according to Figure 1 Detailed descriptions of the same components are omitted.

[0091] Reference Figure 9 ,and Figure 1 Compared with the semiconductor package 10 of the embodiment shown in , the semiconductor package 10 according to this embodiment may further include: a third circuit substrate (or a third circuit board) 500 disposed above the interposer substrate 100; and a fourth connecting member 14 connecting the third circuit substrate 500 and the upper package 200.

[0092] Although not in Figure 9 , the third circuit substrate 500 may include an insulating layer, a conductive layer, and a via layer. The third circuit substrate 500 may serve as an interposer. The upper package 200 may be connected to the third circuit substrate 500 via a fourth connecting member 14. The fourth connecting member 14 may be a solder ball or the like. The first connecting member 11 may connect the interposer substrate 100 and the third circuit substrate 500.

[0093] According to the interposer substrate and the semiconductor package according to another embodiment described above, an additional interposer can be easily provided as needed without significantly changing the overall height of the semiconductor package.

[0094] In the following, reference will be made to Figures 10 to 15 A method for manufacturing the interposer substrate 100 and the semiconductor package 10 according to an embodiment is described.

[0095] Figures 10 to 15 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment.

[0096] Reference Figure 10 and Figure 11 , the core 101 having the cavity 102 may be formed by etching a portion of the glass substrate 1011. The cavity 102 may be formed at the glass substrate 1011 by an etching process (such as a wet etching process, a physical etching process, etc.).

[0097] Reference Figure 12 , the second portion 112 penetrating a portion of the core 101 may be formed from the second surface of the core 101. The second portion 112 may be formed by laser drilling.

[0098] Reference Figure 13 , the conductive member 120 may be filled inside the second portion 112. Figure 13 , the conductive member 120 is shown as being filled in the entire second portion 112 , but the present disclosure is not limited thereto, and the conductive member 120 may be filled in only a portion of the second portion 112 .

[0099] Reference Figure 14, a first portion 111 penetrating another portion of the core 101 may be formed from the first surface of the core 101 to connect to the second portion 112. Thus, a via hole 110 including the second portion 112 and the first portion 111 may be formed. The first portion 111 may be formed by laser drilling. As an example, the first portion 111 may be formed to have a shape symmetrical to the second portion 112. The first portion 111 and the second portion 112 may be formed such that the width of each of the first portion 111 and the second portion 112 increases as each of the first portion 111 and the second portion 112 moves toward the outside of the core 101.

[0100] Reference Figure 14 , can form Figures 1 to 3 The interposer substrate 100 of the embodiment shown in FIG. 1 includes a core 101 , a cavity 102 , and a conductive member 120 .

[0101] Reference Figure 15 , a first electronic component 400 may be disposed within the cavity 102. If desired, a conductive film 401 may be disposed between the first electronic component 400 and the core 101. The conductive film 401 may bond the first electronic component 400 to the core 101. A molding material 402 may be disposed in a space of the cavity 102 where the first electronic component 400 and the conductive film 401 are not disposed. The molding material 402 may secure the first electronic component 400.

[0102] Here, refer to Figure 1 as well as Figure 15 , a first connection member 11 may be formed inside the first portion 111, and an upper package 200 may be provided on the first connection member 11. In addition, a second connection member 12 may be formed on the first electronic element 400 and the conductive member 120 filled in the second portion 112, and a lower package 300 may be provided on the second connection member 12. Figure 1 The semiconductor package 10 of the embodiment.

[0103] According to the method for manufacturing a semiconductor package based on the above-described embodiment, the insertion of a glass core between the upper and lower packages reduces the occurrence of warpage defects. The provision of via holes in the glass core increases thermal stability and signal counts. Furthermore, the method for manufacturing a semiconductor package based on the above-described embodiment improves power transmission characteristics. Furthermore, the formation of a connecting member within the via hole reduces the overall height of the semiconductor package. A via hole structure comprising a first portion and a second portion can be easily formed by forming a via hole comprising through holes symmetrically formed and connected to each other on opposing surfaces of the glass core.

[0104] In the following, reference will be made to Figures 16 to 20A method for manufacturing the interposer substrate 100 and the semiconductor package 10 according to another embodiment is described.

[0105] Figures 16 to 20 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to another embodiment.

[0106] As mentioned above, please refer to Figure 11 and Figure 12 A core 101 is formed having a cavity 102 and a second portion 112. Here, referring to Figure 16 , a through hole 1301 may be formed penetrating from the first surface of the core 101 to the cavity 102. The through hole 1301 may be formed by laser drilling.

[0107] Reference Figure 17 , the conductive member 120 may be filled inside the second portion 112. In addition, the heat dissipation portion 130 may be formed by filling the through hole 1301 with a heat dissipation material.

[0108] exist Figure 17 , the conductive member 120 is shown as being filled in the entire second portion 112 , but the present disclosure is not limited thereto, and the conductive member 120 may be filled in only a portion of the second portion 112 .

[0109] Reference Figure 18 , a first portion 111 may be formed that penetrates another portion of the core 101 from the first surface of the core 101 to form the via hole 110 including the second portion 112 and the first portion 111. The first portion 111 may be formed by laser drilling. As an example, the first portion 111 may be formed to have a shape symmetrical to the second portion 112. The first portion 111 and the second portion 112 may be formed such that the width of each of the first portion 111 and the second portion 112 increases as each of the first portion 111 and the second portion 112 moves toward the outside of the core 101.

[0110] Reference Figure 18 , can form a basis Figure 4 and Figure 5 An interposer substrate 100 according to another embodiment of the present invention includes a core portion 101 , a cavity 102 , a conductive member 120 , and a heat dissipation portion 130 .

[0111] Reference Figure 19 , a first electronic component 400 may be disposed within the cavity 102. If desired, a conductive film 401 may be disposed between the first electronic component 400 and the core 101. The conductive film 401 may bond the first electronic component 400 to the core 101. A molding material 402 may be disposed in a space of the cavity 102 where the first electronic component 400 and the conductive film 401 are not disposed. The molding material 402 may secure the first electronic component 400.

[0112] Reference Figure 20 , a first connection member 11 may be formed inside the first portion 111, and an upper package 200 may be provided on the first connection member 11. In addition, a second connection member 12 may be formed on the first electronic element 400 and the conductive member 120 filled in the second portion 112, and a lower package 300 may be provided on the second connection member 12. Thus, a semiconductor package 10 according to another embodiment may be formed. Here, the method for forming the second connection member 12 is not limited, and may also be used in accordance with the present invention. Figure 19 The second connecting member 12 is formed in the step of.

[0113] According to another embodiment of a method for manufacturing a semiconductor package, a glass core is inserted between the upper and lower packages, thereby reducing the occurrence of warpage defects. The presence of a via hole in the glass core increases thermal stability and signal count, and further improves power transmission characteristics. Furthermore, the formation of a connecting member within the via hole can reduce the overall height of the semiconductor package. A via hole structure comprising a first portion and a second portion can be easily formed by forming a via hole comprising symmetrically connected through-holes formed on two opposing surfaces of the glass core. Heat generated by the electronic components disposed within the cavity can be effectively transferred and dispersed to the exterior of the interposer substrate via the heat dissipation portion.

[0114] While the present disclosure has been described in connection with what are presently considered to be practical embodiments, it will be understood that the disclosure is not limited to the disclosed embodiments, but on the contrary, the disclosure is intended to cover various modifications and equivalents included within the spirit and scope of the appended claims.

Claims

1. An interposer substrate, comprising: a core including a first surface and a second surface opposing each other in a first direction, including a via hole penetrating from the first surface to the second surface, and comprising glass; as well as a conductive member disposed only in a portion of the via hole, Wherein, the via hole comprises: a first portion penetrating a portion of the core from the first surface; and A second portion penetrates another portion of the core from the second surface to be connected to the first portion, and the conductive member is provided at the second portion.

2. The interposer substrate according to claim 1, wherein The core includes a cavity on the second surface, and the via hole is provided in plural numbers around the cavity.

3. The interposer substrate according to claim 1, wherein The conductive member is also provided in a portion of the first portion. 4 . The interposer substrate according to claim 2 , further comprising a heat dissipation portion penetrating the core from the first surface and extending to the cavity.

5. The interposer substrate according to claim 4, wherein The heat dissipation portion is provided in plurality, and the plurality of heat dissipation portions are provided to be spaced apart from each other.

6. The interposer substrate according to claim 4, wherein The heat dissipation portion has a plate shape extending in a plane perpendicular to the first direction. 7 . The interposer substrate according to claim 2 , further comprising a protection portion covering a bottom surface of the cavity in the first direction and a side surface of the cavity in a direction perpendicular to the first direction.

8. The interposer substrate according to claim 1, wherein In the first portion and / or the second portion, a width of one outer end of the core is greater than a width of one inner end of the core opposite to the one outer end in the first direction.

9. The interposer substrate according to claim 1, wherein The first portion and the second portion have symmetrical shapes with respect to a reference surface perpendicular to the first direction.

10. The interposer substrate according to claim 1, wherein Of the first portion and the second portion, the conductive member is provided only in the second portion.

11. An interposer substrate, comprising: a core including a first surface and a second surface opposite to each other in a first direction, including a via hole penetrating from the first surface to the second surface, including a cavity located on the second surface, and comprising glass; a conductive member disposed in a portion of the via hole; as well as a heat dissipation portion, penetrating the core from the first surface and extending to the cavity, Wherein, the via hole comprises: a first portion penetrating a portion of the core from the first surface; and A second portion penetrates another portion of the core from the second surface to be connected to the first portion, and the conductive member is provided at the second portion.

12. The interposer substrate according to claim 11, wherein The via holes are provided in plural numbers around the cavity.

13. The interposer substrate according to claim 11, wherein The conductive member is also provided in a portion of the first portion.

14. The interposer substrate according to claim 11, wherein The heat dissipation portion is provided in plurality, and the plurality of heat dissipation portions are provided to be spaced apart from each other.

15. The interposer substrate according to claim 11, wherein The heat dissipation portion extends in a direction perpendicular to the first direction.

16. The interposer substrate according to claim 11, wherein In the first portion and / or the second portion, a width of one outer end of the core is greater than a width of one inner end of the core opposite to the one outer end in the first direction.

17. The interposer substrate according to claim 11, wherein The first portion and the second portion have symmetrical shapes with respect to a reference surface perpendicular to the first direction.

18. A semiconductor package, comprising: interposer substrate; an upper package disposed at one side of the interposer substrate and including a first circuit substrate including an insulating layer and a conductive layer; as well as a connecting member partially provided in the interposer substrate to connect the upper package and the interposer substrate, Wherein, the interposer substrate comprises: a core including a first surface and a second surface opposing each other in a first direction, including a via hole penetrating from the first surface to the second surface, and comprising glass; and a conductive member disposed in a portion of the via hole, and The via hole includes: a first portion that penetrates a portion of the core from the first surface and provides a space in which the connecting member is disposed; and a second portion that penetrates another portion of the core from the second surface to be connected to the first portion, and the conductive member is disposed at the second portion. 19 . The semiconductor package of claim 18 , further comprising a lower package disposed on the other side of the interposer substrate and including a second circuit substrate including an insulating layer and a conductive layer.

20. The semiconductor package according to claim 18, wherein The core has a cavity on the second surface, and the semiconductor package further includes a heat dissipation portion penetrating the core from the first surface and extending to the cavity.

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