Chip-on-film packaging structure

Abstract

The invention provides a chip-on-film packaging structure. The chip-on-film packaging structure comprises a flexible circuit carrier plate, a chip and a preset patch attaching area, the flexible circuit carrier comprises a flexible substrate, a patterned metal layer and a solder mask layer. The flexible substrate is provided with a chip setting area. The patterned metal layer is disposed on the flexible substrate and includes a plurality of pins. The pins extend outwards from the chip setting area. The solder mask layer is disposed on the flexible substrate and has an opening to define a chip setting region. The solder mask layer partially covers the patterned metal layer and has an alignment slot. The chip is disposed on the flexible circuit board and located in the chip setting area. The chip is electrically connected with the pins. The patch predetermined attaching area is defined on the flexible circuit carrier plate, wherein the alignment slot is located in the patch predetermined attaching area. The chip-on-film packaging structure provided by the invention is beneficial to alignment identification when the patch is attached, so that the patch can be accurately and quickly attached to the flexible circuit carrier plate.

Description

Technical Field

[0001] The present invention relates to a packaging structure, and in particular to a chip-on-film packaging structure. Background Art

[0002] Current chip-on-film (COF) packaging structures typically use a special identification pattern on the copper foil used to form the pins for alignment during various operations. However, as pin density increases, the space available for the identification pattern becomes increasingly limited. Furthermore, flexible circuit substrates are often covered with dark or opaque (e.g., black) solder masks to meet specific requirements, making the copper foil covered by the solder mask obscured. This complicates alignment and identification operations. For example, when attaching heat sinks or other patches to the flexible circuit substrate, there is no clearly identifiable identification pattern near the patch location for alignment. Summary of the Invention

[0003] The present invention is directed to a film flip chip packaging structure, which is helpful for alignment recognition when attaching a patch, so that the patch can be accurately and quickly attached to a flexible circuit carrier.

[0004] According to an embodiment of the present invention, a thin film chip packaging structure includes a flexible circuit carrier, a chip and a predetermined patch attachment area. The flexible circuit carrier includes a flexible substrate, a patterned metal layer and a solder mask. The flexible substrate has a chip setting area. The patterned metal layer is arranged on the flexible substrate and includes a plurality of pins. These pins extend outward from the chip setting area. The solder mask is arranged on the flexible substrate and has an opening to define the chip setting area. The solder mask partially covers the patterned metal layer and has an alignment slot. The chip is arranged on the flexible circuit carrier and is located in the chip setting area. The chip is electrically connected to these pins. The predetermined patch attachment area is defined on the flexible circuit carrier, wherein the alignment slot is located in the predetermined patch attachment area.

[0005] Based on the above, in the design of the thin film chip package structure of the present invention, the solder mask layer of the flexible circuit substrate has an alignment slot, and this alignment slot is located within the predetermined patch attachment area. When the patch is attached to the flexible circuit substrate, the patch placement machine can capture the image of the alignment slot as a basis for patch attachment alignment. Compared to designs that form an alignment pattern with a patterned metal layer, it is not limited by the layout space and does not need to consider whether the alignment pattern can still be clearly identified under the coverage of the solder mask layer. In addition, the location of the alignment slot within the predetermined patch attachment area can reduce the time spent by the patch placement machine to search for the alignment pattern and the actual patch attachment position, allowing the patch to be accurately and quickly attached to the flexible circuit substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1is a schematic top view of a chip-on-film packaging structure according to an embodiment of the present invention;

[0007] Figure 2 is a schematic top view of a chip-on-film packaging structure according to an embodiment of the present invention;

[0008] Figure 3 FIG. 1 is a schematic diagram of connecting an identification pattern and a pin according to an embodiment of the present invention.

[0009] Description of Reference Numerals

[0010] 100, 100a: Chip-on-film packaging structure;

[0011] 110, 110a: flexible circuit carrier;

[0012] 112: Flexible substrate;

[0013] 113: Chip setting area;

[0014] 114, 114a: patterned metal layer;

[0015] 115: pin;

[0016] 116: solder mask;

[0017] 117: Opening;

[0018] 119, 119a: alignment slots;

[0019] 120: chip;

[0020] 130: patch predetermined attachment area;

[0021] 132: patch;

[0022] 132a: heat dissipation layer;

[0023] 132b: Insulation protection layer;

[0024] 140: Encapsulation colloid;

[0025] A: Line blank area;

[0026] D: distance;

[0027] R, R': recognition pattern;

[0028] S: side wall. DETAILED DESCRIPTION

[0029] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0030] The present invention will be more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size, or dimensions of layers or regions in the drawings may be exaggerated for clarity.

[0031] It should be noted that the chip-on-film package structure shown in the following figures is operated in a tape-to-reel manner. Although the heat sink in the following figures is only schematically shown as being applied to a device area on the tape that forms the chip-on-film package structure, the present invention is not limited to this. The heat sink in the following figures can be applied to multiple device areas on the tape at the same time.

[0032] Figure 1 This is a top view of a chip-on-film package structure according to an embodiment of the present invention. Figure 1 In this embodiment, the chip-on-film package structure 100 includes a flexible circuit carrier 110, a chip 120, and a predetermined patch attachment area 130. The flexible circuit carrier 110 includes a flexible substrate 112, a patterned metal layer 114, and a solder mask 116. The flexible substrate 112 has a chip setting area 113. The patterned metal layer 114 is disposed on the flexible substrate 112 and includes a plurality of pins 115, wherein these pins 115 extend outward from the chip setting area 113. The solder mask 116 is disposed on the flexible substrate 112 and has an opening 117 to define the chip setting area 113. The solder mask 116 partially covers the patterned metal layer 114 and has an alignment slot 119. The chip 120 is disposed on the flexible circuit carrier 110 and is located in the chip setting area 113, and the chip 120 is electrically connected to these pins 115. A predetermined chip attachment area 130 is defined on the flexible circuit substrate 110, with the alignment slot 119 located within the predetermined chip attachment area 130. In other words, the predetermined chip attachment area 130 at least partially overlaps with the solder mask 116. It should be noted that the predetermined chip attachment area 130 is a pre-defined attachment area of ​​the chip-on-film package structure 100 when additional chips are added thereto to meet various needs.

[0033] Specifically, in this embodiment, the flexible substrate 112 is made of, for example, polyethylene terephthalate, polyimide, polyethersulfone, polycarbonate, or other suitable flexible materials. Pins 115 and a solder mask 116 are disposed on the same surface of the flexible substrate 112, with the solder mask 116 partially covering the pins 115 to prevent them from being damaged or shorted by foreign matter. The portions of the pins 115 exposed by the solder mask 116 can be used to electrically connect to the chip 120 or external components. The solder mask 116 is a dark or opaque material, such as black solder mask ink, but this is not a limitation. The chip 120 can be flip-chip disposed within the chip mounting area 113 and electrically connected to the pins 115 within the chip mounting area 113 via, for example, bumps (not shown). Furthermore, the chip-on-film package structure 100 of this embodiment may further include an encapsulant 140 that is filled between the chip 120 and the flexible circuit carrier 110 and covers the chip placement area 113 and the four sidewalls S of the chip 120 to protect the electrical contacts between the chip 120 and the flexible circuit carrier 110. In this embodiment, the encapsulant 140 is, for example, an underfill material.

[0034] Furthermore, in this embodiment, the chip placement area 113 is located within the patch attachment area 130, but this is not a limitation. That is, the patch attachment area 130 encompasses the chip placement area 113, so the patch can cover the chip 120 when placed on the flexible circuit board 110. Here, the alignment slot 119 of the solder mask 116 is located outside the projection of the encapsulant 140 onto the flexible circuit board 110. In other words, the encapsulant 140 does not cover the alignment slot 119 of the solder mask 116. In one embodiment, the area of ​​the alignment slot 119 can be, for example, greater than or equal to 1.5 mm x 1.5 mm, which facilitates the capture of an image of the alignment slot 119 by the placement machine.

[0035] Furthermore, the flexible substrate 112 of this embodiment has a circuit blank area A. The patterned metal layer 114 is not disposed in the circuit blank area A, and the alignment slot 119 corresponds to the circuit blank area A. In other words, the flexible circuit carrier 110 of this embodiment has the alignment slot 119 positioned where no patterned metal layer 114 is located. This prevents the patterned metal layer 114 from being damaged or contaminated at the alignment slot 119 due to the lack of protection from the solder mask 116. When viewed from above, the shape of the alignment slot 119 may be, for example, rectangular, diamond-shaped, polygonal, triangular, circular, or elliptical, but is not limited thereto.

[0036] In this embodiment, the chip-on-film package structure 100 includes alignment slots 119 formed in the solder mask 116 of the flexible circuit substrate 110 within the predetermined die attachment area 130. These slots serve as a reference for alignment when attaching the die to the flexible circuit substrate 110. Therefore, if the patterned metal layer 114 cannot be provided with an alignment pattern due to circuit configuration limitations, or if the solder mask 116 is dark or opaque, making the patterned metal layer 114 difficult to clearly identify, the chip placement machine can use the alignment slots 119 in the solder mask 116 to perform die alignment during attachment. Furthermore, the location of the alignment slots 119 within the predetermined die attachment area 130 reduces the time required by the chip placement machine's image capture device to locate the alignment reference pattern and the actual die attachment location, enabling accurate and rapid die attachment to the flexible circuit substrate 110.

[0037] Figure 2 FIG2 is a schematic top view of a chip-on-film packaging structure according to an embodiment of the present invention. Figure 3 This is a schematic diagram of a connection between an identification pattern and a pin according to an embodiment of the present invention. Figure 1 and Figure 2 , the chip-on-film packaging structure 100a of this embodiment is similar to the aforementioned embodiment, and the difference between the two is that the patterned metal layer 114a of the flexible circuit carrier 110a of this embodiment further includes an identification pattern R, wherein the identification pattern R is located in the alignment slot 119a. Furthermore, the alignment slot 119a may deviate from the central position of the patch attachment area 130. For example, the alignment slot 119a of this embodiment is located at a corner adjacent to the packaging colloid 140, but is not limited to this. Here, the boundary spacing distance D between the identification pattern R and the alignment slot 119a, that is, the identification pattern R is an independent pattern. In this embodiment, the identification pattern R may be a dummy pattern. In another embodiment, please refer to Figure 3 The identification pattern R' can also be connected to the pin 115. In other words, the identification pattern R' can be a specific pattern formed by a portion of the pin 115, which still falls within the scope of protection of the present invention. Therefore, in addition to using the alignment slot 119a to perform the alignment operation during chip attachment, the placement machine can also achieve the same purpose by using the identification patterns R and R' exposed by the alignment slot 119a.

[0038] In addition, the chip-on-film package structure 100a of this embodiment further includes a patch 132. The patch 132 is disposed in the patch attachment area 130 and may be, for example, a heat dissipation patch, a structural reinforcement patch, or an electromagnetic shielding patch. In this embodiment, the patch 132 is a heat dissipation patch. The heat dissipation patch 132 corresponds to the chip placement area 113 and covers the chip 120 to directly help dissipate heat from the chip 120. Furthermore, the heat dissipation patch 132 may include a heat dissipation layer 132a, an insulating protective layer 132b, and an adhesive layer (not shown). The heat dissipation layer 132a is attached to the chip 120 and the flexible circuit carrier 110a via an adhesive layer, while the insulating protective layer 132b is formed on the heat dissipation layer 132a via another adhesive layer or coating to protect the heat dissipation layer 132a from damage. The material of the heat dissipation layer 132a may include metal foil or graphite film, wherein the metal foil may be, for example, aluminum foil or copper foil, but the present invention is not limited thereto. The insulating protection layer 132 b is made of polyimide, for example, but the present invention is not limited thereto.

[0039] In summary, in the design of the chip-on-film package structure of the present invention, the solder mask layer of the flexible circuit substrate has an alignment slot, and this alignment slot is located within the predetermined patch attachment area. When the patch is attached to the flexible circuit substrate, the placement machine can capture the image of the alignment slot as a basis for the patch attachment alignment. Compared to designs that form an alignment pattern with a patterned metal layer, this is not limited by the layout space and does not need to consider whether the alignment pattern is still clearly identifiable under the coverage of the solder mask layer. In addition, the location of the alignment slot within the predetermined patch attachment area can reduce the time spent by the placement machine to search for the alignment pattern and the actual patch attachment position, allowing the patch to be accurately and quickly attached to the flexible circuit substrate.

[0040] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip-on-film packaging structure, characterized in that: include: Flexible circuit board, including: A flexible substrate having a chip placement area; a patterned metal layer disposed on the flexible substrate and comprising a plurality of pins extending outward from the chip placement area; and a solder mask layer disposed on the flexible substrate and having an opening to define the chip placement area, the solder mask layer partially covering the patterned metal layer and having an alignment slot; a chip, disposed on the flexible circuit carrier and located in the chip placement area, the chip being electrically connected to the plurality of pins; and A patch predetermined attachment area is defined on the flexible circuit carrier, wherein the alignment slot is located in the patch predetermined attachment area.

2. The chip-on-film packaging structure according to claim 1, wherein: Also includes: The packaging colloid is filled between the chip and the flexible circuit carrier and covers the chip setting area and the four side walls of the chip.

3. The chip-on-film packaging structure according to claim 2, wherein: The chip setting area is located in the patch predetermined attachment area, and the alignment slot is located outside the projection range of the packaging colloid on the flexible circuit carrier.

4. The chip-on-film packaging structure according to claim 1, wherein: The flexible substrate has a circuit blank area, the patterned metal layer is not configured in the circuit blank area, and the alignment slot corresponds to the circuit blank area.

5. The chip-on-film packaging structure according to claim 1, wherein: The patterned metal layer further includes an identification pattern, and the identification pattern is located in the alignment slot.

6. The chip-on-film packaging structure according to claim 5, wherein: The identification pattern is spaced apart from the boundary of the alignment slot.

7. The chip-on-film packaging structure according to claim 1, wherein: In a top view, the alignment slots may have a shape including a rectangle, a diamond, a polygon, a triangle, a circle or an ellipse.

8. The chip-on-film packaging structure according to claim 1, wherein: The solder mask is made of dark material or opaque material.

9. The chip-on-film packaging structure according to claim 1, wherein: The area of ​​the alignment slot is greater than or equal to 1.5 mm×1.5 mm.

10. The chip-on-film packaging structure according to claim 1, wherein: Also includes: The patch is arranged in the patch predetermined attachment area, and the patch includes a heat dissipation patch, a structural reinforcement patch or an electromagnetic shielding patch.

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