Circuit board processing method and circuit board processing apparatus

Abstract

This invention discloses a circuit board processing method and circuit board processing equipment, comprising: processing a first through hole on a multilayer circuit board, the multilayer circuit board including a first solder mask layer and a second solder mask layer respectively disposed on two adjacent circuit boards, the first solder mask layer and the second solder mask layer being disposed opposite to each other, and the first through hole penetrating the first solder mask layer and the second solder mask layer; performing a desmearing process on the multilayer circuit board to form a first space on the first solder mask layer and a second space on the second solder mask layer; depositing a first metal layer on the inner wall of the first through hole, the first space and the second space; removing the first solder mask layer and the second solder mask layer, and electroplating a second metal layer on the first metal layer on the inner wall of the first through hole to obtain a target circuit board including a target metallized hole, so as to completely remove the low-density first metal layer deposited in the first solder mask layer and the second solder mask layer, so as to achieve complete electrical isolation between the two adjacent circuit boards with the first solder mask layer and the second solder mask layer, and achieve zero residual solder.

Description

Technical Field

[0001] This invention relates to the field of circuit board technology, and in particular to a circuit board processing method and circuit board processing equipment. Background Technology

[0002] In the development of high-speed communication products, residual traces on circuit boards can adversely affect signal integrity, thereby impacting product performance. Therefore, controlling the length of these residual traces and minimizing their negative impact on signals has become a crucial challenge in the development of high-speed communication products.

[0003] Currently, back-drilling technology is the main method for controlling residual stake length. However, back-drilling technology is limited by factors such as changes in dielectric thickness during circuit board lamination and the ability to control drilling depth. Excessive back-drilling depth can easily lead to short circuits or open circuits in the circuit board. Conversely, insufficient back-drilling depth results in excessively long residual stakes, affecting electrical conductivity and signal integrity, thus failing to achieve the ideal state of zero residual stakes. Summary of the Invention

[0004] This invention provides a circuit board processing method and circuit board processing equipment to solve the problem that existing circuit board processing technology cannot achieve zero residual stubs, resulting in poor electrical conductivity and signal integrity of the circuit board.

[0005] A circuit board manufacturing method, comprising:

[0006] A first through-hole is fabricated on a multilayer circuit board, the multilayer circuit board including a first solder mask layer and a second solder mask layer respectively disposed on two adjacent circuit boards, the first solder mask layer and the second solder mask layer being disposed opposite to each other, and the first through-hole penetrating the first solder mask layer and the second solder mask layer.

[0007] The multilayer circuit board is subjected to a desmearing process to form a first space on the first solder mask layer and a second space on the second solder mask layer.

[0008] A first metal layer is deposited on the inner wall of the first through-hole, the first space, and the second space;

[0009] Remove the first solder mask layer and the second solder mask layer, and electroplate a second metal layer on the first metal layer on the inner wall of the first through hole to obtain a target circuit board including the target metallized hole.

[0010] Furthermore, before processing the first through-hole on the multilayer circuit board, the circuit board processing method further includes:

[0011] A first solder mask layer is fabricated on the first circuit board;

[0012] A second solder mask layer is fabricated on the second circuit board;

[0013] The first circuit board and the second circuit board are laminated to obtain the multilayer circuit board, wherein the first solder mask layer and the second solder mask layer are disposed opposite to each other.

[0014] Furthermore, the first solder resist layer includes a first solder resist structure and a second solder resist structure; the second solder resist layer includes a third solder resist structure and a fourth solder resist structure;

[0015] The process of fabricating the first solder mask layer on the first circuit board includes:

[0016] A first solder resist is applied at a predetermined location on the first circuit board to form a first solder resist structure; a second solder resist is applied on the first solder resist structure to form a second solder resist structure.

[0017] The process of fabricating a second solder mask layer on the second circuit board includes:

[0018] A first solder resist is applied at a predetermined position on the second circuit board to form a third solder resist structure; a second solder resist is applied on the third solder resist structure to form a fourth solder resist structure.

[0019] Furthermore, the first solder resist structure and the second solder resist structure have different solubilities; the third solder resist structure has the same solubility as the first solder resist structure; and the fourth solder resist structure has the same solubility as the second solder resist structure.

[0020] The diameter of the first solder resist structure is smaller than the diameter of the second solder resist structure; the diameter of the third solder resist structure is equal to the diameter of the first solder resist structure; and the diameter of the fourth solder resist structure is equal to the diameter of the second solder resist structure.

[0021] Furthermore, the first solder resist layer includes a first solder resist structure; the second solder resist layer includes a third solder resist structure;

[0022] The step of performing a desmearing process on the multilayer circuit board to form a first space on the first solder mask layer and a second space on the second solder mask layer includes:

[0023] The first solvent is used to remove the solder mask from the multilayer circuit board, thereby removing the first solder mask structure and forming a first space on the first solder mask layer. The third solder mask structure is then removed, and a second space is formed on the second solder mask layer.

[0024] Furthermore, the first solder resist layer also includes a second solder resist structure, and the second solder resist layer also includes a fourth solder resist structure.

[0025] The process of removing the first solder mask layer and the second solder mask layer, and electroplating a second metal layer on the first metal layer on the inner wall of the first through hole to obtain a target circuit board including the target metallized hole includes:

[0026] Using a second solvent, the second solder resist structure and the fourth solder resist structure are removed, and a second metal layer is electroplated on the first metal layer on the inner wall of the first through hole to obtain a target circuit board including the target metallized hole.

[0027] Furthermore, both the first solvent and the second solvent are alkaline solvents.

[0028] Furthermore, the concentration of the first solvent is less than the concentration of the second solvent.

[0029] Furthermore, the multilayer circuit board also includes an insulating dielectric layer disposed on two adjacent circuit boards, and the first through hole penetrates the insulating dielectric layer;

[0030] The process of electroplating a second metal layer on the first metal layer on the inner wall of the first through hole to obtain a target circuit board including the target metallized hole includes:

[0031] The first metal layer and the second metal layer on the insulating dielectric layer are etched to obtain a target circuit board including a target metallized hole.

[0032] A circuit board processing device for use in the above-described circuit board processing method.

[0033] The aforementioned circuit board processing method and equipment process a first through-hole on a multilayer circuit board. The multilayer circuit board includes a first solder mask layer and a second solder mask layer respectively disposed on two adjacent circuit boards. The first solder mask layer and the second solder mask layer are disposed opposite to each other. The first through-hole penetrates the first solder mask layer and the second solder mask layer. The multilayer circuit board is de-smudged, forming a first space on the first solder mask layer and a second space on the second solder mask layer. This results in the metal material deposited in the first space and the second space having a low density, making it easy to remove when the first through-hole is subsequently metallized. A first metal layer is deposited on the inner wall of the first through-hole, in the first space and the second space. The first solder mask layer and the second solder mask layer are removed. A second metal layer is electroplated on the first metal layer on the inner wall of the first through-hole. This enables the metallization of the first through-hole. At the same time, by removing the first solder mask layer and the second solder mask layer, the low-density first metal layer deposited in the first solder mask layer and the second solder mask layer is completely removed, achieving complete electrical isolation between the two adjacent circuit boards with the first solder mask layer and the second solder mask layer, resulting in a target circuit board with a target metallized hole including zero residual solder. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a flowchart of a circuit board processing method according to an embodiment of the present invention;

[0036] Figure 2 This is another flowchart of a circuit board processing method according to one embodiment of the present invention;

[0037] Figure 3 This is a schematic flowchart of a circuit board processing method according to an embodiment of the present invention.

[0038] In the figure: 10, multilayer circuit board; 11, first through hole; 12, first solder mask layer; 121, first space; 13, second solder mask layer; 131, second space; 14, insulating dielectric layer; 20, first metal layer; 30, second metal layer. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0041] To fully understand this invention, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0042] This embodiment provides a circuit board processing method, such as... Figure 1 and Figure 3 As shown, it includes:

[0043] S101: A first through hole 11 is processed on the multilayer circuit board 10. The multilayer circuit board 10 includes a first solder mask layer 12 and a second solder mask layer 13 respectively disposed on two adjacent circuit boards. The first solder mask layer 12 and the second solder mask layer 13 are disposed opposite to each other. The first through hole 11 penetrates the first solder mask layer 12 and the second solder mask layer 13.

[0044] S102: Perform a descaling process on the multilayer circuit board 10, forming a first space 121 on the first solder mask layer 12 and a second space 131 on the second solder mask layer 13.

[0045] S103: Deposit a first metal layer 20 on the inner wall of the first through hole 11, the first space 121 and the second space 131.

[0046] S104: Remove the first solder mask layer 12 and the second solder mask layer 13, and electroplate the second metal layer 30 on the first metal layer 20 on the inner wall of the first through hole 11 to obtain the target circuit board including the target metallized hole.

[0047] The multilayer circuit board 10 includes at least three circuit boards. Understandably, metal traces are pre-processed on each circuit board layer. Exemplarily, the metal traces can be designed based on practical experience, and then processed on each of the aforementioned circuit boards according to the wiring design. Understandably, the material of the metal traces can be copper, or alternatively, other metals such as silver or gold, without limitation. The first solder mask layer 12 and the second solder mask layer 13 are made of an anti-plating material. Further, the anti-plating material is a material that can be removed by a specific solvent. Optionally, the anti-plating material includes ink, acrylic resin, or phenolic resin; this embodiment uses ink as the material for the first solder mask layer 12 and the second solder mask layer 13 for illustration.

[0048] As an example, in step S101, a first through-hole 11 is machined on the multi-layer circuit board 10. Optionally, the position and aperture size of the first through-hole 11 on the multi-layer circuit board 10 can be selected according to actual experience, as long as the first through-hole 11 penetrates through the first solder mask layer 12 and the second solder mask layer 13, and no limitation is made here. Preferably, the center positions of the first solder mask layer 12 and the second solder mask layer 13 are aligned with the center position of the first through-hole 11. It should be noted that it is necessary to ensure that the multi-layer circuit board 10 includes the first solder mask layer 12 and the second solder mask layer 13 respectively provided on adjacent two-layer circuit boards, and the first solder mask layer 12 and the second solder mask layer 13 are arranged oppositely. Specifically, the adjacent two-layer circuit boards are two-layer circuit boards that need to be electrically isolated in the multi-layer circuit board 10. Exemplarily, the multi-layer circuit board 10 includes N-layer circuit boards. When it is necessary to electrically connect the first to M-layer circuit boards, the above-mentioned adjacent two-layer circuit boards are the M-layer circuit board and the M + 1-layer circuit board. Among them, N≥3, 2≤M<N. In this embodiment, it is ensured that the multi-layer circuit board 10 for machining the first through-hole 11 includes the first solder mask layer 12 and the second solder mask layer 13 respectively provided on adjacent two-layer circuit boards, the first solder mask layer 12 and the second solder mask layer 13 are arranged oppositely, and the first through-hole 11 penetrates through the first solder mask layer 12 and the second solder mask layer 13, so that when the first through-hole 11 is metallized subsequently, the metal material will not be deposited at the positions corresponding to the first solder mask layer 12 and the second solder mask layer 13, thereby isolating two adjacent circuit boards that need to be electrically isolated and achieving zero stub on the first through-hole 11.

[0049] Optionally, the method of machining the first through-hole 11 on the multi-layer circuit board 10 can adopt laser drilling, drilling machine drilling, plasma etching technology or other processes capable of machining the first through-hole 11, as long as the first through-hole 11 penetrates through the first solder mask layer 12 and the second solder mask layer 13, and no limitation is made here.

[0050] As an example, in step S102, the multilayer circuit board 10 undergoes a descaling process to form a first space 121 on the first solder resist layer 12 and a second space 131 on the second solder resist layer 13. In this embodiment, after step S101, i.e., after processing the first through-hole 11 on the multilayer circuit board 10, it is necessary to treat the contaminants after drilling. As an example, a specific solvent can be used, which is a solvent that can clean the contaminants after drilling, and at the same time remove part of the first solder resist layer 12 forming the first space 121 on the first solder resist layer 12, and remove part of the second solder resist layer 13 forming the second space 131 on the second solder resist layer 13. Exemplarily, the specific solvent can be an alkaline solvent. Since the first solder resist layer 12 and the second solder resist layer 13 are inks, using an alkaline solvent to remove at least part of the first solder resist layer 12 and the second solder resist layer 13, thereby cleaning the contaminants after drilling while forming the first space 121 on the first solder resist layer 12 and the second space 131 on the second solder resist layer 13. In this embodiment, by performing a desmearing process on the multilayer circuit board 10, a first space 121 is formed on the first solder mask layer 12 and a second space 131 is formed on the second solder mask layer 13. This results in the metal material deposited in the first space 121 and the second space 131 having a lower density when the first through-hole 11 is subsequently metallized, making it easier to remove. This allows for complete electrical isolation between the two adjacent circuit boards with the first solder mask layer 12 and the second solder mask layer 13.

[0051] As an example, in step S103, a first metal layer 20 is deposited on the inner wall of the first through-hole 11, the first space 121, and the second space 131. In this embodiment, the material of the first metal layer 20 is preferably copper. Optionally, a copper plating process known to those skilled in the art can be used to perform copper plating treatment on the inner wall of the first through-hole 11, the first space 121, and the second space 131 to form the first metal layer 20. Due to the presence of the first space 121 and the second space 131, the density of the first metal layer 20 deposited in the first space 121 and the second space 131 is low, that is, the copper plating at the locations of the first space 121 and the second space 131 is poor, making the first metal layer 20 more sparse, thereby facilitating complete removal. This allows for complete electrical isolation between two adjacent circuit boards with the first solder mask layer 12 and the second solder mask layer 13. At the same time, the formation of the first metal layer 20 on the inner wall of the first through-hole 11 is beneficial for subsequent electroplating processes.

[0052] As an example, in step S104, the first solder mask layer 12 and the second solder mask layer 13 are removed, and a second metal layer 30 is electroplated on the first metal layer 20 on the inner wall of the first through hole 11 to obtain a target circuit board including the target metallized hole. In this example, a specific solvent can be used to completely remove the first solder mask layer 12 and the second solder mask layer 13, thereby completely removing the low-density first metal layer 20 deposited in the first solder mask layer 12 and the second solder mask layer 13. Then, the second metal layer 30 is electroplated on the first metal layer 20 on the inner wall of the first through hole 11, which enables the metallization treatment of the first through hole 11 and simultaneously achieves complete electrical isolation between the two adjacent circuit boards with the first solder mask layer 12 and the second solder mask layer 13, resulting in a target circuit board including the target metallized hole with zero residual solder.

[0053] In this embodiment, a first through-hole 11 is processed on a multilayer circuit board 10. The multilayer circuit board 10 includes a first solder resist layer 12 and a second solder resist layer 13 respectively disposed on two adjacent circuit boards. The first solder resist layer 12 and the second solder resist layer 13 are disposed opposite to each other. The first through-hole 11 penetrates the first solder resist layer 12 and the second solder resist layer 13. The multilayer circuit board 10 is descaled, forming a first space 121 on the first solder resist layer 12 and a second space 131 on the second solder resist layer 13. This results in the metal material deposited in the first space 121 and the second space 131 having a low density when the first through-hole 11 is subsequently metallized, making it easier to remove. A first metal layer 20 is deposited on the inner wall of a through hole 11, the first space 121, and the second space 131. The first solder mask 12 and the second solder mask 13 are removed. A second metal layer 30 is electroplated on the first metal layer 20 on the inner wall of the first through hole 11. This allows the first through hole 11 to be metallized. At the same time, by removing the first solder mask 12 and the second solder mask 13, the low-density first metal layer 20 deposited in the first solder mask 12 and the second solder mask 13 is completely removed. This enables complete electrical isolation between the two adjacent circuit boards with the first solder mask 12 and the second solder mask 13, resulting in a target circuit board with a target metallized hole including zero residual solder.

[0054] In one embodiment, such as Figure 2 As shown, before step S101, before processing the first through hole 11 on the multilayer circuit board 10, the circuit board processing method further includes:

[0055] S201: Process the first solder mask layer 12 on the first circuit board.

[0056] S202: Process the second solder mask layer 13 on the second circuit board.

[0057] S203: The first circuit board and the second circuit board are laminated to obtain a multilayer circuit board 10, wherein the first solder mask layer 12 and the second solder mask layer 13 are arranged opposite to each other.

[0058] As an example, prior to step S201, a pattern transfer is performed on the first circuit board to process the metal lines of the first circuit board. In step S201, the first solder mask layer 12 can be processed on the first circuit board by spraying or screen printing.

[0059] As an example, prior to step S202, a pattern transfer is performed on the second circuit board to process the metal lines of the second circuit board. In step S202, the second solder mask layer 13 can be processed on the second circuit board by spraying or screen printing.

[0060] It should be noted that the specific pattern transfer process in steps S201 and S202 can be a pattern transfer process known to those skilled in the art, and will not be described in detail here.

[0061] As an example, in step S203, the first circuit board and the second circuit board are laminated to obtain a multilayer circuit board 10, with the first solder mask layer 12 and the second solder mask layer 13 disposed opposite to each other. In this embodiment, an insulating dielectric layer 14 is placed between the first circuit board and the second circuit board, and the first circuit board and the second circuit board are laminated to obtain the multilayer circuit board 10. Preferably, the insulating dielectric layer 14 is a prepreg. In this example, the specific process of laminating the first circuit board and the second circuit board is not specifically limited, as long as the first solder mask layer 12 and the second solder mask layer 13 are disposed opposite to each other in the laminated multilayer circuit board 10.

[0062] In this embodiment, a first solder resist layer 12 is processed on a first circuit board, and a second solder resist layer 13 is processed on a second circuit board. By laminating the first circuit board and the second circuit board, a multilayer circuit board 10 including the first solder resist layer 12 and the second solder resist layer 13 disposed opposite to each other can be obtained.

[0063] In one embodiment, the first solder resist layer 12 includes a first solder resist structure and a second solder resist structure; the second solder resist layer 13 includes a third solder resist structure and a fourth solder resist structure; in step S201, processing the first solder resist layer 12 on the first circuit board includes: performing a first solder resist at a preset position on the first circuit board to form a first solder resist structure; and performing a second solder resist on the first solder resist structure to form a second solder resist structure.

[0064] The preset position is the position corresponding to the first through hole 11.

[0065] As an example, a first solder mask is applied to a predetermined location on the first circuit board using spraying or screen printing to form a first solder mask structure. It should be noted that the center of the first solder mask structure is aligned with the predetermined location, i.e., aligned with the center of the first through-hole 11. Similarly, a second solder mask is applied to the first solder mask structure using spraying or screen printing to form a second solder mask structure. It should be noted that the center of the second solder mask structure is also aligned with the predetermined location, i.e., aligned with the center of the first through-hole 11.

[0066] In this embodiment, a two-stage solder resist process is used: a first solder resist is performed at a preset position on the first circuit board to form a first solder resist structure, and a second solder resist is performed on the first solder resist structure to form a second solder resist structure. This allows the first solder resist layer 12 to form a first space 121 in step S102, resulting in a lower density of the metal material deposited in the first space 121, which is easier to remove. Simultaneously, it is completely removed in step S104, thereby achieving complete electrical isolation between the two adjacent circuit boards with the first solder resist layer 12 and the second solder resist layer 13.

[0067] In one embodiment, in step S202, processing a second solder resist layer 13 on the second circuit board includes: performing a first solder resist at a preset position on the second circuit board to form a third solder resist structure; and performing a second solder resist on the third solder resist structure to form a fourth solder resist structure.

[0068] As an example, a first solder mask is applied to a predetermined location on the second circuit board using spraying or screen printing to form a third solder mask structure. It should be noted that the center of the third solder mask structure is aligned with the predetermined location, i.e., aligned with the center of the first through-hole 11. Similarly, a second solder mask is applied to the third solder mask structure using spraying or screen printing to form a fourth solder mask structure. It should be noted that the center of the fourth solder mask structure is also aligned with the predetermined location, i.e., aligned with the center of the first through-hole 11.

[0069] In this embodiment, a second solder resist method is used: a first solder resist is performed at a preset position on the second circuit board to form a third solder resist structure, and a second solder resist is performed on the third solder resist structure to form a fourth solder resist structure. This allows the second solder resist layer 13 to form a second space 131 in step S102, resulting in a lower density of the metal material deposited in the second space 131, which is easier to remove. At the same time, it is completely removed in step S104, so that complete electrical isolation is achieved between the two adjacent circuit boards with the first solder resist layer 12 and the second solder resist layer 13.

[0070] In one embodiment, the solubility of the first solder mask structure and the second solder mask structure is different; the solubility of the third solder mask structure is the same as that of the first solder mask structure, and the solubility of the fourth solder mask structure is the same as that of the second solder mask structure. In this embodiment, ensuring that the solubility of the first solder mask structure and the second solder mask structure is different; the solubility of the third solder mask structure is the same as that of the first solder mask structure, and the solubility of the fourth solder mask structure is the same as that of the second solder mask structure can remove only the first solder mask structure and the third solder mask structure in the above step S102 to form the first space 121 and the second space 131. At the same time, in step S104, the second solder mask structure and the fourth solder mask structure are removed, that is, the first solder mask layer 12 and the second solder mask layer 13 are completely removed, and the first metal layer 20 with a lower density in the first space 121 and the second space 131 is removed, so as to achieve complete electrical isolation between the adjacent two circuit boards provided with the first solder mask layer 12 and the second solder mask layer 13.

[0071] In one embodiment, the diameter of the first solder mask structure is smaller than the diameter of the second solder mask structure; the diameter of the third solder mask structure is equal to the diameter of the first solder mask structure, and the diameter of the fourth solder mask structure is equal to the diameter of the second solder mask structure.

[0072] As an example, ensuring that the diameter of the first solder mask structure is smaller than the diameter of the second solder mask structure; the diameter of the third solder mask structure is equal to the diameter of the first solder mask structure, and the diameter of the fourth solder mask structure is equal to the diameter of the second solder mask structure. Since the solubility of the first solder mask structure and the second solder mask structure is different; the solubility of the third solder mask structure is the same as that of the first solder mask structure, and the solubility of the fourth solder mask structure is the same as that of the second solder mask structure, the first space 121 and the second space 131 with more appropriate sizes can be formed in the above step S102, which is convenient for removing the first metal layer 20 with a lower density in the first space 121 and the second space 131.

[0073] As an example, the diameters of the first solder mask structure and the second solder mask structure can be determined according to the diameter of the first through hole 11 between the adjacent two circuit boards, and it is only necessary to ensure that the diameter of the first solder mask structure is smaller than the diameter of the second solder mask structure. Exemplarily, let the diameter of the first solder mask structure be D1, the diameter of the second solder mask structure be D2, and the diameter of the first through hole 11 be d. D1 = d + K1, D2 = d + K2, where K1 and K2 can be determined according to actual experience, and it is only necessary to ensure that K1 < K2. Preferably, K1 is 150 microns and K2 is 250 microns.

[0074] Furthermore, the thickness of the first solder mask structure and the third solder mask structure is 30 - 50 microns, preferably 40 microns. The thickness of the second solder mask structure and the fourth solder mask structure is 50 - 70 microns, preferably 60 microns.

[0075] In one embodiment, the first solder mask layer 12 includes a first solder mask structure; the second solder mask layer 13 includes a third solder mask structure; performing a desmearing process on the multilayer circuit board 10 to form a first space 121 on the first solder mask layer 12 and a second space 131 on the second solder mask layer 13 includes: using a first solvent to perform a desmearing process on the multilayer circuit board 10 to remove the first solder mask structure, form the first space 121 on the first solder mask layer 12, remove the third solder mask structure, and form the second space 131 on the second solder mask layer 13. The first solder mask layer 12 also includes a second solder mask structure, and the second solder mask layer 13 also includes a fourth solder mask structure; removing the first solder mask layer 12 and the second solder mask layer 13, and electroplating a second metal layer 30 on the first metal layer 20 on the inner wall of the first through hole 11 to obtain a target circuit board including a target metallized hole includes: using a second solvent to remove the second solder mask structure and the fourth solder mask structure, and electroplating a second metal layer 30 on the first metal layer 20 on the inner wall of the first through hole 11 to obtain a target circuit board including a target metallized hole.

[0076] In this embodiment, a first solvent is first used to desmear the multilayer circuit board 10, removing the first solder mask structure, forming a first space 121 on the first solder mask layer 12, and removing the third solder mask structure. A second space 131 is formed on the second solder mask layer 13, so that when the first through hole 11 is subsequently metallized, the metal material deposited in the first space 121 and the second space 131 has a low density, making it easy to remove. Then, a second solvent is used to remove the second solder mask structure and the fourth solder mask structure, and a second metal layer 30 is electroplated on the first metal layer 20 on the inner wall of the first through hole 11, thus enabling the metallization of the first through hole 11. At the same time, by removing the second solder mask structure and the fourth solder mask structure of the first solder mask layer 12 and the second solder mask layer 13, the low-density first metal layer 20 deposited in the first solder mask layer 12 and the second solder mask layer 13 is completely removed, so that the two adjacent circuit boards with the first solder mask layer 12 and the second solder mask layer 13 are completely electrically isolated, resulting in a target circuit board with a target metallized hole including zero residual solder.

[0077] In one embodiment, the first solvent and the second solvent are alkaline solvents.

[0078] In this embodiment, since acidic solutions may corrode the metal circuits in the circuit board, the first and second solvents are alkaline solvents to ensure the reliability of the circuit board processing.

[0079] In one embodiment, the concentration of the first solvent is less than the concentration of the second solvent.

[0080] In this embodiment, the concentration of the first solvent is lower than that of the second solvent. Correspondingly, the first and third solder resist structures are inks that are easily removed by alkaline solvents. The second and fourth solder resist structures are inks that are resistant to weak alkalis but not to strong alkalis.

[0081] In one embodiment, the multilayer circuit board 10 further includes an insulating dielectric layer 14 disposed on two adjacent circuit boards, and a first through hole 11 penetrates the insulating dielectric layer 14; a second metal layer 30 is electroplated on the first metal layer 20 on the inner wall of the first through hole 11 to obtain a target circuit board including the target metallized hole, including etching the first metal layer 20 and the second metal layer 30 on the insulating dielectric layer 14 to obtain the target circuit board including the target metallized hole.

[0082] In this embodiment, the first metal layer 20 and the second metal layer 30 on the insulating dielectric layer 14 are etched to remove excess metal layers in the first through hole 11, thereby obtaining a target circuit board including the target metallized hole.

[0083] This embodiment provides a circuit board processing device for the circuit board processing method described above.

[0084] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A circuit board processing method, characterized in that, include: A first through-hole is fabricated on a multilayer circuit board, the multilayer circuit board including a first solder mask layer and a second solder mask layer respectively disposed on two adjacent circuit boards, the first solder mask layer and the second solder mask layer being disposed opposite to each other, the first through-hole penetrating the first solder mask layer and the second solder mask layer; the first solder mask layer includes a first solder mask structure and a second solder mask structure; the second solder mask layer includes a third solder mask structure and a fourth solder mask structure. The first solvent is used to remove the solder mask from the multilayer circuit board, thereby removing the first solder mask structure and forming a first space on the first solder mask layer. The third solder mask structure is also removed, and a second space is formed on the second solder mask layer. A first metal layer is deposited on the inner wall of the first through-hole, the first space, and the second space; Using a second solvent, the second solder resist structure and the fourth solder resist structure are removed, and a second metal layer is electroplated on the first metal layer on the inner wall of the first through hole to obtain a target circuit board including the target metallized hole.

2. The circuit board processing method as described in claim 1, characterized in that, Before processing the first through hole on the multilayer circuit board, the circuit board processing method further includes: A first solder mask layer is fabricated on the first circuit board; A second solder mask layer is fabricated on the second circuit board; The first circuit board and the second circuit board are laminated to obtain the multilayer circuit board, wherein the first solder mask layer and the second solder mask layer are disposed opposite to each other.

3. The circuit board processing method as described in claim 2, characterized in that, The first solder mask layer includes a first solder mask structure and a second solder mask structure; the second solder mask layer includes a third solder mask structure and a fourth solder mask structure. The process of fabricating the first solder mask layer on the first circuit board includes: A first solder resist is applied at a predetermined location on the first circuit board to form a first solder resist structure; a second solder resist is applied on the first solder resist structure to form a second solder resist structure. The process of fabricating a second solder mask layer on the second circuit board includes: A first solder resist is applied at a predetermined position on the second circuit board to form a third solder resist structure; a second solder resist is applied on the third solder resist structure to form a fourth solder resist structure.

4. The circuit board processing method as described in claim 3, characterized in that, The first solder resist structure and the second solder resist structure have different solubility; the third solder resist structure has the same solubility as the first solder resist structure; and the fourth solder resist structure has the same solubility as the second solder resist structure. The diameter of the first solder resist structure is smaller than the diameter of the second solder resist structure; The diameter of the third solder resist structure is equal to the diameter of the first solder resist structure, and the diameter of the fourth solder resist structure is equal to the diameter of the second solder resist structure.

5. The circuit board processing method as described in claim 1, characterized in that, Both the first solvent and the second solvent are alkaline solvents.

6. The circuit board processing method as described in claim 5, characterized in that, The concentration of the first solvent is less than the concentration of the second solvent.

7. The circuit board processing method as described in claim 1, characterized in that, The multilayer circuit board further includes an insulating dielectric layer disposed on two adjacent circuit boards, and the first through hole penetrates the insulating dielectric layer; The process of electroplating a second metal layer on the first metal layer on the inner wall of the first through hole to obtain a target circuit board including the target metallized hole includes: The first metal layer and the second metal layer on the insulating dielectric layer are etched to obtain a target circuit board including the target metallized hole.

8. A circuit board processing apparatus for implementing the circuit board processing method as described in any one of claims 1-7.

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