Ground-based optical telescope large-target-surface imaging circuit and imaging system

Abstract

The invention relates to the technical field of spliced detector imaging circuits, in particular to a large-target-surface imaging circuit and an imaging system for a foundation optical telescope, which are mainly used for solving the imaging design of a large target surface obtained by splicing a plurality of sCMOS imaging chips. The FPGA is used for functional module design, data flow design, high-dynamic synthesis and synchronous operation design, the FPGA comprises a control center and an sCMOS driving unit, the control center is used for controlling enabling and time sequence of functional modules of the FPGA according to configuration and state monitoring information of an upper computer, the sCMOS driving unit is used for generating and providing clock signals and control signals needed by working of an sCMOS chip, and the sCMOS chip is used for controlling the sCMOS chip to work according to the clock signals and the control signals. And receiving an image signal output by the sCMOS chip. The invention further provides an imaging system, the synchronous control terminal is designed to achieve synchronous control over the multiple imaging circuits, and image collection of the spliced target surface is completed. According to the imaging circuit and system, the large-view-field detection requirement of a large-scale optical telescope on the ground is met.

Description

Technical Field

[0001] The present invention belongs to the technical field of splicing detector imaging circuit design, and in particular relates to a large-target-surface imaging circuit and an imaging system for a ground-based optical telescope. Background Art

[0002] Ground-based large optical telescopes play an indispensable role in space situational awareness and space target detection. Their large aperture design significantly improves optical resolution and sensitivity, while their wide field of view enables them to efficiently monitor and observe a wider area of ​​the sky.

[0003] Internationally, many countries and research institutions have invested heavily in the construction and operation of advanced, large-aperture, wide-field telescopes. The Vera C. Rubin Observatory, located atop Cerro Pajón in Chile, formerly known as the Large Synoptic Survey Telescope (LSST), utilizes a three-reflecting optical system and an 8.4-meter-class primary mirror, enabling ultra-large field-of-view imaging of approximately 9.6 square degrees. Its core objective is to leverage its high sensitivity and large field-of-view to conduct high-frequency, multi-band observations of the entire southern sky. A key imaging device within the telescope system is a 320-megapixel, high-resolution CCD camera, which relies on a tiled detector to achieve ultra-large-area imaging. The camera's focal plane is composed of 21 tightly stitched "Raft" modules, each containing nine scientific CCDs. The total of 189 4k×4k resolution CCDs provides a detection area of ​​3.2 billion pixels. Eight guidance sensors and four wavefront sensors are also deployed on the periphery. Such a large CCD array requires complex drive, high-bandwidth data acquisition and transmission design to ensure that observations can be completed in a short time and massive high-quality data can be quickly output.

[0004] China has also made significant progress in the construction and research of large-aperture, wide-field telescopes. The 2.5-meter Wide Field Survey Telescope (WFST) at the University of Science and Technology of China (USTC)-Purple Mountain Observatory, also known as the "Micius" Survey Telescope, utilizes an internationally advanced prime focus optical design, providing a large field of view, high precision, and wide-band survey capabilities. Its advanced performance is evident in its large prime focus camera, a key component of the WFST's large-field, high-precision, and high-frequency time-domain observations. The WFST camera boasts a total pixel count of 765 million, with a pixel fill factor of 0.89 within a 3-degree field of view. The focal plane layout utilizes a mosaic of three types of CCDs. The scientific imaging area utilizes nine back-illuminated, full-frame, scientific-grade, 9k×9k resolution CCDs, arranged in a 3×3 pattern with a 0.5mm gap. The mosaic requires a peak-to-valley flatness of 20μm. Four back-illuminated, full-frame, 4k×4k resolution CCDs are installed around the scientific imaging area to guide active optical adjustment. It also integrates four 1k×1k resolution back-illuminated frame-transfer CCD guide sensors.

[0005] In terms of detector chips, scientific-grade complementary metal oxide semiconductors (sCMOS) have begun to be used in space target detection. sCMOS is a high-performance image sensor that significantly reduces readout noise while maintaining high speed, offering a wider dynamic range and superior quantum efficiency. In recent years, sCMOS has continued to develop in China, with the GSENSE series of back-illuminated sensors developed by Gpixel reaching internationally advanced levels. When sCMOS chips simultaneously output high- and low-gain images, they can be combined using High Dynamic Range (HDR) synthesis technology to achieve dynamic range expansion. This allows for the simultaneous presentation of details in extremely bright areas while preserving weak signals in dark areas within the same image. This technology offers significant advantages in space target observation. Summary of the Invention

[0006] In view of this, the present invention aims to provide a large-target imaging circuit and imaging system for a ground-based optical telescope, which effectively solves the problems that traditional imaging circuits are unable to effectively drive large-scale spliced ​​detectors, achieve high-dynamic synthesis, synchronous operation, and record exposure time information. In addition, the tests on camera readout noise suppression, dark current suppression, and image dynamic range are at the industry-leading level.

[0007] To achieve the above object, the technical solution created by the present invention is implemented as follows: The present invention provides a large-surface imaging circuit for a ground-based optical telescope, comprising: an sCMOS imaging chip for collecting light signals and converting the light signals into image signals; and an FPGA connected to the sCMOS imaging chip, the FPGA comprising: a control center and an sCMOS driver unit, wherein the control center is used to control the enabling and timing of functional modules in the FPGA based on the host computer configuration and status monitoring information; the sCMOS driver unit is used to generate and provide the clock signals and control signals required for the operation of the sCMOS chip, and receive the image signals output by the sCMOS chip; The control center controls the power supply of different power supplies in the sCMOS imaging chip to be powered on in batches. When at least one batch of power supplies is powered on and stable, the SPI configuration of the sCMOS imaging chip is performed. When all different power supplies are powered on and stable, the sCMOS imaging chip is driven to perform image acquisition and transmission according to the input signal from the host computer.

[0008] Preferably, the sCMOS imaging chip is a splicable back-illuminated sCMOS chip.

[0009] Preferably, during the process of driving the sCMOS imaging chip, 19 power supplies in the sCMOS imaging chip are controlled to be powered on in three batches.

[0010] Preferably, it also includes: a data management unit, which includes: 4 parallel DDR chips connected to the FPGA, and a FLASH chip, wherein the DDR chip is used to cache image signals to facilitate FPGA storage and reading of image signals; the FLASH chip is used to store the configuration parameters of the sCMOS imaging chip and the program code of the FPGA.

[0011] Preferably, the system further includes: a temperature monitoring module and a voltage monitoring module, which control the 19 power supplies in the sCMOS imaging chip to be powered on in batches. Before and after each batch is powered on, the temperature and voltage of the sCMOS imaging chip are monitored by the temperature monitoring module and the voltage monitoring module, and the feedback is sent to the FPGA. When the temperature and / or voltage exceeds the set range, the control center controls the different power supplies in the sCMOS imaging chip to be powered off in batches.

[0012] Preferably, the sCMOS driving unit includes: Clock module, used to provide clock signals for sCMOS imaging chip and FPGA; SPI control module, FPGA configures the working mode and parameters of the sCMOS imaging chip through the SPI control module; A DECODER control module, which is used to control the readout order of image signals of each pixel of the sCMOS imaging chip; The TIMING control module is used to generate the timing for the sCMOS imaging chip to collect optical signals.

[0013] Preferably, the working modes of the sCMOS imaging chip include: high-gain STD mode, low-gain STD mode and HDR imaging mode. In the HDR imaging mode, the sCMOS imaging chip synchronously outputs low-gain image signals and high-gain image signals, and the FPGA realizes high-dynamic synthesis through parallel processing based on the low-gain image signals and the high-gain image signals, generates a high-dynamic image, and sends the high-dynamic image to the host computer.

[0014] Preferably, the sCMOS imaging chip performs ADC acquisition on the image signal corresponding to the pixel at different magnifications, wherein the photon response curve of the low-gain image signal is: ; in, represents the pixel output value of the low-gain image signal, represents the slope of the linear region of the low-gain channel response curve, Indicates the black level offset of low-gain image signals, Represents the number of photons incident on the pixels of the sCMOS imaging chip; The photon response curve of the high-gain image signal is: ; in, represents the pixel output value of the high-gain image signal, Represents the slope of the linear region of the high-gain channel response curve, Indicates the black level offset of high-gain image signals; The photon response curve of high dynamic range image is: ; in, Represents the pixel output value of the high dynamic range image, Indicates the gain ratio of high dynamic range images, Indicates the compensation value of high dynamic image, Indicates the threshold for switching between high-gain image signals and low-gain image signals, Indicates the maximum value of the output data format.

[0015] Another aspect of the present invention provides a ground-based optical telescope large-target imaging system, comprising: a plurality of ground-based optical telescope large-target imaging circuits, a synchronization control terminal, and a host computer; wherein a plurality of sCMOS imaging chips are spliced ​​to form an imaging target surface, and the synchronization control terminal is connected to the FPGA in each ground-based optical telescope large-target imaging circuit and the synchronization control server of the host computer; The synchronization control terminal is used to receive control signals from the synchronization control server of the host computer, distribute and transmit the control signals to the FPGA in the large-target imaging circuit of each ground-based optical telescope, and generate synchronization trigger pulses and transmit them to the FPGA in the large-target imaging circuit of each ground-based optical telescope, so that all FPGAs synchronously drive their corresponding sCMOS imaging chips, and generate high-dynamic images from the image signals collected by the sCMOS imaging chips and send them to the host computer.

[0016] Preferably, the imaging target surface adopts a rolling shutter exposure mode for line-by-line exposure and line-by-line light signal reading, and half of the exposure time of the middle row of the target surface plus the exposure start time of the middle row is recorded as the exposure time of each frame of image signal.

[0017] Compared with the prior art, the present invention can achieve the following beneficial effects: The present invention provides an imaging circuit and system that can be applied to large-scale, spliced ​​detectors in ground-based, large-scale survey telescopes. The imaging circuit uses an FPGA chip as its core processor and integrates functional modules such as sCMOS drive functions, a control center, a data center, a status monitoring module, and an external communication interface. This achieves efficient utilization of hardware resources and highly integrated functions, improving the reliability and stability of the system. In addition, to adapt to large-scale, spliced ​​detectors, the present invention designs a synchronous control terminal and synchronous operation logic, achieving synchronous control and synchronous output of multiple imaging circuits within the spliced ​​detector, ensuring that all detectors perform exposure and data acquisition within the same time window, effectively avoiding data inconsistencies caused by timing deviations, and improving the validity and accuracy of observation data.

[0018] Based on traditional imaging circuits, this invention utilizes the ability of sCMOS imaging chips to output both low-gain and high-gain image signals to design an on-board high-dynamic range (HDR) image synthesis function. This function controls the simultaneous output of low-gain and high-gain images from the sCMOS imaging chip and fuses them through HDR synthesis technology, increasing the maximum dynamic range from 71.5dB to 92.4dB. This effectively addresses the issues of overexposure of bright areas and loss of detail in dark areas in traditional cameras in high-contrast scenes. It achieves the goal of presenting details in extremely bright areas while preserving weak signals in dark areas in the same image, improving image quality and broadening the camera's application range. This makes it easier to use in astronomical observation scenarios with high dynamic range requirements for large ground-based survey telescopes. Furthermore, during the HDR synthesis process, the advantages of FPGA parallel processing are fully utilized to implement HDR image synthesis on-board. Compared to the traditional method of sending high-gain and low-gain images to a host computer for subsequent synthesis processing, this invention significantly improves the efficiency of HDR image synthesis, reducing the image calculation delay to only 16ns, which is much faster than the method of sending images to a host computer for calculation.

[0019] The present invention designs an optical communication data interface to replace the traditional camera CameraLink interface, simplifying the long-distance image transmission link; and designs a function for recording image exposure time information inside the camera with a time resolution of 1μs, which solves the disadvantage of traditional optical telescope imaging systems requiring the installation of event latches, improves time accuracy and simplifies the complexity of the telescope system.

[0020] The imaging circuit of the present invention is applied to a large-surface camera of a ground-based large optical telescope. After testing, it is calculated that the camera readout noise is , dark current , and the dynamic range is 92.4dB, both of which are at the industry-leading level. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which constitute part of the present invention, are intended to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are intended to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings: Figure 1 This is a circuit diagram of a large target imaging circuit of a ground-based optical telescope provided according to an embodiment of the present invention; Figure 2 This is a functional module structure design diagram of an FPGA provided according to an embodiment of the present invention; Figure 3 This is an operation logic diagram of a control center provided according to an embodiment of the present invention; Figure 4 Schematic diagram of data caching and reading according to an embodiment of the present invention; Figure 5 is a schematic diagram of synchronous control of an imaging system provided by an embodiment of the present invention; Figure 6 is a timing diagram of control and status information of an imaging system provided according to an embodiment of the present invention; Figure 7 is a timing diagram of exposure moment information provided according to an embodiment of the present invention; Figure 8 These are the low-gain and high-gain images displayed on the host computer image acquisition interface during testing; Figure 9 It is a low-gain image acquired during testing; Figure 10 It is a high-gain image acquired during the test Figure 11 It is a high-dynamic image acquired during the test; Figure 12 It is a local comparison diagram of the low-gain image and the high-dynamic image acquired during the test; Figure 13 It is a local comparison diagram of the acquired high-gain image and high-dynamic image. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and do not constitute a limitation to the present invention. Similar elements in different embodiments use associated similar element numbers. In the following embodiments, many detailed descriptions are intended to enable the present invention to be better understood. However, those skilled in the art can easily recognize that some of the features can be omitted in different situations, or can be replaced by other elements, materials, or methods. In some cases, some operations related to the present invention are not shown or described in the specification. This is to avoid the core part of the present invention being overwhelmed by too much description. For those skilled in the art, it is not necessary to describe these related operations in detail. They can fully understand the related operations based on the description in the specification and the general technical knowledge in the art.

[0023] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present invention can be combined with each other to form various implementation methods. At the same time, the steps or actions in the method description can also be interchanged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various orders in the description and the drawings are only for the purpose of clearly describing a certain embodiment and are not intended to be a required order, unless otherwise specified that a certain order must be followed.

[0024] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0025] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art can understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0026] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0027] In one embodiment of the present invention, a large-target imaging circuit for a ground-based optical telescope is provided, which is applied to large-field-of-view detection scenarios of ground-based large optical telescopes. In order to achieve large-field-of-view detection, the imaging circuit of the present invention adopts a splicable back-illuminated sCMOS imaging chip. The sCMOS imaging chip adopts a splicing package design and minimizes the size of the package frame as much as possible, so that the sCMOS imaging chip can be applied to a large-target splicing detector. By splicing multiple sCMOS imaging chips, the target surface of a ground-based optical telescope can be obtained to meet the requirements of large-field-of-view detection. For the imaging design of a single sCMOS imaging chip in a spliced ​​detector, please refer to Figure 1 The embodiment of the present invention provides a large-surface imaging circuit for a ground-based optical telescope, including an imaging chip portion and a processing circuit portion. The imaging chip portion uses an sCMOS imaging chip, which collects optical signals and converts the collected optical signals into electrical signals, completing the photoelectric conversion process to achieve digital imaging of the target or scene. The electrical signal is the image signal processed by the subsequent circuit. Since the imaging circuit of the present invention needs to be applied to ground-based optical telescopes, it has high requirements for the sCMOS imaging chip, so a custom design is adopted. The resolution of the sCMOS imaging chip is 16.8 million pixels, the peak quantum efficiency is 92%, and the minimum read noise is The sCMOS imaging chip uses 10 pairs of LVDS (low-voltage differential signaling) to transmit data. Each LVDS pair operates at 420Mbps and supports 12-bit dual-gain imaging mode and 14-bit single-gain imaging mode, supporting imaging at a maximum speed of 4fps at full resolution.

[0028] The processing circuitry utilizes an FPGA, which connects to the sCMOS imaging chip and transmits information via a high-speed connection. Furthermore, because the FPGA's data storage capacity is limited, and the sCMOS imaging chip's single-frame data volume is approximately 386Mb, far exceeding the FPGA's internal storage resources, the imaging circuit in this embodiment of the present invention also includes a data management unit. This unit comprises a DDR chip and a FLASH chip connected in parallel to the FPGA. The DDR chips are four, specifically DDR3 memory chips with a 256M×16 specification, a data read / write rate of 102.4Gbps, and 16Gb of storage space. The DDR chips are used to buffer image signals transmitted from the sCMOS imaging chip to the FPGA, facilitating storage and reading of image signals by the FPGA. The DDR chips effectively increase the bandwidth for data storage and transmission to handle large amounts of image data. The FLASH chips are also four, specifically QSPI FLASH memory chips, with a total storage space of 2Gb. The FLASH chips primarily store circuit control data, such as the sCMOS imaging chip's configuration parameters and the FPGA's program code, enabling the refreshing of control data.

[0029] Since the image signal transmitted from the sCMOS imaging chip to the FPGA for processing needs to be further transmitted to the host computer for subsequent processing, the imaging circuit implemented by the present invention also includes an external interface unit. Unlike the traditional cameralink interface, the external interface unit of the imaging circuit of the embodiment of the present invention includes an optical module and a serial bus transceiver, wherein the optical module is mainly used to transmit the sCMOS imaging chip to the FPGA, and the image signal processed by the FPGA is transmitted to the host computer in the form of optical communication, which is convenient for subsequent processing of the image data. In addition, when the image acquisition process is controlled by the host computer, the control instructions can also be transmitted to the FPGA through the optical module. The serial bus transceiver uses the RS422 serial data bus mainly for receiving and sending the configuration and status information of the sCMOS imaging chip.

[0030] As a preferred embodiment, since the sCMOS imaging chip requires 19 power supplies, and power-on and power-off operations must be performed sequentially and at intervals to ensure safe chip operation, it is also necessary to monitor the temperature and voltage data of the sCMOS imaging chip in real time to prevent the sCMOS imaging chip from burning out due to overheating or overvoltage. The imaging circuit of this embodiment of the present invention also includes a temperature monitoring module and a voltage monitoring module. The temperature monitoring module is connected to the sCMOS imaging chip and monitors the temperature data of the sCMOS imaging chip in real time through the temperature monitoring module and feeds the temperature data back to the FPGA, where it is compared with a set overtemperature threshold. The voltage monitoring module monitors the voltage data of the sCMOS imaging chip in real time and feeds the voltage data back to the FPGA, where it is compared with a set overvoltage threshold. When the FPGA receives temperature and / or voltage data from the sCMOS imaging chip that exceeds the normal range, it promptly controls the sCMOS imaging chip to gradually power off in batches. Accordingly, since the FPGA may also experience overheating, a temperature monitoring module is also provided to monitor the FPGA in real time to prevent overheating and burning out.

[0031] See also Figure 2, FPGA is the core module of the imaging circuit. The embodiment of the present invention also performs modular design on the FPGA, reasonably encapsulates and separates the inside of the FPGA, and modularizes the FPGA according to functional modules. The specific FPGA includes: a control center, an sCMOS drive unit, and a data center, among which the control center is the top-level control module in the imaging circuit, which needs to control the enable and timing of other functional modules according to the upper computer configuration and status monitoring information. The enable refers to the drive signal sent by the control center to each functional module in the FPGA, and the functional module performs the corresponding action according to the enable signal sent by the control center. In the embodiment of the present invention, the enable signals mainly sent by the control center include: the control signal of the sCMOS drive unit, the control signal of the data management unit, the control signal of the temperature monitoring module and the voltage monitoring module, and the control signal of the external interface unit. The external interface unit, designed to facilitate information transmission with the optical module and serial bus transceiver, primarily consists of a camera status transmitter module and a control command receiver module within the FPGA. The camera status transmitter module transmits the sCMOS imaging chip's configuration and hyperparameter information acquired by the FPGA to a host computer for confirmation. The control command receiver module transmits control information from the host computer to the FPGA, thereby controlling the sCMOS imaging chip. The camera status transmitter module includes a camera status transmitter module (light) that outputs to the optical module and a camera status transmitter module (serial) that outputs to the serial bus transceiver. The control command receiver module includes a control command receiver module (light) that inputs the FPGA from the optical module and a control command receiver module (serial) that inputs the FPGA from the serial bus transceiver.

[0032] The sCMOS driver unit includes a clock module, an SPI control module, a DECODER control module, and a TIMING control module. The clock module provides clock signals for the sCMOS imaging chip and FPGA. It uses a low-voltage differential signal to provide the sCMOS imaging chip with a 420MHz SDR clock CLK-IN. This signal serves as the reference clock for the sCMOS imaging chip's internal data stream, ensuring that the sCMOS imaging chip and FPGA share the same reference clock. Furthermore, when the sCMOS imaging chip sends the image signal to the FPGA, it also synchronously sends the DDR clock CLK-OUT.

[0033] The SPI control module transmits various control commands from the control center and configures the operating mode and parameters of the sCMOS imaging chip via the SPI protocol. The sCMOS imaging chip's operating modes include, but are not limited to, high-gain STD mode, low-gain STD mode, and HDR imaging mode. Operating parameters include integration time, window size, and frame rate.

[0034] The DECODER and TIMING control modules are used to transmit signal instructions from the control center to the sCMOS imaging chip in the corresponding format, controlling the internal operating timing of the sCMOS imaging chip. The DECODER control module controls the readout order of image signals from each pixel of the sCMOS imaging chip, while the TIMING control module generates the timing for the sCMOS imaging chip to acquire optical signals.

[0035] The data center is primarily used for data transmission and exchange. Its primary functions are to receive image signals from the sCMOS imaging chip, transmit them to a host computer, and cache the image signals, configuration parameters, and FPGA program code in DDR and FLASH, or read data from DDR and FLASH. Since the sCMOS imaging chip transmits image signals via an LVDS link, an LVDS receiver module is installed at the front end of the data center to receive image data. The LVDS receiver module is primarily used to adapt to the LVDS data transmission link of the sCMOS imaging chip. The sCMOS imaging chip transmits the captured image signals via the LVDS data transmission link to the FPGA. The LVDS receiver module performs serial-to-parallel conversion and multi-channel data alignment on the image signals before transmitting them to the data center. Since the data center needs to transmit the image signals to an optical module, which then transmits them to the host computer, an optical communication transmission arbitration module is installed at the back end of the data center to transmit the image signals to the optical module.

[0036] See also Figure 3The present invention specifically designs the power-on and power-off drivers for the sCMOS imaging chip. Specifically, the sCMOS imaging chip's power supply circuit includes 19 power supplies. During the power-on process, these 19 power supplies are provided to the sCMOS imaging chip in three batches. After the telescope system is powered on, it first obtains temperature and voltage data collected by the temperature monitoring module and the voltage monitoring module. The FPGA compares these temperature and voltage data with set thresholds to determine if the voltage and temperature of the sCMOS imaging chip are normal. The first batch of power supply, supply1, is then controlled to power on. After the first batch of power supply, supply1, stabilizes after powering on, it then obtains temperature and voltage data collected by the temperature monitoring module and the voltage monitoring module. The FPGA compares these temperature and voltage data with set thresholds to determine if the voltage and temperature of the sCMOS imaging chip are normal. The SPI control module configures the sCMOS imaging chip according to the configuration operations issued by the control center, setting the operating mode and parameters of the sCMOS imaging chip. After the sCMOS imaging chip is configured, the FPGA reads back the configuration information of the sCMOS imaging chip. After confirming that the configuration is correct, it performs voltage and temperature detection again. After confirming that the voltage and temperature are normal, the second batch of power supply, supply2, is powered on. After the second batch of power supply, supply2, is powered on and stabilized, the voltage and temperature confirmation is repeated. After confirmation, the third batch of power supply, supply3, is powered on and stabilized. After confirmation, the voltage and temperature confirmation is repeated. After confirmation, the TRAIN function is enabled to sequentially perform bit alignment, word alignment, and channel alignment. After completion, the system enters the idle state to prepare for imaging, that is, to initialize and calibrate the sCMOS imaging chip. In the idle state, the sCMOS imaging chip can be driven and image acquisition and transmission can be performed according to the parameters configured by the host computer, such as the operating mode, exposure time, and frame rate.

[0037] During the power-up process, if any voltage or temperature errors occur during any of the voltage and temperature verification steps, the sCMOS imaging chips are powered down in batches. If image acquisition is terminated by the host computer (i.e., if a camera shutdown command is received), the power-down process is also repeated in three batches: the third power supply (supply3), the second power supply (supply2), and the first power supply (supply1).

[0038] After the sCMOS imaging chip is powered on, it captures images and sends the image signal and feedback clock signal via an LVDS link to the FPGA (referred to as the LVDS signal). Upon receiving the LVDS signal, the FPGA needs to convert it into a low-rate, high-bitwidth signal. This data conversion is typically accomplished using an ISERDES module. Simultaneously, based on the received clock data, closed-loop control delay settings are used to align multi-channel data. This delay setting is typically achieved through an IDELAY module designed into the data center front end. In actual testing, the LVDS signal input from the sCMOS imaging chip is shown in Table 1 below. Signal jitter at the receiver is consistently less than 509 ps, effectively ensuring the stability of received data.

[0039] Table 1 LVDS signal reception test results

[0040] Since the single-frame data volume of the sCMOS imaging chip is about 386Mb, which far exceeds the internal storage resources of the FPGA, the image signal input by the sCMOS imaging chip needs to be written into the DDR chip. The data read and write rate of the DDR chip is 102.4Gbps, and it uses the AXI-Full bus protocol for data writing and reading. The AXI-Full bus protocol is a high-performance, high-bandwidth, low-latency on-chip bus protocol suitable for high-performance memory mapping requirements. The data cache process is as follows: Figure 4 As shown, the data center uses an AXI bus interface, connecting to the MIG core and DDR chip in sequence via the master interface M00_AXI on the data center. Using a dual FIFO ping-pong buffer, the image signal and sCMOS imaging chip configuration data are stored in the DDR via the slave interfaces S00_AXI and S01_AXI, respectively. The image signal and sCMOS imaging chip configuration data are then read by the slave interfaces S02_AXI and S03_AXI, passed through the dual FIFO ping-pong buffer, and finally sent to the image processing server (the host computer) after calculation.

[0041] As a preferred embodiment, the operating modes of the sCMOS imaging chip are specially designed to include a high-gain STD mode, a low-gain STD mode, and an HDR imaging mode. The principle of the HDR imaging mode is to utilize the parallel processing characteristics of the FPGA to control the sCMOS imaging chip to synchronously output low-gain images and high-gain images, that is, to perform two ADC acquisitions of different amplification factors on the pixel point electrical signal. The low-gain and high-gain are then synthesized by the FPGA to generate a high dynamic range image, realizing the HDR imaging mode. Specifically, the photon response curve of the low-gain image signal is: ; in, represents the pixel output value of the low-gain image signal, represents the slope of the linear region of the low-gain channel response curve, Indicates the black level offset of low-gain image signals, Indicates the number of photons incident on the pixels of the sCMOS imaging chip.

[0042] The photon response curve of the high-gain image signal is: ; in, represents the pixel output value of the high-gain image signal, Represents the slope of the linear region of the high-gain channel response curve, Indicates the black level offset of high-gain image signals.

[0043] The low-gain image signal and the high-gain image signal are fused in parallel to obtain the photon response curve of the high-dynamic image: ; in, Represents the pixel output value of the high dynamic range image, Indicates the gain ratio of high dynamic image, Indicates the compensation value of high dynamic image, Indicates the threshold for switching between high-gain image signals and low-gain image signals, Indicates the maximum value of the output data format. By derivation, we can get: ; .

[0044] Because the present invention integrates high-dynamic-range synthesis functionality into the image data stream through high-speed parallel processing using FPGAs, on-chip synthesis is achieved using the FPGA, overcoming the traditional need for image synthesis on a host computer. On-chip synthesis effectively improves the efficiency of high-dynamic-range image synthesis and reduces image calculation latency. Tests have shown that the computational latency of on-chip synthesis is only 16ns, far lower than the latency of traditional synthesis performed on a host computer.

[0045] Based on the aforementioned imaging circuits, an embodiment of the present invention further proposes a large-target imaging system for a ground-based optical telescope. This system specifically serves as an imaging camera for a ground-based optical telescope. Due to the high field-of-view detection requirements, the imaging system includes multiple large-target imaging circuits for ground-based optical telescopes, and multiple sCMOS imaging chips within these circuits are spliced ​​together to form an imaging target surface. In this embodiment of the present invention, 16 imaging circuits are included, and the imaging target surface is formed by splicing 16 sCMOS imaging chips. To achieve synchronous operation of multiple imaging circuits, the system also includes a synchronization control terminal and a host computer for inputting control instructions and outputting images.

[0046] like Figure 5 As shown in the figure, the connection method between the synchronous control terminal and the synchronous control server of the host computer is the same as the connection method between the imaging circuit and the host computer. Both use a set of optical fiber communication, which simplifies the camera's external interface. The synchronous control terminal communicates with each imaging circuit using a serial communication bus. For the synchronous control process of the synchronous control terminal on the imaging circuit, please refer to Figure 6 After receiving control instructions, clock signals, and other pulse signals for the imaging target surface, the synchronous control terminal distributes them to the imaging circuits and simultaneously generates synchronous trigger pulses to control the synchronous operation of all imaging circuits. In addition, during the information feedback process, the synchronous control terminal also synchronously receives feedback signals from each imaging circuit and sends the combined signals to the host computer.

[0047] During the imaging process, the image slices need to accurately match the time and posture of the exposure moment. Therefore, it is necessary to accurately record the time information of each exposure to ensure the time accuracy of the observation data. At the same time, by recording the camera exposure moment information, the synchronization of multiple devices can be confirmed, effectively avoiding the data inconsistency problem caused by timing deviation. Therefore, the embodiment of the present invention is also designed as follows Figure 7 The method for recording exposure time information shown in this paper sets the clock signal resolution to 1µs within the circuit. Furthermore, the imaging target surface uses a rolling shutter exposure method for line-by-line exposure and light signal reading. The exposure time for each image frame is recorded as half the exposure time of the middle row on the target surface plus the exposure start time of the middle row. This exposure data and image data are combined and sent to a host image processing server, enabling synchronized exposure and imaging of a large, spliced ​​target surface.

[0048] In order to verify the effectiveness of the imaging circuit and system of the present invention, the imaging system is powered on and connected to the host computer via optical fiber. The host computer collects and obtains the following Figure 8 The low-gain and high-gain images shown are shown. After parameter control testing, a 4fps imaging rate was achieved with a 16.8MP full-frame resolution, 16-bit image depth, and simultaneous high and low-gain output.

[0049] Further imaging tests were conducted on a test platform consisting of an integrating sphere light source and a darkroom. The integrating sphere used a customized 15 cm opening high brightness uniform light source system USS-2000C, with a light brightness uniformity of ≥98%. After testing on the test platform, the camera readout noise was calculated to be , dark current By adjusting the light source and exposure time, the grayscale of the high-gain and low-gain images were adjusted to about 1 / 2 of the maximum grayscale value, and better imaging effects were obtained.

[0050] Further verification of the high dynamic synthesis function, under different working modes, the following Figure 9 The low-gain image shown, such as Figure 10 The high gain image shown, and Figure 11 As shown in the high dynamic range image. Figure 12 As shown in the figure, a partial comparison of the low-gain image and the high-dynamic image is made. Compared with the low-gain image, the high-dynamic synthetic image has increased the image details at low light levels. After calculation, the dynamic range of the high-dynamic synthetic image is improved by 20.9dB compared with the low-gain image. Figure 13 As shown in the figure, a partial comparison of the high-gain image and the high-dynamic image shows that the high-dynamic synthetic image has increased image details at high light levels compared to the high-gain image. Calculations show that the dynamic range of the high-dynamic synthetic image is 25.1dB higher than that of the high-gain image.

[0051] In summary, the imaging circuit and system of the embodiment of the present invention achieves 16.8 million resolution full-frame 4fps imaging, and the camera readout noise is , dark current , with a dynamic range of 92.4dB, which not only meets the large-target imaging detection needs of ground-based optical telescopes, but also all indicators are at the industry-leading level.

[0052] In short, the above description is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification shall be included in the scope of protection of this specification.

[0053] The systems, devices, modules, or units described in one or more of the above embodiments may be implemented by a computer chip or entity, or by a product having a certain function. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0054] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0055] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the description of the method embodiments.

Claims

1. A large-target imaging circuit for a ground-based optical telescope, characterized in that: include: sCMOS imaging chip, which is used to collect light signals and convert them into image signals; and an FPGA connected to the sCMOS imaging chip, the FPGA comprising: a control center and an sCMOS driver unit, wherein the control center is used to control the enabling and timing of functional modules in the FPGA based on host computer configuration and status monitoring information; the sCMOS driver unit is used to generate and provide clock signals and control signals required for the operation of the sCMOS chip, and receive image signals output by the sCMOS chip; The control center controls different power supplies in the sCMOS imaging chip to be powered on in batches. When at least one batch of power supplies is powered on and stable, the sCMOS imaging chip is configured with SPI. When all different power supplies are powered on and stable, the sCMOS imaging chip is driven to perform image acquisition and transmission according to input signals from a host computer.

2. The large-target-area imaging circuit for a ground-based optical telescope according to claim 1, characterized in that: The sCMOS imaging chip is a splicable back-illuminated sCMOS chip.

3. The large-target-area imaging circuit for a ground-based optical telescope according to claim 1, characterized in that: During the process of driving the sCMOS imaging chip, 19 power supplies in the sCMOS imaging chip are controlled to be powered on in three batches.

4. The large-target-area imaging circuit for a ground-based optical telescope according to claim 1, characterized in that: Also includes: A data management unit includes: four parallel DDR chips connected to the FPGA, and a FLASH chip, wherein the DDR chip is used to cache image signals to facilitate the FPGA to store and read image signals; the FLASH chip is used to store the configuration parameters of the sCMOS imaging chip and the program code of the FPGA.

5. The large-target-area imaging circuit for a ground-based optical telescope according to claim 3, characterized in that: Also includes: The temperature monitoring module and the voltage monitoring module control the batch power-up of the 19 power supplies in the sCMOS imaging chip. Before and after each batch of power-up, the temperature and voltage of the sCMOS imaging chip are monitored by the temperature monitoring module and the voltage monitoring module, and the feedback is fed back to the FPGA. When the temperature and / or voltage exceed the set range, the control center controls the different power supplies in the sCMOS imaging chip to be powered off in batches.

6. The large-target-area imaging circuit for a ground-based optical telescope according to claim 1, characterized in that: The sCMOS driving unit includes: A clock module, configured to provide a clock signal for the sCMOS imaging chip and the FPGA; An SPI control module, wherein the FPGA configures the operating mode and parameters of the sCMOS imaging chip through the SPI control module; A DECODER control module, which is used to control the readout order of the image signal of each pixel of the sCMOS imaging chip; The TIMING control module is used to generate the timing for the sCMOS imaging chip to collect light signals.

7. The large-target-area imaging circuit for a ground-based optical telescope according to claim 6, characterized in that: The operating modes of the sCMOS imaging chip include: high-gain STD mode, low-gain STD mode and HDR imaging mode. In the HDR imaging mode, the sCMOS imaging chip synchronously outputs low-gain image signals and high-gain image signals. The FPGA realizes high-dynamic synthesis through parallel processing based on the low-gain image signals and the high-gain image signals, generates a high-dynamic image, and sends the high-dynamic image to the host computer.

8. The large-target-area imaging circuit for a ground-based optical telescope according to claim 1, characterized in that: The sCMOS imaging chip performs ADC acquisition on the image signals corresponding to the pixels at different magnifications, wherein the photon response curve of the low-gain image signal is: ； in, represents the pixel output value of the low-gain image signal, represents the slope of the linear region of the low-gain channel response curve, Indicates the black level offset of low-gain image signals, represents the number of photons incident on the pixel of the sCMOS imaging chip; The photon response curve of the high-gain image signal is: ； in, represents the pixel output value of the high-gain image signal, Represents the slope of the linear region of the high-gain channel response curve, Indicates the black level offset of high-gain image signals; The photon response curve of high dynamic range image is: ； in, Represents the pixel output value of the high dynamic range image, Indicates the gain ratio of high dynamic image, Indicates the compensation value of high dynamic image, Indicates the threshold for switching between high-gain image signals and low-gain image signals, Indicates the maximum value of the output data format.

9. A ground-based optical telescope large-surface imaging system, characterized in that: The device comprises a plurality of large-target-surface imaging circuits for ground-based optical telescopes according to any one of claims 1 to 8, a synchronous control terminal, and a host computer; Wherein, a plurality of sCMOS imaging chips are spliced ​​to form an imaging target surface, and the synchronization control terminal is connected to the FPGA in each of the large target surface imaging circuits of the ground-based optical telescope and the synchronization control server of the host computer; The synchronization control terminal is used to receive the control signal of the synchronization control server of the host computer, distribute and transmit the control signal to the FPGA in each large-target imaging circuit of the ground-based optical telescope, and generate a synchronization trigger pulse and transmit it to the FPGA in each large-target imaging circuit of the ground-based optical telescope, so that all FPGAs synchronously drive their corresponding sCMOS imaging chips, and generate high-dynamic images from the image signals collected by the sCMOS imaging chips and send them to the host computer.

10. The ground-based optical telescope large-surface imaging system according to claim 9, characterized in that: The imaging target surface adopts rolling shutter exposure mode to perform line-by-line exposure and line-by-line light signal reading, and half of the exposure time of the middle row of the target surface plus the exposure start time of the middle row is recorded as the exposure time of each frame of image signal.

Images