Circuit board and manufacturing method thereof

Abstract

The invention relates to the technical field of printed circuit boards, and discloses a circuit board and a manufacturing method thereof, and the circuit board comprises an embedded layer, a buffer layer and a pressing layer. A heat dissipation base is arranged in the embedded layer, and a power device is arranged on the side, facing the pressing layer, of the heat dissipation base. The buffer layer is provided with an accommodating groove, the orthographic projection of the buffer layer on the surface, deviating from the buffer layer, of the laminated circuit layer and the orthographic projection of the heat dissipation seat on the surface, deviating from the buffer layer, of the laminated circuit layer have an overlapped part, and the power device is lower than the surface, deviating from the embedded layer, of the buffer layer or flush with the surface, deviating from the embedded layer, of the buffer layer; the press-fit layer comprises a press-fit circuit layer and a press-fit connecting layer, part of the press-fit connecting layer is located between the press-fit circuit layer and the buffer layer, the press-fit connecting layer is provided with a first hole, and a first conductive part is arranged in the first hole. The circuit board and the manufacturing method thereof provided by the invention are used for solving the problem that the power device is easy to damage in the process of laminating the embedded layer and the laminating layer together in the related technology.

Description

Technical Field

[0001] The present application relates to the technical field of printed circuit boards, and in particular to a circuit board and a method for manufacturing the same. Background Art

[0002] With the continuous development of the electronic communications industry and automotive electronic technology, they tend to be miniaturized and multifunctional. Therefore, the requirements for related circuit board products are becoming higher and higher. Not only do they need to meet the requirements of use in high-current working environments, have ultra-high voltage resistance and excellent CAF (Conductive Anodic Filament) resistance, but they also need to achieve high-density interconnection and have excellent heat dissipation performance. Therefore, printed circuit boards with embedded power devices (such as power chips) were born.

[0003] In the related art, it is generally necessary to first fix the power device on the heat sink, fix the power device on the surface of the heat sink, and then embed the two as a whole into the embedding layer of the circuit board, and then press the embedding layer and the pressing layer together. During the pressing process, the power device is easily damaged, causing the circuit board to be scrapped. Summary of the Invention

[0004] The present application provides a circuit board and a manufacturing method thereof, which are used to solve the problem in the related art that power devices are easily damaged during the process of pressing the embedded layer and the pressing layer together.

[0005] In a first aspect, an embodiment of the present application provides a circuit board, comprising a stacked embedded layer, a buffer layer, and a lamination layer, wherein the buffer layer is located between the embedded layer and the lamination layer; A heat sink is provided inside the embedded layer, and a power device is provided on the side of the heat sink facing the pressing layer; The buffer layer is provided with a receiving groove, the receiving groove passes through the buffer layer, the power device is located in the receiving groove, the orthographic projection of the buffer layer on the side of the pressed circuit layer facing away from the buffer layer and the orthographic projection of the heat sink on the side of the pressed circuit layer facing away from the buffer layer have an overlapping portion, and the power device is lower than or flush with the surface of the buffer layer facing away from the embedded layer; The pressed layer includes a pressed circuit layer and a pressed connection layer, part of the pressed connection layer is located between the pressed circuit layer and the buffer layer, part of the pressed connection layer fills the gap between the side wall of the accommodating groove and the power device, the pressed connection layer is provided with a first hole, a first conductive part is provided inside the first hole, and part of the pressed circuit layer is connected to the power device through the first conductive part and is electrically conductive.

[0006] In some embodiments, the buffer layer includes a buffer core plate and a buffer connection layer, the accommodating groove passes through the buffer core plate and the buffer connection layer, part of the buffer connection layer is located between the buffer core plate and the embedded layer, and part of the buffer connection layer fills the gap between the side wall of the accommodating groove and the power device.

[0007] In some embodiments, the orthographic projection of the buffer connection layer on the side of the pressed circuit layer facing away from the pressed connection layer and the orthographic projection of the heat sink on the side of the pressed circuit layer facing away from the pressed connection layer have an overlapping portion; and / or, the orthographic projection of the buffer core board on the side of the pressed circuit layer facing away from the pressed connection layer and the orthographic projection of the heat sink on the side of the pressed circuit layer facing away from the pressed connection layer have an overlapping portion.

[0008] In some embodiments, the buffer layer includes an inner circuit layer, the inner circuit layer is provided with an avoidance space, so that the inner circuit layer and the power device are spaced apart, and the accommodating groove passes through the avoidance space.

[0009] In some embodiments, the surface of the embedded layer facing the pressing layer is higher than the surface of the heat sink facing the pressing layer, and the thickness of the buffer layer is greater than or equal to the height of the power device; Alternatively, a surface of the embedded layer facing the pressing layer is flush with a surface of the heat sink facing the pressing layer, and a thickness of the buffer layer is greater than or equal to a height of the power device.

[0010] In some embodiments, the buffer layer is provided with a connection hole, a connection part is provided in the connection hole, the pressed connection layer is provided with a second hole, a second conductive part is provided inside the second hole, and part of the pressed circuit layer is connected to the heat sink in turn through the second conductive part and the connection part and is electrically conductive.

[0011] In some embodiments, the buffer layer includes an inner circuit layer, the inner circuit layer is provided with a avoidance groove, the connection hole passes through the bottom wall of the avoidance groove, and the connection part and the second conductive part are both spaced apart from the side wall of the avoidance groove.

[0012] In some embodiments, the pressed connection layer includes glass fiber cloth, the glass fiber cloth includes glass fiber filaments, and the diameter of the glass fiber filaments is less than or equal to 4 μm.

[0013] In some embodiments, the distance between the sidewall of the receiving groove and the power device is 0.15 mm-0.25 mm.

[0014] In some embodiments, the power device and the receiving groove are both provided in plurality, and the power device and the receiving groove are provided in a one-to-one correspondence.

[0015] In some embodiments, the plurality of power devices are distributed in a non-centrosymmetric structure.

[0016] In some embodiments, two of the buffer layer and two of the pressing layer are provided, and the buffer layer and the pressing layer are provided in a one-to-one correspondence, and the embedded layer is located between the two buffer layers.

[0017] In a second aspect, an embodiment of the present application provides a method for manufacturing a circuit board, which is used to manufacture the circuit board as described in the first aspect, comprising: The embedded layer, the buffer layer and the processing plate are stacked in sequence so that the power device is accommodated in the accommodation groove, the processing plate includes an insulating connection layer and a conductive layer stacked, and the insulating connection layer is located between the conductive layer and the buffer layer; Performing a pressing process on the embedded layer, the buffer layer, and the processing plate so that a portion of the insulating connection layer fills the gap between the sidewall of the receiving groove and the power device; Processing a first functional hole penetrating the conductive layer and a first hole penetrating the insulating connection layer, wherein the first hole and the first functional hole are coaxially arranged, and the insulating connection layer forms the press-fit connection layer; The first conductive part is set in the first hole, and the first filling part is set in the first functional hole. The first filling part is connected to the first conductive part and is electrically conductive. The first filling part and the conductive layer form the pressed circuit layer, and the processing board forms the pressed layer.

[0018] In some embodiments, the embedded layer includes a first core board and a first insulating layer that are stacked, and the embedded layer is provided with a mounting groove, which passes through the first core board and the first insulating layer; when the embedded layer, the buffer layer and the processing board are placed in sequence and stacked, the first insulating layer is located between the first core board and the buffer layer; after the embedded layer, the buffer layer and the processing board are pressed together, the first insulating layer forms a first dielectric layer, part of the first dielectric layer is located between the first core board and the buffer layer, and part of the first dielectric layer fills the gap between the side wall of the mounting groove and the heat sink.

[0019] In some embodiments, the embedded layer includes a second core plate and a second insulating layer that are stacked, the second insulating layer is located between the first core plate and the second core plate, and the mounting groove passes through the second core plate and the second insulating layer; after the embedded layer, the buffer layer and the processing plate are pressed together, the second insulating layer forms a second dielectric layer, part of the second dielectric layer is located between the first core plate and the second core plate, and part of the second dielectric layer fills the gap between the side wall of the mounting groove and the heat sink.

[0020] The circuit board provided by the embodiment of the present application has the following beneficial effects: since it includes a stacked embedded layer, a buffer layer and a pressed layer, the buffer layer is located between the embedded layer and the pressed layer, the buffer layer is provided with a receiving groove, the receiving groove passes through the buffer layer, the power device is located in the receiving groove, the orthographic projection of the buffer layer on the side of the pressed circuit layer facing away from the buffer layer and the orthographic projection of the heat sink on the side of the pressed circuit layer facing away from the buffer layer have an overlapping portion, and the power device is lower than the surface of the buffer layer facing away from the embedded layer or is flush with the surface of the buffer layer facing away from the embedded layer, so when the embedded layer, the buffer layer and the pressed layer are obtained by pressing, the buffer layer can be used to provide buffering protection for the peripheral side of the power device in the receiving groove to prevent the pressed layer from damaging the power device.

[0021] The beneficial effects of the manufacturing method of the circuit board provided in the present application compared with the existing technology can be referred to the description of the beneficial effects of the circuit board provided in the present application compared with the existing technology, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] Figure 1 It is a structural diagram of a circuit board in the related art; Figure 2 It is another structural schematic diagram of a circuit board in the related art; Figure 3 is a flow chart of a method for manufacturing a circuit board in the first embodiment of the present application; Figure 4 This is a schematic structural diagram of the embedded layer, buffer layer and processing plate in the first embodiment of the present application; Figure 5 Yes Figure 4 Schematic diagram showing the lamination process of the embedded layer, the buffer layer and the processing plate, and the processing of the first functional hole penetrating the conductive layer and the first hole penetrating the insulating connection layer; Figure 6 is Figure 5 A schematic structural diagram of a circuit board obtained after a first conductive portion is provided in the first hole and a first filling portion is provided in the first functional hole; Figure 7 This is a schematic structural diagram of a circuit board in the second embodiment of the present application; Figure 8 This is a schematic structural diagram of a circuit board in the third embodiment of the present application; Figure 9 yes Figure 8 The top view of the heat sink, power device and buffer core board in the circuit board shown; Figure 10 It is a structural diagram of the circuit board in the fourth embodiment of the present application.

[0024] The meanings of the marks in the figure are: 1. Embedded layer; 2. Heat sink; 3. Power chip; 4. Prepreg; 5. Circuit layer; 10. Embedded layer; 101, mounting slot; 11, first core board; 12, first dielectric layer; 120, first insulating layer; 13, second core board; 14, second dielectric layer; 140, second insulating layer; 20. Buffer layer; 201, accommodating groove; 21, buffer core plate; 210, first connecting hole; 211, first connecting portion; 212, inner circuit layer; 2121, avoidance groove; 2122, avoidance space; 22, buffer connection layer; 220, second connecting hole; 221, second connecting portion; 30. Lamination layer; 301, processing board; 3011, conductive layer; 3012, insulating connection layer; 31, pressing circuit layer; 3101, first functional hole; 3102, second functional hole; 32, pressing connection layer; 3201, first hole; 3202, second hole; 321, first conductive portion; 322, second conductive portion; 40. Heat sink; 50. Power devices. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0026] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0027] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0028] References to "one embodiment," "some embodiments," or "an embodiment" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present invention. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner.

[0029] In order to illustrate the technical solution of the present application, the following description is given with reference to specific drawings and embodiments.

[0030] With the continuous development of the electronic communications industry and automotive electronic technology, they tend to be miniaturized and multifunctional. Therefore, the requirements for related circuit board products are becoming higher and higher. Not only do they need to meet the requirements of use in high-current working environments, have ultra-high voltage resistance and excellent CAF (Conductive Anodic Filament) resistance, but they also need to achieve high-density interconnection and have excellent heat dissipation performance. Therefore, printed circuit boards with embedded power devices (such as power chips) were born.

[0031] Currently, there are two common heat sinks used for power devices: metal heat sinks, most commonly made of copper blocks, and ceramic blocks. In the copper block heat sink, the power device is typically secured within the copper block's grooves, typically hollowed out by mechanical depth control or etching. In the ceramic block heat sink, however, since grooves cannot be created through mechanical depth control or etching, the power chip is typically secured directly to the ceramic block's surface, leaving the entire chip exposed on one side of the ceramic base.

[0032] Please refer to Figure 1 In the related art, it is generally necessary to first fix the power device (such as the power chip 3) on the heat sink 2, and then fix the power device on the surface of the heat sink. Then, the two are embedded as a whole in the embedding layer 1 of the circuit board, and then the embedding layer 1 and the pressing layer are pressed together. The pressing layer generally includes a circuit layer 5 made of copper foil. During the pressing process, due to the weak supporting performance of the prepreg 4 between the embedding layer 1 and the pressing layer, the side of the power device is not protected, and the pressure of the press directly acts on the position of the power device, which is easy to crush and damage the power device, causing the circuit board to be scrapped.

[0033] Please refer to Figure 2 On the other hand, there is a risk of insufficient glue filling when pressing the embedded layer 1 and the pressing layer together. Since the size of the power device is usually smaller than the heat sink 2, and generally one or more power devices are welded to a ceramic bottom heat sink 2, the overall area of ​​the power device is smaller than the heat sink 2. On the side of the heat sink 2 facing the power device, the window of the semi-cured sheet 4 is larger than the heat sink 2. The pressing layer in the area other than the power device is in a suspended state. Therefore, after the power device is mounted on the heat sink 2, the semi-cured sheet 4 will flow glue during pressing in addition to filling the heat sink 2 and the embedded layer. 1 (core board) In addition to the gaps between the openings, the non-power device mounting area on the top of the heat sink 2 also needs to be filled, so multiple semi-cured sheets 4 are needed. However, even if multiple semi-cured sheets are added for lamination, due to the large gaps in the embedded area of ​​the power device, a large amount of flow glue is required to fill the embedded area during lamination. After lamination, the uniformity of the dielectric layer of the entire board is poor, which will still lead to the problem of depression in the embedded area of ​​the power device, and further lead to the problem that the laser blind hole processing parameters of the embedded area of ​​the power device are difficult to control, and the electroplating filling parameters are difficult to set, making it difficult to produce the outer circuit layer 5.

[0034] In view of this, the present application provides a circuit board and a manufacturing method thereof, which includes a stacked embedded layer, a buffer layer and a pressing layer, the buffer layer is located between the embedded layer and the pressing layer, the buffer layer is provided with a receiving groove, the receiving groove passes through the buffer layer, the power device is located in the receiving groove, the positive projection of the buffer layer on the side of the pressed circuit layer facing away from the buffer layer and the positive projection of the heat sink on the side of the pressed circuit layer facing away from the buffer layer have an overlapping part, and the power device is lower than the surface of the buffer layer facing away from the embedded layer or is flush with the surface of the buffer layer facing away from the embedded layer, so when the embedded layer, the buffer layer and the pressing layer are obtained by pressing, the buffer layer can be used to provide buffering protection for the peripheral side of the power device in the receiving groove to prevent the pressing layer from damaging the power device.

[0035] Please refer to Figures 3 to 6 A first embodiment of the present application provides a circuit board, comprising a stacked embedded layer 10 , a buffer layer 20 and a laminated layer 30 , wherein the buffer layer 20 is located between the embedded layer 10 and the laminated layer 30 .

[0036] A heat sink 40 is provided inside the embedded layer 10 , and a power device 50 is provided on a side of the heat sink 40 facing the pressing layer 30 .

[0037] The heat sink 40 can be a metal block (such as a copper block) or a ceramic block. When the heat sink 40 is a copper block, there is no need to mechanically control the depth or etch the grooves, thereby reducing the cost of making the grooves in the heat sink 40. The power device 50 can be a power chip, etc.

[0038] The buffer layer 20 is provided with a receiving groove 201, which penetrates the buffer layer 20. The power device 50 is located in the receiving groove 201. The orthographic projection of the buffer layer 20 on the side of the pressed circuit layer 31 facing away from the buffer layer 20 and the orthographic projection of the heat sink 40 on the side of the pressed circuit layer 31 facing away from the buffer layer 20 have an overlapping portion, and the power device 50 is lower than the surface of the buffer layer 20 facing away from the embedded layer 10 or is flush with the surface of the buffer layer 20 facing away from the embedded layer 10.

[0039] For example, the thickness of the power device 50 is 0.2 mm, and the surface of the buffer layer 20 facing away from the buried layer 10 is 0.1 mm higher than the power device 50 .

[0040] The buffer layer 20 may include a core plate and / or a dielectric layer. The length and width of the accommodating groove 201 are both smaller than the heat sink 40. The power device 50 can be loosely fitted within the accommodating groove 201. Because the buffer layer 20 is closer to the power device 50, when the embedded layer 10, the buffer layer 20, and the press-fit layer 30 are formed by pressing together, the buffer layer 20 can provide buffering protection around the power device 50 within the accommodating groove 201, preventing the press-fit layer 30 from damaging the power device 50.

[0041] The pressed layer 30 includes a pressed circuit layer 31 and a pressed connection layer 32. Part of the pressed connection layer 32 is located between the pressed circuit layer 31 and the buffer layer 20, and part of the pressed connection layer 32 fills the gap between the side wall of the accommodating groove 201 and the power device 50. The pressed connection layer 32 is provided with a first hole 3201, and a first conductive part 321 is provided inside the first hole 3201. Part of the pressed circuit layer 31 is connected to the power device 50 through the first conductive part 321 and is electrically conductive.

[0042] The pressed circuit layer 31 can be made of copper, silver, or aluminum. The pressed connection layer 32 can be formed by pressing and curing one or more sheets of polypropylene (PP). The first conductive portion 321 can be made of copper, silver, or aluminum. Multiple pressed circuit layers 31 and multiple pressed connection layers 32 can be provided.

[0043] The method for manufacturing the circuit board provided in the above embodiment includes: S100: The embedded layer 10, the buffer layer 20 and the processing plate 301 are placed in sequence and stacked so that the power device 50 is accommodated in the accommodating groove 201. The processing plate 301 includes a stacked insulating connection layer 3012 and a conductive layer 3011. The insulating connection layer 3012 is located between the conductive layer 3011 and the buffer layer 20.

[0044] S200 : performing a pressing process on the embedded layer 10 , the buffer layer 20 and the processing board 301 , so that a portion of the insulating connection layer 3012 fills the gap between the sidewall of the receiving groove 201 and the power device 50 .

[0045] Among them, since the orthographic projection of the buffer layer 20 on the side of the pressed circuit layer 31 facing away from the buffer layer 20 and the orthographic projection of the heat sink 40 on the side of the pressed circuit layer 31 facing away from the buffer layer 20 have an overlapping part, the power device 50 is lower than the surface of the buffer layer 20 facing away from the embedded layer 10 or is flush with the surface of the buffer layer 20 facing away from the embedded layer 10. Therefore, during pressing, the buffer core board 21 and the buffer connection layer 22 are used to buffer and protect the surrounding side of the power device 50 in the accommodating groove 201, which plays a buffering role and disperses the pressure of the press. The pressure will not be concentrated on the power device 50, thereby avoiding crushing or damage to the power device 50.

[0046] S300 : processing a first functional hole 3101 penetrating the conductive layer 3011 and a first hole 3201 penetrating the insulating connection layer 3012 , wherein the first hole 3201 and the first functional hole 3101 are coaxially arranged, and the insulating connection layer 3012 forms a press-fit connection layer 32 .

[0047] The first functional hole 3101 penetrating the conductive layer 3011 and the first hole 3201 penetrating the insulating connection layer 3012 can be machined by mechanical drilling or laser drilling.

[0048] S400: A first conductive portion 321 is set in the first hole 3201, and a first filling portion is set in the first functional hole 3101. The first filling portion is connected to the first conductive portion 321 and is electrically conductive. The first filling portion and the conductive layer 3011 form a laminated circuit layer 31, and the processing board 301 forms a laminated layer 30.

[0049] The first conductive portion 321 may be provided in the first hole 3201 by electroplating and filling the hole, and the first filling portion may be provided in the first functional hole 3101 . Meanwhile, the conductive layer 3011 may be thickened by electroplating.

[0050] From the above, it can be seen that the circuit board and the manufacturing method thereof provided in the embodiment of the present application include a stacked embedded layer 10, a buffer layer 20 and a pressing layer 30, the buffer layer 20 is located between the embedded layer 10 and the pressing layer 30, the buffer layer 20 is provided with a receiving groove 201, the receiving groove 201 passes through the buffer layer 20, the power device 50 is located in the receiving groove 201, the orthographic projection of the buffer layer 20 on the side of the pressing circuit layer 31 facing away from the buffer layer 20 and the orthographic projection of the heat sink 40 on the side of the pressing circuit layer 31 facing away from the buffer layer 20 have an overlapping part, and the power device 50 is lower than the surface of the buffer layer 20 facing away from the embedded layer 10 or is flush with the surface of the buffer layer 20 facing away from the embedded layer 10, so when the embedded layer 10, the buffer layer 20 and the pressing layer 30 are obtained by pressing, the buffer layer 20 can be used to provide buffering protection for the peripheral side of the power device 50 in the receiving groove 201 to prevent the pressing layer 30 from damaging the power device 50.

[0051] In the first embodiment, the buffer layer 20 includes a buffer core plate 21 and a buffer connection layer 22, the accommodating groove 201 passes through the buffer core plate 21 and the buffer connection layer 22, part of the buffer connection layer 22 is located between the buffer core plate 21 and the embedded layer 10, and part of the buffer connection layer 22 fills the gap between the side wall of the accommodating groove 201 and the power device 50.

[0052] By adopting the above solution, the buffer core plate 21 and the buffer connection layer 22 can better buffer and protect the peripheral side of the power device 50 in the accommodating groove 201, play a better buffering role, and disperse the pressure of the press.

[0053] It is understood that the buffer core board 21 can be an optical core board or a double-sided copper-clad core board. In the first embodiment, the buffer core board 21 is an FR-4 optical core board, which can be obtained by etching away the copper on both sides of the double-sided copper-clad board. The optical core board can be made of a fiberglass material or without fiberglass. The buffer core board 21 is relatively hard and provides a good buffering effect. The buffer connecting layer 22 can be formed by laminating and curing one or more sheets of PP (prepreg). The accommodating groove 201 can be machined by milling or laser processing.

[0054] It can also be understood that the thickness of the buffer layer 20 will become smaller after lamination. For example, the thickness of the power device 50 is 0.2mm, and the thickness of the buffer layer 20 needs to be designed to be about 0.25mm-0.3mm. Therefore, a buffer core board 21 with a thickness of about 0.15mm can be selected, and two PP sheets with a thickness of about 0.075mm can be selected for the buffer connection layer 22. The total thickness before lamination is about 0.3mm. After lamination, the PP glue flow will reduce the thickness by about 0.05mm. After lamination, the thickness of the buffer layer 20 will be above 0.25mm. Such a design can not only make the pressure of the press act on the position of the buffer core board 21 during lamination, but also meet the thickness requirements of the buffer connection layer 22 as a dielectric layer. At the same time, it can also improve the uniformity of the thickness of the buffer connection layer 22 of the corresponding layer, thereby improving the production of subsequent laser drilling and electroplating filling processes.

[0055] Among them, the orthographic projection of the buffer connection layer 22 on the side of the pressed circuit layer 31 facing away from the pressed connection layer 32 and the orthographic projection of the heat sink 40 on the side of the pressed circuit layer 31 facing away from the pressed connection layer 32 have overlapping parts; and / or, the orthographic projection of the buffer core board 21 on the side of the pressed circuit layer 31 facing away from the pressed connection layer 32 and the orthographic projection of the heat sink 40 on the side of the pressed circuit layer 31 facing away from the pressed connection layer 32 have overlapping parts.

[0056] Such an arrangement can better provide buffer protection for the peripheral side of the power device 50 in the receiving groove 201, play a better buffering role, and disperse the pressure of the press.

[0057] Please refer to Figure 6 Optionally, the surface of the embedded layer 10 facing the laminate layer 30 is higher than the surface of the heat sink 40 facing the laminate layer 30 , and the thickness of the buffer layer 20 is greater than or equal to the height of the power device 50 .

[0058] By adopting the above solution, the power device 50 can be easily positioned below the surface of the buffer layer 20 facing away from the buried layer 10 .

[0059] In other embodiments, the surface of the embedded layer 10 facing the lamination layer 30 is flush with the surface of the heat sink 40 facing the lamination layer 30 , and the thickness of the buffer layer 20 is greater than or equal to the height of the power device 50 .

[0060] Such an arrangement can facilitate the high-efficiency device to be lower than the surface of the buffer layer 20 away from the buried layer 10 or flush with the surface of the buffer layer 20 away from the buried layer 10 .

[0061] In the first embodiment, the surface of the embedded layer 10 facing the laminated layer 30 is higher than the surface of the heat sink 40 facing the laminated layer 30, and the sum of the thicknesses of the buffer core plate 21 and the buffer connection layer 22 is greater than or equal to the height of the power device 50; and / or, the surface of the embedded layer 10 facing the laminated layer 30 is flush with the surface of the heat sink 40 facing the laminated layer 30, and the sum of the thicknesses of the buffer core plate 21 and the buffer connection layer 22 is greater than or equal to the height of the power device 50.

[0062] Optionally, the buffer layer 20 is provided with a connecting hole, a connecting part is provided in the connecting hole, the pressed connecting layer 32 is provided with a second hole 3202, a second conductive part 322 is provided inside the second hole 3202, and part of the pressed circuit layer 31 is connected to the heat sink 40 in turn through the second conductive part 322 and the connecting part and is electrically conductive.

[0063] With such configuration, part of the pressed circuit layer 31 can be connected to the heat sink 40 through the second conductive portion 322 and the connecting portion in sequence and electrically conductive, and the heat of the heat sink 40 can be conducted away through this part of the pressed circuit layer 31 .

[0064] In the first embodiment, the connection hole includes a first connection hole 210 provided in the buffer core board 21 and a second connection hole 220 provided in the buffer connection layer 22, and the connection part includes a first connection part 211 provided inside the first connection hole 210 and a second connection part 221 provided inside the second connection hole 220. The first connection part 211 is connected to the second connection part 221, and the partially pressed circuit layer 31 is connected to the heat sink 40 in turn through the second conductive part 322, the first connection part 211 and the second connection part 221 and is electrically conductive.

[0065] It is understood that the first connecting portion 211, the second connecting portion 221, and the second conductive portion 322 can all be made of copper, silver, or aluminum. When the first conductive portion 321 is provided in the first hole 3201 by electroplating, and the first filling portion is provided in the first functional hole 3101, the first connecting portion 211, the second connecting portion 221, and the second conductive portion 322 can be electroplated and filled in the first connecting hole 210, the second connecting hole 220, and the second hole 3202, respectively.

[0066] It should be noted that the pressed circuit layer 31 may include a control network and a heat dissipation network. The control network is connected to the power device 50 through the first conductive part 321 and is electrically conductive. The heat dissipation network is connected to the heat sink 40 through the second conductive part 322, the first connection part 211 and the second connection part 221 in turn and is electrically conductive.

[0067] Please refer to Figures 4 to 6In the first embodiment, the embedded layer 10 includes a first core plate 11 and a first insulating layer 120 that are stacked, and the embedded layer 10 is provided with a mounting groove 101, which penetrates the first core plate 11 and the first insulating layer 120; when the embedded layer 10, the buffer layer 20 and the processing plate 301 are placed in sequence and stacked, the first insulating layer 120 is located between the first core plate 11 and the buffer layer 20; after the embedded layer 10, the buffer layer 20 and the processing plate 301 are pressed together, the first insulating layer 120 forms a first dielectric layer 12, part of the first dielectric layer 12 is located between the first core plate 11 and the buffer layer 20, and part of the first dielectric layer 12 fills the gap between the side wall of the mounting groove 101 and the heat sink 40.

[0068] By adopting the above solution, the first dielectric layer 12 can fill the gap between the side wall of the mounting groove 101 and the heat sink 40 to ensure that the gap between the side wall of the mounting groove 101 and the heat sink 40 is fully filled, thereby better fixing the heat sink 40.

[0069] It should be noted that, in some embodiments, the buffer layer 20 includes a buffer core plate 21 , a buffer connection layer 22 and a first dielectric layer 12 as an integrated structure.

[0070] Optionally, the embedded layer 10 includes a second core board 13 and a second insulating layer 140 arranged in a stacked manner, the second insulating layer 140 is located between the first core board 11 and the second core board 13, and the mounting groove 101 passes through the second core board 13 and the second insulating layer 140; after the embedded layer 10, the buffer layer 20 and the processing board 301 are pressed together, the second insulating layer 140 forms a second dielectric layer 14, part of the second dielectric layer 14 is located between the first core board 11 and the second core board 13, and part of the second dielectric layer 14 fills the gap between the side wall of the mounting groove 101 and the heat sink 40.

[0071] With this arrangement, the first dielectric layer 12 and the second dielectric layer 14 can fill the gap between the side wall of the mounting groove 101 and the heat sink 40 , ensuring that the gap between the side wall of the mounting groove 101 and the heat sink 40 is fully filled, thereby better fixing the heat sink 40 .

[0072] It should be noted that the first core board 11 and the second core board 13 can both be optical core boards, single-sided copper-clad core boards, or double-sided copper-clad core boards, and one or more of the first core board 11, the first insulating layer 120, the second insulating layer 140, and the second core board 13 can be provided. The first insulating layer 120 and the second insulating layer 140 can both be provided as PP.

[0073] Optionally, part of the buffer connection layer 22 fills the gap between the side wall of the mounting groove 101 and the heat sink 40 .

[0074] In this way, the first dielectric layer 12, the second dielectric layer 14 and the buffer connection layer 22 can fill the gap between the side wall of the mounting groove 101 and the heat sink 40, ensuring that the gap between the side wall of the mounting groove 101 and the heat sink 40 is fully filled, thereby better fixing the heat sink 40.

[0075] In the related art, the press-fit connection layer 32 needs to be provided with multiple sheets of PP to fill the gap between the side wall of the buffer connection layer 22 filling the accommodating groove 201 and the power device 50, and to fill the surrounding of the heat sink 40. Therefore, multiple sheets of PP are required, and thicker PP is usually selected. However, the glass fiber of thick PP is relatively coarse and the glue content is relatively low. Laser drilling processing will cause glass fiber residue in the hole, affecting the subsequent hole filling electroplating and bringing reliability risks. At the same time, the low glue content may also lead to insufficient glue filling between the gaps.

[0076] In view of this, please refer to Figure 6 In the first embodiment, the pressed connection layer 32 includes glass fiber cloth, the glass fiber cloth includes glass fiber filaments, and the diameter of the glass fiber filaments is less than or equal to 4 μm.

[0077] By adopting the above solution, glass fiber residue can be avoided in the first hole 3201 and the second hole 3202 during processing, thereby avoiding the impact of the subsequent setting of the first conductive part 321 and the second conductive part 322 in the first hole 3201 and the second hole 3202 respectively.

[0078] It should be noted that the buffer connection layer 22 comprises glass fiber cloth, which comprises glass fiber filaments with a diameter less than or equal to 4 μm. This configuration can prevent glass fiber residue inside the second connection hole 220 from affecting subsequent hole filling electroplating.

[0079] Optionally, the distance between the sidewall of the receiving groove 201 and the power device 50 is 0.15 mm-0.25 mm, such as 0.15 mm, 0.18 mm, 0.20 mm, 0.22 mm, 0.23 mm or 0.25 mm.

[0080] Such a configuration can not only effectively protect the peripheral side of the power device 50 in the accommodating groove 201 through the buffer core plate 21 and the buffer connection layer 22, but also prevent the gap between the side wall of the accommodating groove 201 and the power device 50 from being too large and unable to be filled by the buffer connection layer 22 and the press-fit connection layer 32.

[0081] Please refer to Figure 7 In the second embodiment, the buffer layer 20 includes an inner circuit layer 212 , and the inner circuit layer 212 is provided with an avoidance space 2122 so that the inner circuit layer 212 and the power device 50 are spaced apart, and the accommodating groove 201 passes through the avoidance space 2122 .

[0082] By adopting the above solution, it is possible to avoid electrical conduction between the inner circuit layer 212 and the power device 50, thereby preventing a short circuit.

[0083] Optionally, the buffer layer 20 includes an inner circuit layer 212 , which is provided with a avoidance groove 2121 , a connection hole passes through the bottom wall of the avoidance groove 2121 , and the connection portion and the second conductive portion 322 are both spaced apart from the side wall of the avoidance groove 2121 .

[0084] Such a configuration can prevent the connecting portion and the second conductive portion 322 from being electrically connected to the inner circuit layer 212 and causing a short circuit.

[0085] It is understandable that the inner circuit layer 212 can be provided on the buffer core board 21 .

[0086] Optionally, the inner circuit layer 212 is further provided with an avoidance window, which is opposite to the heat sink 40 and larger than the heat sink 40, such as 0.1 mm larger, to prevent the problem of subsequent conduction between the pressed circuit layer 31 and the heat sink 40.

[0087] Please refer to Figure 8 and Figure 9 In the third embodiment, a plurality of power devices 50 and a plurality of receiving grooves 201 are provided, and the power devices 50 and the receiving grooves 201 are provided in a one-to-one correspondence.

[0088] By adopting the above solution, the gaps between adjacent power devices 50 can be filled with glue, defects such as glue shortage in the layer and board surface depression can be avoided, and the difficulty of the circuit manufacturing process of the pressed circuit layer 31 can be reduced.

[0089] It can be understood that part of the buffer core board 21 is located between adjacent power devices 50, which can reduce the amount of glue filling between adjacent power devices 50. Each gap has sufficient buffer connection layer 22 and press connection layer 32 to fill, solving the problem of press-fit voids caused by insufficient glue filling, which affects product reliability, and a series of abnormal problems such as the outer layer circuit film not being firmly attached due to the depression of the board surface, resulting in circuit corrosion and scrapping.

[0090] Optionally, the plurality of power devices 50 are distributed in a non-centrosymmetric structure.

[0091] With such a configuration, it is possible to check through the receiving groove 201 of the buffer layer 20 whether the power device 50 and the heat sink base are placed upside down.

[0092] It should be noted that the multiple power devices 50 are distributed in a non-center-symmetric structure, that is, the initial arrangement shape of the multiple power devices 50 is a first shape, and the arrangement shape of the multiple power devices 50 after rotating any angle around the center line of the multiple power devices 50 is a second shape, and the first shape and the second shape are different.

[0093] It can be understood that the plurality of accommodating grooves 201 are distributed in a non-centrosymmetrical structure.

[0094] For example, a plurality of power devices 50 and a heat sink 40 form a power module. For example, for a power module with a ceramic block as a base, especially a ceramic block with a regular shape, it is difficult to distinguish the direction of the power module by the shape of the ceramic block because the ceramic block has poor machinability. In the related art, the window of the semi-cured sheet is larger than the heat sink 40 as a whole. When the power module is embedded in the pressing process, it is impossible to identify whether it is placed upside down according to the shape of the heat sink 40.

[0095] In the embodiment of the present application, after the power module is placed in the mounting groove 101, the buffer layer 20 can be used to check whether the power module is placed in the wrong direction. By visually comparing the positions of the power device 50 and the receiving groove 201, the power module is not placed in the wrong direction. If the positions are aligned, the power module is placed in the wrong direction and needs to be readjusted. After the power module is checked for any abnormalities in its orientation, the embedding layer 10 and the buffer layer 20 are riveted together.

[0096] For example, embedded windows can be opened on the first core plate 11, the second core plate 13, the first dielectric layer 12, and the second dielectric layer 14 so that the entire structure is approximately 0.1 mm larger than the heat sink 40. Subsequently, the mounting groove 101 is formed, and the inner layer circuits of the first core plate 11 and the second core plate 13 are manufactured in a conventional manner. Two sets of riveting holes are designed for the first core plate 11, the second core plate 13, the first dielectric layer 12, and the second dielectric layer 14. The first set of riveting holes is used for riveting the first core plate 11, the second core plate 13, the first dielectric layer 12, and the second dielectric layer 14. The second set of riveting holes is used for riveting the first core plate 11, the second core plate 13, the first dielectric layer 12, the second dielectric layer 14, the buffer connection layer 22, and the buffer core plate 21.

[0097] The power chip can be firstly attached to the heat sink 40 to form a power module, and then the power module can be moved into a browning fixture and browned, and then baked.

[0098] Fusion and riveting: the first core plate 11, the second core plate 13, the first dielectric layer 12 and the second dielectric layer 14 are pressed and stacked in sequence, firstly fused and then riveted, and the first group of riveting holes are selected for riveting.

[0099] Place the power module: After riveting, affix a high-temperature film to one side of the embedded layer 10 away from the buffer layer 20, and then place the power module into the mounting groove 101 formed by the embedded window in the previous process. Pay attention to the direction of placement and do not place it upside down.

[0100] Secondary riveting: Before this process, use the buffer layer 20 to verify that the power module is correctly oriented. If misaligned, the power module must be re-oriented. After the power module is properly aligned, the embedding layer 10 and buffer layer 20 are riveted together again, using a second set of riveting holes.

[0101] The buffer core plate 21 and the buffer connection layer 22 can both be machined to have windows by means of mechanical milling or laser processing, and the windows on the buffer core plate 21 and the windows on the buffer connection layer 22 constitute the accommodating groove 201 .

[0102] Pressing and pre-stacking: The embedded layer 10, the buffer layer 20, the power module and the processing board 301 are formed into a whole. After pressing, part of the glue of the first dielectric layer 12 of the embedded layer 10, the buffer connection layer 22 of the buffer layer 20 and the insulating connection layer 3012 of the processing board 301 flows into the gap between the side wall of the accommodating groove 201 and the power device 50; the buffer connection layer 22 of the buffer layer 20 and the insulating connection layer 3012 of the processing board 301 partially fill the gap area between adjacent chips, so that the power device 50 is fixed in the embedded layer 10 and the buffer layer 20, and each area has enough glue to fill.

[0103] Laser drilling: The laser processing parameters are set according to the thickness of the insulating connecting layer 3012. Because fine glass fiber is selected and the insulating connecting layer 3012 in this area has good uniformity, the processing parameters of this process are easier to set, and there will be no quality problems such as residual glass fiber in the laser blind hole and residual glue at the bottom of the hole.

[0104] Plasma: Select the corresponding processing parameters according to the type of material, and the rest requirements are controlled according to the normal embedded power chip production requirements.

[0105] Copper cladding: Normal production according to normal processing parameters.

[0106] Via Filling: Via filling electroplating parameters are set based on the thickness of the press-fit connection layer 32 and the diameter of the laser-cut holes. The uniform thickness of the press-fit connection layer 32 reduces the difficulty of via filling electroplating. Anomalies such as recessed openings of the first and second functional holes 3101 and 3102, or localized core wrapping of the first and second holes 3201 and 3202, are avoided.

[0107] Outer layer circuit: The circuit production of the outer layer pressed circuit layer 31 is completed by film lamination, exposure, development and etching. Due to sufficient pressing and filling, there is no local depression on the board surface, there is no abnormality in the film lamination process, and there is no abnormality in the circuit etching caused by chemical corrosion of the circuit.

[0108] AOI (Automated Optical Inspection): AOI inspection is completed through conventional methods.

[0109] Solder Mask / Characterization: Solder mask / charactorization is done by conventional means.

[0110] Forming: Forming is done by conventional means, dividing the large panel into multiple unit panels.

[0111] Electrical testing: Test according to the requirements of embedded power chips.

[0112] OSP (Organic Solderability Preservative): Made according to the requirements for embedded power chips.

[0113] Quality inspection / packaging and shipment: Complete quality inspection through conventional methods until packaging and shipment.

[0114] Please refer to Figure 10 In the fourth embodiment, two buffer layers 20 and two pressing layers 30 are provided, and the buffer layers 20 and the pressing layers 30 are provided in a one-to-one correspondence, and the embedded layer 10 is located between the two buffer layers 20.

[0115] By adopting the above solution, the embedded layer 10 can be located inside the circuit board, thereby obtaining a circuit board with a fully embedded structure.

[0116] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A circuit board, characterized in that: It comprises a buried layer, a buffer layer and a pressing layer which are stacked, wherein the buffer layer is located between the buried layer and the pressing layer; A heat sink is provided inside the embedded layer, and a power device is provided on the side of the heat sink facing the pressing layer; The buffer layer is provided with a receiving groove, the receiving groove passes through the buffer layer, the power device is located in the receiving groove, the orthographic projection of the buffer layer on the side of the pressed circuit layer facing away from the buffer layer and the orthographic projection of the heat sink on the side of the pressed circuit layer facing away from the buffer layer have an overlapping portion, and the power device is lower than or flush with the surface of the buffer layer facing away from the embedded layer; The pressed layer includes a pressed circuit layer and a pressed connection layer, part of the pressed connection layer is located between the pressed circuit layer and the buffer layer, part of the pressed connection layer fills the gap between the side wall of the accommodating groove and the power device, the pressed connection layer is provided with a first hole, a first conductive part is provided inside the first hole, and part of the pressed circuit layer is connected to the power device through the first conductive part and is electrically conductive.

2. The circuit board according to claim 1, wherein: The buffer layer includes a buffer core plate and a buffer connection layer, the accommodating groove passes through the buffer core plate and the buffer connection layer, part of the buffer connection layer is located between the buffer core plate and the embedded layer, and part of the buffer connection layer fills the gap between the side wall of the accommodating groove and the power device.

3. The circuit board according to claim 2, wherein: The orthographic projection of the buffer connection layer on the side of the pressed circuit layer facing away from the pressed connection layer and the orthographic projection of the heat sink on the side of the pressed circuit layer facing away from the pressed connection layer have an overlapping portion; and / or, the orthographic projection of the buffer core board on the side of the pressed circuit layer facing away from the pressed connection layer and the orthographic projection of the heat sink on the side of the pressed circuit layer facing away from the pressed connection layer have an overlapping portion.

4. The circuit board according to claim 1, wherein: The buffer layer includes an inner circuit layer, and the inner circuit layer is provided with an avoidance space so that the inner circuit layer and the power device are spaced apart, and the accommodating groove runs through the avoidance space.

5. The circuit board according to claim 1, wherein: The surface of the embedded layer facing the pressing layer is higher than the surface of the heat sink facing the pressing layer, and the thickness of the buffer layer is greater than or equal to the height of the power device; Alternatively, a surface of the embedded layer facing the pressing layer is flush with a surface of the heat sink facing the pressing layer, and a thickness of the buffer layer is greater than or equal to a height of the power device.

6. The circuit board according to claim 1, wherein: The buffer layer is provided with a connection hole, a connection part is provided in the connection hole, the pressed connection layer is provided with a second hole, a second conductive part is provided inside the second hole, and part of the pressed circuit layer is connected to the heat sink through the second conductive part and the connection part in sequence and is electrically conductive.

7. The circuit board according to claim 6, characterized in that The buffer layer includes an inner circuit layer, the inner circuit layer is provided with a avoidance groove, the connection hole passes through the bottom wall of the avoidance groove, and the connection part and the second conductive part are both spaced apart from the side wall of the avoidance groove.

8. The circuit board according to claim 1, wherein: The pressed connection layer includes glass fiber cloth, the glass fiber cloth includes glass fiber filaments, and the diameter of the glass fiber filaments is less than or equal to 4 μm.

9. The circuit board according to any one of claims 1 to 8, characterized in that: The distance between the side wall of the accommodating groove and the power device is 0.15 mm to 0.25 mm.

10. The circuit board according to any one of claims 1 to 8, characterized in that: The power device and the receiving groove are both provided in plurality, and the power device and the receiving groove are provided in a one-to-one correspondence.

11. The circuit board according to claim 10, characterized in that: The plurality of power devices are distributed in a non-centrosymmetric structure.

12. The circuit board according to any one of claims 1 to 8, characterized in that: Two of the buffer layers and two of the pressing layers are provided, and the buffer layers and the pressing layers are provided in a one-to-one correspondence, and the embedded layer is located between the two buffer layers.

13. A method for manufacturing a circuit board, characterized in that: Used to manufacture a circuit board according to any one of claims 1 to 12, comprising: The embedded layer, the buffer layer and the processing plate are stacked in sequence so that the power device is accommodated in the accommodation groove, the processing plate includes an insulating connection layer and a conductive layer stacked, and the insulating connection layer is located between the conductive layer and the buffer layer; Performing a pressing process on the embedded layer, the buffer layer, and the processing plate so that a portion of the insulating connection layer fills the gap between the sidewall of the receiving groove and the power device; Processing a first functional hole penetrating the conductive layer and a first hole penetrating the insulating connection layer, wherein the first hole and the first functional hole are coaxially arranged, and the insulating connection layer forms the press-fit connection layer; The first conductive part is set in the first hole, and the first filling part is set in the first functional hole. The first filling part is connected to the first conductive part and is electrically conductive. The first filling part and the conductive layer form the pressed circuit layer, and the processing board forms the pressed layer.

14. The method for manufacturing a circuit board according to claim 13, wherein: The embedded layer includes a first core plate and a first insulating layer that are stacked together, and the embedded layer is provided with a mounting groove, which passes through the first core plate and the first insulating layer; when the embedded layer, the buffer layer and the processing plate are placed in sequence and stacked, the first insulating layer is located between the first core plate and the buffer layer; after the embedded layer, the buffer layer and the processing plate are pressed together, the first insulating layer forms a first dielectric layer, part of the first dielectric layer is located between the first core plate and the buffer layer, and part of the first dielectric layer fills the gap between the side wall of the mounting groove and the heat sink.

15. The method for manufacturing a circuit board according to claim 14, wherein: The embedded layer includes a second core plate and a second insulating layer that are stacked together, the second insulating layer is located between the first core plate and the second core plate, and the mounting groove passes through the second core plate and the second insulating layer; after the embedded layer, the buffer layer and the processing plate are pressed together, the second insulating layer forms a second dielectric layer, part of the second dielectric layer is located between the first core plate and the second core plate, and part of the second dielectric layer fills the gap between the side wall of the mounting groove and the heat sink.

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