Semiconductor device, manufacturing method thereof and memory system

Abstract

The embodiment of the invention discloses a semiconductor device and a manufacturing method thereof and a memory system, the semiconductor device comprises a first semiconductor structure, the first semiconductor structure comprises a semiconductor column extending along a first direction, and the semiconductor column comprises a first end and a second end which are oppositely arranged in the first direction; the bit line is positioned on one side, close to the first end, of the semiconductor column and is coupled with the first end; the bit lines extend along a second direction; a word line located on one side of the semiconductor pillar in the second direction, the word line extending in a third direction; the third direction intersects with the second direction, and a plane formed by the second direction and the third direction intersects with the first direction; the conductive structures are located between two adjacent semiconductor columns, and the conductive structures extend in the third direction; a distance between a part of the conductive structure and the bit line in the first direction is smaller than a distance between the word line and the bit line in the first direction.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a semiconductor device and a manufacturing method thereof, as well as a memory system. Background Art

[0002] Some semiconductor devices, such as dynamic random access memory (DRAM), may include a memory array and peripheral circuits. The peripheral circuits control the memory array and operate the memory array for read, write, or refresh operations. To improve the performance of memory devices, there is much room for improvement in memory devices and their manufacturing methods. Summary of the Invention

[0003] According to a first aspect of an embodiment of the present disclosure, a semiconductor device is provided, comprising a first semiconductor structure, comprising: a semiconductor column extending along a first direction, the semiconductor column comprising a first end and a second end oppositely arranged in the first direction; a bit line located on a side of the semiconductor column close to the first end and coupled to the first end; the bit line extending along a second direction; a word line located on a side of the semiconductor column in the second direction, the word line extending along a third direction; the third direction intersecting with the second direction, and a plane formed by the second direction and the third direction intersecting with the first direction; a conductive structure located between two adjacent semiconductor columns, the conductive structure extending along the third direction; a distance between a portion of the conductive structure and the bit line in the first direction is less than a distance between the word line and the bit line in the first direction.

[0004] In some embodiments, at least one end of the conductive structure in the third direction is spaced apart from the bit line in the first direction by a distance smaller than a distance between the word line and the bit line in the first direction.

[0005] In some embodiments, a dimension of a portion of the conductive structure in the first direction is greater than or equal to a dimension of the word line in the first direction.

[0006] In some embodiments, the conductive structure has two oppositely disposed ends in the third direction, and the distance between the portion of the conductive structure and the bit line in the first direction is greater than the distance between the word line and the bit line in the first direction.

[0007] In some embodiments, the first semiconductor structure further includes: a contact structure located on a side of the conductive structure close to the bit line in the first direction; the contact structure is coupled to at least one end of the conductive structure in the third direction.

[0008] In some embodiments, a constituent material of the semiconductor pillar includes silicon, and a constituent material of the bit line includes metal silicide.

[0009] In some embodiments, the first semiconductor structure further includes a gate dielectric layer located between the word line and the semiconductor pillar.

[0010] In some embodiments, the word line includes a first word line and a second word line, the semiconductor pillar includes a first side and a second side oppositely arranged in the second direction, and the semiconductor pillar includes a first semiconductor pillar and a second semiconductor pillar adjacently arranged in the second direction; the first word line is located on the first side of the first semiconductor pillar, and the second word line is located on the second side of the second semiconductor pillar.

[0011] In some embodiments, the conductive structure is located between the second side of the first semiconductor pillar and the first side of the second semiconductor pillar.

[0012] In some embodiments, the first semiconductor structure further includes: a capacitor structure located on a side of the semiconductor pillar away from the bit line and coupled to the second end.

[0013] In some embodiments, the capacitor structure includes: a first electrode, a first dielectric layer surrounding the first electrode, and a second electrode; the first dielectric layer is located between the first electrode and the second electrode.

[0014] In some embodiments, the semiconductor device further includes: a second semiconductor structure, the second semiconductor structure including a peripheral circuit, located on a side of the bit line away from the semiconductor pillar; and the second semiconductor structure is bonded to the first semiconductor structure.

[0015] According to some aspects of the embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided to form a first semiconductor structure, and the method for forming the first semiconductor structure includes: forming a semiconductor column extending along a first direction, the semiconductor column including a first end and a second end oppositely arranged in the first direction; forming a bit line on a side of the semiconductor column close to the first end, the bit line being coupled to the first end; the bit line extending along a second direction; forming a word line extending along a third direction on one side of the semiconductor column in the second direction; the third direction intersects with the second direction, and a plane formed by the second direction and the third direction intersects with the first direction; forming a conductive structure between two adjacent semiconductor columns, the conductive structure extending along the third direction; wherein a distance between a portion of the conductive structure and the bit line in the first direction is less than a distance between the word line and the bit line in the first direction.

[0016] In some embodiments, the method of forming the semiconductor pillar includes: etching the semiconductor layer to form a first groove extending along the second direction; etching the semiconductor layer to form a second groove and a third groove extending along the third direction and alternately arranged in the second direction; wherein the second groove and the first groove divide the semiconductor layer into the semiconductor pillars, and the size of the second groove in the first direction is smaller than the size of the first groove.

[0017] In some embodiments, the method of forming the conductive structure includes: etching the bottom of the third trench so that the size of the third trench in the first direction is larger than the size of the second trench in the first direction; and forming the conductive structure in the third trench.

[0018] In some embodiments, the method of forming the conductive structure includes: forming a second dielectric layer on the inner wall of the third trench; penetrating the second dielectric layer at the bottom of the third trench, and etching the semiconductor layer below the bottom of the third trench so that the size of the third trench in the first direction is larger than the size of the second trench in the first direction; after penetrating the second dielectric layer, forming the conductive structure in the third trench.

[0019] In some embodiments, the method of forming the first semiconductor structure further includes: forming a gate dielectric layer and a word line on the sidewalls of the second trench, wherein the word lines on the two sidewalls of the second trench in the second direction are respectively a first word line and a second word line.

[0020] In some embodiments, the method of forming the first semiconductor structure further includes: forming a capacitor structure on a side of the semiconductor pillar close to the second end, wherein the capacitor structure is coupled to the second end.

[0021] In some embodiments, the capacitor structure includes: a first electrode, a first dielectric layer surrounding the first electrode, and a second electrode; the first dielectric layer is located between the first electrode and the second electrode.

[0022] In some embodiments, the method of forming the first semiconductor structure further includes: filling the second trench and the first trench to form a third dielectric layer, forming the conductive structure between adjacent filled second trenches; and thinning the semiconductor layer to expose the third dielectric layer.

[0023] In some embodiments, the method of forming the first semiconductor structure also includes: removing a portion of the third dielectric layer covering the conductive structure to expose one side of the conductive structure in the first direction; etching a portion of the conductive structure to form a notch to reduce the size of the portion of the conductive structure in the first direction.

[0024] In some embodiments, the conductive structure has two opposite ends in the third direction; when the gap is formed, at least one of the two ends is retained.

[0025] In some embodiments, the method of forming the first semiconductor structure further includes: forming a contact structure on a side of the conductive structure close to the bit line along the first direction, wherein the contact structure is coupled to at least one end of the conductive structure in the third direction.

[0026] In some embodiments, the semiconductor layer comprises silicon, and the method of forming the bit line comprises: forming a metal silicide layer by thinning a remaining portion of the semiconductor layer extending along the second direction to form the bit line.

[0027] In some embodiments, the method for manufacturing the semiconductor device further includes: providing a second semiconductor structure; and bonding the second semiconductor structure and the first semiconductor structure on a side of the bit line away from the bit line.

[0028] According to some aspects of the embodiments of the present disclosure, there is provided a memory system including: a memory device including the semiconductor device; and a memory controller coupled to the memory device and controlling the memory device.

[0029] An embodiment of the present disclosure provides a semiconductor device including a first semiconductor structure, wherein the first semiconductor structure includes a semiconductor pillar extending along a first direction, a bit line coupled to a first end of the semiconductor pillar and extending along a second direction, a word line located on a side of the semiconductor pillar and extending along a third direction, and a conductive structure located between two adjacent semiconductor pillars and extending along the third direction; a distance between a portion of the conductive structure and the bit line in the first direction is smaller than a distance between the word line and the bit line in the first direction; this portion of the conductive structure can protrude from the word line toward the bit line in the first direction, thereby facilitating the wiring of the conductive structure along the first direction, while other portions of the conductive structure do not protrude from the word line, thereby reducing leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic diagram of a storage array according to an exemplary embodiment;

[0031] Figures 2 to 10 is a schematic structural diagram of different parts of a semiconductor device according to an embodiment of the present disclosure;

[0032] Figure 11 is a flow chart of a method for manufacturing a first semiconductor structure according to an embodiment of the present disclosure;

[0033] Figures 12 to 30is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0034] Figure 31 and Figure 32 It is a schematic diagram of a system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0036] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0037] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion.

[0038] It should be understood that, in addition to the orientations shown in the figures, spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then, elements or features described as "below" or "beneath" or "under" other elements will be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0039] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] It should be understood that “some embodiments” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, “in some embodiments” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the sequence numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.

[0041] The semiconductor device in the embodiments of the present disclosure may be a DRAM, or at least a portion of a DRAM memory device, and may be applicable to double data rate synchronous dynamic random access memory (SDR) using DDR4 or DDR5 memory specifications, or low power double data rate synchronous dynamic random access memory (LPDDR5) memory specifications. It should be noted that the embodiments of the present disclosure are not limited to DRAM, but for clarity of description, DRAM will be used as an example in the subsequent description.

[0042] In DRAM, the memory array can be arranged in rows and columns so that the memory cell can be addressed by specifying the row and column of the array. The memory array includes multiple word lines and multiple bit lines. The word lines and bit lines intersect, and the memory cell at the intersection of the selected word line and the selected bit line is selected to perform read, write or refresh operations. Figure 1As illustrated, the memory array may include multiple word lines WLn, WLn+1, WLn-1, and WLn-2, ​​and multiple bit lines BLn, BLn+1, BLn-1, and BLn-2, ​​with the word lines and bit lines intersecting. A memory cell in the memory array may include a capacitor and a transistor, with each memory cell comprising a transistor and a capacitor. A word line may also be a conductive structure, such as a gate layer, serving as the gate of a transistor. One controlled terminal (source) of the transistor is coupled to one electrode (second electrode) of the capacitor, and the other controlled terminal (drain) of the transistor is coupled to the bit line. The other electrode (first electrode) of the capacitor may be grounded or have another voltage applied (e.g., vdd / 2). Figure 1 As shown, the memory cell array is arranged in an array of x rows and y columns, and the rows and columns may be perpendicular or non-perpendicular. The x direction may be the second direction mentioned in the embodiment of the present disclosure, and the y direction may be the third direction mentioned in the embodiment of the present disclosure. The extension direction of the bit line may be parallel to the x direction or have an angle with the x direction, and the extension direction of the word line may be parallel to the y direction or have an angle with the y direction. The orthographic projection of the word line on the xoy plane is perpendicular to the orthographic projection of the bit line on the xoy plane, or is not perpendicular but has a certain angle, and the embodiment of the present disclosure does not limit this. The z direction exemplified below may be the first direction, and the z direction may be perpendicular to the plane xoy, or intersect with the xoy plane but is not perpendicular.

[0043] During a read or write operation, a wordline select signal is used to select the corresponding wordline, and a column select signal is used to select the corresponding bitline. Simultaneous selection of the wordline and bitline locates the selected memory cell. The transistor of the selected memory cell is then turned on by the operating voltage applied by the wordline, enabling a read, write, or refresh operation to be performed on the selected memory cell. In some embodiments, the capacitor can be replaced with other memory structures, including but not limited to phase-change memory structures, resistive memory structures, or magnetic memory structures.

[0044] In some embodiments, a capacitor represents a logical 1 or 0 by the amount of charge stored in it, or the voltage difference across the capacitor. A voltage signal on the word line is applied to the gate, turning the transistor on or off, thereby selecting or deselecting the capacitor. Data stored in the capacitor can then be read through the bit line, or data can be written to the capacitor for storage.

[0045] According to a first aspect of an embodiment of the present disclosure, a semiconductor device is provided. The structural schematic diagram of the semiconductor device can be as follows: Figures 2 to 5 As shown; Figure 2 This is an example diagram of the xoy cross section of a semiconductor device. Figure 3 、 Figure 4 as well as Figure 5 They are Figure 2In the example xoy cross-sectional view of the semiconductor device at AA', BB', and CC', the first direction may include the z-direction, the second direction may include the x-direction, and the third direction may include the y-direction. The semiconductor device may include a first semiconductor structure 101, comprising: a semiconductor pillar 111 extending along a first direction, the semiconductor pillar 111 including a first end and a second end oppositely disposed in the first direction; a bit line 113 located on a side of the semiconductor pillar 111 proximate to the first end and coupled to the first end; the bit line 113 extending along a second direction; a word line 116 located on a side of the semiconductor pillar 111 in the second direction, the word line 116 extending along a third direction; the third direction intersecting the second direction, with a plane formed by the second and third directions intersecting the first direction; a conductive structure 115 located between two adjacent semiconductor pillars 111, the conductive structure 115 extending along the third direction; a portion of the conductive structure 115 being located closer to the bit line 113 in the first direction than the word line 116 is located in the first direction.

[0046] For example, Figure 2 As shown in FIG, the bit line 113 extends along the x direction, the conductive structure 115 (or back gate) extends along the y direction, and the word line 116 extends along the y direction. Figure 2 The buffer layer 112 is not shown in the figure, and the extending direction of the word line 116 can be indicated by the extending direction of the buffer layer 112, which is the y direction. Figure 3 and Figure 4 As shown, buffer layer 112 is located at the end of word line 116 in the z-direction, near bit line 113. Buffer layer 112 is used during the fabrication of word line 116 to increase the etching process window, adjust the z-direction dimensions of word line 116, increase insulation isolation between the word line end and other components, and reduce leakage current breakdown at the word line end. First semiconductor structure 101 also includes a first contact structure 121 coupled to word line 116, through which power is supplied to word line 116; a second contact structure 122 coupled to conductive structure 115; and a third contact structure 123 coupled to bit line 113.

[0047] It should be noted that, because the word line 116 is blocked by the buffer layer 112, Figure 2 Two first contact structures 121 are provided on both sides of the buffer layer 112. One buffer layer 112 corresponds to two word lines 116 and two semiconductor pillars 111. One first contact structure 121 on one side of the buffer layer 112 is coupled to one word line 116, and one first contact structure 121 on the other side is coupled to another word line 116, thereby achieving independent power supply to different word lines 116. The second contact structure 122 can be located on either side of the conductive structure 115 in the y-direction, or both sides of a conductive structure 115 can have a second contact structure 122. Figure 2The second contact structures 122 shown in the example are staggered in distribution. The odd-numbered second contact structures 122 can be located on the right side of the conductive structure 115, and the even-numbered second contact structures 122 can be located on the left side of the conductive structure 115. That is, the second contact structures 122 on any two adjacent conductive structures 115 are located on different sides, so as to increase the distance between the second contact structures 122 and reduce mutual interference.

[0048] The second contact structure 122 leads the electrical signal out of the conductive structure 115, so that the conductive structure 115 between adjacent semiconductor pillars 111 is connected to a low potential, such as ground or negative voltage, thereby improving the coupling effect between adjacent transistors, reducing the parasitic capacitance between adjacent semiconductor pillars 111, and improving device stability. Figure 2 The third contact structures 123 shown in the example are staggered. Odd-numbered third contact structures 123 may be located on the upper side of the bit line 113, and even-numbered third contact structures 123 may be located on the lower side of the bit line 113. That is, the third contact structures 123 on any two adjacent bit lines 113 are located on different sides. The first contact structure 121, the second contact structure 122, and the third contact structure 123 may extend along the z-direction, including but not limited to conductive plugs, conductive strips, conductive channels, and other structures, such as Figure 3 The second contact structure 122 is shown extending along the z-direction.

[0049] Figure 3 and Figure 4 The semiconductor pillar 111 extending along the z direction has a first end and a second end oppositely arranged in the z direction. The first end and the second end have the same type of doping. Both ends serve as the active region of the transistor (drain or source, the source and drain can be interchanged). The middle area between the first end and the second end can have a doping type opposite to that of the first end as the channel of the transistor. The first end can be Figure 3 One end of the center is in the z direction, and the second end can be Figure 3 The first end of the negative z-direction is coupled to the bit line 113, and the second end is coupled to the capacitor structure 141. The transistor may further include a word line 116 and a gate dielectric layer 132 between the word line 116 and the semiconductor pillar 111. The word line 116 serves as a control gate of the transistor.

[0050] Exemplarily, the gate dielectric layer 132 and the buffer layer 112 may be composed of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride, or aluminum oxide. Different layers of the same material may contact each other without a physical boundary. For example, the gate dielectric layer 132 may include silicon oxide, and the buffer layer 112 may include silicon nitride, to improve the selectivity of the etching process.

[0051] For example, the contact structure and word line 116 may be made of conductive materials including, but not limited to, tungsten, gold, silver, copper, chromium, nickel, titanium, or aluminum. The semiconductor pillars may be made of materials including, but not limited to, elemental semiconductor materials (e.g., silicon, germanium), Group III-V compound semiconductor materials, Group II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art.

[0052] In some embodiments, the first ends of the plurality of semiconductor pillars 111 arranged in the x-direction are connected by semiconductor material. When forming the semiconductor pillars 111, the semiconductor material between the adjacent semiconductor pillars 111 in the y-direction is removed. The semiconductor material between the adjacent semiconductor pillars 111 in the x-direction is not completely removed. The remaining semiconductor material may have no obvious physical boundary with the first end. The plurality of semiconductor pillars 111 arranged in the x-direction are Figure 3 The first ends shown are connected by semiconductor material in a fence or zigzag shape.

[0053] In some embodiments, the semiconductor pillar 111 is formed of silicon, and the bit line 113 is formed of metal silicide.

[0054] When forming bit line 113, a portion of the remaining semiconductor material is subjected to metal silicide treatment to form a metal-semiconductor compound. This metal-semiconductor compound can reduce the contact barrier with third contact structure 123, thereby reducing contact resistance and increasing adhesion between bit line 113 and third contact structure 123. The remaining semiconductor material can also be heavily doped to increase conductivity to form bit line 113. Exemplarily, semiconductor pillar 111 may include silicon, such as any crystalline silicon, including single crystal silicon, polycrystalline silicon, or amorphous silicon. Bit line 113 is a metal silicide formed based on silicon, such as titanium silicide, zirconium silicide, tantalum silicide, tungsten silicide, nickel silicide, and the like. Figure 2 The residual semiconductor material at the AA' position where the third conductive structure 115 is not provided extends along the x direction and is connected to the first end. The cross-sectional structure at xoz is as follows: Figure 3 As shown, this portion of semiconductor material has not undergone a metal silicide process and does not serve as an energized bit line 113, but may be referred to as a dummy bit line 114. Multiple bit lines 113 are located between two dummy bit lines 114, and the semiconductor pillars 111 corresponding to these dummy bit lines 114 do not serve as switching transistors for selecting the capacitor structure 141. In other embodiments, this portion of semiconductor material may undergo a metal silicide process to form a dummy bit line 114, which is not provided with a contact structure lead.

[0055] Reference Figure 3As shown, the second contact structure 122 may penetrate the semiconductor material connected to the first end of the semiconductor pillar 111. When the conductive structure 115 extends along the y direction, or the second contact structure 122 faces the area between adjacent bit lines 113 in the z direction, the second contact structure 122 may not face the semiconductor material connected to the first end of the semiconductor pillar 111 in the z direction, and the second contact structure 122 may not contact the semiconductor material. The bit line 113 may be as shown in FIG. Figure 5 In the example, the bit line 113 is formed based on semiconductor material through a metal silicidation process. The physical boundary between the bit line 113 and the semiconductor pillar 111 may be unclear or irregular. The third contact structure 123 is located on the bit line 113 and coupled to the bit line 113 . Figure 5 The first ends of the plurality of semiconductor pillars 111 arranged along the x-direction are connected by semiconductor material, and the plurality of semiconductor pillars 111 form a fence shape, and the first ends are not completely interrupted.

[0056] In some embodiments, the bit line 113 may be formed by depositing a conductive layer on one side of the semiconductor pillar 111 near the first end, such as depositing a conductive material such as tungsten, gold, silver, copper, chromium, nickel, titanium or aluminum. In this embodiment, when forming the semiconductor pillars 111, the semiconductor material between the adjacent semiconductor pillars 111 in the y direction is removed, and the semiconductor material between the adjacent semiconductor pillars 111 in the x direction is removed. Figure 6 In the example shown, there is no residual semiconductor material connection between adjacent semiconductor pillars 111 arranged in the x direction, and there is no residual semiconductor material connection between adjacent semiconductor pillars 111 arranged in the y direction. No bit line 113 is set between the second contact structure 122 and the semiconductor pillar 111. This part of the semiconductor pillar 111 is used to provide support. In other embodiments, Figure 6 A dummy bit line 114 is provided on one side of the semiconductor pillar 111 close to the first end. The dummy bit line 114 is not provided with a contact structure for wiring. The second contact structure 122 penetrates the dummy bit line 114 and is coupled to the conductive structure 115 .

[0057] In the embodiment of the present disclosure, the conductive structure 115 is located between two adjacent semiconductor pillars 111 in the x-direction. A portion of the conductive structure 115 is located at a distance from the bit line 113 in the z-direction that is less than the distance from the word line 116 in the z-direction. This portion of the conductive structure 115 may protrude from the word line 116 toward the bit line 113 in the z-direction, being closer to the bit line 113 than the word line 116. The portion protruding from the word line 116 may be used to couple with the second contact structure 122, thereby reducing the difficulty of manufacturing the second contact structure 122. The portion of the conductive structure 115 that does not protrude from the word line 116 may reduce leakage. The portion of the conductive structure 115 that protrudes from the word line 116 may be located at any position of the conductive structure 115, for example, it may be Figure 3As shown, it is located at any one of the two ends in the y direction, or it can be located at any position between the two ends in the y direction, and can be specifically set according to the lead position of the conductive structure 115 or the preset position of the lead; Figure 4 As shown, other non-lead regions of the conductive structure 115 may not protrude from the word line 116 , and the upper surface of the conductive structure 115 may be flush with or lower than the upper surface of the word line 116 to reduce leakage.

[0058] In some embodiments, reference Figure 3 As shown, the distance from the bit line 113 in the first direction is smaller than the distance from the word line 116 in the first direction; at least one end of the conductive structure 115 in the third direction is closer to the bit line 113 than to the word line 116.

[0059] The conductive structure 115 has two opposite ends in the y direction, at least one of the two ends protrudes from the word line 116 in the z direction, or both ends protrude from the word line 116. The portion of the conductive structure 115 protruding from the word line 116 is used as a landing portion of the second contact structure 122, coupled to the second contact structure 122, and the conductive structure 115 is connected to a low potential, such as ground or a negative voltage, to improve the coupling effect between adjacent transistors, reduce the parasitic capacitance between adjacent semiconductor pillars 111, and improve device stability.

[0060] In some embodiments, one end of the conductive structure 115 in the y direction protrudes from the word line 116, and the other portion is flush with or lower than the word line 116. The cross-sectional shape of the conductive structure 115 in the yoz plane is L-shaped, or both ends of the conductive structure 115 in the y direction protrude from the word line 116, and the middle area of ​​the two ends is flush with or lower than the word line 116. The cross-sectional shape of the conductive structure 115 in the yoz plane is convex at both ends and concave in the middle.

[0061] In some embodiments, reference Figure 3 as well as Figure 5 As shown, the conductive structure 115 crosses and overlaps with the semiconductor pillar 111 in the x direction and protrudes toward the bit line 113 in the z direction, and the distance from the bit line 113 in the z direction is smaller than the distance from the word line 116 in the z direction to the bit line 113; Figure 4 As shown, the portion of the conductive structure 115 that does not cross or overlap with the semiconductor pillar 111 in the x-direction does not protrude from the word line 116 in the z-direction. The surface of the conductive structure 115 near the bit line 113 in the z-direction may be flush with the surface of the word line 116 near the bit line 113, or lower than the surface of the word line 116. This portion is electrically isolated from the bit line 113 by a dielectric layer to reduce leakage. The conductive structure 115 extends entirely along the y-direction. The cross-sectional shape of the conductive structure 115 in the yoz plane may be a fence shape or a sawtooth shape, as shown in FIG. Figure 7 As shown, there are protrusions with gaps between the protrusions. The protrusions are the parts where the conductive structure 115 crosses and overlaps with the semiconductor pillars 111 in the x direction, and the gaps are the parts that do not cross and overlap with the semiconductor pillars 111 in the x direction. The shapes of the multiple semiconductor pillars 111 arranged along the x direction are also similar to Figure 7 The jagged, protruding portions are semiconductor pillars 111 , and the first ends of the plurality of semiconductor pillars 111 are connected without being interrupted.

[0062] In some embodiments, a dimension of a portion of the conductive structure 115 in the first direction is greater than or equal to a dimension of the word line 116 in the first direction. Figure 3 as well as Figure 5 As shown, a side surface of the conductive structure 115 close to the bit line 113 in the z direction protrudes from the bit line 113 so as to be coupled to the second contact structure 122, and a side surface of the conductive structure 115 away from the bit line 113 in the z direction may be flush with or not flush with a surface of the word line 116 away from the bit line 113, and a size in the z direction of a portion of the conductive structure 115 protruding from the word line 116 may be greater than or equal to a size of the word line 116 in the z direction. When the side surface of the portion away from the bit line 113 in the z direction is higher than the surface of the word line 116 away from the bit line 113, the size of the conductive structure 115 in the z direction may be equal to the size of the word line 116 in the z direction.

[0063] In some embodiments, the conductive structure 115 has two opposite ends in the third direction. The distance between the two ends of the conductive structure 115 and the bit line 113 in the first direction is greater than the distance between the word line 116 and the bit line 113 in the first direction. Some portions of the conductive structure 115 protrude beyond the word line 116 in the z-direction, while other portions are flush with or lower than the word line 116. The portion below the word line 116 is further away from the bit line 113 in the z-direction and is further away from the bit line 113 than the distance between the word line 116 and the bit line 113. One end of the conductive structure 115 in the y-direction protrudes beyond the word line 116, while the other portions are flush with or lower than the word line 116. The cross-sectional shape of the conductive structure 115 in the yoz plane is L-shaped. Alternatively, both ends of the conductive structure 115 in the y-direction protrude beyond the word line 116, while the middle region between the two ends is flush with or lower than the word line 116. The cross-sectional shape of the conductive structure 115 in the yoz plane is convex at both ends and concave in the middle. The cross-sectional shape of the conductive structure 115 in the yoz plane can be Figure 7 The fence or serrated shape shown.

[0064] For example, the constituent materials of the conductive structure 115 may include, but are not limited to, conductive materials such as tungsten, gold, silver, copper, chromium, nickel, titanium, aluminum, or titanium nitride.

[0065] In some embodiments, the first semiconductor structure 101 further includes a contact structure. Figure 3 The second contact structure 122 is located on one side of the conductive structure 115 in the first direction close to the bit line 113; the contact structure is coupled to at least one end of the conductive structure 115 in the third direction. Figure 2 As shown, the second contact structure 122 is located at one end of the conductive structure 115 in the y direction, and can be located at the edge of the conductive structure 115, and coupled to the conductive structure 115; the second contact structure 122 can also be located in the middle area between the two ends of the conductive structure 115 in the y direction, and coupled to the conductive structure 115. The second contact structure 122 can correspond to the portion of the conductive structure 115 protruding from the word line 116 in the z direction, such as Figure 7 The raised portion may correspond to the z direction Figure 2 As shown, the bit line 113 extending along the x direction is not provided with the third contact structure 123 for wiring. The bit line 113 serves as a virtual bit line 114. The virtual bit line 114 can be provided at the edge of the memory array. The second contact structure 122 can be provided on one side of the conductive structure 115 in the y direction. Figure 3 The dummy bit line 114 is shown to pass through the dummy bit line 114 until it is coupled to the conductive structure 115. The dummy bit line 114 can be provided at Figure 2 At any position of the middle bit line 113 , the third contact structure 123 is not disposed on the dummy bit line 114 .

[0066] In some embodiments, the first semiconductor structure 101 further includes a gate dielectric layer 132 located between the word line 116 and the semiconductor pillar 111 .

[0067] In some embodiments, the word line 116 includes a first word line 1161 and a second word line 1162, the semiconductor column 111 includes a first side and a second side relatively arranged in the second direction, and the semiconductor column 111 includes a first semiconductor column 1111 and a second semiconductor column 1112 adjacently arranged in the second direction; the first word line 1161 is located on the first side of the first semiconductor column 1111, and the second word line 1162 is located on the second side of the second semiconductor column 1112.

[0068] In some embodiments, the conductive structure 115 is located between the second side of the first semiconductor pillar 1111 and the first side of the second semiconductor pillar 1112 .

[0069] Reference Figure 5As shown, semiconductor pillars 111 are disposed on opposite sides in the x-direction. The first side may be the left side of semiconductor pillar 111, and the second side may be the right side of semiconductor pillar 111. A gate dielectric layer 132 and word lines 116 are disposed on one side of semiconductor pillar 111, while the other side may not be provided with gate dielectric layer 132 or word lines 116. Each semiconductor pillar 111 is controlled to be turned on and off by the word lines 116 on its side. A first word line 1161 is located on the left side of the first semiconductor pillar 1111, while no word line 116 is disposed on the right side of the first semiconductor pillar 1111. A second word line 1162 is located on the right side of the second semiconductor pillar 1112, while no word line 116 is disposed on the left side of the second semiconductor pillar 1112. A conductive structure 115 is located between the first semiconductor pillar 1111 and the second semiconductor pillar 1112. Two word lines 116 are disposed between two adjacent conductive structures 115, and two semiconductor pillars 111 are disposed between two adjacent conductive structures 115.

[0070] Reference Figure 5 As shown, a dielectric layer, such as a second dielectric layer 131, may be provided between the conductive structure 115 and the semiconductor pillar 111 to electrically isolate the conductive structure 115 from the semiconductor pillar 111, thereby reducing the interference of the voltage of the conductive structure 115 on the threshold voltage of the semiconductor pillar 111 and causing the threshold voltage of the semiconductor pillar 111 to shift, thereby improving device stability. The composition material of the second dielectric layer 131 may be different from or the same as that of the gate dielectric layer 132. For example, the second dielectric layer 131 includes silicon nitride. A third dielectric layer 133 (or a filling layer) is also provided between adjacent semiconductor pillars 111. The third dielectric layer 133 is used to provide support and insulation isolation between components. The composition material of the third dielectric layer 133 between adjacent word lines 116 may be the same as that of the gate dielectric layer 132, such as silicon oxide. There may be no obvious physical boundary between the gate dielectric layer 132 and the third dielectric layer 133.

[0071] In some embodiments, wordline 116 may include a conductive single-layer structure, such as tungsten. Wordline 116 may also include a conductive multi-layer structure, such as a first sub-wordline and a second sub-wordline. The first sub-wordline is located between semiconductor pillar 111 and the second sub-wordline, and the first sub-wordline is smaller in the x-direction than the second sub-wordline. The first sub-wordline is used to increase adhesion between gate dielectric layer 132 and the second sub-wordline. For example, the first sub-wordline may include titanium nitride, and the second sub-wordline may include tungsten.

[0072] In some embodiments, reference Figures 3 to 6 As shown, the first semiconductor structure 101 further includes a capacitor structure 141 located on a side of the semiconductor pillar 111 away from the bit line 113 and coupled to the second end.

[0073] Reference Figure 5As shown, the semiconductor pillar 111 may be located between the capacitor structure 141 and the bit line 113, and the electrode of the capacitor structure 141 relatively close to the semiconductor pillar 111 is coupled to the second end. A contact portion 151 may be provided between the semiconductor pillar 111 and the capacitor structure 141. The contact portion 151 is provided corresponding to the semiconductor pillar 111, and the arrangement of the contact portion 151 corresponds to the arrangement of the semiconductor pillar 111. One semiconductor pillar 111 is coupled to the capacitor structure 141 through the contact portion 151. The contact portion 151 may include, but is not limited to, conductive materials such as tungsten, gold, silver, copper, chromium, nickel, titanium, aluminum, titanium nitride, or metal silicide. The conductive portion may include a single-layer conductive structure or a multi-layer conductive structure, such as a conductive block and a connecting layer. The connecting layer is located between the conductive block and the semiconductor pillar 111. The conductive block may include tungsten, and the connecting layer may include metal silicide or titanium nitride. The connecting layer is used to increase the adhesion between the conductive block and the semiconductor pillar 111 and to reduce contact resistance.

[0074] In some embodiments, reference Figure 8 and Figure 9 As shown, the capacitor structure 141 includes a first electrode 1411 , a first dielectric layer 1412 surrounding the first electrode 1411 , and a second electrode 1413 ; the first dielectric layer 1412 is located between the first electrode 1411 and the second electrode 1413 .

[0075] Reference Figure 8 and Figure 9 As shown, the capacitor structure 141 may include a columnar structure, and the size of the end of the capacitor structure 141 away from the bit line 113 in the x-direction and / or the y-direction is equal to the size of the end of the capacitor structure 141 close to the bit line 113, or is larger than the size of the end of the capacitor structure 141 close to the bit line 113. Figure 8 In the figure, along the x-direction, the capacitor structure 141 includes: a first electrode 1411, a first dielectric layer 1412 surrounding the first electrode 1411, and a second electrode 1413; the first dielectric layer 1412 is located between the first electrode 1411 and the second electrode 1413. The first electrode 1411 can be a columnar structure, and the first dielectric layer 1412 and the second electrode 1413 are film structures surrounding the first electrode 1411. Figure 9 In the figure, along the x-direction, the capacitor structure 141 may further include a core, and a first electrode 1411, a first dielectric layer 1412, and a second electrode 1413 are arranged around the core. The core may be a columnar structure, and the first electrode 1411, the first dielectric layer 1412, and the second electrode 1413 are all film structures. The second electrode 1413 of the capacitor structure 141 may be coupled to an end of its corresponding semiconductor pillar 111 away from the bit line 113. The first electrodes 1411 of multiple capacitor structures 141 may be coupled to an interconnect structure to achieve grounding or access to other operating voltages. The interconnect structure may include Figures 3 to 6The first interconnect layer 161 is shown.

[0076] Exemplary materials for the first electrode 1411 and the second electrode 1413 may include, but are not limited to, conductive materials such as tungsten, gold, silver, platinum, copper, aluminum, titanium, or nickel. Materials for the first dielectric layer 1412 and the core may include, but are not limited to, insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0077] In some embodiments, reference Figure 10 As shown, the semiconductor device 100 further includes: a second semiconductor structure 102, the second semiconductor structure 102 including a peripheral circuit 170, located on a side of the bit line 113 away from the semiconductor pillar 111; the second semiconductor structure 102 is bonded to the first semiconductor structure 101; the bonding may include hybrid bonding.

[0078] Before bonding, the surfaces to be bonded of the first semiconductor structure 101 and the second semiconductor structure 102 respectively have a first bonding contact and a second bonding contact, which respectively lead the electrical signals of the semiconductor structures to the surfaces to be bonded. The bonding contacts may include structures such as pads and conductive plugs. The surfaces to be bonded of the first semiconductor structure 101 and the second semiconductor structure 102 are bonded, and the interface where the two surfaces to be bonded are in contact is the bonding interface. The first bonding contact and the second bonding contact are in contact and bonded at the bonding interface to realize the electrical signal interconnection between the first semiconductor structure 101 and the second semiconductor structure 102. The first bonding contact and the second bonding contact may not have a physical boundary after bonding, and can be regarded as the bonding contact 152 in the figure, which runs through the bonding interface. The portion of the bonding contact 152 located on the first semiconductor is the first bonding contact before bonding, and the portion of the bonding contact 152 located on the second semiconductor is the second bonding contact before bonding. Figure 10 The third contact structure 123 coupled to the bit line 113 is illustrated. The third contact structure 123 leads the electrical signal of the bit line 113 to the bonding interface and couples to at least one bonding contact 152. Through the bonding contact 152, the third contact structure 123 interconnects the electrical signal with the second semiconductor structure 102, for example, with the peripheral circuit 170. Due to device obstruction, the first contact structure 121 coupled to the word line 116 and the second contact structure 122 coupled to the conductive structure 115 are not shown. The word line 116 is coupled to the peripheral circuit 170 through the first contact structure 121 and the bonding contact 152. The conductive structure 115 is coupled to the peripheral circuit 170 through the second contact structure 122 and the bonding contact 152. The semiconductor device also includes a fourth contact structure 124. The fourth contact structure 124 leads the electrical signal of the first interconnect layer 161 to the bonding interface and couples to at least one bonding contact 152. Through the bonding contact 152, the third contact structure 123 is coupled to the peripheral circuit 170.

[0079] In some embodiments, the semiconductor device further includes a pad 153 and a fifth contact structure 125, which are located on a side of the first semiconductor structure 101 away from the peripheral circuit 170. The fifth contact structure 125 leads the electrical signal from the pad 153 to the bonding interface and interconnects the electrical signal with the second semiconductor structure 102 via the bonding contact 152. The pad 153 can serve as an IO interface of the semiconductor device for external power supply or external communication of the semiconductor device.

[0080] By way of example, peripheral circuitry 170 may include, but is not limited to, a sense amplifier circuit, a row decoder circuit, a column decoder circuit, and a voltage generator circuit. The sense amplifier circuit is coupled to the bit line 113 and can be configured to capture slight voltage fluctuations on the bit line 113 and locally restore the capacitor voltage of the memory cell based on the voltage fluctuations. The sense amplifier circuit may include a latch that latches the restored capacitor voltage value, allowing the information stored in the memory cell to be transferred from the capacitor to the amplifier circuit. The sense amplifier circuit may include a differential sense amplifier circuit, which is coupled to two bit lines 113 and operates using a selected bit line 113 and a complementary bit line 113 serving as a reference line to detect and amplify the voltage difference between the pair of bit lines 113. The row decoder circuit is configured to address the memory array rows and apply operating voltages to the word lines 116. The column decoder circuit is configured to address the memory array columns and apply or receive voltages to the bit line 113. The voltage generator circuit generates the required high and low voltages for each device.

[0081] In some embodiments, the second semiconductor structure 102 and the first semiconductor structure 101 are not fixed by bonding, and no bonding contact 152 may be provided between the first semiconductor structure 101 and the second semiconductor structure 102 .

[0082] According to some aspects of the embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, wherein a first semiconductor structure 101 is formed, and a semiconductor device 102 is formed. Figure 11 As shown, the method for forming the first semiconductor structure 101 includes:

[0083] forming a semiconductor column extending along a first direction, wherein the semiconductor column includes a first end and a second end oppositely disposed in the first direction;

[0084] forming a bit line on a side of the semiconductor pillar close to the first end, the bit line being coupled to the first end; the bit line extending along a second direction;

[0085] A word line extending along a third direction is formed on one side of the semiconductor pillar in the second direction; the third direction intersects the second direction, and a plane formed by the second direction and the third direction intersects the first direction;

[0086] A conductive structure is formed between two adjacent semiconductor pillars, and the conductive structure extends along the third direction; wherein a distance between a portion of the conductive structure and the bit line in the first direction is smaller than a distance between the word line and the bit line in the first direction.

[0087] In some embodiments, the semiconductor pillars 111 may be formed by etching the semiconductor layer 110 or the semiconductor substrate, and may be formed by etching once or multiple times. The etching process may include, but is not limited to, dry etching, wet etching, and any combination thereof.

[0088] In some embodiments, the method of forming the semiconductor pillar 111 includes: etching the semiconductor layer 110 to form a first trench 11 extending along the second direction; etching the semiconductor layer 110 to form a second trench 12 and a third trench 13 extending along the third direction and alternately arranged in the second direction; wherein the third trench 13, the second trench 12 and the first trench 11 divide the semiconductor layer 110 into semiconductor pillars 111, and the size of the second trench 12 in the first direction is smaller than the size of the first trench 11.

[0089] Reference Figure 12 As shown, a semiconductor layer 110 is provided, and the semiconductor layer 110 can be a semiconductor substrate or a semiconductor layer 110 on a substrate; the semiconductor layer 110 is etched to form a first trench 11 extending along the x direction, and a plurality of first trenches 11 can be arranged along the y direction, and the first trench 11 may not penetrate, or may not penetrate the semiconductor layer 110. Figure 13 As shown, a semiconductor layer 110 having a first trench 11 is etched to form second trenches 12 and third trenches 13 extending in the y-direction and arranged alternately in the x-direction. The portion of the semiconductor layer 110 between the second trenches 12 and the third trenches 13 forms a semiconductor pillar 111 extending in the z-direction. The second trenches 12 and the third trenches 13 may not penetrate the semiconductor layer 110. The depth of the third trench 13 in the z-direction may be less than or equal to the depth of the first trench 11 in the z-direction, and the depth of the second trench 12 in the z-direction may be less than the depth of the first trench 11 in the z-direction. The etching process uses a first mask layer 134 overlying the semiconductor layer 110 as an etching mask to define the trench shape. The first mask layer 134 may include silicon nitride, silicon oxynitride, or amorphous carbon, for example. The trench shapes illustrated in the figure are merely examples and are not limited to the illustrated trench shapes having a wide top and a narrow bottom.

[0090] In some embodiments, the third trench 13 and the second trench 12 can be formed successively. Figure 14 As shown, the semiconductor layer 110 having the first trench 11 is etched to form second trenches 12 extending in the y direction and arranged in the x direction, and the depth of the second trench 12 in the z direction is less than the depth of the first trench 11 in the z direction; Figure 15As shown, the second trench 12 is filled to form a sacrificial structure 135. The filling material can be an insulating material, such as silicon oxide, or a spin-on insulating medium. The cross-sectional schematic diagram of the structure after filling in the xoy plane is as follows: Figure 16 As shown, the cross-sectional diagram at DD' is as follows Figure 15 A third trench 13 is formed between two adjacent sacrificial structures 135. The third trench 13 can be formed by etching once or by etching multiple times. Figure 17 The third trench 13 is shown, and the bottom of the third trench 13 is then etched so that the third trench 13 extends in the z-direction toward the semiconductor layer 110. This makes the depth of the third trench 13 in the z-direction greater than the depth of the second trench 12 in the z-direction. In other words, the dimension of the third trench 13 in the z-direction is greater than the dimension of the sacrificial structure 135 in the second trench 12 in the z-direction. The etching mask used to etch the third trench 13 is a second mask layer 136 covering the first mask layer 134. The first mask layer 134 may include silicon nitride, and the second mask layer 136 may include silicon oxide.

[0091] In some embodiments, the method of forming the conductive structure 115 includes: etching Figure 17 The bottom of the third trench 13 makes the size of the third trench 13 in the first direction larger than the size of the second trench 12 in the first direction, that is, the size of the third trench 13 in the z direction is larger than the size of the sacrificial structure 135 in the z direction; a conductive structure 115 is formed in the third trench 13.

[0092] In some embodiments, the method of forming the conductive structure 115 includes: forming a second dielectric layer 131 on the inner wall of the third trench 13; penetrating the second dielectric layer 131 at the bottom of the third trench 13, and etching the semiconductor layer 110 below the bottom of the third trench 13 so that the size of the third trench 13 in the first direction is larger than the size of the second trench 12 in the first direction; after penetrating the second dielectric layer 131, forming the conductive structure 115 in the third trench 13.

[0093] Reference Figure 18 As shown, in Figure 17 A second dielectric layer 131 is formed on the sidewalls and bottom of the third trench 13; Figure 19 As shown, the second dielectric layer 131 at the bottom of the third trench 13 is penetrated along the z direction, and the semiconductor layer 110 below the bottom of the third trench 13 is etched, but the semiconductor layer 110 may not be penetrated, so that the size of the third trench 13 in the z direction is larger than the size of the sacrificial structure 135 in the z direction; Figure 19 A portion of the sidewall of the third trench 13 shown in FIG is covered with the second dielectric layer 131, and the sidewall and bottom of the third trench 13 below the second dielectric layer 131 are exposed to the semiconductor layer 110. Figure 20 As shown, in Figure 19The third trench 13 is filled with a conductive material, and the conductive material can fill the third trench 13. The conductive material at the top of the third trench 13 is etched to form a conductive structure 115, so that the upper surface of the conductive structure 115 is lower than the upper surface of the sacrificial structure 135, so as to increase the distance between the contact portion 151 subsequently formed between the semiconductor pillar 111 and the capacitor structure 141 and the conductive structure 115 in the z direction, thereby reducing leakage between the conductive structure 115 and the contact portion 151.

[0094] Exemplarily, the formation process of the second dielectric layer 131 and the conductive structure 115 may include a deposition process, and the deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

[0095] In some embodiments, the method of forming the first semiconductor structure 101 further includes: forming a gate dielectric layer 132 and a word line 116 on the sidewalls of the second trench 12, wherein the word lines 116 on the two sidewalls of the second trench 12 in the second direction are respectively a first word line 1161 and a second word line 1162.

[0096] Reference Figure 21 As shown, etching removes Figure 20 The sacrificial structure 135 releases the space of the second trench 12; Figure 22 As shown, a gate dielectric layer 132 and a word line 116 are sequentially formed on the sidewalls of the second trench 12. The word line 116 on the left sidewall of the second trench 12 is a first word line, and the word line 116 on the right sidewall of the second trench 12 is a second word line. Exemplarily, a first dielectric material layer is formed on the sidewalls and bottom of the second trench 12, a portion of the first dielectric material layer on the sidewalls of the second trench 12 is etched, and the first dielectric layer 1412 on a portion of the sidewalls near the bottom of the second trench 12 is retained. The first dielectric layer 1412 on the bottom of the second trench 12 is retained to form a buffer layer 112; a gate dielectric layer 132 is formed on both sidewalls of the second trench 12, and a conductive material layer is formed on the gate dielectric layer 132. The conductive material layer may cover the sidewalls and bottom of the second trench 12. The conductive material layer on the bottom of the second trench 12 is etched away to form the word line 116. Figure 22 The illustrated word line 116 may be located in the middle of the second trench 12, above the buffer layer 112. The remaining space within the second trench 12 and the remaining space in the third trench 13 on the conductive structure 115 are filled with an insulating material to electrically isolate the word line 116 and provide support. The filling process may include deposition or spin coating; the filling material may include silicon oxide, and the buffer layer 112 may include silicon nitride.

[0097] In some embodiments, reference Figure 23 As shown, a connected ring-shaped word line 116 is formed in the second trench 12, and openings 14 can be formed at both ends of the word line 116 along the y direction and pass through the word line 116 along the z direction to divide the ring-shaped word line 116 into two independent word lines 116, such as a first word line 1161 and a second word line 1162. The first word line 1161 and the second word line 1162 can independently apply voltage to control the opening and closing of the semiconductor column 111. Figure 23 One of the annular word lines 116 may be provided with two openings 14, and the two openings 14 are respectively located on different long sides extending along the y-direction; one opening 14 is located at the left end of the word line 116 and passes through one long side of the annular word line 116, and the other opening 14 is located at the right end of the word line 116 and passes through the other long side of the annular word line 116.

[0098] In some embodiments, reference Figure 24 As shown, the method for forming the first semiconductor structure 101 further includes: forming a capacitor structure 141 on a side of the semiconductor pillar 111 close to the second end, wherein the capacitor structure 141 is coupled to the second end.

[0099] The method of forming the capacitor structure 141 may include forming a capacitor hole penetrating the dielectric layer, the capacitor hole exposing the second end of the semiconductor column 111, forming a second electrode 1413, a first dielectric layer 1412 and a first electrode 1411 in the capacitor hole, and the second electrode 1413 is coupled to the second end of the semiconductor column 111.

[0100] In some embodiments, reference Figure 8 and Figure 9 As shown, the capacitor structure 141 includes: a first electrode 1411, a first dielectric layer 1412 surrounding the first electrode 1411, and a second electrode 1413; the first dielectric layer 1412 is located between the first electrode 1411 and the second electrode 1413. In some embodiments, referring to Figure 24 As shown, a first interconnection layer 161 is formed in the first semiconductor structure 101 , and the first electrodes 1411 of the plurality of capacitor structures 141 can be coupled to the first interconnection layer 161 to achieve grounding or access to other operating voltages.

[0101] In some embodiments, the method of forming the first semiconductor structure 101 further includes: filling the second trench 12 and the first trench 11 to form a third dielectric layer 133, forming the conductive structure 115 between adjacent filled second trenches 12; and thinning the semiconductor layer 110 to expose the third dielectric layer 133.

[0102] The third dielectric layer 133 may include a filler Figure 12 The portion of the first groove 11, and the Figure 22The portion of the second trench 12 after the word line 116 is filled is shown. The third dielectric layer 133 may include silicon oxide, and the filling process may include deposition or spin coating. A carrier wafer 20 is set on the side of the capacitor structure 141 away from the semiconductor pillar 111. The carrier wafer 20 is used as a support to thin the semiconductor layer 110 to expose the third dielectric layer 133. The cross-sectional diagram of the semiconductor structure after thinning in the xoy plane is shown as follows Figure 25 As shown, the semiconductor layer 110 is not interrupted when the semiconductor pillar 111 is formed, and the remaining portion of the semiconductor layer 110 is connected to the first end of the semiconductor pillar 111. The remaining semiconductor layer 110 can be metallized to form a bit line 113, or the remaining portion of the semiconductor layer 110 can be heavily doped to form the bit line 113, or a conductive line can be formed on the remaining semiconductor layer 110 as the bit line 113. Figure 25 The third dielectric layer 133 exposed between the semiconductor layers 110 is shown, and the third dielectric layer 133 blocked by the semiconductor layer 110 in the z direction is not shown. The third dielectric layer 133 etched away is a portion similar to EE' that is not blocked by the semiconductor layer 110. Figure 26 Shown Figure 25 The cross-sectional view of the structure at EE' is shown in FIG. 1 , and the carrier wafer 20 can be as shown in FIG. Figure 26 shown.

[0103] In some embodiments, reference Figure 27 As shown, the method for forming the first semiconductor structure 101 also includes: removing a portion of the third dielectric layer 133 covering the conductive structure 115 to expose one side of the conductive structure 115 in the first direction; etching a portion of the conductive structure 115 to form a notch to reduce the size of the portion of the conductive structure 115 in the first direction.

[0104] Removal Figure 26 The third dielectric layer 133 exposed between the semiconductor layers 110 and the third dielectric layer 133 blocked by the semiconductor layer 110 in the z direction are not etched away to expose the conductive structure 115; the conductive structure 115 is in the z direction. Figure 25 The intersection of the third dielectric layer 133 is Figure 27 As shown in FIG, the conductive structure 115 is in the z direction. Figure 25 The intersection of the semiconductor layer 110 is not Figure 27 Revealed in.

[0105] A portion of the exposed conductive structure 115 is etched to remove at least a portion of the conductive structure 115 to form a notch. The notch can be formed in any portion of the exposed conductive structure 115 .

[0106] In some embodiments, the conductive structure 115 has two opposite ends in the third direction; when the gap is formed, at least one of the two ends is retained.

[0107] Reference Figure 28 As shown, the conductive structure 115 has two opposite ends in the y direction. For example, at FF', the semiconductor layer 110 in this part is not provided with a bit line 113 or a virtual bit line 114 without power supply is provided. The conductive structure 115 in this part can be used to set a contact structure. The contact structure leads the electrical signal of the conductive structure 115, so that the conductive structure 115 between adjacent semiconductor pillars 111 is connected to a low potential, such as ground or negative voltage, to improve the coupling effect between adjacent transistors, reduce the parasitic capacitance between adjacent semiconductor pillars 111, and improve the stability of the device. The word line 116 is connected in the z direction. Figure 28 The buffer layer 112 is blocked and not shown, and the extending direction of the word line 116 is indicated by the buffer layer 112 . Figure 28 HH' is the middle position of the two ends of the conductive structure 115 in the y direction, and HH' is the position where the conductive structure 115 does not cross the semiconductor layer 110. Figure 29 As shown, the conductive structure 115 at HH' is etched to reduce the size of the conductive structure 115 in the z direction to form a gap to reduce leakage; Figure 30 As shown, the conductive structure 115 at FF' is covered by the semiconductor layer 110 and is not etched. The size of this portion of the conductive structure 115 in the z direction is not reduced, which facilitates the landing of the contact structure, reduces the size of the contact structure in the z direction, and reduces the difficulty of manufacturing. Figure 28 At HH' shown, any portion of the conductive structure 115 that does not intersect the semiconductor layer 110 can be etched to reduce leakage; similarly, at FF', any portion of the conductive structure 115 that intersects the semiconductor layer 110 is not etched, and the semiconductor layer 110 corresponding to this portion may not be provided with a bit line 113 or a virtual bit line 114 that does not provide a lead or power supply.

[0108] In some embodiments, the method of forming the first semiconductor structure 101 further includes forming a contact structure on a side of the conductive structure 115 close to the bit line 113 along the first direction, wherein the contact structure is coupled to at least one end of the conductive structure 115 in the third direction.

[0109] In some embodiments, the semiconductor layer 110 is made of silicon, and the method of forming the bit line 113 includes forming a metal silicide layer by thinning the remaining portion of the semiconductor layer 110 extending along the second direction to form the bit line 113 .

[0110] exist Figure 30 The second contact structure 122 is formed on the conductive structure 115. The second contact structure 122 can be as follows Figure 3 In the example shown, the second contact structure 122 can penetrate the semiconductor layer 110 along the z direction and couple to the conductive structure 115. Figure 25The thinning of the semiconductor layer 110 to expose the third dielectric layer 133 may be formed after etching the conductive structure 115 and before forming the second contact structure 122 , or after forming the second contact structure 122 .

[0111] based on Figure 28 Bit lines 113 are formed in the semiconductor layer 110 where the second contact structure 122 is not provided. A metal layer is deposited on a portion of the semiconductor layer 110 away from the semiconductor pillars 111. The metal layer and the semiconductor layer 110 are heat treated to form a metal-semiconductor compound layer to serve as the bit lines 113. For example, the semiconductor layer 110 may include silicon, and the bit lines 113 may include metal silicides such as titanium silicide, zirconium silicide, tantalum silicide, tungsten silicide, or nickel silicide. For the semiconductor layer 110 where the second contact structure 122 is provided, the bit lines 113 may not be provided, or dummy bit lines 114 may be formed, without leads. Figure 2 The virtual bit line 114 is located at both ends of the y direction, such as AA'; after the bit line 113 is formed at the middle position of the two ends of the y direction, such as CC', a third contact structure 123 is formed to couple with the bit line 113. Figure 2 As shown, a first contact structure 121 is coupled to the word line 116 .

[0112] In some embodiments, reference Figure 10 As shown, the method for fabricating a semiconductor device further includes providing a second semiconductor structure 102; and bonding the second semiconductor structure 102 to the first semiconductor structure 101 on a side of the bit line 113 away from the bit line 113. The second semiconductor structure 102 includes a peripheral circuit 170, which is coupled to at least the capacitor structure 141, the bit line 113, and the word line 116. The bonding process may include hybrid bonding.

[0113] Before bonding, the surfaces to be bonded of the first semiconductor structure 101 and the second semiconductor structure 102 respectively form a first bonding contact and a second bonding contact, respectively, to lead the electrical signals of the semiconductor structures to the surfaces to be bonded, and the bonding contacts may include structures such as pads and conductive plugs. The surfaces to be bonded of the first semiconductor structure 101 and the second semiconductor structure 102 are bonded, and the interface where the two surfaces to be bonded are in contact is the bonding interface. The first bonding contact and the second bonding contact are in contact and bonded at the bonding interface to realize the electrical signal interconnection between the first semiconductor structure 101 and the second semiconductor structure 102. The first bonding contact and the second bonding contact may not have a physical boundary after bonding, and can be regarded as the bonding contact 152 in the figure, which runs through the bonding interface. The portion of the bonding contact 152 located on the first semiconductor is the first bonding contact before bonding, and the portion of the bonding contact 152 located on the second semiconductor is the second bonding contact before bonding. After the first semiconductor structure 101 and the second semiconductor structure 102 are bonded, Figure 30 The carrier wafer 20 is shown removed.

[0114] In some embodiments, a fourth contact structure 124 coupled to the first interconnect layer 161 is further formed. Furthermore, a pad 153 and a fifth contact structure 125 are further formed on a side of the first semiconductor structure 101 away from the peripheral circuit 170. The pad 153 can serve as an I / O interface for the semiconductor device, providing external power or communication. The first, second, third, fourth, and fifth contact structures 121, 122, 123, 124, and 125 can be coupled to the peripheral circuit 170 via bonding contacts 152.

[0115] According to some aspects of the embodiments of the present disclosure, there is provided a memory system including: a memory device including a semiconductor device; and a memory controller coupled to the memory device and controlling the memory device.

[0116] The semiconductor device according to the embodiment of the present disclosure can be Figures 2 to 6 、 Figure 10 As shown, the semiconductor device can be used as a DRAM, or at least a part of a DRAM. Figure 31 As shown, an embodiment of the present disclosure provides a memory system 202 , including a memory device 204 including the above-mentioned semiconductor device; and a memory controller 206 coupled to the memory device 204 and controlling the memory device 204 .

[0117] Reference Figure 31As shown, the embodiment of the present disclosure provides a system 200 including a host 208. The system 200 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 31 As shown in FIG, system 200 may include a host 208 and a memory system 202, wherein the memory system 202 has one or more memory devices 204 and a memory controller 206. The host 208 may be a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 208 may be configured to send data to the memory device 204 or receive data from the memory device 204.

[0118] According to some embodiments, the memory controller 206 is coupled to the memory device 204 and the host 208 and is configured to control the memory device 204 to perform reads, writes, or refreshes. The memory controller 206 can manage the data stored in the memory device 204 and communicate with the host 208. The memory device 204 includes a DRAM, or a package structure formed by stacking multiple DRAMs, such as an HBM or HMC package structure. The memory system 202 can serve as the memory of the host 208 in the system 200 or as a cache for the system 200. In some specific examples, the memory system 202 can be used as an auxiliary in a solid-state drive, which can improve the read and write performance of the solid-state drive. Currently, high-end solid-state drive products often choose to embed DRAM to improve product performance and random read and write speeds. For example, when writing files, especially small files, the small files are processed by DRAM and then stored in flash memory, making the solid-state drive storage more efficient and faster. Flash includes non-volatile memory, including but not limited to 2D NAND memory or 3D NAND memory.

[0119] In other embodiments, referring to Figure 32 As shown, system 200 may include only a host 208 and a memory device 204 coupled thereto. A controller for controlling memory device 204 may be located within host 208, such as a memory controller integrated within a central processing unit (CPU), or a southbridge or northbridge chip integrated into the motherboard of system 200. Memory device 204 may include, but is not limited to, double data rate synchronous dynamic random access memory (SDRAM) using the DDR4 or DDR5 memory specifications, and low power double data rate synchronous dynamic random access memory (LPDDR5) memory specifications.

[0120] In some embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are directly coupled or indirectly coupled to each other. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments without conflict.

[0121] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: A first semiconductor structure is included, wherein the first semiconductor structure includes: a semiconductor column extending along a first direction, the semiconductor column comprising a first end and a second end oppositely disposed in the first direction; a bit line located on a side of the semiconductor pillar close to the first end and coupled to the first end; the bit line extends along a second direction; a word line located on one side of the semiconductor pillar in the second direction, the word line extending along a third direction; the third direction intersects the second direction, and a plane formed by the second direction and the third direction intersects the first direction; A conductive structure is located between two adjacent semiconductor pillars, and the conductive structure extends along the third direction; a distance between a portion of the conductive structure and the bit line in the first direction is smaller than a distance between the word line and the bit line in the first direction.

2. The semiconductor device according to claim 1, wherein At least one end of the conductive structure in the third direction has a distance from the bit line in the first direction that is smaller than a distance from the word line to the bit line in the first direction.

3. The semiconductor device according to claim 1, wherein A dimension of a portion of the conductive structure in the first direction is greater than or equal to a dimension of the word line in the first direction.

4. The semiconductor device according to claim 1, wherein The conductive structure has two opposite ends in the third direction, and a distance between the two ends of the conductive structure and the bit line in the first direction is greater than a distance between the word line and the bit line in the first direction.

5. The semiconductor device according to claim 2, wherein The first semiconductor structure further includes: A contact structure is located on a side of the conductive structure close to the bit line in the first direction; the contact structure is coupled to at least one end of the conductive structure in the third direction. The semiconductor device according to claim 1 , wherein: The semiconductor pillar is made of silicon, and the bit line is made of metal silicide.

7. The semiconductor device according to claim 1, wherein The first semiconductor structure further includes: The gate dielectric layer is located between the word line and the semiconductor column.

8. The semiconductor device according to claim 1, wherein The word line includes a first word line and a second word line, the semiconductor pillar includes a first side and a second side arranged opposite to each other in the second direction, and the semiconductor pillar includes a first semiconductor pillar and a second semiconductor pillar arranged adjacent to each other in the second direction; the first word line is located on the first side of the first semiconductor pillar, and the second word line is located on the second side of the second semiconductor pillar.

9. The semiconductor device according to claim 8, wherein The conductive structure is located between the second side of the first semiconductor pillar and the first side of the second semiconductor pillar.

10. The semiconductor device according to claim 1, wherein The first semiconductor structure further includes: The capacitor structure is located at a side of the semiconductor column away from the bit line and is coupled to the second end.

11. The semiconductor device according to claim 10, wherein: The capacitor structure includes: A first electrode, a first dielectric layer surrounding the first electrode, and a second electrode; the first dielectric layer is located between the first electrode and the second electrode.

12. The semiconductor device according to claim 1, wherein The semiconductor device further includes: The second semiconductor structure includes a peripheral circuit and is located on a side of the bit line away from the semiconductor column; the second semiconductor structure is bonded to the first semiconductor structure.

13. A method for manufacturing a semiconductor device, characterized in that: A first semiconductor structure is formed, wherein the method of forming the first semiconductor structure includes: forming a semiconductor column extending along a first direction, wherein the semiconductor column includes a first end and a second end oppositely disposed in the first direction; forming a bit line on a side of the semiconductor pillar close to the first end, the bit line being coupled to the first end; the bit line extending along a second direction; A word line extending along a third direction is formed on one side of the semiconductor pillar in the second direction; the third direction intersects the second direction, and a plane formed by the second direction and the third direction intersects the first direction; A conductive structure is formed between two adjacent semiconductor pillars, and the conductive structure extends along the third direction; wherein a distance between a portion of the conductive structure and the bit line in the first direction is smaller than a distance between the word line and the bit line in the first direction.

14. The manufacturing method according to claim 13, characterized in that: The method of forming the semiconductor pillar includes: The semiconductor layer is etched to form a first groove extending along the second direction; the semiconductor layer is etched to form a second groove and a third groove extending along the third direction and alternately arranged in the second direction; wherein the second groove and the first groove divide the semiconductor layer into the semiconductor pillars, and the size of the second groove in the first direction is smaller than the size of the first groove.

15. The manufacturing method according to claim 14, characterized in that: The method of forming the conductive structure includes: etching a bottom of the third trench so that a size of the third trench in the first direction is larger than a size of the second trench in the first direction; The conductive structure is formed in the third trench.

16. The manufacturing method according to claim 14, characterized in that: The method of forming the conductive structure includes: forming a second dielectric layer on the inner wall of the third trench; penetrating the second dielectric layer at the bottom of the third trench and etching the semiconductor layer below the bottom of the third trench so that the dimension of the third trench in the first direction is larger than the dimension of the second trench in the first direction; After penetrating the second dielectric layer, the conductive structure is formed in the third trench.

17. The production method according to claim 15 or 16, characterized in that: The method of forming the first semiconductor structure further includes: A gate dielectric layer and a word line are formed on the sidewalls of the second trench, wherein the word lines on the two sidewalls of the second trench in the second direction are respectively a first word line and a second word line.

18. The manufacturing method according to claim 17, characterized in that: The method of forming the first semiconductor structure further includes: A capacitor structure is formed on one side of the semiconductor column close to the second end, and the capacitor structure is coupled to the second end.

19. The manufacturing method according to claim 18, characterized in that: The capacitor structure includes: A first electrode, a first dielectric layer surrounding the first electrode, and a second electrode; the first dielectric layer is located between the first electrode and the second electrode.

20. The manufacturing method according to claim 17, characterized in that: The method of forming the first semiconductor structure further includes: Filling the second trenches and the first trenches to form a third dielectric layer, and forming the conductive structure between adjacent filled second trenches; The semiconductor layer is thinned to expose the third dielectric layer.

21. The manufacturing method according to claim 20, characterized in that: The method of forming the first semiconductor structure further includes: removing a portion of the third dielectric layer covering the conductive structure, to expose one side of the conductive structure in the first direction; A portion of the conductive structure is etched to form a notch, so as to reduce a size of the portion of the conductive structure in the first direction.

22. The manufacturing method according to claim 21, characterized in that: The conductive structure has two opposite ends in the third direction; when the gap is formed, at least one of the two ends is retained.

23. The manufacturing method according to claim 22, characterized in that: The method of forming the first semiconductor structure further includes: A contact structure is formed on a side of the conductive structure close to the bit line along the first direction, and the contact structure is coupled to at least one end of the conductive structure in the third direction.

24. The manufacturing method according to claim 20, characterized in that: The semiconductor layer comprises silicon, and the method for forming the bit line comprises: A metal silicide layer is formed based on thinning the remaining portion of the semiconductor layer extending along the second direction to form the bit line.

25. The manufacturing method according to claim 24, characterized in that: The method for manufacturing the semiconductor device further includes: A second semiconductor structure is provided; and the second semiconductor structure and the first semiconductor structure are bonded on a side of the bit line away from the bit line.

26. A memory system, characterized in that: include: A memory device comprising the semiconductor device according to any one of claims 1 to 12; as well as A memory controller is coupled to the memory device and controls the memory device.

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