Semiconductor structure with dielectric liner and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate; a bit line structure disposed over the substrate; a plurality of capacitor contact structures disposed adjacent to the bit line structure; a plurality of dielectric pads disposed in the capacitor contact structures, where each dielectric pad surrounds at least a portion of a corresponding capacitor contact structure; and a plurality of landing pads, each of which is disposed to partially cover an upper surface and a sidewall of the corresponding capacitor contact structure. The substrate comprises an isolation layer, a plurality of active areas are defined by the isolation layer, and a plurality of source electrode areas and drain electrode areas are arranged in the active areas.

Description

Technical Field

[0001] This application claims priority to U.S. patent application No. 18 / 596,967 (i.e., the priority date is "March 6, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor structure and a method for preparing the semiconductor structure, and more particularly to a semiconductor structure having a dielectric liner and a method for preparing the semiconductor structure. Background Art

[0003] Semiconductor structures are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor structures are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers onto a semiconductor substrate. Microlithography is then used to pattern these various material layers to form circuit components and devices on the substrate. As the semiconductor industry advances to advanced technology process nodes, pursuing greater device density, higher performance, and lower costs, precise control of microlithography across a wafer becomes challenging, limiting product performance and yield.

[0004] The above description of “prior art” only provides background technology, does not admit that the above description of “prior art” reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the Invention

[0005] One embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; a bitline structure disposed above the substrate; a plurality of capacitor contact structures disposed adjacent to the bitline structure; a plurality of dielectric liners disposed within the capacitor contact structures, wherein each dielectric liner surrounds at least a portion of a corresponding capacitor contact structure; and a plurality of landing pads disposed to partially cover a top surface and a sidewall of the corresponding capacitor contact structure. The substrate includes an isolation layer defining a plurality of active regions, and a plurality of source and drain regions disposed within the active regions.

[0006] Another embodiment of the present disclosure provides a method for fabricating a semiconductor structure. The method includes providing a substrate; forming a bit line structure on the substrate; forming a capacitor contact structure adjacent to the bit line structure, wherein the capacitor contact structure protrudes from the substrate; recessing an upper surface of the bit line structure; and forming a landing pad layer to partially cover an upper surface of the capacitor contact structure and partially cover a sidewall of the capacitor contact structure.

[0007] Another embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a polysilicon layer having a first surface and a second surface opposite the first surface; a substrate disposed on the second surface of the polysilicon layer; a plurality of bitline structures disposed on the substrate; and a spacer structure disposed on each lateral sidewall of the bitline structure. In a cross-sectional view, the polysilicon layer includes a pair of dielectric liners disposed in the polysilicon layer and on the lateral sidewalls of the spacer structure, wherein the dielectric liners are separated from each other and the paired dielectric liners face each other.

[0008] Yet another embodiment of the present disclosure provides a method for fabricating a semiconductor structure. The method includes receiving a substrate; forming a bit line structure on an upper surface of the substrate; forming a gap substructure on the bit line structure, wherein the gap substructure includes a sacrificial layer sandwiched between a first dielectric layer and a second dielectric layer; forming a polysilicon layer above the upper surface of the substrate and forming a pair of dielectric liners in the polysilicon layer, wherein the polysilicon layer has a first surface and a second surface opposite to the first surface; removing the sacrificial layer to form a gap between the first dielectric layer and the second dielectric layer; reducing a width of the gap; and forming a sealing layer to seal the gap.

[0009] In summary, the present application discloses a method for fabricating a semiconductor structure and a semiconductor structure thereof. The presence of a dielectric liner in the semiconductor structure prevents storage leakage from the bit line structure to the polysilicon layer and can protect the accuracy of data stored in the bit line structure.

[0010] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used quite easily to modify or design other structures or processes to achieve the same purposes as those of the present disclosure. It should also be understood by those skilled in the art to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] A more complete understanding of the present disclosure can be obtained by referring to the detailed description and claims.The present disclosure should also be understood to be associated with the reference numerals of the drawings, which represent similar elements throughout the description.

[0012] Figure 1 is a schematic cross-sectional view illustrating a semiconductor structure according to some embodiments of the present disclosure.

[0013] Figure 21 is a flow chart illustrating a method for preparing a semiconductor structure according to some embodiments of the present disclosure.

[0014] Figures 3 to 29 is a schematic cross-sectional view illustrating an intermediate stage in forming a semiconductor structure according to some embodiments of the present disclosure.

[0015] Figure 30 is a schematic cross-sectional view illustrating a semiconductor structure according to an alternative embodiment of the present disclosure.

[0016] Figure 31 is a flow chart illustrating a method for fabricating a semiconductor structure according to an alternative embodiment of the present disclosure.

[0017] Figure 32 is a schematic cross-sectional view illustrating a semiconductor structure according to an alternative embodiment of the present disclosure.

[0018] Figure 33 is a flow chart illustrating a method for fabricating a semiconductor structure according to an alternative embodiment of the present disclosure.

[0019] Figures 34 to 36 is a cross-sectional schematic diagram illustrating an alternative embodiment of the present disclosure for manufacturing Figure 32 The intermediate stage of semiconductors.

[0020] The description of the accompanying drawings is as follows:

[0021] 1A: Semiconductor Structure

[0022] 1B: Semiconductor Structure

[0023] 10: Preparation method

[0024] 11: Base

[0025] 11': Base

[0026] 11a: Surface

[0027] 12: Bit line structure

[0028] 13': Gap substructure

[0029] 14': Polysilicon layer

[0030] 15: Metal layer

[0031] 16': Adhesive layer

[0032] 17': Landing Pad

[0033] 18: Gap sublayer

[0034] 19: Sealing layer

[0035] 21: First bit line structure

[0036] 22: Second bit line structure

[0037] 31: First interstitial

[0038] 32: Second gap

[0039] 33: First nitride layer

[0040] 34: Oxide layer

[0041] 35: Second nitride layer

[0042] 36: Air Gap

[0043] 37: Sidewall

[0044] 38: Sidewall

[0045] 39: Multi-layer

[0046] 41: Polysilicon layer

[0047] 42: Dielectric liner

[0048] 43: Sacrificial layer

[0049] 44: Fourth dielectric layer

[0050] 45: Second polysilicon layer

[0051] 51: Landing Pad

[0052] 52: Metal layer

[0053] 53: Opening

[0054] 61: Depression

[0055] 101: Base

[0056] 102: Patterned Mask

[0057] 102': Photoresist

[0058] 103: Isolation layer

[0059] 104: Patterned Mask

[0060] 104': Photoresist

[0061] 105: Active Zone

[0062] 107-1: Source region

[0063] 107-3: Drain region

[0064] 131': first dielectric layer

[0065] 132': Sacrificial layer

[0066] 133: Dielectric layer

[0067] 133': Second dielectric layer

[0068] 133a: Gap subsection

[0069] 133b: Gap subsection

[0070] 134: Gap

[0071] 135: Gap

[0072] 141': Dielectric liner

[0073] 191: Linear layer

[0074] 192: Plane layer

[0075] 211: First conductive layer

[0076] 211a: Upper surface

[0077] 212: Second conductive layer

[0078] 213: First dielectric layer

[0079] 215: Upper surface

[0080] 216: Lower surface

[0081] 217: Sidewall

[0082] 221: Second dielectric layer

[0083] 221a: Upper surface

[0084] 222: The third conductive layer

[0085] 223: The third dielectric layer

[0086] 225: Upper surface

[0087] 226: Lower surface

[0088] 227: Sidewall

[0089] 261: Upper surface

[0090] 262: Upper surface

[0091] 301: Bit line structure

[0092] 303: Bit line conductive layer

[0093] 305: Bit line intermediate conductive layer

[0094] 307: conductive layer on the bit line

[0095] 309: Bit line mask layer

[0096] 309TS: upper surface

[0097] 311: Upper surface

[0098] 311BS: bottom surface

[0099] 312: Bit line contact

[0100] 313: Upper part

[0101] 313BS: bottom surface

[0102] 314: Bitline spacer

[0103] 321: Upper surface

[0104] 341: Upper surface

[0105] 401: Capacitor contact structure

[0106] 402: Dielectric liner

[0107] 403: Capacitor contacts the lower conductive layer

[0108] 403SW: Sidewall

[0109] 405: Capacitor contacts the middle conductive layer

[0110] 405SW: Sidewall

[0111] 407: Capacitor contacts the upper conductive layer

[0112] 407SW: Sidewall

[0113] 407TS: upper surface

[0114] 412: Partial

[0115] 413: Upper surface

[0116] 415: Sidewall

[0117] 417: Part

[0118] 418: Upper surface

[0119] 419: Upper surface

[0120] 421: Upper surface

[0121] 422: Lower surface

[0122] 431: Upper surface

[0123] 432: Part

[0124] 453: Upper surface

[0125] 501: Landing pad

[0126] 511: Neck

[0127] 521: Upper surface

[0128] 522: Upper surface

[0129] B14': Second surface

[0130] BS: Lower surface

[0131] BS1: lateral sidewall

[0132] BS2: lateral sidewall

[0133] F11: Top surface

[0134] F14': First surface

[0135] H: Height

[0136] H1: Height

[0137] H2: Height

[0138] H3: Height

[0139] H4: Height

[0140] H5: Height

[0141] H6: Height

[0142] H7: Height

[0143] M10: Preparation Method

[0144] O101: Steps

[0145] O103: Steps

[0146] O105: Steps

[0147] O107: Steps

[0148] O109: Steps

[0149] O111: Steps

[0150] O113: Steps

[0151] O115: Steps

[0152] R1: recessed part

[0153] S1: Preparation method (lateral sidewall)

[0154] S11: Steps

[0155] S13: Steps

[0156] S15: Steps

[0157] S17: Steps

[0158] S19: Steps

[0159] S101: Steps

[0160] S102: Step

[0161] S103: Steps

[0162] S104: Steps

[0163] S105: Steps

[0164] S106: Steps

[0165] S107: Steps

[0166] S108: Steps

[0167] S109: Steps

[0168] S110: Steps

[0169] S111: Steps

[0170] S151: Steps

[0171] SW1: lateral sidewall

[0172] SW2: lateral sidewall

[0173] T: thickness

[0174] T131': thickness

[0175] T133a': thickness

[0176] T133b': thickness

[0177] T134: Width

[0178] T135: Width

[0179] TS: Top surface

[0180] W1: width

[0181] W2: width DETAILED DESCRIPTION

[0182] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, the description of a first component formed on a second component may include embodiments in which the first and second components are in direct contact, and may also include embodiments in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is for simplicity and clarity, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0183] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive concept of the present disclosure, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0184] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0185] As the semiconductor industry has advanced to advanced technology process nodes in pursuit of greater device density, it has achieved advanced lithographic precision. To further reduce device size, device size and the distances between different devices must be proportionally reduced. However, as device size and the distances between different devices decrease, the challenge of precisely controlling these sizes and distances arises. For example, after an etching operation, a landing pad may be disconnected by a sharp corner of a bitline structure.

[0186] Figure 11 is a schematic cross-sectional view illustrating a semiconductor structure according to some embodiments of the present disclosure. The semiconductor structure may include a substrate 11, a first bit line structure 21 disposed above the substrate 11, a second bit line structure 22 disposed above the substrate 11, a polysilicon layer 41 disposed above the substrate 11 and surrounded by the first bit line structure 21 and the second bit line structure 22, a dielectric liner 42 surrounding at least a portion 417 of the polysilicon layer 41, and a landing pad 51 disposed above the polysilicon layer 41, the dielectric liner 42, and the second bit line structure 22.

[0187] In some embodiments, substrate 11 may have a multilayer structure, or substrate 11 may include a multilayer compound semiconductor structure. In some embodiments, substrate 11 includes a semiconductor structure, an electronic component, an electronic element, or a combination thereof. In some embodiments, substrate 11 includes a transistor or a functional unit of a transistor. In some embodiments, substrate 11 includes active components, passive components, and / or conductive components. Active components may include memory chips (e.g., dynamic random access memory (DRAM) chips, static random access memory (SRAM) chips, etc.), power management chips (e.g., power management integrated circuit (PMIC) chips), logic chips (e.g., system-on-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microcontroller, etc.), radio frequency (RF) chips, sensor chips, microelectromechanical system (MEMS) chips, signal processing chips (e.g., digital signal processing (DSP) chips), front-end chips (e.g., analog front-end (AFE) chips), or other active components. Passive components may include capacitors, resistors, inductors, fuses, or other passive components. The conductive elements may include metal lines, metal islands, conductive vias, contacts, or other conductive elements.

[0188] The active components, passive components, and / or conductive components described above can be formed in and / or on a semiconductor substrate. The semiconductor substrate can be a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The semiconductor substrate can include an elemental semiconductor including silicon or germanium in single crystal, polycrystalline, or amorphous form; a compound semiconductor material including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate can be a SiGe alloy having a gradient SiGe feature, wherein the Si and Ge composition changes from one ratio at one location of the gradient SiGe feature to another ratio at another location. In some embodiments, the SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy can be mechanically strained by another material in contact with the SiGe alloy.

[0189] The first cell line structure 21 includes a first conductive layer 211, a second conductive layer 212 disposed over the first conductive layer 211, and a first dielectric layer 213 disposed over the second conductive layer 212. In some embodiments, a height of the first dielectric layer 213 is greater than a height H3 of the second conductive layer 212. In some embodiments, a height of the second conductive layer 212 is greater than a height H1 of the first conductive layer 211. In some embodiments, the first conductive layer 211 comprises aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), titanium silicon nitride (TiSiN), or other suitable materials. In some embodiments, the first conductive layer 211 comprises tungsten (W). In some embodiments, the second conductive layer 212 includes a material that is different from a material of the first conductive layer 211. In some embodiments, the first dielectric layer 213 includes silicon nitride, metal nitride, or a combination thereof.

[0190] The second bit line structure 22 includes a second dielectric layer 221, a third conductive layer 222 disposed over the second dielectric layer 221, and a third dielectric layer 223 disposed over the third conductive layer 222. In some embodiments, a height of the third dielectric layer 223 is greater than a height H4 of the third conductive layer 222. In some embodiments, the height H4 of the third conductive layer 222 is greater than a height H2 of the second dielectric layer 221. In some embodiments, the second dielectric layer 221 comprises silicon nitride, metal nitride, or a combination thereof. In some embodiments, the third dielectric layer 223 comprises a nitride material that is the same as a nitride material of the second dielectric layer 221. In some embodiments, the third conductive layer 222 includes aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), titanium silicon nitride (TiSiN), or other suitable materials. In some embodiments, the third conductive layer 222 includes tungsten (W).

[0191] In some embodiments, the first dielectric layer 213, the second dielectric layer 221, and the third dielectric layer 223 include the same material. In some embodiments, the second conductive layer 212 and the third conductive layer 222 include the same material.

[0192] In some embodiments, a height H1 of the first conductive layer 211 of the first bit line structure 21 is substantially equal to a height H2 of the second dielectric layer 221 of the second bit line structure 22. In some embodiments, a height H3 of the second conductive layer 212 of the first bit line structure 21 is substantially equal to a height H4 of the third conductive layer 222 of the second bit line structure 22.

[0193] The semiconductor structure may further include a first spacer 31 surrounding the first bit line structure 21 and a second spacer 32 surrounding the second bit line structure 22. In some embodiments, the detailed structures and configurations of the first spacer 31 and the second spacer 32 are substantially identical. For the sake of brevity, only the first spacer 31 is described in the following description, and a detailed description of the second spacer 32 is omitted. However, such omission is not intended to limit the present disclosure.

[0194] In some embodiments, the first spacer 31 may be a multi-layer 39 structure. In some embodiments, the first spacer 31 includes a first nitride layer 33, an oxide layer 34, and a second nitride layer 35. In some embodiments, the oxide layer 34 is interposed between the first nitride layer 33 and the second nitride layer 35. In some embodiments, a thickness of the first nitride layer 33 is substantially equal to a thickness of the second nitride layer 35. In some embodiments, a thickness of the oxide layer 34 is less than a thickness of the first nitride layer 33 or the second nitride layer 35. In some embodiments, the first nitride layer 33 and the second nitride layer 35 comprise the same nitride material. In some embodiments, the oxide layer 34 comprises silicon oxide. In some embodiments, the first nitride layer 33 or the second nitride layer 35 comprises silicon nitride.

[0195] In some embodiments, first spacers 31 are disposed along a sidewall 217 of first bit line structure 21. In some embodiments, second spacers 32 are disposed along a sidewall 227 of second bit line structure 22. In some embodiments, first spacers 31 and second spacers 32 surround polysilicon layer 41 and dielectric liner 42.

[0196] A polysilicon layer 41 is disposed above the substrate 11 and surrounded by the first bit line structure 21 and the second bit line structure 22. In some embodiments, the polysilicon layer 41 is disposed between the first bit line structure 21 and the second bit line structure 22 adjacent to the first bit line structure 21. In some embodiments, a top surface 453 of the polysilicon layer 41 is higher than the second conductive layer 212 and higher than the third conductive layer 222. In some embodiments, a top surface 453 of the polysilicon layer 41 is lower than a top surface 261 of the first bit line structure 21 and lower than a top surface 262 of the second bit line structure 22. The polysilicon layer 41 can serve as a contact for forming an electrical connection with other electronic components, devices, or elements in the substrate 11. In some embodiments, the polysilicon layer 41 can include multiple electrically isolated portions (i.e., the polysilicon layer 41 between the first bit line structure 21 and the second bit line structure 22 can be one of the multiple portions), and different portions of the polysilicon layer 41 can be electrically connected to different electronic components, devices, or elements in the substrate 11.

[0197] In some embodiments, the first spacer 31 and the second spacer 32 protrude from the upper surface 453 of the polysilicon layer 41. In some embodiments, a top surface 311 of the first spacer 31 and a top surface 321 of the second spacer 32 are higher than the upper surface 453 of the polysilicon layer 41.

[0198] As described above, dielectric liner 42 surrounds portion 417 of polysilicon layer 41. In some embodiments, dielectric liner 42 is disposed along a sidewall 415 of polysilicon layer 41. In some embodiments, dielectric liner 42 has a thickness substantially less than half a width of polysilicon layer 41.

[0199] In some embodiments, a top surface 421 of the dielectric liner 42 is higher than a top surface 215 of the second conductive layer 212, and a bottom surface 422 of the dielectric liner 42 is lower than a bottom surface 216 of the second conductive layer 212. In other words, a height of the dielectric liner 42 is substantially greater than a height H3 of the second conductive layer 212 of the first cell line structure 21.

[0200] In some embodiments, an upper surface 421 of the dielectric liner 42 is higher than an upper surface 225 of the third conductive layer 222, and a lower surface 422 of the dielectric liner 42 is lower than a lower surface 226 of the third conductive layer 222. In other words, the height of the dielectric liner 42 is substantially greater than a height H4 of the third conductive layer 222 of the second bit line structure 22.

[0201] One or more landing pads 51 may be disposed over the polysilicon layer 41, the dielectric liner 42, and the second bit line structure 22. In some embodiments, the landing pads 51 include one or more metal materials, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), titanium silicon nitride (TiSiN), other suitable materials, or combinations thereof. In some embodiments, each landing pad 51 is disposed over a corresponding portion of the polysilicon layer 41. In some embodiments, the landing pads 51 are electrically isolated from each other.

[0202] In some embodiments, the landing pad 51 includes a neck portion 511 aligned with the upper surface 262 of the second bit line structure 22. In some embodiments, the neck portion 511 is a portion of the landing pad 51 having a minimum width. In some embodiments, the upper surface 421 of the dielectric liner 42 is lower than the neck portion 511 of the landing pad 51.

[0203] Figure 2: is a flow chart illustrating a method S1 for preparing a semiconductor structure according to some embodiments of the present disclosure. The preparation method S1 includes a plurality of steps (S101, S102, S103, S104, S105, S106, S107, S108, S109, S110, and S111), and the description and drawings should not be construed as limiting the order of the steps. In step S101, a substrate is provided. In step S102, a first conductive layer is disposed above the substrate. In step S103, portions of the first conductive layer are removed. In step S104, a second dielectric layer is disposed adjacent to the first conductive layer. In step S105, a second conductive layer is disposed above the first conductive layer and the second dielectric layer, and a first dielectric layer is disposed above the second conductive layer. In step S106, the first dielectric layer, the second conductive layer, and portions of the second dielectric layer are removed to form a first bit line structure comprising the first conductive layer, the second conductive layer, and the first dielectric layer; a second bit line structure comprising the second dielectric layer, a third conductive layer, and a third dielectric layer; and a recess between the first and second bit line structures. In step S107, a first spacer is formed around the first bit line structure and a second spacer is formed around the second bit line structure. In step S108, a first polysilicon layer is formed within the recess and over the substrate. In step S109, a dielectric liner is formed along a sidewall of the first spacer, a sidewall of the second spacer, and over the first polysilicon layer. In step S110, a second polysilicon layer is formed over the first polysilicon layer. In step S111, portions of the dielectric liner are removed. It should be understood that the steps of preparation method S1 can be rearranged or otherwise modified within the scope of various aspects. Additional processes can be provided before, during, and after preparation method S1, and only some other processes are briefly described here. Therefore, within the scope of various aspects described herein, other embodiments are possible.

[0204] Figures 3 to 29 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure according to a method similar to Figure 1 The semiconductor structure shown is constructed in various manufacturing stages of the manufacturing method S1. Figures 3 to 29 The stages shown are also Figure 2 In the subsequent discussion, reference is made to Figure 2 The process steps are discussed Figures 3 to 29 Manufacturing stages shown.

[0205] Please refer to Figure 3 , Figure 31 is a cross-sectional schematic diagram of a stage of the preparation method S1 of some embodiments of the present disclosure. In step S101, a substrate 11 is provided, received or formed. In some embodiments, the substrate 11 may have a multi-layer structure, or the substrate 11 may include a multi-layer compound semiconductor structure. In some embodiments, the substrate 11 includes a semiconductor structure, an electronic component, an electronic element or a combination thereof. In some embodiments, the substrate 11 includes a transistor or a functional unit of a transistor. In some embodiments, the substrate 11 includes an active element, a passive element and / or a conductive element. In some embodiments, the substrate 11 and Figure 1 The substrate 11 can be formed according to conventional methods for forming semiconductor substrates.

[0206] Please refer to Figure 4 , Figure 4 FIG. 1 is a cross-sectional view of a stage of the preparation method S1 according to an embodiment of the present disclosure. In some embodiments, step S102 is performed after step S101. In step S102, a first conductive layer 211 is disposed or formed on the substrate 11.

[0207] Please refer to Figures 5 to 8 , Figures 5 to 8 1 is a cross-sectional schematic diagram of a stage of the preparation method S1 of some embodiments of the present disclosure. In some embodiments, step S103 is performed after step S102 and includes multiple steps.

[0208] Please refer to Figures 5 to 6 , Figures 5 to 6 It is a cross-sectional schematic diagram of one stage of the preparation method S1 of some embodiments of the present disclosure. Figure 2 In step S103, a patterned mask 102 is disposed above the first conductive layer 211. In some embodiments, Figure 5 As shown, the patterned mask 102 is provided by placing a photoresist 102' on the first conductive layer 211, and then removing some parts of the photoresist 102' to form the following Figure 6 A patterned mask 102 is shown.

[0209] In some embodiments, the photoresist 102' is provided by spin coating or any other suitable process. In some embodiments, portions of the photoresist 102' are removed by etching or any other suitable process. Figure 6 As shown, after the patterned mask 102 is formed, at least a portion of the first conductive layer 211 is exposed through the patterned mask 102 .

[0210] Please refer to Figures 7 to 8 , Figures 7 to 8is a cross-sectional view of a stage of the preparation method S1 of some embodiments of the present disclosure. Some portions of the first conductive layer 211 are removed. In some embodiments, the removal of these portions of the first conductive layer 211 includes etching or any other suitable process. In some embodiments, as Figure 7 As shown, after removing the portions of the first conductive layer 211, at least a portion of a surface 11a of the substrate 11 is exposed. Figure 8 In some of the embodiments shown, after the portions of the first conductive layer 211 are removed, the patterned mask 102 is removed by etching, stripping, or any other suitable process.

[0211] Please refer to Figure 9 , Figure 9 FIG2 is a schematic cross-sectional view of a stage of preparation method S1 according to some embodiments of the present disclosure. In step S104, a second dielectric layer 221 is disposed or formed above the substrate 11 and adjacent to the first conductive layer 211. In some embodiments, an upper surface 211a of the first conductive layer 211 and an upper surface 221a of the second dielectric layer 221 are substantially coplanar. In some embodiments, a height H1 of the first conductive layer 211 is substantially equal to a height H2 of the second dielectric layer 221.

[0212] Please refer to Figure 10 , Figure 10 FIG1 is a schematic cross-sectional view of a stage of preparation method S1 according to some embodiments of the present disclosure. In step S105, a second conductive layer 212 is disposed over the first conductive layer 211 and the second dielectric layer 221, and a first dielectric layer 213 is disposed over the second conductive layer 212. In some embodiments, the thickness of the first dielectric layer 213 is greater than the thickness of the second conductive layer 212. In some embodiments, the thickness of the second conductive layer 212 is greater than a height H1 of the first conductive layer 211 and greater than a height H2 of the second dielectric layer 221.

[0213] In some embodiments, each of the second dielectric layer 221 and the first dielectric layer 213 includes one or more dielectric materials. In some embodiments, the dielectric material includes a polymer material, an organic material, an inorganic material, a photoresist material, or a combination thereof. In some embodiments, the dielectric material includes one or more low-k dielectric materials having a dielectric constant (k value) less than 3.9. In some embodiments, the low-k dielectric material includes fluorine-doped silicon dioxide, organosilicate glass (OSG), carbon-doped oxide (CDO), porous silicon dioxide, spin-on organic polymer dielectric, spin-on silicon-based polymer dielectric, or a combination thereof. In some embodiments, the dielectric material includes one or more high-k dielectric materials having a dielectric constant (k value) greater than 3.9. The high-k dielectric material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), or other suitable materials. Other suitable materials are also within the contemplated scope of the present disclosure. In some embodiments, the dielectric material includes silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), metal nitride, or a combination thereof.

[0214] In some embodiments, the second dielectric layer 221 or the first dielectric layer 213 comprises silicon nitride, metal nitride, or a combination thereof. In some embodiments, the second dielectric layer 221 or the first dielectric layer 213 is formed using a blanket deposition technique. In some embodiments, the second dielectric layer 221 or the first dielectric layer 213 is formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), or a combination thereof.

[0215] In some embodiments, the first conductive layer 211 or the second conductive layer 212 includes aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), other suitable conductive materials, oxides of the above metals, or combinations thereof. In some embodiments, the first conductive layer 211 or the second conductive layer 212 includes tungsten (W). In some embodiments, the second conductive layer 212 includes a material different from a material of the first conductive layer 211. In some embodiments, the first conductive layer 211 or the second conductive layer 212 is formed using a fabrication technique including CVD, PVD, sputtering, electroplating, electroless plating, or combinations thereof.

[0216] Please refer to Figures 11 to 14 , Figures 11 to 14 Schematic cross-sectional view of a stage of the preparation method S1 of some embodiments of the present disclosure. In some embodiments, step S106 is performed after step S105 and includes multiple steps.

[0217] Please refer to Figures 11 to 12 , Figures 11 to 12 FIG. 1 is a cross-sectional view of a stage of the preparation method S1 of some embodiments of the present disclosure. According to step S106, as Figure 12 As shown, a patterned mask 104 is disposed above the first dielectric layer 213. In some embodiments, as shown in FIG. Figure 11 As shown, the patterned mask 104 is provided by placing a photoresist 104' on the first dielectric layer 213, and then removing some portions of the photoresist 104' to form a patterned mask 104'. Figure 12 A patterned mask 104 is shown.

[0218] In some embodiments, the photoresist 104' is provided by spin coating or any other suitable process. In some embodiments, portions of the photoresist 104' are removed by etching or any other suitable process. In some embodiments, after forming the patterned mask 104, at least a portion of the first dielectric layer 213 is exposed through the patterned mask 104, such as Figure 12 shown.

[0219] Please refer to Figures 13 to 14 , Figures 13 to 14 1 is a cross-sectional view illustrating a stage of the preparation method S1 of some embodiments, wherein portions of the first dielectric layer 213 , the second conductive layer 212 , and the second dielectric layer 221 are removed.

[0220] In some embodiments, the removal of the portions of the first dielectric layer 213 , the second conductive layer 212 , and the second dielectric layer 221 includes etching or any other suitable process.

[0221] In some embodiments, after removing Figure 13 After the portions of the first dielectric layer 213 , the second conductive layer 212 and the second dielectric layer 221 are formed, a first bit line structure 21 , a second bit line structure 22 and a recess 61 between the first bit line structure 21 and the second bit line structure 22 are formed.

[0222] The first cell line structure 21 includes a first conductive layer 211 , a second conductive layer 212 and a first dielectric layer 213 .

[0223] The second bit line structure 22 includes a second dielectric layer 221, a third conductive layer 222, and a third dielectric layer 223. In some embodiments, a width W1 of the first bit line structure 21 is substantially equal to a width W2 of the second bit line structure 22.

[0224] In some embodiments, as Figure 14 As shown, after removing the portions of the first dielectric layer 213 , the second conductive layer 212 , and the second dielectric layer 221 , the patterned mask 104 is removed by etching, stripping, or any other suitable process.

[0225] Please refer to Figures 15 to 16 , Figures 15 to 16 1 is a cross-sectional schematic diagram of a stage of the preparation method S1 according to some embodiments of the present disclosure. In some embodiments, step S107 is performed after step S106 and includes multiple steps.

[0226] Please refer to Figure 15 , Figure 15 is a cross-sectional schematic diagram of a stage of the preparation method S1 of some embodiments of the present disclosure. After forming the first bit line structure 21 and the second bit line structure 22, one or more conformal layers are formed over the first bit line structure 21, the second bit line structure 22 and the substrate 11. In some embodiments, each conformal layer includes a dielectric material, and two adjacent conformal layers may include different dielectric materials. In some embodiments, the dielectric material includes one or more low-k dielectric materials having a dielectric constant (k value) less than 3.9. In some embodiments, the low-k dielectric material includes fluorine-doped silicon dioxide, organosilicate glass (OSG), carbon-doped oxide (CDO), porous silicon dioxide, spin-on organic polymer dielectric, spin-on silicon-based polymer dielectric, or a combination thereof. In some embodiments, the dielectric material includes one or more high-k dielectric materials having a dielectric constant (k value) greater than 3.9. The high-k dielectric material may include hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), lanthanum oxide (La 2 O 3 ), yttrium oxide (Y 2 O 3 ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), or other suitable materials. Other suitable materials are also within the contemplated scope of the present disclosure.

[0227] like Figure 15As shown, in some embodiments, the plurality of conformal layers include a first nitride layer 33, a second nitride layer 35, and an oxide layer 34 disposed between the first nitride layer 33 and the second nitride layer 35. In some embodiments, a profile of each of the first nitride layer 33, the oxide layer 34, and the second nitride layer 35 conforms to a profile of the first bit line structure 21, the second bit line structure 22, and the substrate 11. In some embodiments, the first nitride layer 33, the oxide layer 34, and the second nitride layer 35 are each formed using a fabrication technique including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or a combination thereof. In some embodiments, the fabrication technique of each of the first nitride layer 33, the oxide layer 34, and the second nitride layer 35 includes conformal deposition. In some embodiments, a thickness of the first nitride layer 33 is substantially equal to a thickness of the second nitride layer 35. In some embodiments, the thickness of the oxide layer 34 is less than the thickness of the first nitride layer 33 or the second nitride layer 35. In some embodiments, the first nitride layer 33 and the second nitride layer 35 comprise the same nitride material. In some embodiments, the oxide layer 34 comprises silicon oxide. In some embodiments, the first nitride layer 33 or the second nitride layer 35 comprises silicon nitride.

[0228] Please refer to Figure 16 , Figure 16 FIG2 is a schematic cross-sectional view of a stage of fabrication method S1 according to some embodiments of the present disclosure. After forming a conformal layer (e.g., first nitride layer 33, oxide layer 34, and second nitride layer 35), multiple horizontal portions of the conformal layer are removed to form a first spacer 31 surrounding the first bit line structure 21 and a second spacer 32 surrounding the second bit line structure 22. In some embodiments, removing the horizontal portions of the conformal layer includes performing a wet etching operation, a dry etching operation, or a combination thereof to form the first spacer 31 and the second spacer 32. In some embodiments, removing the horizontal portions of the conformal layer includes performing a selective wet etching operation, a directional dry etching operation, an ion beam etching operation, a reactive ion etching operation, or a combination thereof.

[0229] In some embodiments, the horizontal portions of the second nitride layer 35, the horizontal portions of the oxide layer 34, and the horizontal portions of the first nitride layer 33 are simultaneously removed by a single etching operation. In some embodiments, the horizontal portions of the second nitride layer 35, the horizontal portions of the oxide layer 34, and the horizontal portions of the first nitride layer 33 are individually removed by separate etching operations. Removing the horizontal portions of the second nitride layer 35, the oxide layer 34, and the first nitride layer 33 by multiple etching operations can be similar to the multiple etching operations for forming the first bit line structure 21 and the second bit line structure 22, and will not be further described here. In some embodiments, the first spacers 31 surround the plurality of sidewalls 217 of the first bit line structure 21, and the second spacers surround the plurality of sidewalls 227 of the second bit line structure 22, as shown in FIG. Figure 16 In some embodiments, a top surface 261 of the first bit line structure 21 and a top surface 262 of the second bit line structure are exposed through the first spacer 31 and the second spacer 32, respectively. In some embodiments, a height of the first spacer 31 is substantially equal to a height of the first bit line structure 21, and a height of the second spacer 32 is substantially equal to a height of the second bit line structure 22.

[0230] Please refer to Figures 17 to 20 , Figures 17 to 20 1 is a cross-sectional schematic diagram of a stage of the preparation method S1 according to some embodiments of the present disclosure. In some embodiments, step S108 is performed after step S107 and includes multiple steps.

[0231] Please refer to Figure 17 , Figure 17 is a cross-sectional schematic diagram of a stage of the preparation method S1 according to some embodiments of the present disclosure. After forming the first spacer 31 and the second spacer 32, in step S108, the first polysilicon layer 41 is disposed in the recess 61 and above the substrate 11. In some embodiments, the manufacturing technology of the first polysilicon layer 41 includes a blanket deposition. In some embodiments, the blanket deposition includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD) or a combination thereof. In some embodiments, the first polysilicon layer 41 covers the upper surfaces 261 and 262 of the first bit line structure 21 and the second bit line structure 22. In some embodiments, Figure 17 The illustrated first polysilicon layer 41 includes a height that is substantially greater than a height of the first bit line structure 21 and the second bit line structure 22 .

[0232] Please refer to Figure 18 , Figure 18: is a cross-sectional view of a stage of the preparation method S1 of some embodiments of the present disclosure. After depositing the first polysilicon layer 41, a sacrificial layer 43 is formed on the first polysilicon layer 41. In some embodiments, the sacrificial layer 43 covers at least an upper surface 419 of the first polysilicon layer 41. It should be understood that Figure 18 Only a portion of the first polysilicon layer 41 is shown; the upper surface 419 of the first polysilicon layer 41 may be non-planar. The sacrificial layer 43 is configured to provide a planar surface for subsequent etching or polishing operations to provide a better planarization result. In some embodiments, the sacrificial layer 43 has an upper surface 431, and the upper surface 431 is planar. The sacrificial layer 43 is used to compensate for the uneven portion of the upper surface 419 of the first polysilicon layer 41. In some embodiments, the sacrificial layer 43 includes a dielectric material, an anti-reflective coating material, an oxide-containing material, or other suitable material. In some embodiments, the sacrificial layer 43 includes silicate glass, silicon oxide, silane oxide, or a combination thereof. In some embodiments, the sacrificial layer 43 includes borophosphosilicate glass (BPSG). In some embodiments, the sacrificial layer 43 includes a dielectric material that is different from the dielectric material of the first dielectric layer 213 of the first bit line structure 21 or the third dielectric layer 223 of the second bit line structure 22. In some embodiments, the sacrificial layer 43 includes a dielectric material that is different from the dielectric material of the second nitride layer 35 of the first spacer 31 or the second spacer 32. In some embodiments, the sacrificial layer 43 includes silicon.

[0233] Please refer to Figure 19 , Figure 19 is a schematic cross-sectional view of a stage of the preparation method S1 of some embodiments of the present disclosure. After forming the sacrificial layer 43, a planarization process is performed on the sacrificial layer 43 and the first polysilicon layer 41. In some embodiments, the planarization process includes ion beam etching, directional dry etching, reactive ion etching, solution wet etching, chemical mechanical polishing (CMP), or a combination thereof. In some embodiments, the planarization process has a high selectivity for a material of the sacrificial layer 43. In some embodiments, the planarization process has a high selectivity for a material of the first polysilicon layer 41. In some embodiments, the planarization process has a low selectivity for a material of the first dielectric layer 213 and / or a material of the first spacer 31. In some embodiments, the planarization process stops when the upper surface 261 of the first bit line structure 21 and the upper surface 262 of the second bit line structure 22 are exposed. In some embodiments, an upper surface 418 of the polysilicon layer 41 is substantially coplanar with the upper surface 261 of the first bit line structure 21 and the upper surface 262 of the second bit line structure 22.

[0234] Please refer to Figure 20 , Figure 20is a schematic cross-sectional view of a stage of the preparation method S1 of some embodiments of the present disclosure. After planarization is performed on the sacrificial layer 43 and the first polysilicon layer 41, some portions of the first polysilicon layer are removed. In some embodiments, the removal of these portions of the first polysilicon layer 41 includes etching or any other suitable process. In some embodiments, a height H5 of the first polysilicon layer 41 is obtained only after the portions of the first polysilicon layer are removed. In some embodiments, the height H5 is less than the height H1 of the first conductive layer 211 of the first bit line structure 21, or less than the height H2 of the second dielectric layer 221 of the second bit line structure 22. In some embodiments, after removing these portions of the first polysilicon layer 41, the first bit line structure 21 or the second bit line structure 22 protrudes from the first polysilicon layer 41 and is exposed through the first polysilicon layer 41.

[0235] Please refer to Figure 21 to Figure 22 , Figure 21 to Figure 22 1 is a cross-sectional view of a stage of the preparation method S1 of some embodiments of the present disclosure. In some embodiments, step S109 is performed after step S108 and includes multiple steps.

[0236] Please refer to Figure 21 , Figure 21 FIG2 is a schematic cross-sectional view of a stage of fabrication method S1 according to some embodiments of the present disclosure. After depositing the first polysilicon layer 41, a fourth dielectric layer 44 is formed over the first bit line structure 21, the second bit line structure 22, the first spacer 31, the second spacer 32, and the first polysilicon layer 41.

[0237] In some embodiments, the fourth dielectric layer 44 comprises a dielectric material. In some embodiments, the dielectric material comprises one or more low-k dielectric materials having a dielectric constant (k value) less than 3.9. In some embodiments, the low-k dielectric material comprises fluorine-doped silicon dioxide, organosilicate glass (OSG), carbon-doped oxide (CDO), porous silicon dioxide, spin-on organic polymer dielectric, spin-on silicon-based polymer dielectric, or a combination thereof. In some embodiments, the dielectric material comprises one or more high-k dielectric materials having a dielectric constant (k value) greater than 3.9. The high-k dielectric material may comprise hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), or other suitable materials. Other suitable materials are also within the contemplated scope of the present disclosure. In some embodiments, the fabrication technique of the fourth dielectric layer 44 comprises a conformal deposition.

[0238] Please refer to Figure 22 , Figure 22is a schematic cross-sectional view of a stage of the preparation method S1 of some embodiments of the present disclosure. After depositing the fourth dielectric layer 44, a horizontal portion of the fourth dielectric layer 44 is removed to form a dielectric liner 42 along a sidewall 37 of the first spacer 31, along a sidewall 38 of the second spacer 32, and above the first polysilicon layer 41. In some embodiments, the removal of the horizontal portion of the fourth dielectric layer 44 includes performing a wet etching operation, a dry etching operation, or a combination thereof to form the dielectric liner 42. In some embodiments, the removal of the horizontal portion of the fourth dielectric layer 44 includes selective wet etching, directional dry etching, ion beam etching, reactive ion etching, or a combination thereof. In some embodiments, a lower surface 422 of the dielectric liner 42 is substantially coplanar with an upper surface 413 of the first polysilicon layer 41.

[0239] Please refer to Figure 23 to Figure 24 , Figure 23 to Figure 24 1 is a cross-sectional schematic diagram of a stage of the preparation method S1 of some embodiments of the present disclosure. In some embodiments, step S110 is performed after step S109 and includes multiple steps.

[0240] Please refer to Figure 23 , Figure 23 FIG2 is a schematic cross-sectional view of a stage of fabrication method S1 according to some embodiments of the present disclosure. After dielectric liner 42 is formed, a second polysilicon layer 45 is disposed over first bit line structure 21, first spacer 31, dielectric liner 42, first polysilicon layer 41, second bit line structure 22, and second spacer 32. In some embodiments, first polysilicon layer 41 and second polysilicon layer 45 comprise the same material.

[0241] Please refer to Figure 24 , Figure 24 FIG1 is a schematic cross-sectional view of a stage of fabrication method S1 according to some embodiments of the present disclosure. After depositing second polysilicon layer 45, in step S110, portions of second polysilicon layer 45 are removed to form second polysilicon layer 45. In some embodiments, after removing these portions of second polysilicon layer 45, a height H6 of second polysilicon layer 45 is achieved. In some embodiments, after removing these portions of second polysilicon layer 45, first bit line structure 21 and second bit line structure 22 protrude from second polysilicon layer 45 and are exposed through second polysilicon layer 45.

[0242] Please refer to Figure 25 , Figure 25is a schematic cross-sectional view of a stage of preparation method S1 in some embodiments of the present disclosure. In some embodiments, step S111 is performed after step S110. After forming second polysilicon layer 45, portions of dielectric liner 42 are removed. In some embodiments, after removing these portions of dielectric liner 42, a height H7 of dielectric liner 42 is obtained. In some embodiments, height H7 of dielectric liner 42 is substantially equal to height H6 of the second polysilicon layer. In some embodiments, a top surface 453 of second polysilicon layer 45 is substantially coplanar with a top surface 421 of dielectric liner 42.

[0243] In some embodiments, an upper surface 421 of the dielectric liner 42 is higher than an upper surface 215 of the second conductive layer 212 of the first pixel line structure 21, and a lower surface 422 of the dielectric liner 42 is lower than a lower surface 216 of the second conductive layer 212 of the first pixel line structure 21. In other words, a height of the dielectric liner 42 is substantially greater than a height of the second conductive layer 212 of the first pixel line structure 21.

[0244] In some embodiments, an upper surface 421 of the dielectric liner 42 is higher than an upper surface 225 of the third conductive layer 222, and a lower surface 422 of the dielectric liner 42 is lower than a lower surface 226 of the third conductive layer 222. In other words, the height of the dielectric liner 42 is substantially greater than the height of the third conductive layer 222 of the second bit line structure 22.

[0245] Please refer to Figure 26 , Figure 26 is a schematic cross-sectional view of a stage of fabrication method S1 according to some embodiments of the present disclosure. After removing the portions of dielectric liner 42, fabrication method S1 further includes forming a metal layer 52 to cover first bit line structure 21, second bit line structure 22, first spacer 31, second spacer 32, dielectric liner 42, and second polysilicon layer 45. In some embodiments, metal layer 52 comprises aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), titanium silicon nitride (TiSiN), other suitable materials, or combinations thereof. In some embodiments, metal layer 52 comprises tungsten, copper, or combinations thereof. In some embodiments, the metal layer 52 is formed by a process including CVD, PVD, LPCVD, PECVD, sputtering, electroplating, or a combination thereof. In some embodiments, the metal layer 52 covers at least the upper surface 261 of the first bit line structure 21 and the upper surface 262 of the second bit line structure 22. Figure 26Only a portion of the metal layer 52 is shown, and the upper surface 521 of the metal layer 52 may be a non-planar surface.

[0246] Please refer to Figure 27 , Figure 27 : is a cross-sectional schematic diagram of a stage of the preparation method S1 of some embodiments of the present disclosure. After forming the metal layer 52, the preparation method S1 may further include a planarization. In some embodiments, the planarization includes ion beam etching, directional dry etching, reactive ion etching, solution wet etching, CMP, or a combination thereof. In some embodiments, the planarization includes a grinding operation (e.g., a CMP operation). In some embodiments, an upper surface 522 of the metal layer 52 is formed after the planarization. In some embodiments, the upper surface 522 is a flat surface disposed below Figure 26 At a height of the upper surface 521 shown.

[0247] Please refer to Figure 28 , Figure 28 is a schematic cross-sectional view of a stage of the preparation method S1 of some embodiments of the present disclosure. After planarization, the preparation method S1 may further include removing portions of the metal layer 52 to form a landing pad 51. In some embodiments, a plurality of openings 53 are formed in the metal layer 52, thereby defining a plurality of landing pads 51. In some embodiments, during the removal of the portions of the metal layer 52, an upper portion 313 of the first spacer 31 surrounding the first bit line structure 21 is partially removed. In some embodiments, portions of the first spacer 31 and the second spacer 32 are exposed through the plurality of openings 53. In alternative embodiments, only portions of the metal layer 52 are removed. In some embodiments, the configuration of the first bit line structure 21, the second bit line structure 22, the first spacer 31, and the second spacer 32 remains the same before, during, and after the removal of the portion of the metal layer 52.

[0248] In some embodiments, the landing pad 51 is disposed above the second polysilicon layer 45 and the second bit line structure 22 and includes a neck 511 aligned with the upper surface 262 of the second bit line structure 22. In some embodiments, the upper surface 421 of the dielectric liner 42 is located below the neck 511 of the landing pad 51.

[0249] Please refer to Figure 29 , Figure 29: is a cross-sectional schematic diagram of a stage of the preparation method S1 of some embodiments of the present disclosure. After forming the landing pad 51, the preparation method S1 may further include removing some portions of the oxide layer 34 to form an air gap 36 surrounded by the first nitride layer 33, the second nitride layer 35 and the oxide layer 34. Thereby, the air gap 36 is formed to replace the removed portion of the oxide layer 34. In some embodiments, the removal of such portions of the oxide layer 34 includes vapor phase etching, solution wet etching or a combination thereof. In some embodiments, gas phase hydrogen fluoride (HF) is used to remove such portions of the oxide layer 34. In some embodiments, an upper surface 341 of the oxide layer 34 is lower than the lower surface 422 of the dielectric liner 42. Thereby, a similar Figure 1 The semiconductor structure shown.

[0250] Please refer to Figure 30 , Figure 30 FIG1 is a schematic cross-sectional view illustrating a semiconductor structure 1A according to an alternative embodiment of the present disclosure. The semiconductor structure 1A may include a substrate 101, a bit line structure 301 disposed on the substrate 101, a capacitor contact structure 401 disposed adjacent to the bit line structure 301, and a landing pad layer 501 disposed to cover a portion of a top surface 407TS of the capacitor contact structure 401 and an upper portion of a sidewall 407SW of the capacitor contact structure 401. Figure 30 The semiconductor structure 1A in Figure 1 The semiconductor structures of and are similar in many respects, so the description of similar features will not be repeated here. The main differences are described below.

[0251] The substrate 101 may include an organic semiconductor or a layered semiconductor, such as silicon / silicon germanium, silicon-on-insulator (SOI), or silicon-germanium-on-insulator (SOI). When the substrate 101 includes SOI, the substrate 101 may include an upper semiconductor layer and a lower semiconductor layer formed of silicon, and a buried insulating layer that may separate the upper semiconductor layer from the lower semiconductor layer. For example, the buried insulating layer may include a crystalline or amorphous oxide, nitride, or any combination thereof.

[0252] In some embodiments, an isolation layer 103 may be formed in the substrate 101, and a plurality of active regions 105 may be defined by the isolation layer 103. An upper surface of the isolation layer 103 may be substantially coplanar with an upper surface of the substrate 101. For example, the isolation layer 103 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or fluoride-doped silicate. It should be understood that silicon oxynitride in the present disclosure refers to a substance containing silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen. In some embodiments, a source region 107-1 and a drain region 107-3 may be formed on each upper portion of the active regions 105. The source region 107-1 and the drain region 107-3 may be doped with a dopant such as phosphorus, arsenic, antimony, or boron.

[0253] The bitline structure 301 may include a bitline lower conductive layer 303 disposed above the substrate 101, a bitline intermediate conductive layer 305 disposed above the bitline lower conductive layer 303, and a bitline upper conductive layer 307 disposed above the bitline intermediate conductive layer 305. For example, the bitline lower conductive layer 303 may include polysilicon, polycrystalline germanium, polycrystalline silicon germanium, titanium, tantalum, tungsten, copper, aluminum, tungsten silicide, cobalt silicide, or titanium silicide. For example, the bitline intermediate conductive layer 305 may include titanium nitride or tantalum nitride. For example, the bitline upper conductive layer 307 may include tungsten, tantalum, titanium, copper, or aluminum. The bitline intermediate conductive layer 305 may reduce or possibly prevent diffusion of a conductive material in the bitline conductive layer 307 toward the bitline lower conductive layer 303.

[0254] In some embodiments, the semiconductor structure 1A further includes a bit line contact 312 formed in the substrate 101, wherein the bit line structure 301 may be disposed on the bit line contact 312. The bit line contact 312 may be formed in each of the source regions 107-1. An upper surface of the bit line contact 312 may be substantially coplanar with an upper surface of the substrate 101. For example, the bit line contact 312 may include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, a metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), a metal nitride (e.g., titanium nitride), a transition metal aluminide, or a combination thereof. The bit line contact 312 may be electrically coupled to the source region 107-1.

[0255] In some embodiments, the semiconductor structure 1A further includes a plurality of bitline spacers 314 configured to protrude from the substrate 101 and attach to sidewalls of the bitline structure 301. The bitline spacers 314 may include silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, or silicon nitride oxide. In some embodiments, portions of a lower surface 313BS of the bitline spacers 314 may be substantially coplanar with a lower surface 311BS of the bitline contact 312.

[0256] In some embodiments, the semiconductor structure 1A further includes a bit line capping layer 309 over the substrate 101 and on the bit line structure 301. A top surface 309TS of the bit line capping layer 309 may be referred to as a top surface of the bit line structure 301. For example, the bit line capping layer 309 may include silicon nitride, silicon oxynitride, silicon oxynitride, boron nitride, silicon boron nitride, boron phosphide, or silicon boron carbonitride.

[0257] The capacitor contact structure 401 may protrude from the substrate 101. The capacitor contact structure 401 includes a capacitor contact lower conductive layer 403 protruding from the substrate 101, a capacitor contact middle conductive layer 405 disposed on the capacitor contact lower conductive layer 403, and a capacitor contact upper conductive layer 407 disposed on the capacitor contact middle conductive layer 405. The upper surface 407TS of the capacitor contact upper conductive layer 407 may be referred to as the upper surface of the capacitor contact structure 401. The capacitor contact structure 401 may be electrically coupled to the drain region 107-3. For example, the capacitor contact lower conductive layer 403 may include polysilicon, polycrystalline germanium, or polycrystalline silicon germanium. In some embodiments, the capacitor contact lower conductive layer 403 may be doped with a dopant such as phosphorus, arsenic, antimony, or boron. For example, the capacitor contact middle conductive layer 405 may include cobalt silicide, titanium silicide, nickel silicide, nickel platinum silicide, or tantalum silicide. An upper surface of the capacitor contact intermediate conductive layer 405 may be at a vertical plane that is lower than a vertical level of the upper surface 309TS of the bit line cap layer 309 .

[0258] In some embodiments, semiconductor structure 1A further includes a dielectric liner 402 surrounding at least a portion 412 of capacitor contact lower conductive layer 403 and a portion 432 of capacitor contact middle conductive layer 405. In some embodiments, bit line spacers 314 surround capacitor contact lower conductive layer 403, capacitor contact middle conductive layer 405, capacitor contact upper conductive layer 407, and dielectric liner 402. In some embodiments, dielectric liner 402 is disposed along a sidewall 403SW of capacitor contact lower conductive layer 403 and along a sidewall 405SW of capacitor contact middle conductive layer 405.

[0259] A landing pad layer 501 may be formed to partially cover the capacitor contact structure 401. The landing pad layer 501 may cover a portion of the upper surface 407TS of the capacitor contact upper conductive layer 407 and an upper portion of the sidewall 407SW of the capacitor contact upper conductive layer 407. In other words, the landing pad layer 501 may partially cover the capacitor contact upper conductive layer 407. The landing pad layer 501 may include tungsten, copper, or aluminum. A photolithography process followed by an etching process may be performed to form the landing pad layer 501.

[0260] Figure 31 1 is a flow chart illustrating a method 10 for preparing a semiconductor structure 1A according to an alternative embodiment of the present disclosure. The method 10 may include steps S11, S13, S15, S17, and S19, and may be referred to as Figure 30 A description of the process and intermediate stages for fabricating semiconductor structure 1A is provided to facilitate further understanding.

[0261] Please refer to Figure 30 and Figure 31 In some embodiments, step S11 of the preparation method 10 includes: providing a substrate 101 ; forming an isolation layer 103 in the substrate 101 ; and defining a plurality of active regions 105 through the isolation layer 103 .

[0262] In some embodiments, step S13 of the manufacturing method 10 includes: forming a plurality of bit line structures 301 on the substrate 101 .

[0263] In some embodiments, the formation of the bit line structure 301 includes: forming a bit line lower conductive layer 303 over the substrate 101; forming a bit line intermediate conductive layer 305 over the bit line lower conductive layer 303; forming a bit line upper conductive layer 307 over the bit line intermediate conductive layer 305; and forming a bit line cap layer 309 over the bit line conductive layer 307.

[0264] In some embodiments, step S15 of the fabrication method 10 includes forming a capacitor contact structure 401 adjacent to the bit line structure 301 and protruding from the substrate 101 .

[0265] In some embodiments, the formation of the capacitor contact structure 401 includes: forming a capacitor contact lower conductive layer 403 protruding from the substrate 101; forming a capacitor contact middle conductive layer 405 on the capacitor contact lower conductive layer 403; and forming a capacitor contact upper conductive layer 407 on the capacitor contact middle conductive layer 405.

[0266] In some embodiments, step S15 of preparation method 10 also includes step S151: forming a dielectric liner 402 along a side wall 403SW of the capacitor contact lower conductive layer 403 and along a side wall 405SW of the capacitor contact middle conductive layer 405 to surround at least a portion 412 of the capacitor contact lower conductive layer 403 and a portion 432 of the capacitor contact middle conductive layer 405.

[0267] In some embodiments, step S17 of the fabrication method 10 includes recessing the upper surfaces 309TS of the bit line structures 301 .

[0268] In some embodiments, step S19 of the preparation method 10 includes: forming a plurality of landing pad layers 501 to partially cover the capacitor contact structure 401 , wherein the landing pad layers 501 cover a portion of an upper surface 407TS of the capacitor contact structure 401 and an upper portion of a sidewall 407SW of the capacitor contact structure 401 .

[0269] Figure 32 FIG2 is a cross-sectional view illustrating a semiconductor structure 1B according to an alternative embodiment of the present disclosure. The semiconductor structure 1B may include a polysilicon layer 14 ′, a substrate 11 ′, a bit line structure 12 , and a spacer substructure 13 ′.

[0270] The polysilicon layer 14' has a first surface F14' and a second surface B14' opposite the first surface F14'. In some embodiments, the substrate 11' is disposed on the second surface B14' of the polysilicon layer 14'. In some embodiments, the bit line structure 12 is disposed on the substrate 11', penetrates the polysilicon layer 14', and protrudes from the first surface F14' of the polysilicon layer 14'.

[0271] The substrate 11 ′ and the bit line structure 12 are similar Figure 1 The semiconductor structure shown includes a substrate 11 and a first bit line structure 21 (or a second bit line structure 22 ). Therefore, the description of the substrate 11 ′ and the bit line structure 12 will not be repeated here.

[0272] A gap substructure 13' is disposed on lateral sidewalls BS1 and BS2 of bitline structure 12. In some embodiments, gap substructure 13' may include a first dielectric layer 131' and a second dielectric layer 133', wherein second dielectric layer 133' includes gap subsegments 133a and 133b of dielectric layer 133, wherein gap subsegment 133b is disposed within polysilicon layer 14' and gap subsegment 133a is disposed outside polysilicon layer 14'. In some embodiments, gap substructure 13' includes a gap 135 sandwiched between first dielectric layer 131' and second dielectric layer 133'. A thickness T133a' of gap subsegment 133a of dielectric layer 133 is less than a thickness T133b' of gap subsegment 133b of dielectric layer 133. In some embodiments, a width T135 of gap 135 is in a range from 3 nanometers to 5 nanometers. In some embodiments, the thickness T133a' of the gap sub-portion 133a is in a range of 4 to 8.5 nanometers. In some embodiments, the thickness T133b' of the gap sub-portion 133b is in a range of 5.5 to 10 nanometers. In some embodiments, the thickness T131' of the first dielectric layer 131' is in a range of 5.5 to 12 nanometers. In some embodiments, the thickness T131' of the first dielectric layer 131' is substantially equal to the thickness T133b' of the gap sub-portion 133b. In some embodiments, the first dielectric layer 131' and the second dielectric layer 133' are made of the same material. In some embodiments, the first dielectric layer 131' and the second dielectric layer 133' include a nitride (e.g., silicon nitride). In some embodiments, the first dielectric layer 131' and the second dielectric layer 133' include an oxide (e.g., silicon oxide).

[0273] In some embodiments, the semiconductor structure 1B further includes a pair of dielectric liners 141' disposed in the polysilicon layer 14' and on the lateral sidewalls SW1 and SW2 of the gap sub-portion 133b of the dielectric layer 133, wherein the dielectric liners 141' are spaced apart from each other and face each other. In some embodiments, the pair of dielectric liners 141' are disposed between the bit line structure 12 and the adjacent bit line structure 12. In some embodiments, the dielectric liner 141' is disposed to penetrate the polysilicon layer 14'. In some embodiments, an upper surface TS of the dielectric liner 141' is substantially coplanar with the first surface F14' of the polysilicon layer 14'. In some embodiments, a lower surface BS of the dielectric liner 141' is substantially coplanar with the second surface B14' of the polysilicon layer 14'. The dielectric liner 141' may include Figure 1 The dielectric liner 42 of the semiconductor structure shown is made of the same material. A height H of the dielectric liner 141 ′ may be equal to or less than a thickness T of the polysilicon layer 14 ′.

[0274] In some embodiments, the semiconductor structure 1B further includes a metal layer 15 disposed above the polysilicon layer 14′, a landing pad 17′ disposed above the metal layer 15, and an adhesive layer 16′ disposed between the metal layer 15 and the landing pad 17′, wherein the adhesive layer 16′ lines portions of the upper surface of the metal layer 15, sidewalls of the spacer substructure 13′, upper surfaces of the spacer substructure 13′, and portions of the bit line structure 12.

[0275] In some embodiments, the semiconductor structure 1B further includes a spacer layer 18 covering the exposed portions of the liner metal layer 15 , the adhesion layer 16 ′, the landing pad 17 ′, the bit line structure 12 , and the spacer structure 13 ′, and a sealing layer 19 covering the spacer layer 18 .

[0276] Figure 33 1 is a flow chart illustrating a method M10 for preparing a semiconductor structure 1B according to an alternative embodiment of the present disclosure. The method M10 may include steps O101, O103, O105, O107, O109, O111, O113, and O115, and for further understanding, refer to Figure 32 and Figures 34 to 36 Provides a description of the processes and intermediate stages used to manufacture semiconductors.

[0277] Please refer to Figure 33 and Figure 34 In some embodiments, step O101 of the preparation method M10 includes receiving a substrate 11', wherein the substrate 11' is Figure 1 The substrates 11 of the semiconductor structures shown are identical or similar.

[0278] In some embodiments, step O103 of method M10 includes forming a plurality of bit line structures 12 on a top surface F11 of a substrate 11', wherein a plurality of recessed portions R1 are formed on the top surface F11 of the substrate 11' adjacent to two sides of one of the bit line structures 12, and adjacent bit line structures 12 are formed on a flat portion of the top surface F11 of the substrate 11' without adjacent recessed portions R1.

[0279] In some embodiments, step O105 of method M10 includes forming a spacer substructure 13 ′ on the bit line structure 12 , wherein the spacer substructure 13 ′ includes a sacrificial layer 132 ′ sandwiched between a first dielectric layer 131 ′ and a second dielectric layer 133 ′.

[0280] In some embodiments, step O107 of preparation method M10 includes forming a polysilicon layer 14' above the upper surface F11 of the substrate 11', wherein the polysilicon layer 14' has a first surface F14' and a second surface B14' opposite to the first surface F14'; and forming a pair of dielectric pads 141' in the polysilicon layer 14' and on the lateral side walls SW1 and SW2 of the gap sub-portion 133b of the second dielectric layer 133', wherein the dielectric pads 141' are spaced apart from each other and face each other.

[0281] In some embodiments, step O109 of method M10 includes forming a metal layer 15 over polysilicon layer 14'; forming an adhesion layer 16' to line portions of the upper surfaces of metal layer 15, sidewalls of spacer substructures 13', upper surfaces of spacer substructures 13', and portions of bit line structure 12; and forming a plurality of landing pads 17' over metal layer 15 and on adhesion layer 16'.

[0282] Please refer to Figure 33 and Figure 35 In some embodiments, step O111 of method M10 includes removing the sacrificial layer 132 ′ to form a gap 134 between the first dielectric layer 131 ′ and the second dielectric layer 133 ′, wherein the gap 134 has a width T134 .

[0283] Please refer to Figure 33 and Figure 36 In some embodiments, step O113 of method M10 includes depositing a lining such as Figure 35 The intermediate structure shown has a gap sub-spacer 18 to reduce the width T134 of the gap 134. Figure 36 As shown, a width T135 of gap 135 is reduced. That is, width T135 of gap 135 is less than width T134 of gap 134. It should be understood that in some embodiments, gap sub-layer 18 comprises the same material as first dielectric layer 131' and / or second dielectric layer 133'. In some embodiments, if gap sub-layer 18 and first dielectric layer 131' comprise the same material, no distinct interface exists between gap sub-layer 18 and first dielectric layer 131'. In some embodiments, gap sub-layer 18 may be fabricated using atomic layer deposition.

[0284] Please refer to Figure 33 and Figure 32 In some embodiments, step O115 of method M10 includes forming a sealing layer 19 to seal the gap. In some embodiments, sealing layer 19 is a multi-layer structure. In some embodiments, sealing layer 19 includes a linear layer 191 and a planar layer 192.

[0285] Therefore, the present disclosure provides a novel bitline structure and method for fabricating the same. The bitline structure of the present disclosure includes a dielectric liner disposed along a sidewall of a polysilicon layer. The dielectric liner prevents charges (e.g., charges stored in a capacitor disposed on a landing pad) from leaking into the polysilicon layer. Furthermore, due to the deposition of the dielectric liner, a neck portion of the landing pad does not need to be narrowed because an upper surface of the dielectric liner is lower than the neck portion of the landing pad.

[0286] One embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; a bitline structure disposed above the substrate; a plurality of capacitor contact structures disposed adjacent to the bitline structure; a plurality of dielectric liners disposed within the capacitor contact structures, wherein each dielectric liner surrounds at least a portion of a corresponding capacitor contact structure; and a plurality of landing pads disposed to partially cover a top surface and a sidewall of the corresponding capacitor contact structure. The substrate includes an isolation layer defining a plurality of active regions, and a plurality of source and drain regions disposed within the active regions.

[0287] Another embodiment of the present disclosure provides a method for fabricating a semiconductor structure. The method includes providing a substrate; forming a bit line structure on the substrate; forming a capacitor contact structure adjacent to the bit line structure, wherein the capacitor contact structure protrudes from the substrate; recessing an upper surface of the bit line structure; and forming a landing pad layer to partially cover an upper surface of the capacitor contact structure and partially cover a sidewall of the capacitor contact structure.

[0288] Another embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a polysilicon layer having a first surface and a second surface opposite the first surface; a substrate disposed on the second surface of the polysilicon layer; a plurality of bitline structures disposed on the substrate; and a spacer structure disposed on each lateral sidewall of the bitline structure. In a cross-sectional view, the polysilicon layer includes a pair of dielectric liners disposed in the polysilicon layer and on the lateral sidewalls of the spacer structure, wherein the dielectric liners are separated from each other and the paired dielectric liners face each other.

[0289] Yet another embodiment of the present disclosure provides a method for fabricating a semiconductor structure. The method includes receiving a substrate; forming a bit line structure on an upper surface of the substrate; forming a gap substructure on the bit line structure, wherein the gap substructure includes a sacrificial layer sandwiched between a first dielectric layer and a second dielectric layer; forming a polysilicon layer above the upper surface of the substrate and forming a pair of dielectric liners in the polysilicon layer, wherein the polysilicon layer has a first surface and a second surface opposite to the first surface; removing the sacrificial layer to form a gap between the first dielectric layer and the second dielectric layer; reducing a width of the gap; and forming a sealing layer to seal the gap.

[0290] In summary, the present application discloses a method for fabricating a semiconductor structure and a semiconductor structure thereof. The presence of a dielectric liner in the semiconductor structure prevents storage leakage from the bit line structure to the polysilicon layer and can protect the accuracy of data stored in the bit line structure.

[0291] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above may be implemented in different ways, and other processes or combinations thereof may be substituted for many of the processes described above.

[0292] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with this disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of this application.

Claims

1. A semiconductor structure comprising: a substrate having an isolation layer; a plurality of active regions defined by the isolation layer; a plurality of source regions and a plurality of drain regions, disposed in the plurality of active regions; a bit line structure disposed above the substrate; a plurality of capacitor contact structures disposed adjacent to the bit line structure; a plurality of dielectric liners disposed in the plurality of capacitor contact structures, wherein each dielectric liner surrounds at least a portion of a corresponding capacitor contact structure; as well as A plurality of landing pad layers are arranged to partially cover an upper surface and a side wall of a corresponding capacitor contact structure.

2. The semiconductor structure of claim 1 , wherein the bit line structure comprises a bit line lower conductive layer disposed above the substrate, a bit line middle conductive layer disposed above the bit line lower conductive layer, and a bit line upper conductive layer disposed above the bit line middle conductive layer.

3. The semiconductor structure of claim 2, wherein the bit line conductive layer comprises polysilicon, polycrystalline germanium, polycrystalline silicon germanium, titanium, tantalum, tungsten, copper, aluminum, tungsten silicide, cobalt silicide, or titanium silicide. 4 . The semiconductor structure as claimed in claim 3 , wherein the bit line intermediate conductive layer comprises titanium nitride or tantalum nitride. 5 . The semiconductor structure of claim 4 , wherein the bit line conductive layer comprises tungsten, tantalum, titanium, copper or aluminum.

6. The semiconductor structure of claim 1, further comprising a bit line contact disposed in the substrate. 7 . The semiconductor structure of claim 6 , wherein the bit line structure is disposed on the bit line contact. 8 . The semiconductor structure of claim 7 , further comprising a plurality of bit line capping layers disposed above the substrate, wherein each bit line capping layer is disposed on a corresponding bit line structure.

9. The semiconductor structure of claim 1 , wherein the capacitor contact structure comprises a capacitor contact lower conductive layer disposed in the substrate and protruding from the substrate, a capacitor contact middle conductive layer disposed on the capacitor contact lower conductive layer, and a capacitor contact upper conductive layer disposed on the capacitor contact middle conductive layer.

10. The semiconductor structure of claim 8, further comprising a plurality of bit line spacers disposed in the substrate and protruding from the substrate, wherein the bit line spacers are located between the bit line structure and the capacitor contact structure, and wherein a lower surface of the bit line spacers is coplanar with a lower surface of the bit line contact.

11. The semiconductor structure of claim 8 , further comprising a plurality of bit line spacers disposed on the substrate, wherein the plurality of bit line spacers are located between the bit line structure and the capacitor contact structure, wherein an upper surface of the plurality of bit line spacers is coplanar with an upper surface of the bit line contact.

12. A method for preparing a semiconductor structure, comprising: providing a substrate; forming a bit line structure on the substrate; forming a capacitor contact structure adjacent to the bit line structure, wherein the capacitor contact structure protrudes from the substrate; recessing an upper surface of the bit line structure; as well as A landing pad layer is formed to partially cover an upper surface of the capacitor contact structure and partially cover a sidewall of the capacitor contact structure.

13. The preparation method according to claim 12, further comprising: forming an isolation layer in the substrate; as well as A plurality of active regions are defined by the isolation layer.

14. The method according to claim 12, wherein forming the bit line structure comprises: forming a bit line conductive layer above the substrate; forming a bit line intermediate conductive layer above the bit line conductive layer; A bit line upper conductive layer is formed on the bit line middle conductive layer; and a bit line cap layer is formed on the bit line upper conductive layer.

15. The method according to claim 12, wherein forming the capacitor contact structure comprises: forming a capacitor contact lower conductive layer protruding from the substrate; forming a capacitor contact middle conductive layer on the capacitor contact lower conductive layer; and forming a capacitor contact upper conductive layer on the capacitor contact middle conductive layer.

16. The method according to claim 15, wherein forming the capacitor contact structure further comprises: A dielectric liner is formed along a sidewall of the capacitor contact lower conductive layer and along a sidewall of the capacitor contact middle conductive layer, wherein the dielectric liner surrounds at least a portion of the capacitor contact lower conductive layer and a portion of the capacitor contact middle conductive layer. 17 . The method of claim 12 , further comprising forming a bit line contact in the substrate, wherein the bit line structure is disposed on the bit line contact.

18. The preparation method as described in claim 17 further includes forming a plurality of bit line spacers between the bit line structure and the capacitor contact structure, wherein the plurality of bit line spacers are arranged in the substrate and protrude from the substrate, wherein a lower surface of the plurality of bit line spacers is coplanar with a lower surface of the bit line contact.

19. The preparation method as described in claim 17 further includes forming a plurality of bit line spacers between the bit line structure and the capacitor contact structure, wherein the plurality of bit line spacers are arranged on the substrate, wherein an upper surface of the plurality of bit line spacers is coplanar with an upper surface of the bit line contact.

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