SONOS device and manufacturing method thereof

Abstract

The invention relates to an SONOS device and a manufacturing method thereof. The SONOS device comprises a substrate which comprises a front surface and a back surface which are oppositely distributed along a first direction; the tunneling oxide layer covers the front surface of the substrate; the charge trapping layer comprises a first silicon nitride layer, a second silicon nitride layer and a third silicon nitride layer which are sequentially stacked on the surface, away from the substrate, of the tunneling oxide layer in the first direction, and the oxygen content of the first silicon nitride layer is larger than that of the third silicon nitride layer; the dielectric constant of the second silicon nitride layer is greater than that of the third silicon nitride layer, and the third silicon nitride layer is used for preventing charges in the second silicon nitride layer from diffusing outwards; and the charge barrier layer is located on the surface, deviating from the second silicon nitride layer, of the third silicon nitride layer. According to the invention, the data retention performance of the SONOS device at high temperature is greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a SONOS device and a manufacturing method thereof. Background Art

[0002] SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) is a non-volatile memory device widely used in embedded memory, high-density memory, and low-power memory. A SONOS device typically includes a silicon substrate, a tunneling oxide layer covering the surface of the silicon substrate, a charge trapping layer covering the surface of the tunneling oxide layer, a charge blocking layer covering the surface of the charge trapping layer, and a control gate layer covering the surface of the blocking layer.

[0003] The traditional SONOS device manufacturing process first deposits a silicon oxide layer on a silicon substrate as the tunneling oxide layer. Next, a silicon nitride layer is deposited on the surface of the tunneling oxide layer as the charge trapping layer. Finally, a silicon oxide insulating layer is added to the charge trapping layer as the charge blocking layer. Polycrystalline silicon is then grown on the surface of the charge blocking layer as the control gate layer. The silicon nitride layer in the ONO (silicon oxide-silicon nitride-silicon oxide) dielectric layer is the primary dielectric layer responsible for storage capabilities. Charge loss in SONOS memory is primarily caused by defects introduced in the tunneling oxide layer during program / erase cycles, a factor that decreases with increasing operating temperature. Currently, vertical hole transport and hole accumulation in the charge trapping layer are the primary drivers of charge loss in traditional SONOS memory. For specialized storage devices with extremely high data retention requirements under high-temperature operating environments, traditional SONOS devices cannot provide adequate data retention due to the limitations of their charge trapping layer structure, thus limiting performance improvements and expanding their application areas.

[0004] Therefore, how to improve the data retention capability of SONOS devices so that SONOS devices have high data retention performance even in high-temperature working environments, thereby improving SONOS performance and expanding its application areas. Summary of the Invention

[0005] The present invention provides a SONOS device and a manufacturing method thereof, which are used to improve the data retention capability of the SONOS device, so that the SONOS device has high data retention performance even in a high-temperature working environment, thereby achieving improvement in the performance of the SONOS device and expansion of the application field.

[0006] According to some embodiments, the present invention provides a SONOS device, comprising: a substrate comprising a front surface and a back surface oppositely distributed along a first direction; a tunneling oxide layer covering the front surface of the substrate; a charge trapping layer, comprising a first silicon nitride layer, a second silicon nitride layer, and a third silicon nitride layer stacked sequentially along the first direction on a surface of the tunneling oxide layer facing away from the substrate, wherein the oxygen content of the first silicon nitride layer is greater than the oxygen content of the third silicon nitride layer, the dielectric constant of the second silicon nitride layer is greater than the dielectric constant of the third silicon nitride layer, and the third silicon nitride layer is used to prevent charges in the second silicon nitride layer from diffusing outward; The charge blocking layer is located on a surface of the third silicon nitride layer facing away from the second silicon nitride layer.

[0007] In some embodiments, the first silicon nitride layer directly covers the surface of the tunnel oxide layer facing away from the substrate, the second silicon nitride layer directly covers the surface of the first silicon nitride layer, and the third silicon nitride layer directly covers the surface of the second silicon nitride layer.

[0008] In some embodiments, the second silicon nitride layer includes a doping element, and the doping element is any one of hafnium, aluminum, lanthanum, zirconium, titanium, and strontium, or a combination of two or more thereof.

[0009] In some embodiments, the density of the third silicon nitride layer is greater than the density of the second silicon nitride layer.

[0010] In some embodiments, the oxygen content in the first silicon nitride layer is 4%-5%.

[0011] In some embodiments, the total thickness of the charge trapping layer is 80 Å to 90 Å.

[0012] In some embodiments, the thickness of the first silicon nitride layer is 30 Å to 40 Å, and the thickness of the second silicon nitride layer is 30 Å to 40 Å.

[0013] In some embodiments, it further includes: The control gate layer covers the surface of the charge blocking layer away from the charge trapping layer, and the material of the control gate layer includes polysilicon.

[0014] According to some other embodiments, the present invention further provides a method for manufacturing a SONOS device, comprising the following steps: forming a substrate, the substrate comprising a front surface and a back surface oppositely distributed along a first direction; forming a tunneling oxide layer on the front surface of the substrate; forming a charge trapping layer on the tunneling oxide layer, the charge trapping layer comprising a first silicon nitride layer, a second silicon nitride layer, and a third silicon nitride layer stacked sequentially along the first direction on a surface of the tunneling oxide layer facing away from the substrate, the first silicon nitride layer having a greater oxygen content than the third silicon nitride layer, the second silicon nitride layer having a greater dielectric constant than the third silicon nitride layer, and the third silicon nitride layer being used to prevent charges in the second silicon nitride layer from diffusing outward; A charge blocking layer is formed on a surface of the third silicon nitride layer facing away from the second silicon nitride layer.

[0015] In some embodiments, the material of the substrate includes silicon; and the specific steps of forming a tunneling oxide layer on the front surface of the substrate include: The tunnel oxide layer is formed on the front surface of the substrate by an in-situ water vapor generation process.

[0016] In some embodiments, the specific steps of forming a charge trapping layer on the tunneling oxide layer include: forming the first silicon nitride layer on the substrate directly covering the surface of the tunnel oxide layer; forming a second silicon nitride layer directly covering a surface of the first silicon nitride layer facing away from the tunnel oxide layer; A third silicon nitride layer is formed directly covering a surface of the second silicon nitride layer facing away from the first silicon nitride layer.

[0017] In some embodiments, the specific steps of forming the first silicon nitride layer on the substrate directly covering the surface of the tunnel oxide layer include: A silicon source gas, a nitrogen source gas, and an oxygen source gas are transported onto the substrate to form the first silicon nitride layer having an oxygen content of 4% to 5%.

[0018] In some embodiments, the silicon source gas includes SiH2Cl2, the nitrogen source gas includes NH3, and the oxygen source gas includes N2O.

[0019] In some embodiments, the specific steps of forming the second silicon nitride layer directly covering the surface of the first silicon nitride layer facing away from the tunnel oxide layer include: The silicon source gas, the nitrogen source gas and the doping source gas are transported onto the substrate to form the second silicon nitride layer including a doping element, wherein the doping element is any one of hafnium, aluminum, lanthanum, zirconium, titanium and strontium, or a combination of two or more thereof.

[0020] In some embodiments, the thickness of the first silicon nitride layer is 30 Å to 40 Å, and the thickness of the second silicon nitride layer is 30 Å to 40 Å.

[0021] In some embodiments, the specific steps of forming the third silicon nitride layer directly covering the surface of the second silicon nitride layer facing away from the first silicon nitride layer include: The silicon source gas and the nitrogen source gas are transported onto the substrate to form the third silicon nitride layer, wherein the density of the third silicon nitride layer is greater than the density of the second silicon nitride layer.

[0022] In some embodiments, the specific steps of forming a charge blocking layer on a surface of the third silicon nitride layer facing away from the second silicon nitride layer include: An in-situ water vapor generation process is used to oxidize a portion of the third silicon nitride layer to form the charge blocking layer.

[0023] In some embodiments, the total thickness of the charge trapping layer is 80 Å to 90 Å.

[0024] The SONOS device and its manufacturing method provided by the present invention comprise a charge trapping layer comprising a first silicon nitride layer, a second silicon nitride layer, and a third silicon nitride layer stacked sequentially along a first direction on a surface of the tunneling oxide layer facing away from the substrate. The first silicon nitride layer has a greater oxygen content than the third silicon nitride layer, and the second silicon nitride layer has a greater dielectric constant than the third silicon nitride layer. The third silicon nitride layer is used to block outward diffusion of charge from the second silicon nitride layer. This reduces the barrier height during electron tunneling through the first silicon nitride layer, which has a higher oxygen content, thereby improving programming / erase efficiency. Furthermore, the device improves interface quality and reduces interface state density, thereby reducing the negative impact of charge injection on the reliability of the SONOS device. The second silicon nitride layer, which has a higher dielectric constant, has a higher charge trapping density, making it easier for charge to be stored in the second silicon nitride layer, thereby improving the durability of the non-volatile memory cell. The third silicon nitride layer prevents charge from being lost to upper layers or the external environment, and its uniformity and high density enhance the structural stability of the SONOS device. The present invention provides the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer in the charge trapping layer. Through the synergistic effect of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer, the programming / erasing efficiency of the SONOS device is improved, and the data retention performance (i.e., durability) of the SONOS device at high temperatures (e.g., 125° C.) is greatly improved, thereby achieving improved performance of the SONOS device and expanding its application fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly describes the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0026] Figure 1 is a schematic structural diagram of a SONOS device according to a specific embodiment of the present invention; Figure 2 is a performance comparison diagram of a SONOS device in a specific embodiment of the present invention and a SONOS device having only a single-layer charge trapping layer; Figure 3 is a flow chart of a method for manufacturing a SONOS device in a specific embodiment of the present invention; Figure 4 is a schematic structural diagram after a tunnel oxide layer is formed on a substrate in a specific embodiment of the present invention; Figure 5 is a schematic structural diagram of a specific embodiment of the present invention after a first silicon nitride layer is formed on the tunnel oxide layer; Figure 6 is a schematic structural diagram of a specific embodiment of the present invention after a second silicon nitride layer is formed on the first silicon nitride layer; Figure 7 is a schematic structural diagram of a specific embodiment of the present invention after a third silicon nitride layer is formed on the second silicon nitride layer; Figure 8 It is a schematic structural diagram of a specific embodiment of the present invention after a charge blocking layer is formed on the third silicon nitride layer.

[0027] Description of Reference Numerals 10 substrate 101 front 102 back 11 Tunneling oxide layer 12 first silicon nitride layer 13 Second silicon nitride layer 14Third silicon nitride layer 15 Charge blocking layer 16 Control gate layer DETAILED DESCRIPTION The specific embodiments of the SONOS device and the manufacturing method thereof provided by the present invention are described in detail below with reference to the accompanying drawings.

[0028] This specific embodiment provides a SONOS device, Figure 1 FIG. 1 is a schematic diagram of the structure of a SONOS device in a specific embodiment of the present invention. Figure 1 As shown, the SONOS device includes: The substrate 10 includes a front surface 101 and a back surface 102 that are opposite to each other along a first direction D1; a tunneling oxide layer 11 covering the front surface 101 of the substrate 10; a charge trapping layer, comprising a first silicon nitride layer 12, a second silicon nitride layer 13, and a third silicon nitride layer 14 stacked sequentially along the first direction D1 on a surface of the tunneling oxide layer 11 facing away from the substrate 10, wherein the oxygen content of the first silicon nitride layer 12 is greater than the oxygen content of the third silicon nitride layer 14, the dielectric constant of the second silicon nitride layer 13 is greater than the dielectric constant of the third silicon nitride layer 14, and the third silicon nitride layer 14 is used to prevent charges in the second silicon nitride layer 13 from diffusing outward; The charge blocking layer 15 is located on a surface of the third silicon nitride layer 14 facing away from the second silicon nitride layer 13 .

[0029] For example, the substrate 10 is a silicon substrate, and includes a front surface 101 and a back surface 102 that are oppositely distributed along the first direction D1. The substrate 10 includes an active region, which includes a channel region and a source region and a drain region that are distributed on opposite sides of the channel region along a second direction D2. The second direction D2 is parallel to the front surface 101 of the substrate 10. The tunneling oxide layer 11 can be made of silicon dioxide and covers the channel region of the substrate 10. The charge trapping layer includes a first silicon nitride layer 12 located on a surface of the tunneling oxide layer 11 facing away from the substrate 10, a second silicon nitride layer 13 located on a surface of the first silicon nitride layer 12 facing away from the tunneling oxide layer 11, and a third silicon nitride layer 14 located on a surface of the second silicon nitride layer 13 facing away from the first silicon nitride layer 12. That is, the charge trapping layer is a multi-layer stacked structure and includes at least the first silicon nitride layer 12, the second silicon nitride layer 13, and the third silicon nitride layer 14. The charge blocking layer 15 is located on a surface of the charge trapping layer facing away from the tunneling oxide layer 11. In one example, the material of the charge blocking layer 15 is also silicon dioxide. The tunneling oxide layer 11, the charge trapping layer, and the charge blocking layer 15 together constitute an ONO structure.

[0030] In this specific embodiment, the charge trapping layer is configured as a multilayer structure comprising at least the first silicon nitride layer 12, the second silicon nitride layer 13, and the third silicon nitride layer 14. This reduces the barrier height during electron tunneling through the first silicon nitride layer 12, which has a higher oxygen content, thereby improving programming / erase efficiency. This also improves interface quality and reduces interface state density, thereby reducing the negative impact of charge injection on the reliability of the SONOS device. The second silicon nitride layer 13, with its higher dielectric constant, increases the charge trapping density, making it easier for charge to be stored in the second silicon nitride layer 13, thereby improving the durability of the non-volatile memory cell. The third silicon nitride layer 14 prevents charge from being lost to upper layers or the external environment, and its uniformity and high density enhance the structural stability of the SONOS device. In this specific embodiment, the first silicon nitride layer 12, the second silicon nitride layer 13, and the third silicon nitride layer 14 are provided in the charge trapping layer. Through the synergistic effect of the first silicon nitride layer 12, the second silicon nitride layer 13, and the third silicon nitride layer 14, the operating voltage thereof is increased by 0.6V to 1V compared with the operating voltage of a conventional SONOS device, and the data retention performance of the SONOS device at high temperature (e.g., 125°C) is greatly improved, thereby achieving improvement in the performance of the SONOS device and expansion of its application fields.

[0031] Figure 2 1 is a performance comparison diagram of a SONOS device in a specific embodiment of the present invention and a SONOS device having only a single-layer charge trapping layer. Figure 2 The blue curve in the figure represents the data retention performance curve for a conventional SONOS device (i.e., the charge trapping layer comprises only a single silicon nitride layer), while the green curve represents the data retention performance curve for a SONOS device according to this embodiment (i.e., the charge trapping layer comprises the first silicon nitride layer 12, the second silicon nitride layer 13, and the third silicon nitride layer 14). After baking the conventional SONOS device and the SONOS device according to this embodiment at 125°C for 150 hours, the programming voltage of the SONOS device according to this embodiment decreased by approximately 15%, while the programming voltage of the conventional SONOS device decreased by approximately 30%. This demonstrates that the data retention performance of the SONOS device according to this embodiment has been significantly improved.

[0032] In some embodiments, the first silicon nitride layer 12 directly covers the surface of the tunneling oxide layer 11 facing away from the substrate 10, the second silicon nitride layer 13 directly covers the surface of the first silicon nitride layer 12, and the third silicon nitride layer 14 directly covers the surface of the second silicon nitride layer 13.

[0033] Specifically, the charge capture layer includes only the first silicon nitride layer 12, the second silicon nitride layer 13 directly covering the surface of the first silicon nitride layer 12, and the third silicon nitride layer 14 directly covering the surface of the second silicon nitride layer 13, thereby improving the data retention performance of the SONOS device at high temperature and avoiding the charge capture layer being too thick and affecting the gate control performance of the SONOS device.

[0034] In some embodiments, the second silicon nitride layer 13 includes a doping element, and the doping element is any one of hafnium, aluminum, lanthanum, zirconium, titanium, and strontium, or a combination of two or more thereof.

[0035] For example, by doping the second silicon nitride layer 13 with any one of hafnium, aluminum, lanthanum, zirconium, titanium, and strontium, or a combination of two or more, the dielectric constant of the second silicon nitride layer 13 can be significantly increased, simplifying the process and facilitating mass production. Furthermore, by adjusting the type and concentration of the doping element in the second silicon nitride layer 13, the dielectric constant of the second silicon nitride layer 13 can be flexibly adjusted, thereby increasing the flexibility of SONOS device manufacturing. In one example, the doping element is hafnium.

[0036] In some embodiments, the density of the third silicon nitride layer 14 is greater than the density of the second silicon nitride layer 13 .

[0037] Specifically, by increasing the density of the third silicon nitride layer 14, on the one hand, the charge stored in the second silicon nitride layer 13 can be prevented from being lost to the upper layer or the external environment, thereby improving the structural stability of the SONOS device; on the other hand, the third silicon nitride layer 14 with a higher density can also block the doping elements in the second silicon nitride layer 13 from diffusing outward, thereby maintaining the dielectric constant of the second silicon nitride layer 13 stable, thereby further improving the data retention performance of the SONOS device at high temperatures.

[0038] In some embodiments, the oxygen content in the first silicon nitride layer 12 is 4%-5%.

[0039] The oxygen content of the first silicon nitride layer 12 refers to the atomic percentage of oxygen atoms in the first silicon nitride layer 12. By setting the oxygen content of the first silicon nitride layer 12 to 4% to 5%, on the one hand, by increasing the oxygen content in the first silicon nitride layer 12, the barrier height during electron tunneling can be reduced, thereby improving programming / erase efficiency. At the same time, the interface quality can be improved and the interface state density can be reduced, thereby reducing the negative impact of the charge injection process on the reliability of the SONOS device. On the other hand, the increase in leakage current caused by excessively high oxygen content in the first silicon nitride layer 12 can also be avoided.

[0040] In some embodiments, the total thickness of the charge trapping layer is 80 Å to 90 Å.

[0041] For example, the sum of the thickness of the first silicon nitride layer 12 along the first direction D1, the thickness of the second silicon nitride layer 13 along the first direction D1, and the thickness of the third silicon nitride layer 14 along the first direction D1 is 80 Å to 90 Å.

[0042] In some embodiments, the thickness of the first silicon nitride layer 12 is 30 Å to 40 Å, and the thickness of the second silicon nitride layer 13 is 30 Å to 40 Å, so as to improve the data retention capability of the SONOS device while improving the response speed of programming and erasing of the SONOS device.

[0043] In some embodiments, the SONOS device further comprises: The control gate layer 16 covers the surface of the charge blocking layer 15 facing away from the charge trapping layer, and the material of the control gate layer 16 includes polysilicon.

[0044] This specific embodiment also provides a method for manufacturing a SONOS device. Figure 3 This is a flow chart of the method for manufacturing a SONOS device in a specific embodiment of the present invention. The structural diagram of the SONOS device manufactured in this specific embodiment can be found in Figure 1 .like Figure 1 and Figure 3 As shown, the manufacturing method of the SONOS device includes the following steps: Step S31, forming a substrate 10, wherein the substrate 10 includes a front surface 101 and a back surface 102 that are oppositely distributed along a first direction D1; Step S32, forming a tunneling oxide layer 11 on the front surface 101 of the substrate 10; Step S33: forming a charge trapping layer on the tunneling oxide layer 11, the charge trapping layer comprising a first silicon nitride layer 12, a second silicon nitride layer 13, and a third silicon nitride layer 14 stacked in sequence along the first direction D1 on a surface of the tunneling oxide layer 11 facing away from the substrate 10, the oxygen content of the first silicon nitride layer 12 being greater than the oxygen content of the third silicon nitride layer 14, the dielectric constant of the second silicon nitride layer 13 being greater than the dielectric constant of the third silicon nitride layer 14, and the third silicon nitride layer 14 being used to prevent charges in the second silicon nitride layer 13 from diffusing outward; In step S34 , a charge blocking layer 15 is formed on a surface of the third silicon nitride layer 14 facing away from the second silicon nitride layer 13 .

[0045] Figure 4 1 is a schematic diagram of a structure after a tunneling oxide layer is formed on a substrate in a specific embodiment of the present invention. In some embodiments, the material of the substrate 10 includes silicon; the specific steps of forming the tunneling oxide layer on the front surface of the substrate include: The tunnel oxide layer 11 is formed on the front surface 101 of the substrate 10 by an in-situ water vapor generation process.

[0046] For example, the substrate 10 includes the front surface 101 and the back surface 102 that are relatively distributed along the first direction D1. The substrate 10 includes an active region, which includes a channel region and a source region and a drain region distributed on opposite sides of the channel region along a second direction D2. The second direction D2 is parallel to the front surface 101 of the substrate 10. An in-situ water vapor generation process is used to oxidize a portion of the substrate 10 starting from the front surface 101 of the substrate 10 to form the tunneling oxide layer 11 made of silicon dioxide and located above the channel region, as shown in FIG. Figure 4 In one example, the thickness of the tunnel oxide layer 11 along the first direction D1 is 15 Å to 20 Å.

[0047] In some embodiments, the specific steps of forming the charge trapping layer on the tunneling oxide layer 11 include: forming the first silicon nitride layer 12 on the substrate 10 and directly covering the surface of the tunnel oxide layer 11; forming a second silicon nitride layer 13 directly covering a surface of the first silicon nitride layer 12 facing away from the tunnel oxide layer 11; A third silicon nitride layer 14 is formed directly covering the surface of the second silicon nitride layer 13 facing away from the first silicon nitride layer 12 .

[0048] Figure 5Schematic diagram of the structure after forming the first silicon nitride layer on the tunnel oxide layer according to a specific embodiment of the present invention. In some embodiments, the specific steps of forming the first silicon nitride layer 12 directly covering the surface of the tunnel oxide layer 11 on the substrate 10 include: A silicon source gas, a nitrogen source gas, and an oxygen source gas are transported onto the substrate 10 to form the first silicon nitride layer 12 having an oxygen content of 4% to 5%.

[0049] In some embodiments, the silicon source gas includes SiH2Cl2, the nitrogen source gas includes NH3, and the oxygen source gas includes N2O.

[0050] In one example, the first silicon nitride layer 12 can be formed using a low-pressure chemical vapor deposition process to flexibly adjust the oxygen content in the first silicon nitride layer 12. For example, after forming the tunneling oxide layer 11, the silicon source gas (e.g., SiH2Cl2) and the nitrogen source gas (e.g., NH3) are transferred to the substrate 10, and the flow ratio of the silicon source gas to the nitrogen source gas is controlled to be ‌6:1‌, and the oxygen source gas (e.g., N2O) is simultaneously transferred to the substrate 10, thereby forming the oxygen-rich first silicon nitride layer 12, as shown in FIG. Figure 5 Wherein, the oxygen source gas transmission flow rate can be 100 sccm~150 sccm.

[0051] Figure 6 1 is a schematic diagram of the structure after forming a second silicon nitride layer on the first silicon nitride layer in a specific embodiment of the present invention. In some embodiments, the specific steps of forming the second silicon nitride layer 13 directly covering the surface of the first silicon nitride layer 12 facing away from the tunneling oxide layer 11 include: The silicon source gas, the nitrogen source gas and the doping source gas are transported onto the substrate 10 to form the second silicon nitride layer 13 including doping elements, such as Figure 6 As shown, the doping element is any one of hafnium, aluminum, lanthanum, zirconium, titanium and strontium, or a combination of two or more thereof.

[0052] In one example, the first silicon nitride layer 12 can be formed using an atmospheric pressure chemical vapor deposition process. For example, after forming the oxygen-rich first silicon nitride layer 12, the silicon source gas (e.g., SiH2Cl2) and the nitrogen source gas (e.g., NH3) are continuously delivered to the substrate 10, and hafnium tetrachloride or an organic hafnium precursor is simultaneously introduced as the dopant source gas. The dopant source gas decomposes to generate the dopant element. The flow rate of the dopant source gas is controlled between 5 sccm and 10 sccm, and the dopant source gas accounts for 2% of the total gas flow rate (the total gas includes the silicon source gas, the nitrogen source gas, and the dopant source gas), so as to control the doping concentration of the dopant element in the second silicon nitride layer 13.

[0053] In some embodiments, the thickness of the first silicon nitride layer 12 is 30 Å to 40 Å, and the thickness of the second silicon nitride layer 13 is 30 Å to 40 Å, so as to improve the data retention capability of the SONOS device while improving the response speed of programming and erasing of the SONOS device.

[0054] Figure 7 Schematic diagram of the structure after forming a third silicon nitride layer on the second silicon nitride layer according to a specific embodiment of the present invention. Figure 7 As shown, the specific steps of forming the third silicon nitride layer 14 directly covering the surface of the second silicon nitride layer 13 facing away from the first silicon nitride layer 12 include: The silicon source gas and the nitrogen source gas are transported onto the substrate 10 to form the third silicon nitride layer 14 , and the density of the third silicon nitride layer 14 is greater than the density of the second silicon nitride layer 13 .

[0055] Figure 8 FIG. 1 is a schematic diagram of a structure after a charge blocking layer is formed on the third silicon nitride layer according to a specific embodiment of the present invention. Figure 8 As shown, the specific steps of forming the charge blocking layer 15 on the surface of the third silicon nitride layer 14 away from the second silicon nitride layer 13 include: A portion of the third silicon nitride layer 14 is oxidized by an in-situ water vapor generation process to form the charge blocking layer 15 .

[0056] In some embodiments, the total thickness of the charge trapping layer is 80 Å to 90 Å.

[0057] For example, after forming the second silicon nitride layer 13 having a high dielectric constant, the silicon source gas and the nitrogen source gas are transferred to the substrate 10, and the third silicon nitride layer 14 with a higher density is formed by a low pressure chemical vapor deposition process, as shown in FIG. Figure 7The thickness of the third silicon nitride layer 14 along the first direction D1 is 60 Å to 70 Å. Afterwards, a portion of the third silicon nitride layer 14 is oxidized by an in-situ water vapor generation process to form the charge blocking layer 15, as shown. Figure 8 As shown, the total thickness of the remaining third silicon nitride layer 14, the first silicon nitride layer 12 and the second silicon nitride layer 13 is 80 Å to 90 Å. Then, polysilicon is deposited on the surface of the charge blocking layer 15 away from the third silicon nitride layer 14 to form the control gate layer 16, as shown. Figure 1 shown.

[0058] This embodiment provides a SONOS device and a manufacturing method thereof. A charge trapping layer comprises a first silicon nitride layer, a second silicon nitride layer, and a third silicon nitride layer stacked sequentially along a first direction on a surface of the tunneling oxide layer facing away from the substrate. The first silicon nitride layer has a greater oxygen content than the third silicon nitride layer, and the second silicon nitride layer has a greater dielectric constant than the third silicon nitride layer. The third silicon nitride layer is used to block outward diffusion of charge from the second silicon nitride layer. This reduces the barrier height during electron tunneling through the first silicon nitride layer, which has a higher oxygen content, thereby improving programming / erase efficiency. Furthermore, the device improves interface quality and reduces interface state density, thereby reducing the negative impact of charge injection on the reliability of the SONOS device. The higher dielectric constant of the second silicon nitride layer increases the charge trapping density, making it easier for charge to be stored in the second silicon nitride layer, thereby improving the durability of the non-volatile memory cell. The third silicon nitride layer prevents charge from being lost to upper layers or the external environment. Its uniformity and high density enhance the structural stability of the SONOS device. In this specific embodiment, the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer are provided in the charge trapping layer. Through the synergistic effect of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer, the programming / erase efficiency of the SONOS device is improved, and the data retention performance (i.e., endurance performance) of the SONOS device at high temperatures (e.g., 125° C.) is greatly improved, thereby achieving improvement in the performance of the SONOS device and expansion of its application fields.

[0059] It should be noted that the terms "including," "having," and their variations, as used in this document, are intended to cover non-exclusive inclusions. Terms such as "first," "second," and the like are used to distinguish similar items and are not necessarily used to describe a specific order or precedence, unless the context clearly indicates otherwise. Such usage should be understood to be interchangeable where appropriate. The term "one or more" may be used to describe a feature, structure, or characteristic in the singular, or in the plural, depending at least in part on the context, to describe a feature, structure, or combination of features. The term "based on" should be understood as not necessarily intended to express an exclusive set of factors, but may alternatively, also depending at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described. Furthermore, the embodiments of the present invention and the features therein may be combined with one another, unless there is a conflict. Furthermore, descriptions of well-known components and technologies have been omitted from the above description to avoid unnecessary confusion regarding the concepts of the present invention. In each of the above embodiments, each embodiment focuses on its differences from the other embodiments, and reference may be made to the same or similar parts between the embodiments.

[0060] The above description is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A SONOS device, characterized in that: include: a substrate comprising a front surface and a back surface oppositely distributed along a first direction; a tunneling oxide layer covering the front surface of the substrate; a charge trapping layer, comprising a first silicon nitride layer, a second silicon nitride layer, and a third silicon nitride layer stacked sequentially along the first direction on a surface of the tunneling oxide layer facing away from the substrate, wherein the oxygen content of the first silicon nitride layer is greater than the oxygen content of the third silicon nitride layer, the dielectric constant of the second silicon nitride layer is greater than the dielectric constant of the third silicon nitride layer, and the third silicon nitride layer is used to prevent charges in the second silicon nitride layer from diffusing outward; The charge blocking layer is located on a surface of the third silicon nitride layer facing away from the second silicon nitride layer.

2. The SONOS device according to claim 1, wherein: The first silicon nitride layer directly covers the surface of the tunnel oxide layer facing away from the substrate, the second silicon nitride layer directly covers the surface of the first silicon nitride layer, and the third silicon nitride layer directly covers the surface of the second silicon nitride layer.

3. The SONOS device according to claim 1, wherein: The second silicon nitride layer includes a doping element, and the doping element is any one of hafnium, aluminum, lanthanum, zirconium, titanium and strontium, or a combination of two or more of the elements.

4. The SONOS device according to claim 1, wherein: The density of the third silicon nitride layer is greater than the density of the second silicon nitride layer.

5. The SONOS device according to claim 1, wherein: The oxygen content in the first silicon nitride layer is 4% to 5%.

6. The SONOS device according to claim 1, wherein: The total thickness of the charge trapping layer is 80Å~90Å.

7. The SONOS device according to claim 1, wherein: The thickness of the first silicon nitride layer is 30Å~40Å, and the thickness of the second silicon nitride layer is 30Å~40Å.

8. The SONOS device according to claim 1, wherein: Also includes: The control gate layer covers the surface of the charge blocking layer away from the charge trapping layer, and the material of the control gate layer includes polysilicon.

9. A method for manufacturing a SONOS device, characterized in that: The steps include: forming a substrate, the substrate comprising a front surface and a back surface oppositely distributed along a first direction; forming a tunneling oxide layer on the front surface of the substrate; forming a charge trapping layer on the tunneling oxide layer, the charge trapping layer comprising a first silicon nitride layer, a second silicon nitride layer, and a third silicon nitride layer stacked sequentially along the first direction on a surface of the tunneling oxide layer facing away from the substrate, the first silicon nitride layer having a greater oxygen content than the third silicon nitride layer, the second silicon nitride layer having a greater dielectric constant than the third silicon nitride layer, and the third silicon nitride layer being used to prevent charges in the second silicon nitride layer from diffusing outward; A charge blocking layer is formed on a surface of the third silicon nitride layer facing away from the second silicon nitride layer.

10. The method for manufacturing a SONOS device according to claim 9, wherein: The material of the substrate includes silicon; and the specific steps of forming a tunneling oxide layer on the front surface of the substrate include: The tunnel oxide layer is formed on the front surface of the substrate by an in-situ water vapor generation process.

11. The method for manufacturing a SONOS device according to claim 9, wherein: The specific steps of forming a charge trapping layer on the tunneling oxide layer include: forming the first silicon nitride layer on the substrate directly covering the surface of the tunnel oxide layer; forming a second silicon nitride layer directly covering a surface of the first silicon nitride layer facing away from the tunnel oxide layer; A third silicon nitride layer is formed directly covering a surface of the second silicon nitride layer facing away from the first silicon nitride layer.

12. The method for manufacturing a SONOS device according to claim 11, wherein: The specific steps of forming the first silicon nitride layer on the substrate directly covering the surface of the tunnel oxide layer include: A silicon source gas, a nitrogen source gas, and an oxygen source gas are transported onto the substrate to form the first silicon nitride layer having an oxygen content of 4% to 5%.

13. The method for manufacturing a SONOS device according to claim 12, wherein: The silicon source gas includes SiH2Cl2, the nitrogen source gas includes NH3, and the oxygen source gas includes N2O.

14. The method for manufacturing a SONOS device according to claim 12, wherein: The specific steps of forming a second silicon nitride layer directly covering the surface of the first silicon nitride layer facing away from the tunnel oxide layer include: The silicon source gas, the nitrogen source gas and the doping source gas are transported onto the substrate to form the second silicon nitride layer including a doping element, wherein the doping element is any one of hafnium, aluminum, lanthanum, zirconium, titanium and strontium, or a combination of two or more thereof.

15. The method for manufacturing a SONOS device according to claim 12, wherein: The thickness of the first silicon nitride layer is 30Å~40Å, and the thickness of the second silicon nitride layer is 30Å~40Å.

16. The method for manufacturing a SONOS device according to claim 12, wherein: The specific steps of forming a third silicon nitride layer directly covering the surface of the second silicon nitride layer facing away from the first silicon nitride layer include: The silicon source gas and the nitrogen source gas are transported onto the substrate to form the third silicon nitride layer, wherein the density of the third silicon nitride layer is greater than the density of the second silicon nitride layer.

17. The method for manufacturing a SONOS device according to claim 16, wherein: The specific steps of forming a charge blocking layer on a surface of the third silicon nitride layer facing away from the second silicon nitride layer include: An in-situ water vapor generation process is used to oxidize a portion of the third silicon nitride layer to form the charge blocking layer.

18. The method for manufacturing a SONOS device according to claim 9, wherein: The total thickness of the charge trapping layer is 80Å~90Å.

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