Semiconductor structure and forming method thereof
By sharing the first source-drain doping region and the second gate structure in a semiconductor structure, the problem of low storage density of a charge trapping type flash memory is solved, and the storage density is improved.
Patent Information
- Application Number
- CN202510776747.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-11
- Publication Date
- 2025-09-09
AI Technical Summary
The storage density of existing charge trap flash memories is relatively low.
By forming an electron capture layer covering the sidewalls and top of the first gate structure in the semiconductor structure, and removing part of the electron capture layer between the paired first gate structures to expose the substrate surface, a first source-drain doped region is formed, and a second gate structure is formed above it, so that the first source-drain doped region and the second gate structure are shared, thereby reducing the area of a single storage area.
The storage density is improved, the area of the storage area is reduced, and the storage density of the storage device is enhanced.
Smart Images
Figure CN120614830A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art
[0002] Charge-Trapping-Memory (CTM) is a non-volatile memory with silicon nitride as its main storage medium. It has good anti-erasure and write resistance, low operating voltage and low power consumption, and its process is simple and compatible with standard complementary metal oxide semiconductor (CMOS) technology, so it is widely used.
[0003] However, existing devices have low storage density. Summary of the Invention
[0004] The problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve storage density.
[0005] The present invention provides a method for forming a semiconductor structure, comprising: providing a substrate having a pair of first gate structures on the substrate; forming an electron capture layer on the substrate, the electron capture layer covering the sidewalls and top of the first gate structure; removing at least a portion of the electron capture layer between the pair of first gate structures to expose the surface of the substrate; forming a first source-drain doped region in the exposed substrate located between the pair of first gate structures; forming a second gate structure above the first source-drain doped region, the second gate structure covering at least the sidewalls and surface of the electron capture layer; and forming a second source-drain doped region in the substrate on a side of the first gate structure away from the second gate structure.
[0006] Optionally, before removing at least a portion of the electron-trapping layer between the pair of first gate structures, the forming method further comprises: forming a hard mask layer on the substrate, wherein the hard mask layer covers the electron-trapping layer and has a trench between the hard mask layers, wherein the trench is located between the pair of first gate structures;
[0007] The step of removing at least a portion of the electron-trapping layer between the pair of first gate structures to expose the surface of the substrate comprises: removing the hard mask layer and the electron-trapping layer above the top of the first gate structure, and the hard mask layer exposed by the trench and the electron-trapping layer below the hard mask layer, to expose the surface of the substrate between the pair of first gate structures and the top of the first gate structure;
[0008] After the surface of the substrate is exposed, the first source-drain doping region is formed, and then the remaining portion of the hard mask layer is removed.
[0009] Optionally, in the step of removing at least a portion of the electron-trapping layer between the pair of first gate structures, the method further comprises:
[0010] further removing a portion of the electron trapping layer on the other side of the first gate structure to expose a substrate surface for forming the second source-drain doped region;
[0011] Using a first etching process, the hard mask layer and the electron capture layer above the top of the first gate structure, as well as the hard mask layer exposed by the trench and the electron capture layer below the hard mask layer are removed;
[0012] A second etching process is used to remove the remaining portion of the hard mask layer, where the first etching process is different from the second etching process.
[0013] Optionally, the step of forming an electron capture layer on the substrate includes:
[0014] forming a tunneling oxide layer on the substrate that conformally covers the sidewalls and top of the first gate structure;
[0015] forming a charge storage layer on the substrate conformally covering the tunneling oxide layer;
[0016] forming a blocking layer on the substrate conformally covering the charge storage layer;
[0017] Wherein, the tunneling oxide layer, the charge storage layer and the blocking layer serve as the electron trapping layer.
[0018] Optionally, in the step of removing at least a portion of the electron-trapping layer between the pair of first gate structures, an opening is provided in the electron-trapping layer, and the opening exposes the surface of the substrate;
[0019] Before forming the second gate structure, the forming method further includes: forming a second gate oxide layer in the opening;
[0020] In the step of forming the second gate structure, the second gate structure also covers the second gate oxide layer, or, in the step of forming the second gate structure, the second gate structure covers the sidewall and surface of the electron trapping layer and covers a portion of the second gate oxide layer.
[0021] Optionally, in the step of forming the second gate structure above the first source / drain doped region, an electron trapping layer on a side of the first gate structure away from the first source / drain doped region is further removed to expose a substrate surface for forming the second source / drain doped region;
[0022] Before forming the second source-drain doped region, the forming method further includes: forming a sidewall spacer on the sidewall of the exposed electron capture layer;
[0023] A first gate oxide layer is provided between the substrate and the first gate structure.
[0024] Optionally, the first gate structure is a selection gate, the second gate structure is a control gate, the first source-drain doped region is a source, and the second source-drain doped region is a drain.
[0025] Correspondingly, the present invention also provides a semiconductor structure comprising: a substrate; a pair of first gate structures located on the substrate; a first source-drain doped region located in the substrate between the pair of first gate structures; an electron-trapping layer covering the sidewalls of each first gate structure and the substrate between the pair of first gate structures, and exposing a portion of the surface of the first source-drain doped region; a second gate structure located on the substrate between the pair of first gate structures and covering at least the sidewalls and surface of the electron-trapping layer; a second source-drain doped region located in the substrate on a side of the first gate structure away from the second gate structure
[0026] Optionally, the semiconductor structure further comprises:
[0027] a first gate oxide layer, located between the substrate and the first gate structure;
[0028] a second gate oxide layer, located on the substrate and in contact with a portion of the sidewall of the electron-trapping layer and a bottom of the second gate structure;
[0029] The sidewall is located on the substrate and covers the sidewall of the electron trapping layer close to the second source-drain doped region.
[0030] Optionally, the first gate structure is a selection gate, the second gate structure is a control gate, the first source-drain doped region is a source, and the second source-drain doped region is a drain.
[0031] Optionally, the electron-trapping layer comprises:
[0032] a tunneling oxide layer, located on the substrate and covering sidewalls of each first gate structure;
[0033] a charge storage layer covering the sidewalls and surface of the tunnel oxide layer;
[0034] The blocking layer covers the sidewalls and the surface of the charge storage layer.
[0035] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0036] In the method for forming a semiconductor structure provided by the present invention, after forming an electron-trapping layer covering the sidewalls and top of a first gate structure, at least a portion of the electron-trapping layer between the paired first gate structures is removed to expose the surface of the substrate, thereby forming a first source-drain doped region within the substrate between the paired first gate structures. Furthermore, by forming a second gate structure above the first source-drain doped region, with the second gate structure covering at least the sidewalls and surface of the electron-trapping layer, the first source-drain doped region and the second gate structure are shared, thereby reducing the area of a single storage region and thereby improving storage density.
[0037] In the semiconductor structure provided by the present invention, the first source-drain doped region is located in the substrate between the paired first gate structures, and the second gate structure is located on the substrate between the paired first gate structures and at least covers the sidewalls and surface of the electron capture layer, thereby realizing the sharing of the first source-drain doped region and the second gate structure, which can reduce the area of a single storage area and thus improve the storage density. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figures 1 to 9 1 is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention;
[0039] Figure 10 1 is a schematic structural diagram corresponding to each step in the second embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0040] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.
[0041] As described in the background art, the storage density of the charge trap flash memory is relatively low.
[0042] Specifically, different storage areas in a charge trap flash memory are independent of each other. Under a certain unit size, the number of storage areas formed is small, resulting in low storage density.
[0043] To address the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure. After forming an electron-trapping layer covering the sidewalls and top of a first gate structure, at least a portion of the electron-trapping layer is removed between the paired first gate structures to expose the surface of the substrate, thereby forming a first source-drain doped region within the substrate between the paired first gate structures. Furthermore, by forming a second gate structure above the first source-drain doped region, with the second gate structure covering at least the sidewalls and surface of the electron-trapping layer, the first source-drain doped region and the second gate structure are shared. This reduces the area of a single storage region, thereby improving storage density.
[0044] Specifically, the electron capture layer in this embodiment can be an oxide-nitride-oxide (ONO) structure, and the ONO structure can serve as a dielectric for storing charge. By applying a positive voltage to the first gate structure, the second gate structure, and the drain in the semiconductor structure, and grounding the source, the voltages at these three ends generate two electric fields, one in the vertical channel direction and the other in the horizontal direction along the channel. Under the action of the horizontal electric field, the electrons in the channel accelerate along the channel. When the electrons obtain sufficient energy, they can enter the nitride layer under the action of the vertical channel electric field and be stored in an area near the source.
[0045] In this way, by sharing the first source-drain doping region and the second gate structure, the area of the storage region can be reduced, thereby improving the storage density.
[0046] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are exemplarily described below with reference to the accompanying drawings.
[0047] Figures 1 to 9 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
[0048] See also Figure 1 , providing a substrate 100 having a pair of first gate structures 106 thereon.
[0049] In this embodiment, the substrate 100 may provide a process operation basis for a semiconductor structure formation process, wherein the semiconductor structure may include a fin field effect transistor (FinFET) or a gate all around transistor (GAA).
[0050] In this embodiment, the material of substrate 100 includes silicon. In other embodiments, substrate 100 may be made of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. Substrate 100 may also be other types of substrates, such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of substrate 100 may be a material suitable for process requirements or easy to integrate.
[0051] In some embodiments, the base may further include a substrate, a plurality of discrete fins located above the substrate, and an isolation structure located on the substrate where the fins are exposed. The isolation structure may cover part of the sidewalls of the fins, and the top of the isolation structure is lower than the top of the fins.
[0052] In this embodiment, the isolation structure serves to electrically isolate adjacent transistors.
[0053] In some embodiments, the isolation structure may be made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride.
[0054] In this embodiment, the material of the isolation structure may be silicon oxide.
[0055] In this embodiment, in the step of providing the substrate 100 , a well region 102 is further formed in the substrate 100 .
[0056] By adjusting the doping concentration of the well region 102 , the threshold voltage can be adjusted to ensure that the transistor can be normally turned on or off during programming / erase operations.
[0057] The first gate structure 106 is a selection gate SG, which plays a role in selection. When the voltage applied to the selection gate SG is greater than the threshold voltage, a channel between the source and drain doping regions is formed on the surface of the well region 102 covered by the selection gate SG. Figure 7 )When the operating voltage is applied, the entire channel between the source and the drain is turned on.
[0058] In this embodiment, the steps of forming the first gate structure 106 include: forming a first gate material layer (not shown) on the substrate 100; performing patterning processing to remove part of the first gate material layer to expose the surface of the substrate 100, and the remaining part of the first gate material layer serves as the first gate structure 106.
[0059] In this embodiment, the material of the first gate structure 106 is polysilicon.
[0060] See next Figure 1 In the step of providing the substrate 100 , a first gate oxide layer 104 is further provided between the substrate 100 and the first gate structure 106 .
[0061] The first gate oxide layer 104 serves as an insulating layer to isolate the first gate structure 106 from the substrate 100 . By adjusting the thickness of the first gate oxide layer 104 , the threshold voltage and the electric field strength in the channel can be adjusted.
[0062] In this embodiment, the first gate oxide layer 104 is formed in the step of forming the first gate structure 106 .
[0063] For example, a first gate oxide material layer (not shown) is formed on the substrate 100 , and the first gate material layer is located on the first gate oxide material layer; and a patterning process is performed to form the first gate oxide layer 104 .
[0064] See also Figure 2 , an electron capture layer 114 is formed on the substrate 100 , and the electron capture layer 114 covers the sidewalls and the top of the first gate structure 106 .
[0065] The electron-trapping layer 114 as a whole functions as a data storage layer.
[0066] In this embodiment, the step of forming the electron capture layer 114 on the substrate 100 may include:
[0067] A tunneling oxide layer 108 is formed on the substrate 100 to conformally cover the sidewalls and top of the first gate structure 106 .
[0068] The tunnel oxide layer 108 is used to allow charges to be injected or escaped through the quantum tunneling effect.
[0069] In this embodiment, the tunnel oxide layer 108 is formed by using an atomic layer deposition process and / or a low pressure chemical vapor deposition process.
[0070] In this embodiment, the material of the tunnel oxide layer 108 may include silicon oxide. Selecting silicon oxide as the material for the tunnel oxide layer 108 can improve process compatibility and reduce process risks. Furthermore, compared to organic materials, silicon oxide has greater hardness and density, which helps improve the protective effect of the tunnel oxide layer 108 on the surface of the substrate 100.
[0071] In one embodiment, the tunnel oxide layer 108 is made of silicon oxide. Silicon oxide has good adhesion to the substrate 100, which helps improve the stability and processing performance of subsequent processes. Furthermore, silicon oxide is a commonly used silicon oxide in semiconductor processes, which can reduce the difficulty and process cost of forming the tunnel oxide layer 108 and improve process compatibility.
[0072] See also Figure 2 The tunnel oxide layer 108 also covers the sidewalls of the first gate oxide layer 104 .
[0073] A charge storage layer 110 is formed on the substrate 100 and conformally covers the tunnel oxide layer 108 .
[0074] The charge storage layer 110 is used to capture and store charges (electrons or holes). By adjusting the composition and thickness of the charge storage layer 110 , different charge storage capacities and charge retention times can be achieved.
[0075] In this embodiment, the charge storage layer 110 is formed by using an atomic layer deposition process and / or a low pressure chemical vapor deposition process.
[0076] In this embodiment, the material of the charge storage layer 110 is silicon nitride.
[0077] A blocking layer 112 is formed on the substrate 100 to conformally cover the charge storage layer 110 .
[0078] The blocking layer 112 is used to prevent charges from leaking from the charge storage layer 110 to the second gate structure 124 (see Figure 7 ).
[0079] In this embodiment, the barrier layer 112 is formed by using an atomic layer deposition process and / or a low pressure chemical vapor deposition process.
[0080] In this embodiment, the material of the barrier layer 112 is silicon oxide.
[0081] In this embodiment, the tunneling oxide layer 108 , the charge storage layer 110 , and the blocking layer 112 serve as the electron trapping layer 114 .
[0082] See also Figures 3 and 4 At least a portion of the electron trapping layer 114 between the pair of first gate structures 106 is removed to expose the surface of the substrate 100 .
[0083] By exposing the surface of the substrate 100, the first source-drain doped region 118 (see Figure 6 ) provides process space, which is beneficial to reducing the difficulty of forming the first source and drain doping region 118.
[0084] See also Figure 3 Before removing at least a portion of the electron-trapping layer 114 between the pair of first gate structures 106 , the forming method further includes:
[0085] A hard mask layer 116 is formed on the substrate 100 . The hard mask layer 116 covers the electron trapping layer 114 . A trench G is defined between the hard mask layers 116 . The trench G is located between the pair of first gate structures 106 .
[0086] More specifically, the hard mask layer 116 covers the top surface of the barrier layer 112 .
[0087] By forming the hard mask layer 116, on the one hand, a spatial position can be pre-occupied for forming the second gate structure 124; on the other hand, by ensuring that the hard mask layer 116 and the barrier layer 112 have an etching selectivity, only a portion of the electron capture layer 114 can be removed, so that the retained electron capture layer 114 can play a charge storage role.
[0088] In this embodiment, a deposition process is used to form a hard mask layer 116 on the electron trapping layer 114 .
[0089] It should be noted that in this embodiment, the hard mask layer 116 satisfies the following requirements: the thickness of the first portion located on the substrate 100 is the same as or substantially the same as the thickness of the second portion located on the electron-capturing layer 114; the width of the third portion between the first and second portions is the same; and the junction between the third and second portions has an arc-shaped slope. Thus, when the hard mask layer 116 is subsequently removed, the hard mask layer 116 on the substrate 100 and the electron-capturing layer 114 is removed, while the remaining portion of the hard mask layer 116 remains.
[0090] In this embodiment, the material of the hard mask layer 116 includes one or more of polysilicon, carbon, silicon nitride, and silicon oxynitride.
[0091] In one embodiment, the material of the hard mask layer 116 is silicon nitride.
[0092] See also Figure 4 The step of removing at least a portion of the electron-trapping layer 114 between the pair of first gate structures 106 to expose the surface of the substrate 100 includes:
[0093] The hard mask layer 116 and the electron-trapping layer 114 above the top of the first gate structure 106 are removed to expose the top of the first gate structure 106 and the hard mask layer 116 exposed by the trench G, and the electron-trapping layer 114 below the hard mask layer 116 to expose the surface of the substrate 100 between the pair of first gate structures 106 and the top of the first gate structure 106.
[0094] In other words, only the hard mask layer 116 covering the sidewalls of the electron-trapping layer 114 is retained, so that the remaining portion of the hard mask layer 116 covers the sidewalls and surface of the electron-trapping layer 114 .
[0095] By exposing the top of the first gate structure 106, on the one hand, it is helpful to reduce the difficulty of subsequently forming a contact plug electrically connected to the first gate structure 106; on the other hand, it is convenient to remove part of the electron capture layer 114 between the paired first gate structures 106, thereby exposing the surface of the substrate 100 and reducing the difficulty of forming the first source and drain doped region 118.
[0096] In this embodiment, a first etching process is used to remove the hard mask layer 116 and the electron capture layer 114 above the top of the first gate structure 106, exposing the top of the first gate structure 106, the hard mask layer 116 exposed by the trench G, and the electron capture layer 114 located below the hard mask layer 116.
[0097] In some embodiments, the first etching process can be a dry etching process. By using a dry etching process, the gas composition can be adjusted in real time to achieve etching selectivity between different layers of the electron-trapping layer 114. Furthermore, dry etching has anisotropic properties, allowing it to etch materials vertically, forming steep sidewall structures. The electron-trapping layer 114 is often used in memory devices, and this precise geometry can improve semiconductor storage stability.
[0098] See next Figure 4 In the step of removing at least a portion of the electron trapping layer 114 between the pair of first gate structures 106, a portion of the electron trapping layer 114 on the other side of the first gate structure 106 is also removed to expose the second source-drain doped region 128 (see Figure 9 ) substrate 100.
[0099] That is, in the same step, the substrate 100 for forming the first source / drain doping region 118 and the second source / drain doping region 128 is exposed, thereby simplifying the process steps.
[0100] See also Figure 5 , forming a first source-drain doped region 118 in the exposed substrate 100 between the pair of first gate structures 106 .
[0101] The first source / drain doped region 118 may be used as a source or a drain of a field effect transistor. When the field effect transistor is working, the first source / drain doped region 118 may be used to provide a carrier source.
[0102] In this embodiment, the first source-drain doped region 118 serves as a source. That is, the paired first gate structures 106 in this solution share a source. The reason for sharing the source is that, in this embodiment, the source is generally grounded. Therefore, by sharing the source, when one memory cell needs to be driven, another memory cell is not mistakenly driven, thereby achieving independent control of different memory cells.
[0103] In this embodiment, the first source / drain doped region 118 may include a stress layer doped with ions. The stress layer may be used to provide stress to the channel region, thereby improving carrier mobility.
[0104] Specifically, when forming an NMOS transistor, the first source / drain doping region 118 may include a stress layer doped with N-type ions, and the material of the stress layer may be Si or SiC; when forming a PMOS transistor, the first source / drain doping region 118 may include a stress layer doped with P-type ions, and the material of the stress layer may be Si or SiGe.
[0105] In this embodiment, an ion implantation process is used to form the first source / drain doped region 118 .
[0106] See also Figure 6 After the surface of the substrate 100 is exposed, the first source-drain doped region 118 is formed, and then the remaining portion of the hard mask layer 116 is removed.
[0107] In this embodiment, a second etching process is used to remove the remaining portion of the hard mask layer 116 .
[0108] In some embodiments, the second etching process may be a wet etching process, that is, the first etching process is different from the second etching process.
[0109] It should be noted that, in this embodiment, the first etching process is a dry etching process, and the second etching process is a wet etching process.
[0110] See next Figure 6 During the second etching process to remove the remaining portion of the hard mask layer 116, the electron capture layer 114 covering the sidewall of the first gate structure 106 is retained. This portion of the electron capture layer 114 can serve as an isolation structure to achieve isolation between the first gate structure 106 and the second gate structure 124, while at least reducing the step of forming the isolation structure again.
[0111] See also Figure 7 and Figure 8 A second gate structure 124 is formed above the first source / drain doped region 118 , and the second gate structure 124 at least covers the sidewalls and the surface of the electron trapping layer 114 .
[0112] The second gate structure 124 may serve as a control gate CG, which controls the conduction of the channel.
[0113] Specifically, when the voltage applied to the second gate structure 124 is greater than the threshold voltage (Vth), the channel below the second gate structure 124 is turned on, thereby forming a current path between the source and the drain.
[0114] In this embodiment, the second gate structure 124 , the first gate structure 106 and the electron-trapping layer 114 are used in combination to store data.
[0115] In some embodiments, when a high voltage is applied to the second gate structure 124, electrons are injected into the charge storage layer of the electron-trapping layer 114 through the tunneling effect, changing the threshold voltage of the device and storing data "1." When a reverse voltage is applied to the second gate structure 124, electrons are released from the charge storage layer, restoring the initial state and storing data "0."
[0116] Accordingly, during this process, the first gate structure 106 is used to select a specific cell in the memory array, avoiding interference with other cells and ensuring that only the target cell is operated.
[0117] In this embodiment, see Figure 7 and Figure 8 The steps of forming the second gate structure 124 may include: forming a second gate material layer 122 covering the first gate structure 106 and the electron capture layer 114 on the substrate 100; performing a dry etching process to remove the second gate material layer above the top of the first gate structure 106; removing the second gate material layer on the side of the first gate structure 106 away from the first source and drain doped region 118, and using the remaining portion of the second gate material layer 122 as the second gate structure 124.
[0118] It should be pointed out that in the step of removing the second gate material layer on the side of the first gate structure 106 away from the first source-drain doped region 118, the electron capture layer 114 on the side of the first gate structure 106 away from the first source-drain doped region 118 is also removed, exposing the substrate surface for forming the second source-drain doped region, so as to increase the process window for forming the second source-drain doped region 128 and provide space for the formation of the sidewall 126.
[0119] In this embodiment, the second gate structure 124 is a polysilicon gate structure.
[0120] See next Figure 4 and 5 In the step of removing at least a portion of the electron-trapping layer 114 between the pair of first gate structures 106 , an opening K is formed in the electron-trapping layer 114 , and the opening K exposes the surface of the substrate 100 .
[0121] In other words, the sidewalls of the electron-trapping layer 114 exposed by the opening K are used as a mask to implant ions into the exposed substrate 100 to form the first source-drain doped regions 118 .
[0122] Accordingly, before forming the second gate structure 124 , the forming method further includes: forming a second gate oxide layer 120 in the opening K.
[0123] The second gate oxide layer 120 serves as an insulating layer to isolate the second gate structure 124 from the substrate 100 . By adjusting the thickness of the second gate oxide layer 120 , the threshold voltage and the electric field strength in the channel can be adjusted.
[0124] In this embodiment, a thermal oxidation process is used to form the second gate oxide layer 120 , and the second gate oxide layer 120 has high density and is free of pinhole or void defects, thereby preventing lateral charge diffusion and improving isolation between storage cells.
[0125] In the step of forming the second gate structure 124 , the second gate structure 124 also covers the second gate oxide layer 120 .
[0126] In this embodiment, the height of the second gate oxide layer 120 is lower than the height of the electron-trapping layer 114, so the second gate structure 124 does not fill the entire space within the paired first gate structures 106. As a result, one second gate structure 124 is in contact with all the electron-trapping layers 114 at the same time, thereby controlling the data storage and erasure process of the electron-trapping layer 114 located between the substrate 100 and the second gate structure 124.
[0127] See also Figure 9 A second source-drain doped region 128 is formed in the substrate 100 on a side of the first gate structure 106 away from the second gate structure 124 .
[0128] The second source / drain doped region 128 can be used as the other of the source or the drain of the field effect transistor. When the field effect transistor is working, the second source / drain doped region 128 can provide a carrier source.
[0129] In this embodiment, the second source / drain doped region 128 may include a stress layer doped with ions. The stress layer may be used to provide stress to the channel region, thereby improving carrier mobility.
[0130] Specifically, when forming an NMOS transistor, the second source / drain doping region 128 may include a stress layer doped with N-type ions, and the material of the stress layer may be Si or SiC; when forming a PMOS transistor, the second source / drain doping region 128 may include a stress layer doped with P-type ions, and the material of the stress layer may be Si or SiGe.
[0131] In this embodiment, the second source / drain doped region 128 may serve as a drain, so that a conductive channel may be formed between the second source / drain doped region 128 and the first source / drain doped region 118 .
[0132] In this embodiment, the parameters of the first source / drain doping region 118 and the second source / drain doping region 128 are different.
[0133] For example, the depth of the first source-drain doping region 118 in the substrate 100 is less than the depth of the second source-drain doping region 128 in the substrate 100. In this way, during data storage and erasure processing, the shallow junction state of the first source-drain doping region 118 is maintained, which can prevent lateral diffusion from interfering with the isolation between the second source-drain doping regions 128. The deep junction state of the second source-drain doping region 128 improves its own voltage resistance.
[0134] For example, the doping concentration of the first source / drain doping region 118 is greater than the doping concentration of the second source / drain doping region 128 , which reduces the on-resistance of the first source / drain doping region 118 to achieve bidirectional power conduction; and the lower doping concentration of the second source / drain doping region 128 improves its own withstand voltage strength.
[0135] In this embodiment, see Figure 9 Before forming the second source / drain doped region 128 , the forming method further includes: forming a sidewall spacer 126 on the exposed sidewall of the electron trapping layer 114 .
[0136] The side walls 126 can play a protective role.
[0137] Furthermore, ions may be implanted into the substrate 100 using the sidewalls of the spacer 126 as a mask to form the second source / drain doped regions 128 .
[0138] See also Figure 10 This embodiment also provides another method for forming a semiconductor structure. The similarities between this embodiment and the above-mentioned embodiment will not be repeated here.
[0139] The difference between this embodiment and the previous embodiment is that in the step of forming the second gate structure 224 , the second gate structure 224 is a discrete structure, so that the second gate structure 224 covers the sidewalls and surface of the electron-trapping layer 114 and partially covers the second gate oxide layer 120 .
[0140] In other words, the second gate structure and the electron capture layer have a one-to-one correspondence, and the channel below the second gate structure can be turned on by selectively applying voltage to the second gate structure, thereby achieving data storage and erasure operations for the electron capture layer below the second gate structure.
[0141] Accordingly, when forming the spacer 126 , the spacer 126 is also formed above the second gate oxide layer 120 and covers the sidewalls of the second gate structure 224 .
[0142] The present invention also provides a semiconductor structure, see Figure 9The semiconductor structure may include: a substrate 100; a pair of first gate structures 106 located on the substrate 100; a first source-drain doped region 118 located in the substrate 100 between the pair of first gate structures 106; an electron-trapping layer 114 covering the sidewalls of each first gate structure 106 and the substrate 100 between the pair of first gate structures 106, and exposing a portion of the surface of the first source-drain doped region 118; a second gate structure 124 located on the substrate 100 between the pair of first gate structures 106 and covering at least the sidewalls and surface of the electron-trapping layer 114; and a second source-drain doped region 128 located in the substrate 100 on a side of the first gate structure 106 away from the second gate structure 124.
[0143] In this embodiment, the substrate 100 may provide a process operation basis for a semiconductor structure formation process, wherein the semiconductor structure may include a fin field effect transistor (FinFET) or a gate all around transistor (GAA).
[0144] In this embodiment, the material of substrate 100 includes silicon. In other embodiments, substrate 100 may be made of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. Substrate 100 may also be other types of substrates, such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of substrate 100 may be a material suitable for process requirements or easy to integrate.
[0145] In some embodiments, the base may further include a substrate, a plurality of discrete fins located above the substrate, and an isolation structure located on the substrate where the fins are exposed. The isolation structure may cover part of the sidewalls of the fins, and the top of the isolation structure is lower than the top of the fins.
[0146] In this embodiment, the isolation structure serves to electrically isolate adjacent transistors.
[0147] In some embodiments, the isolation structure may be made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride.
[0148] In this embodiment, the material of the isolation structure may be silicon oxide.
[0149] In this embodiment, the substrate 100 further has a well region 102 .
[0150] By adjusting the doping concentration of the well region 102 , the threshold voltage can be adjusted to ensure that the transistor can be normally turned on or off during programming / erase operations.
[0151] The first gate structure 106 is a select gate SG, which performs a selection function. When the voltage applied to the select gate SG is greater than the threshold voltage, a channel is formed on the surface of the well region 102 covered by the select gate SG, connecting the source and drain doped regions. When an operating voltage is applied to the second gate structure 124, the entire channel between the source and drain is conductive.
[0152] In this embodiment, the material of the first gate structure 106 is polysilicon.
[0153] See next Figure 9 The semiconductor structure may further include: a first gate oxide layer 104 located between the substrate 100 and the first gate structure 106 .
[0154] The first gate oxide layer 104 serves as an insulating layer to isolate the first gate structure 106 from the substrate 100 . By adjusting the thickness of the first gate oxide layer 104 , the threshold voltage and the electric field strength in the channel can be adjusted.
[0155] The electron-trapping layer 114 as a whole functions as a data storage layer.
[0156] In this embodiment, the electron capture layer 114 formed on the substrate 100 may include: a tunneling oxide layer 108, located on the substrate 100 and covering the sidewalls of each first gate structure 106; a charge storage layer 110, covering the sidewalls and surface of the tunneling oxide layer 108; and a blocking layer 112, covering the sidewalls and surface of the charge storage layer 110.
[0157] The tunnel oxide layer 108 is used to allow charges to be injected or escaped through the quantum tunneling effect.
[0158] In this embodiment, the material of the tunnel oxide layer 108 may include silicon oxide. Selecting silicon oxide as the material for the tunnel oxide layer 108 can improve process compatibility and reduce process risks. Furthermore, compared to organic materials, silicon oxide has greater hardness and density, which helps improve the protective effect of the tunnel oxide layer 108 on the surface of the substrate 100.
[0159] In one embodiment, the tunnel oxide layer 108 is made of silicon oxide. Silicon oxide has good adhesion to the substrate 100, which helps improve the stability and processing performance of subsequent processes. Furthermore, silicon oxide is a commonly used silicon oxide in semiconductor processes, which can reduce the difficulty and process cost of forming the tunnel oxide layer 108 and improve process compatibility.
[0160] The charge storage layer 110 is used to capture and locally store charges (electrons or holes). By adjusting the composition and thickness of the charge storage layer 110 , different charge storage capacities and charge retention times can be achieved.
[0161] In this embodiment, the material of the charge storage layer 110 is silicon nitride.
[0162] The blocking layer 112 is used to prevent charges from leaking from the charge storage layer 110 to the second gate structure 124 .
[0163] In this embodiment, the material of the barrier layer 112 is silicon oxide.
[0164] It should be noted that when the first gate oxide layer 104 is formed on the substrate 100 , the electron-trapping layer 114 also covers the sidewalls of the first gate oxide layer 104 .
[0165] The first source / drain doped region 118 may be used as a source or a drain of a field effect transistor. When the field effect transistor is working, the first source / drain doped region 118 may be used to provide a carrier source.
[0166] In this embodiment, the first source-drain doped region 118 serves as a source. That is, the paired first gate structures 106 in this embodiment share a source. The reason for sharing the source is that, generally, the source is grounded. Therefore, by sharing the source, there is no risk of driving one memory cell by mistake when driving another, thus achieving independent control of different memory cells.
[0167] In this embodiment, the first source / drain doped region 118 may include a stress layer doped with ions. The stress layer may be used to provide stress to the channel region, thereby improving carrier mobility.
[0168] Specifically, when the semiconductor structure is an NMOS transistor, the first source-drain doped region 118 may include a stress layer doped with N-type ions, and the material of the stress layer may be Si or SiC; when the semiconductor structure is a PMOS transistor, the first source-drain doped region 118 may include a stress layer doped with P-type ions, and the material of the stress layer may be Si or SiGe.
[0169] The second gate structure 124 may serve as a control gate CG, which controls the conduction of the channel.
[0170] Specifically, when the voltage applied to the second gate structure 124 is greater than the threshold voltage (Vth), the channel below the second gate structure 124 is turned on, thereby forming a current path between the source and the drain.
[0171] In this embodiment, the second gate structure 124 , the first gate structure 106 and the electron-trapping layer 114 are used in combination to store data.
[0172] In some embodiments, when a high voltage is applied to the second gate structure 124, electrons are injected into the charge storage layer of the electron-trapping layer 114 through the tunneling effect, changing the threshold voltage of the device and storing data "1." When a reverse voltage is applied to the second gate structure 124, electrons are released from the charge storage layer, restoring the initial state and storing data "0."
[0173] Accordingly, during this process, the first gate structure 106 is used to select a specific cell in the memory array, avoiding interference with other cells and ensuring that only the target cell is operated.
[0174] In this embodiment, the second gate structure 124 is a polysilicon gate structure.
[0175] In this embodiment, the second gate structure 124 fills the space between the paired first gate structures 106 . The semiconductor structure may further include: a second gate oxide layer 120 , located on the substrate 100 and in contact with a portion of the sidewall of the electron-trapping layer 114 and the bottom of the second gate structure 124 .
[0176] In other words, the second gate oxide layer 120 only contacts a portion of the sidewalls of the electron capture layer 114, so that the second gate structure 124 can cover the sidewalls of the remaining portion of the electron capture layer 114. One second gate structure 124 contacts all of the electron capture layers 114 at the same time, thereby controlling the data storage and erasure process of the electron capture layer 114 located between the substrate 100 and the second gate structure 124.
[0177] The second source-drain doped region 128 is located in the substrate 100 on a side of the first gate structure 106 away from the second gate structure 124 .
[0178] The second source / drain doped region 128 can be used as the other of the source or the drain of the field effect transistor. When the field effect transistor is working, the second source / drain doped region 128 can provide a carrier source.
[0179] In this embodiment, the second source / drain doped region 128 may include a stress layer doped with ions. The stress layer may be used to provide stress to the channel region, thereby improving carrier mobility.
[0180] Specifically, when the semiconductor structure is an NMOS transistor, the second source-drain doping region 128 may include a stress layer doped with N-type ions, and the material of the stress layer may be Si or SiC; when the semiconductor structure is a PMOS transistor, the second source-drain doping region 128 may include a stress layer doped with P-type ions, and the material of the stress layer may be Si or SiGe.
[0181] In this embodiment, the second source-drain doped region 128 serves as a drain, so that a conductive channel can be formed between the first source-drain doped region 118 and the second source-drain doped region 128 .
[0182] In this embodiment, the parameters of the first source / drain doping region 118 and the second source / drain doping region 128 are different.
[0183] For example, the depth of the first source-drain doping region 118 in the substrate 100 is less than the depth of the second source-drain doping region 128 in the substrate 100. In this way, during data storage and erasure processing, the shallow junction state of the first source-drain doping region 118 is maintained, which can prevent lateral diffusion from interfering with the isolation between the second source-drain doping regions 128. The deep junction state of the second source-drain doping region 128 improves its own voltage resistance.
[0184] For example, the doping concentration of the first source / drain doping region 118 is greater than the doping concentration of the second source / drain doping region 128 , which reduces the on-resistance of the first source / drain doping region 118 to achieve bidirectional power conduction; and the lower doping concentration of the second source / drain doping region 128 improves its own withstand voltage strength.
[0185] In this embodiment, the semiconductor structure may further include a spacer 126 located on the substrate 100 and covering the sidewall of the electron-trapping layer 114 adjacent to the second source-drain doped region 128 .
[0186] The side walls 126 can play a protective role.
[0187] Correspondingly, the second source / drain doped region 128 is located in the substrate 100 on one side of the spacer 126 .
[0188] In addition, see Figure 10 , the present application also provides another semiconductor structure, and the similarities between this embodiment and the previous embodiment are not repeated here.
[0189] The difference between this embodiment and the previous embodiment is that the second gate structure 224 is a discrete structure, so that the second gate structure 224 covers the sidewalls and the surface of the electron-trapping layer 114 and covers a portion of the second gate oxide layer 120 .
[0190] In other words, the second gate structure 224 has a one-to-one correspondence with the electron capture layer 114 , and data storage and erasure operations can be implemented for the electron capture layer below the second gate structure by selectively applying voltage to the second gate structure to turn on the channel below the second gate structure.
[0191] Accordingly, the spacer 126 is also located above the second gate oxide layer 120 and covers the sidewalls of the second gate structure 224 .
[0192] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate having a pair of first gate structures thereon; forming an electron-trapping layer on the substrate, wherein the electron-trapping layer covers the sidewalls and the top of the first gate structure; removing at least a portion of the electron-trapping layer between the pair of first gate structures to expose the surface of the substrate; forming a first source-drain doped region in the exposed substrate between the pair of first gate structures; forming a second gate structure above the first source-drain doped region, wherein the second gate structure at least covers the sidewalls and the surface of the electron-trapping layer; A second source-drain doped region is formed in the substrate on a side of the first gate structure away from the second gate structure.
2. The method for forming a semiconductor structure according to claim 1, wherein: Before removing at least a portion of the electron capture layer between the pair of first gate structures, the forming method further includes: forming a hard mask layer on the substrate, the hard mask layer covering the electron capture layer, and having a trench between the hard mask layers, the trench being located between the pair of first gate structures; The step of removing at least a portion of the electron-trapping layer between the pair of first gate structures to expose the surface of the substrate comprises: removing the hard mask layer and the electron-trapping layer above the top of the first gate structure, and the hard mask layer exposed by the trench and the electron-trapping layer below the hard mask layer, to expose the surface of the substrate between the pair of first gate structures and the top of the first gate structure; After the surface of the substrate is exposed, the first source-drain doping region is formed, and then the remaining portion of the hard mask layer is removed.
3. The method for forming a semiconductor structure according to claim 2, wherein: The step of removing at least a portion of the electron-trapping layer between the pair of first gate structures further includes: removing a portion of the electron trapping layer on the other side of the first gate structure to expose a substrate for forming the second source and drain doped regions; Using a first etching process, the hard mask layer and the electron capture layer above the top of the first gate structure, as well as the hard mask layer exposed by the trench and the electron capture layer below the hard mask layer are removed; A second etching process is used to remove the remaining portion of the hard mask layer, where the first etching process is different from the second etching process.
4. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming an electron capture layer on the substrate comprises: forming a tunneling oxide layer on the substrate that conformally covers the sidewalls and top of the first gate structure; forming a charge storage layer on the substrate conformally covering the tunneling oxide layer; forming a blocking layer on the substrate conformally covering the charge storage layer; Wherein, the tunneling oxide layer, the charge storage layer and the blocking layer serve as the electron trapping layer.
5. The method for forming a semiconductor structure according to claim 1, wherein: In the step of removing at least a portion of the electron-trapping layer between the pair of first gate structures, an opening is formed in the electron-trapping layer, and the opening exposes the surface of the substrate; Before forming the second gate structure, the forming method further includes: forming a second gate oxide layer in the opening; In the step of forming the second gate structure, the second gate structure also covers the second gate oxide layer, or, in the step of forming the second gate structure, the second gate structure covers the sidewall and surface of the electron trapping layer and covers a portion of the second gate oxide layer.
6. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming a second gate structure above the first source / drain doped region, an electron trapping layer on a side of the first gate structure away from the first source / drain doped region is removed to expose a substrate surface for forming the second source / drain doped region; Before forming the second source-drain doped region, the forming method further includes: forming a sidewall spacer on the sidewall of the exposed electron capture layer; A first gate oxide layer is provided between the substrate and the first gate structure.
7. The method for forming a semiconductor structure according to claim 1, wherein: The first gate structure is a selection gate, the second gate structure is a control gate, the first source-drain doped region is a source, and the second source-drain doped region is a drain.
8. A semiconductor structure, characterized in that include: substrate; A pair of first gate structures, located on the substrate; a first source-drain doped region located in the substrate between the pair of first gate structures; an electron trapping layer covering the sidewalls of each first gate structure and the substrate between the paired first gate structures, and exposing a portion of the surface of the first source and drain doped regions; a second gate structure, located on the substrate between the pair of first gate structures and covering at least the sidewalls and the surface of the electron-trapping layer; The second source-drain doped region is located in the substrate on a side of the first gate structure away from the second gate structure.
9. The semiconductor structure according to claim 8, wherein: Also includes: a first gate oxide layer, located between the substrate and the first gate structure; a second gate oxide layer, located on the substrate and in contact with a portion of the sidewall of the electron-trapping layer and a bottom of the second gate structure; The sidewall is located on the substrate and covers the sidewall of the electron trapping layer close to the second source-drain doped region.
10. The semiconductor structure according to claim 8, wherein: The first gate structure is a selection gate, the second gate structure is a control gate, the first source-drain doped region is a source, and the second source-drain doped region is a drain.
11. The semiconductor structure according to claim 8, wherein: The electron-trapping layer comprises: a tunneling oxide layer, located on the substrate and covering sidewalls of each first gate structure; a charge storage layer covering the sidewalls and surface of the tunnel oxide layer; The blocking layer covers the sidewalls and the surface of the charge storage layer.