Semiconductor element with spacer and preparation method thereof

Abstract

The invention provides a semiconductor element and a preparation method of the semiconductor element. The semiconductor device includes an interposer having a first surface and a second surface parallel to the first surface; a conductive via extending between the first surface and the second surface of the interposer; an insulating layer separating the conductive via from the interposer; a first electronic component disposed on the second surface and electrically connected to the conductive via; a first conductive element on the first surface of the interposer and electrically connected to the conductive via; a spacer conformally located on the first surface of the interposer and on each sidewall of the first conductive element; and a passivation layer disposed on the spacer. The passivation layer has a first dielectric constant, and the spacer has a second dielectric constant less than the first dielectric constant.

Description

Technical Field

[0001] This application claims priority to U.S. patent application No. 18 / 599,258 (i.e., the priority date is "March 8, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device having a spacer and a method for manufacturing the semiconductor device having the spacer. Background Art

[0003] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor device sizes are steadily shrinking to meet the increasing demand for computing power. However, various challenges have emerged during this scaling process, and these problems are increasing. Consequently, achieving improvements in quality, yield, performance, and reliability, while also reducing complexity, remains a constant challenge.

[0004] The above description of “prior art” only provides background technology, does not admit that the above description of “prior art” reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the Invention

[0005] One embodiment of the present disclosure provides a semiconductor device, comprising an interposer having a first surface and a second surface parallel to the first surface; a conductive via extending between the first and second surfaces of the interposer; an insulating layer separating the conductive via from the interposer; a first electronic component disposed on the second surface and electrically connected to the conductive via; a first conductive element disposed on the first surface of the interposer and electrically connected to the conductive via; a spacer conformally disposed on the first surface of the interposer and on each sidewall of the first conductive element; and a passivation layer disposed on the spacer. The passivation layer has a first dielectric constant, and the spacer has a second dielectric constant less than the first dielectric constant.

[0006] Another embodiment of the present disclosure provides a semiconductor device including an interposer having a first surface and a second surface parallel to the first surface, wherein the interposer defines a first cavity and a second cavity extending between the first and second surfaces; an insulating via located within the first cavity; a first electronic component located on the second surface of the interposer and electrically connected to the insulating via; a second electronic component located within the second cavity; a first conductive component located on the first surface of the interposer and electrically connected to the insulating via; a spacer conformally positioned on the first surface of the interposer and on each sidewall of the first conductive component; and a passivation layer located on the spacer. The passivation layer has a first dielectric constant, and the spacer has a second dielectric constant less than the first dielectric constant.

[0007] Another embodiment of the present disclosure provides a method for fabricating a semiconductor device, comprising providing an interposer including a first surface and a second surface parallel to the first surface; recessing a first cavity from the second surface; forming an insulating layer to fill the first cavity; forming a conductive via to penetrate the insulating layer; thinning the interposer from the first surface to expose the conductive via; forming a first conductive element on the first surface of the interposer and electrically connected to the conductive via; conformally forming a spacer on the first surface of the interposer and on each sidewall of the first conductive element; forming a passivation layer on the spacer; and performing a hybrid bonding technique to bond the first electronic device to the second surface of the interposer and electrically connect to the conductive via. The passivation layer has a first dielectric constant, and the spacer has a second dielectric constant less than the first dielectric constant.

[0008] Due to the design of the semiconductor device disclosed herein, an insulating via (e.g., a conductive via) has relatively small parasitic capacitance compared to a through-substrate via. Furthermore, the depth of the insulating via can be controlled by determining the depth of a cavity in the interposer, and the protective layer can prevent the interposer from being over-polished. As a result, the depth of the insulating via can be relatively well controlled compared to a through-substrate via. In addition, RC delay can be reduced by using passivation layers and spacers with different dielectric constants. As a result, the performance of the semiconductor device can be improved.

[0009] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used quite easily to modify or design other structures or processes to achieve the same purposes as those of the present disclosure. It should also be understood by those skilled in the art to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] When with Figure 1 Various aspects of the present disclosure will be best understood from the following detailed description when read together. It should be understood that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0011] Figure 1 is a top schematic diagram illustrating the layout of semiconductor components according to some embodiments of the present disclosure.

[0012] Figure 2 FIG. 1 is a top schematic diagram illustrating a cross section of a semiconductor device along line AA′ according to some embodiments of the present disclosure.

[0013] Figure 3 and Figure 4 yes Figure 2 A partially enlarged schematic diagram of .

[0014] Figure 5 1 is a flow chart illustrating a method for manufacturing a semiconductor device according to different embodiments of the present disclosure.

[0015] Figure 6 is a top view schematically illustrating a wafer according to some embodiments of the present disclosure.

[0016] Figures 7 to 33 It is a cross-sectional schematic diagram illustrating another embodiment of the present disclosure. Figure 2 One or more stages of a semiconductor component are shown.

[0017] The description of the accompanying drawings is as follows:

[0018] 10: Semiconductor components

[0019] 10a: Area

[0020] 10b: Region

[0021] 10c: Region

[0022] 20: Preparation method

[0023] 102: Wafer

[0024] 104: Area

[0025] 110: Intermediary layer

[0026] 110b1: bottom

[0027] 110b2: bottom

[0028] 110s1: Surface

[0029] 110s2: Surface

[0030] 110s3: Surface

[0031] 110s4: Surface

[0032] 110v1: Cavity

[0033] 110v2: Cavity

[0034] 112: Dielectric layer

[0035] 114: Mask

[0036] 116: Protective layer

[0037] 116s1: Surface

[0038] 118: Insulation layer

[0039] 120: Mask

[0040] 122: Opening

[0041] 124: Seed layer

[0042] 124s1: Surface

[0043] 126: Conductive vias

[0044] 126s1: Surface

[0045] 128: Mask

[0046] 130: Protective layer

[0047] 130s1: Surface

[0048] 130s2: Surface

[0049] 132a: Conductive materials

[0050] 132b: Electrical connector

[0051] 134: Mask

[0052] 136: Opening

[0053] 138: Conductive column

[0054] 150: Package structure

[0055] 152: Electronic components

[0056] 152s1: Surface

[0057] 152s2: Surface

[0058] 154: Redistribution Structure

[0059] 156: Conductive pad

[0060] 158: Encapsulation colloid

[0061] 160: Encapsulation colloid

[0062] 160s1: Surface

[0063] 162: Dielectric layer

[0064] 164: Mask

[0065] 166: Opening

[0066] 168: Opening

[0067] 170: Conductive elements

[0068] 172: Conductive elements

[0069] 174: Carrier

[0070] 176: Sacrificial Layer

[0071] 178: Passivation layer

[0072] 180: Conductive elements

[0073] 180s1: Surface

[0074] 180s2: Surface

[0075] 180s3: Sidewall

[0076] 182: Electrical connector

[0077] 184: Holder

[0078] 186a: Electronic components

[0079] 186b: Electronic components

[0080] 187: Adhesive layer

[0081] 188a: Electronic components

[0082] 188b: Electronic components

[0083] 189: Passivation layer

[0084] 190: Conductive elements

[0085] 194: Motherboard

[0086] 194s1: Surface

[0087] 194s2: Surface

[0088] 196: Electrical connector

[0089] 198: Wire

[0090] 250: Interstitial

[0091] 250s1: Surface

[0092] 250s2: Surface

[0093] 251: Interstitial Materials

[0094] D1: Depth

[0095] D2: Depth

[0096] S11: Steps

[0097] S13: Steps

[0098] S15: Steps

[0099] S17: Steps

[0100] S19: Steps

[0101] S21: Steps

[0102] S23: Steps

[0103] S25: Steps

[0104] S27: Steps

[0105] W1: width

[0106] W2: width

[0107] Z: Direction DETAILED DESCRIPTION

[0108] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, the description of a first component formed on a second component may include embodiments in which the first and second components are in direct contact, and may also include embodiments in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is for simplicity and clarity, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0109] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0110] It should be understood that when forming a component on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0111] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive concept of the present disclosure, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0112] Unless the context indicates otherwise, as used herein, terms such as "same," "equal," "planar," or "coplanar" when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but rather mean nearly identical orientation, layout, location, shape, size, amount, or other measure within acceptable variances that may occur, for example, due to manufacturing processes. The term "substantially" may be used herein to convey this meaning. For example, terms such as substantially the same, substantially equal, or substantially planar may be exactly the same, equal, or planar, or may be the same, equal, or planar within an acceptable variance, which may occur, for example, due to a manufacturing process.

[0113] In this disclosure, a semiconductor device generally refers to a device that can operate by utilizing semiconductor characteristics, and an electro-optical device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the category of semiconductor devices.

[0114] It should be understood that in the description of the present disclosure, above (or up) corresponds to the direction of the Z-direction arrow, and below (or down) corresponds to the relative direction of the Z-direction arrow.

[0115] Figure 1 is a top schematic diagram illustrating the layout of the semiconductor device 10 according to some embodiments of the present disclosure.

[0116] In some embodiments, semiconductor element 10 may include an interposer 110. Interposer 110 may include an elemental semiconductor including silicon or germanium in single crystal, polycrystalline, or amorphous form; a compound semiconductor material including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or combinations thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a gradient Ge feature, wherein the Si and Ge composition changes from one ratio at one location of the gradient SiGe feature to another ratio at another location. In another embodiment, the SiGe alloy may be formed over a silicon substrate. In some embodiments, the SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy.

[0117] In some embodiments, the semiconductor device 10 may include at least one region 10 a , at least one region 10 b , and at least one region 10 c on or within the interposer 110 .

[0118] In some embodiments, region 10a may be configured to support an electronic component having a terminal (eg, a conductive pad) connected to other components via a wire.

[0119] In some embodiments, the region 10 b may be configured to accommodate a package structure or an electronic component disposed within the interposer 110 .

[0120] In some embodiments, the region 10 c may be configured to form a through insulation via (TIV), such as a through oxide via (TOV), which may electrically connect two devices disposed on opposite sides of the interposer 110 .

[0121] Figure 2 FIG. 1 is a top schematic diagram illustrating a cross section of the semiconductor device 10 along the line AA′ according to some embodiments of the present disclosure. Figure 3 and Figure 4 They are partially enlarged schematic diagrams of area 10a and area 10c respectively.

[0122] The interposer 110 (or substrate) may have a surface 110s1 (or a lower surface) and a surface 110s2 (or an upper surface) opposite to the surface 110s1 . In other words, the surface 110s1 and the surface 110s2 may be parallel to each other.

[0123] The semiconductor element 10 may include a dielectric layer 112 and a protective layer 116. In some embodiments, the dielectric layer 112 may be disposed on the surface 110s2 of the interposer 110. In some embodiments, the protective layer 116 may be disposed on the dielectric layer 112. The protective layer 116 may be separated from the interposer 110 by the dielectric layer 112. The dielectric layer 112 and the protective layer 116 may have different materials. Each of the dielectric layer 112 and the protective layer 116 may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or a combination thereof. In some embodiments, the dielectric layer 112 may include silicon oxide or be made of silicon oxide. In some embodiments, the protective layer 116 may include silicon nitride or be made of silicon nitride. In some embodiments, the protective layer 116 may be used as a polishing stop layer (e.g., a chemical mechanical polishing (CMP) stop layer) or an etch stop layer.

[0124] The interposer 110 may define a cavity 110v1. In some embodiments, the cavity 110v1 may extend between a surface 110s1 and a surface 110s2 of the interposer 110. The protective layer 116 may be disposed on a surface 110s3 of the interposer 110 within the cavity 110v1. In some embodiments, the protective layer 116 may contact the surface 110s3 of the interposer 110 within the cavity 110v1.

[0125] like Figure 3 As shown, the semiconductor element 10 may include an insulating layer 118. The insulating layer 118 may fill the cavity 110v1 of the interposer 110. The insulating layer 118 may be separated from the surface 110s3 of the interposer 110 by the protective layer 116. In some embodiments, the insulating layer 118 may penetrate the interposer 110. The insulating layer 118 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The insulating layer 118 and the protective layer 116 may include different materials. In some embodiments, the insulating layer 118 may include silicon oxide or be made of silicon oxide. The protective layer 116 may include a surface 116s1 (or a lower surface). In some embodiments, the surface 116s1 may be substantially coplanar with the surface 110s1 of the interposer 110.

[0126] The semiconductor device 10 may include a seed layer 124. The seed layer 124 may be disposed on a side surface of the insulating layer 118. The seed layer 124 may be separated from the protective layer 116 by the insulating layer 118. The seed layer 124 may include a conductive material, such as tantalum nitride (TaN), titanium, titanium nitride (TiN), or other suitable materials. The seed layer 124 may include a surface 124s1 (or a lower surface). In some embodiments, the surface 124s1 may be substantially coplanar with the surface 110s1 of the interposer 110. In some embodiments, the surface 124s1 and the surface 116s1 may be located at the same plane (or height).

[0127] The semiconductor device 10 may include a conductive via 126. The conductive via 126 may be disposed on a side surface of the seed layer 124. The conductive via 126 may be separated from the insulating layer 118 by the seed layer 124. The protective layer 116 may be disposed between the conductive via 126 and the interposer 110. In some embodiments, the conductive via 126 may completely penetrate the interposer 110. The conductive via 126 may include a conductive material, such as copper (Cu), tungsten (W), silver (Ag), gold (Au), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), alloys thereof, combinations thereof, or other suitable materials.

[0128] The conductive via 126 may include a surface 126s1 (or a lower surface). In some embodiments, the surface 126s1 may be substantially coplanar with the surface 124s1 of the seed layer 124. In some embodiments, the surface 126s1 and the surface 110s1 may be located at the same level (or height). In some embodiments, the conductive via 126 may also be referred to as a through-insulation via (TIV), such as a through-oxide via (TOV).

[0129] Please refer back Figure 2, the semiconductor element 10 may include a protective layer 130. In some embodiments, the protective layer 130 may be disposed on the surface 110s2 of the interposer 110. In some embodiments, the protective layer 130 may be disposed on the dielectric layer 112. The protective layer 130 may be separated from the interposer 110 by the dielectric layer 112. The protective layer 130 and the dielectric layer 112 may include different materials. The protective layer 130 may include silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. In some embodiments, the protective layer 130 may include or be made of silicon nitride. In some embodiments, the protective layer 130 may serve as a polishing stop layer (e.g., a CMP stop layer) or an etch stop layer. The protective layer 130 may include a surface 130s1 (or a lower surface) and a surface 130s2 (or an upper surface). In some embodiments, the surface 130s1 of the protective layer 130 may be substantially coplanar with the surface 110s1 of the interposer 110. In some embodiments, the level (or height) of the surface 130s1 of the protective layer 130 may be equal to the level of the surface 116s1 of the protective layer 116. In some embodiments, the level (or height) of the surface 130s1 of the protective layer 130 may be equal to the level (or height) of the surface 126s1 of the conductive via 126. In some embodiments, the level (or height) of the surface 130s1 of the protective layer 130 may be equal to the level of the surface 124s1 of the seed layer 124.

[0130] The semiconductor device 10 may include a cavity 110v2. In some embodiments, the cavity 110v2 may extend between surfaces 110s1 and 110s2 of the interposer 110. The protective layer 130 may be disposed on a surface 110s4 of the interposer 110 within the cavity 110v2. In some embodiments, the protective layer 130 may contact the surface 110s4 of the interposer 110 within the cavity 110v2.

[0131] like Figure 4 As shown, the semiconductor device 10 may include a plurality of electrical connectors 132b. In some embodiments, the electrical connectors 132b may be disposed on the bottom of the cavity 110v2. The electrical connectors 132b may be exposed from the surface 110s1 of the interposer 110. The electrical connectors 132b may include a solder material, such as an alloy of gold and tin solder or an alloy of silver and tin solder.

[0132] Semiconductor device 10 may include a plurality of conductive pillars 138. In some embodiments, conductive pillars 138 may be disposed on electrical connector 132b. Conductive pillars 138 may be electrically connected to electrical connector 132b. In some embodiments, conductive pillars 138 may include or be made of a conductive material such as Cu, W, Ag, Au, Ru, Ir, Ni, Os, Rh, Al, Mo, Co, alloys thereof, combinations thereof, or other suitable materials.

[0133] The semiconductor device 10 may include a package structure 150 . In some embodiments, the package structure 150 may be disposed within the cavity 110v2 . The package structure 150 may include a plurality of electronic components 152 , a redistribution structure 154 , a plurality of conductive pads 156 , and an encapsulant 158 ​​.

[0134] Each electronic component 152 may include a memory element, such as a dynamic random access memory (DRAM) element, a one-time programmable (OTP) memory element, a static random access memory (SRAM) element, or other suitable memory element. In some embodiments, the electronic component 152 may include a logic element (e.g., a system-on-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a microcontroller, etc.), a radio frequency (RF) element, a sensor element, a microelectromechanical system (MEMS) element, a signal processor element (e.g., a digital signal processing (DSP) element), a front-end element (e.g., an analog front-end (AFE) element), or other elements. The electronic component 152 may have a surface 152s1 (or a lower surface) and a surface 152s2 (or an upper surface) opposite the surface 152s1. The surface 152s1 may face the surface 110s1 of the interposer 110.

[0135] The redistribution structure 154 may include conductive pads, traces, vias, layers, or other interconnects therein. For example, the redistribution structure 154 may include one or more transmission lines (eg, communication cables) and one or more ground lines and / or ground planes therein.

[0136] Conductive pad 156 may be electrically connected to redistribution structure 154. Conductive pad 156 may be electrically connected to conductive pillar 138. In some embodiments, conductive pad 156 may be bonded to conductive pillar 138. In some embodiments, conductive pad 156 may be exposed from encapsulant 158. In some embodiments, conductive pad 156 may include or be made of a conductive material such as Cu, W, Ag, Au, Ru, Ir, Ni, Os, Rh, Al, Mo, Co, alloys thereof, combinations thereof, or other suitable materials.

[0137] In some embodiments, encapsulant 158 ​​may encapsulate electronic component 152. Encapsulant 158 ​​may seal conductive pad 156. In some embodiments, encapsulant 158 ​​may comprise a molding material, such as a phenolic resin, an epoxy resin, a silicone resin, or other suitable encapsulant. It may also comprise a suitable filler, such as powdered SiO2.

[0138] Semiconductor device 10 may include an encapsulant 160. In some embodiments, encapsulant 160 may be disposed within cavity 110v2 of interposer 110. In some embodiments, encapsulant 160 may encapsulate package structure 150. In some embodiments, encapsulant 160 may encapsulate electronic component 152. In some embodiments, encapsulant 160 may encapsulate encapsulant 158. In some embodiments, encapsulant 160 may encapsulate conductive pillar 138. In some embodiments, encapsulant 160 may encapsulate electrical connector 132b. In some embodiments, encapsulant 160 may contact protective layer 130. In some embodiments, encapsulant 160 may be separated from interposer 110 by protective layer 130. In some embodiments, encapsulant 160 may penetrate interposer 110. In some embodiments, encapsulant 160 may completely penetrate interposer 110. In some embodiments, encapsulant 160 may include a molding material, which may include, for example, a phenolic resin, an epoxy resin, a silicone resin, or other suitable encapsulant. Suitable fillers, such as powdered SiO 2 , may also be included. The encapsulant 160 may have a surface 160 s 1 (or upper surface). In some embodiments, the surface 160 s 1 of the encapsulant 160 may be substantially coplanar with the surface 130 s 2 of the protective layer 130 .

[0139] Please refer back Figure 2, the semiconductor device 10 may include a dielectric layer 162. The dielectric layer 162 may be disposed on the surface 110s2 of the interposer 110. The dielectric layer 162 may be disposed on the protective layer 130. The dielectric layer 162 may be disposed on the encapsulant 160. The dielectric layer 162 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate (FSG), a low-k dielectric material, combinations thereof, and / or other suitable materials. In some embodiments, the material of the dielectric layer 162 may be the same as the material of the protective layer 130.

[0140] The semiconductor device 10 may include a plurality of conductive elements 170. In some embodiments, the conductive elements 170 may penetrate the dielectric layer 162. In some embodiments, the conductive elements 170 may penetrate a portion of the electronic component 152. In some embodiments, the conductive elements 170 may penetrate the electronic component 152 from the surface 152s2. In some embodiments, the conductive elements 170 may be electrically connected to the electronic component 152. In some embodiments, the conductive elements 170 may taper toward the interposer 110. The conductive elements 170 may include or be made of a conductive material such as Cu, W, Ag, Au, Ru, Ir, Ni, Os, Rh, Al, Mo, Co, alloys thereof, combinations thereof, or other suitable materials.

[0141] The semiconductor device 10 may include a plurality of conductive elements 172. In some embodiments, the conductive elements 172 may penetrate the dielectric layer 162. In some embodiments, the conductive elements 172 may penetrate the protective layer 130. In some embodiments, the conductive elements 172 may be electrically connected to the conductive vias 126. In some embodiments, the conductive elements 172 may taper toward the interposer 110. In some embodiments, the conductive elements 170 and the conductive elements 172 may be located at the same level (or height). In some embodiments, the conductive elements 170 and the conductive elements 172 may have different dimensions (e.g., length, width, or area). The conductive elements 172 may include or be made of a conductive material such as Cu, W, Ag, Au, Ru, Ir, Ni, Os, Rh, Al, Mo, Co, alloys thereof, combinations thereof, or other suitable materials.

[0142] The semiconductor device 10 may include a passivation layer 178. The passivation layer 178 may be disposed on the surface 110s1 of the interposer 110. The passivation layer 178 may include a dielectric material such as polyimide-isoindolequinazolinedione (PIQ), polybenzoxazole (PBO), benzocyclobutene (BCB), or other suitable materials.

[0143] like Figure 4 As shown, the semiconductor element 10 may include a plurality of conductive elements 180. In some embodiments, the conductive elements 180 may penetrate the passivation layer 178. In some embodiments, the conductive elements 180 may be disposed on a surface 110s1 of the interposer 110. In some embodiments, the conductive elements 180 may be electrically connected to the electrical connector 132b. In some embodiments, the conductive elements 180 may be electrically connected to the conductive vias 126. Specifically, the conductive elements 180 may have a surface 180s1 (or upper surface) and a surface 180s2 (or lower surface). The width W1 of the surface 180s1 may be greater than or equal to the width W2 of the surface 180s2. The conductive elements 180 may include a conductive material such as Cu, W, Ag, Au, Ru, Ir, Ni, Os, Rh, Al, Mo, Co, alloys thereof, combinations thereof, or other suitable materials, or may be made of a conductive material such as Cu, W, Ag, Au, Ru, Ir, Ni, Os, Rh, Al, Mo, Co, alloys thereof, combinations thereof, or other suitable materials.

[0144] like Figures 2 to 4 As shown, the semiconductor element 10 may include a plurality of spacers 250. In some embodiments, the spacers 250 may be conformally disposed on the surface 110s1 of the interposer 110 to separate the interposer 110 from the passivation layer 178. In some embodiments, the spacers 250 may be conformally disposed on the insulating layer 118 to separate the insulating layer 118 from the passivation layer 178. In some embodiments, the spacers 250 may be conformally disposed on the encapsulant 160 to separate the encapsulant 160 from the passivation layer 178. In some embodiments, the spacers 250 may be conformally disposed on each sidewall 180s3 of the conductive element 180 to laterally separate the conductive element 180 from the passivation layer 178.

[0145] In some embodiments, the spacer 250 may have a surface 250s1 (or upper surface) and a surface 250s2 (or lower surface). In some embodiments, the surface 250s1 may be substantially coplanar with the surface 116s1 of the protective layer 116. In some embodiments, the surface 250s1 may be substantially coplanar with the surface 110s1 of the interposer 110. In some embodiments, the surface 250s1 may be substantially coplanar with the surface 124s1 of the seed layer 124. In some embodiments, the surface 250s1 may be substantially coplanar with the surface 126s1 of the conductive via 126. In some embodiments, the surface 250s1 may be substantially coplanar with the surface 180s1 of the conductive element 180. In some embodiments, the surface 250s1 may be substantially coplanar with the surface 130s1 of the protective layer 130. In some embodiments, the surface 250s2 may be substantially coplanar with the surface 180s2 of the conductive element 180.

[0146] In some embodiments, the spacers 250 and the passivation layer 178 that separate the conductive elements 180 from each other have different dielectric constants. Specifically, the passivation layer 178 can have a first dielectric constant, and the spacers 250 can have a second dielectric constant that is less than the first dielectric constant. Thus, an effective dielectric constant of the dielectric layer combining the passivation layer 178 and the spacers 250 can be reduced, thereby reducing the resistance-capacitance (RC) delay of the semiconductor device 10. In some embodiments, the spacers 250 and the passivation layer 178 can include oxide-based dielectrics. For example, the spacers 250 can include a low-k oxide-based dielectric, such as carbon-doped silicon oxide or fluorinated oxide, and the passivation layer 178 can include silicon oxide or silicon dioxide.

[0147] The semiconductor element 10 may include a plurality of electrical connectors 182. The electrical connectors 182 may be electrically connected to the conductive element 180. The electrical connectors 182 may include a solder material, such as an alloy of gold and tin solder or an alloy of silver and tin solder.

[0148] Semiconductor element 10 may include electronic component 186a and electronic component 186b. In some embodiments, electronic component 186a and electronic component 186b may be disposed on region 10a. In some embodiments, electronic component 186a and electronic component 186b may be disposed on surface 110s2 of interposer 110. In some embodiments, electronic component 186a and electronic component 186b may not overlap cavity 110v1 and cavity 110v2. Electronic component 186a may be connected to surface 110s2 via an adhesive layer 187. In some embodiments, an active surface (not illustrated) of electronic component 186a (or electronic component 186b) may face away from interposer 110. Each of electronic component 186a and electronic component 186b may include a memory element, such as a dynamic random access memory (DRAM) element, a one-time programmable (OTP) memory element, a static random access memory (SRAM) element, or other suitable memory element. In some embodiments, each of the electronic components 186a and 186b may include logic elements (e.g., system-on-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microcontroller, etc.), radio frequency (RF) elements, sensor elements, microelectromechanical systems (MEMS) elements, signal processing elements (e.g., digital signal processing (DSP) elements), front-end elements (e.g., analog front-end (AFE) elements), or other elements.

[0149] Semiconductor element 10 may include electronic component 188a and electronic component 188b. In some embodiments, electronic component 188a and electronic component 188b may be disposed on surface 110s2 of interposer 110. In some embodiments, electronic component 188a may be disposed on or above region 10b. In some embodiments, electronic component 188a may be electrically connected to electronic component 152. In some embodiments, electronic component 188a may be disposed directly above package structure 150. In some embodiments, electronic component 188b may be disposed on or above region 10c. In some embodiments, electronic component 188b may be electrically connected to conductive via 126. In some embodiments, electronic component 188b may be disposed directly above conductive via 126. In some embodiments, an active surface (not noted) of electronic component 188a (or electronic component 188b) may face interposer 110. Each of the electronic components 188 a and 188 b may include a memory element, such as a dynamic random access memory (DRAM) element, a one-time programmable (OTP) memory element, a static random access memory (SRAM) element, or other suitable memory element. In some embodiments, each of the electronic components 188 a and 188 b may include a logic element (e.g., a system-on-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a microcontroller, etc.), a radio frequency (RF) element, a sensor element, a microelectromechanical system (MEMS) element, a signal processing element (e.g., a digital signal processing (DSP) element), a front-end element (e.g., an analog front-end (AFE) element), or other elements.

[0150] The semiconductor device 10 may include a passivation layer 189. The passivation layer 189 may be disposed on the active surface of the electronic device 188a (or the electronic device 188b). The passivation layer 189 may include a dielectric material such as PIQ, PBO, BCB, or other suitable materials.

[0151] Semiconductor element 10 may include a plurality of conductive elements 190. In some embodiments, conductive elements 190 may be electrically connected to electronic element 188a (or electronic element 188b). In some embodiments, conductive elements 190 may be electrically connected to conductive element 170. Conductive elements 190 may penetrate passivation layer 189. Conductive elements 190 may include or be made of a conductive material such as Cu, W, Ag, Au, Ru, Ir, Ni, Os, Rh, Al, Mo, Co, alloys thereof, combinations thereof, or other suitable materials.

[0152] The semiconductor device 10 may include a motherboard 194. The motherboard 194 may be disposed on a surface 110s1 of the interposer 110. The motherboard 194 may be electrically connected to the electronic component 188a via the package structure 150. The motherboard 194 may be electrically connected to the electronic component 188b via the conductive via 126. The motherboard 194 may be electrically connected to the electronic component 186a (or the electronic component 186b). For example, the motherboard 194 may include a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. The motherboard 194 may include a redistribution layer (RDL) or traces for electrical connection between components. The motherboard 194 may have a surface 194s1 (or a lower surface) and a surface 194s2 (or an upper surface) opposite the surface 194s1. The surface 194s2 of the motherboard 194 may face the interposer 110.

[0153] The semiconductor device 10 may include a plurality of electrical connectors 196. The electrical connectors 196 may be disposed on a surface 194s1 of the motherboard 194. Each electrical connector 196 may be electrically connected to an external component (not shown). The electrical connectors 196 may include a solder material, such as an alloy of gold and tin solder or an alloy of silver and tin solder.

[0154] The semiconductor device 10 may include a plurality of conductive lines 198. In some embodiments, the conductive lines 198 may be configured to electrically connect the electronic component 186a (or the electronic component 186b) to the motherboard 194. The conductive lines 198 may be connected to a surface 194s2 of the motherboard 194.

[0155] In a comparative semiconductor device, a TSV is provided in an interposer to electrically connect a plurality of devices on opposite surfaces of the interposer. As the size of the semiconductor device decreases, it becomes more difficult to control the depth of the TSV. In addition, the parasitic capacitance of the TSV may adversely affect the performance of the semiconductor device. In the present embodiment, the semiconductor device 10 includes a TIV (e.g., conductive via 126). The TIV may penetrate the interposer. Compared to the TSV, the parasitic capacitance of the TIV is relatively small. In addition, the depth of the TIV can be controlled by determining the depth of the cavity (e.g., 110v1), and the protective layer (e.g., 116) can prevent the interposer 110 from being over-polished. As a result, the depth of the TIV can be relatively well controlled compared to the TSV.

[0156] Figure 5 2 is a flow chart illustrating a method 20 for manufacturing a semiconductor device according to different embodiments of the present disclosure.

[0157] The manufacturing method 20 begins with step S11 , wherein an interposer is provided. The interposer has a lower surface and an upper surface.

[0158] The manufacturing method 20 proceeds to step S13 , wherein a first cavity may be formed in the interposer, a first protection layer may be formed in the first cavity, and a TIV may be formed in the first cavity.

[0159] The manufacturing method 20 proceeds to step S15 , wherein a second cavity may be formed in the interposer, a second protective layer may be formed in the second cavity, and a package structure including a plurality of first electronic components may be disposed in the second cavity.

[0160] The fabrication method 20 proceeds to step S17 , where a grinding technique may be performed to remove the lower surface of the interposer, the first protection layer, and a portion of the second protection layer to expose the TIV.

[0161] The fabrication method 20 continues with step S19 , where a conductive element may be formed on the lower surface of the interposer and electrically connected to the TIV.

[0162] The manufacturing method 20 continues with step S21 , in which a plurality of spaces are conformally formed on the lower surface of the interposer and on each sidewall of the conductive element.

[0163] The manufacturing method 20 proceeds to step S23 , wherein a passivation layer may be formed on the plurality of spacers. The passivation layer may have a different dielectric constant than that of the spacers.

[0164] The manufacturing method 20 proceeds to step S25 , where a second electronic component, a third electronic component, and a fourth electronic component are attached to the upper surface of the interposer. The second electronic component can be electrically connected to the TIV. The third electronic component can be electrically connected to the package structure.

[0165] The manufacturing method 20 proceeds to step S27 , wherein a motherboard is attached to the lower surface of the interposer, and a conductive line is formed to electrically connect the fourth electronic component and the motherboard.

[0166] Preparation method 20 is merely an example and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional steps may be provided before, during, or after each step of preparation method 20, and some of the steps described may be replaced, eliminated, or reordered for additional embodiments of the preparation method. In some embodiments, preparation method 20 may include Figure 5 In some embodiments, the preparation method 20 may include Figure 5 One or more steps are depicted.

[0167] Figure 61 is a top view schematic diagram illustrating a wafer according to some embodiments of the present disclosure. Wafer 102 may be sawn along saw lines into a plurality of regions 104. Each region 104 may correspond to a semiconductor die after wafer 102 is sawn. Region 104 may include a substrate (or an interposer), and a plurality of active components and / or passive components may be attached to or formed on the substrate. Active components may include memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, etc.), power management dies (e.g., power management integrated circuit (PMIC) dies), logic dies (e.g., system-on-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microcontroller, etc.), radio frequency (RF) dies, sensor dies, microelectromechanical system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end dies (AFE)), or other active components. Passive components may include capacitors, resistors, inductors, fuses, or other passive components.

[0168] Figures 7 to 33 It is a cross-sectional schematic diagram illustrating another embodiment of the present disclosure. Figure 2 The semiconductor component 10 is shown at one or more stages. Figures 7 to 31 A cross-sectional view of region 104 is illustrated at a stage prior to sawing wafer 102 . Figure 32 and Figure 33 A cross-sectional view of region 104 is illustrated at a stage after wafer 102 has been sawn.

[0169] Please refer to Figure 7 , an interposer 110 may be provided. The interposer 110 may have a surface 110s1 and a surface 110s2. In some embodiments, a dielectric layer 112 may be formed on the surface 110s2 of the interposer 110. The fabrication technique of the dielectric layer 112 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable techniques. In some embodiments, a mask 114 may be formed on the dielectric layer 112. The mask 114 may include, for example, a positive or negative photoresist of a polymer. The mask 114 may be patterned to have an opening, which may be configured to define a cavity 110v1 of the interposer 110. In some embodiments, a lithography technique and an etching technique may be performed to remove a portion of the interposer 110. In some embodiments, the cavity 110v1 may be recessed from the surface 110s2 of the interposer 110. The cavity 110v1 may have a depth D1 between the surface 110s2 of the interposer 110 and the bottom 110b1 of the cavity 110v1.

[0170] Please refer to Figure 8, the mask 114 can be removed, and a protective layer 116 can be formed on the dielectric layer 112. The protective layer 116 can be formed on the surface 110s2 of the interposer 110. The protective layer 116 can be formed on the surface 110s3 of the interposer 110. The protective layer 116 can be formed on the bottom 110b1 of the cavity 110v1. An insulating layer 118 can be formed on the protective layer 116 and fill the cavity 110v1. The fabrication technology of each of the protective layer 116 and the insulating layer 118 may include CVD, ALD, PVD or other suitable technology. In some embodiments, a polishing technology such as chemical mechanical polishing (CMP) can be performed on the insulating layer 118 to expose the protective layer 116.

[0171] Please refer to Figure 9 A mask 120 may be formed over the protective layer 116 and the insulating layer 118. The mask 120 may include, for example, a polymer positive or negative photoresist. The mask 120 may be patterned to form a plurality of openings 122. Each opening 122 may penetrate the insulating layer 118. The openings 122 may be configured to define a region for a TIV or a TOV.

[0172] Please refer to Figure 10 , a seed layer 124 may be formed within the opening 122 , as Figure 9 As shown. Seed layer 124 can contact insulating layer 118. Conductive via 126 can be formed in opening 122, as shown. Figure 9 As shown. Conductive vias 126 can be formed on the seed layer 124. The fabrication techniques of each of the conductive vias 126 and the seed layer 124 can include CVD, ALD, PVD, electroplating, or other suitable techniques. In some embodiments, the conductive vias 126 and the insulating layer 118 can define a TIV. In some embodiments, the conductive vias 126 can include Cu, tungsten (W), silver (Ag), gold (Au), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), alloys thereof, combinations thereof, or other suitable materials. In some embodiments, the conductive vias 126 and the insulating layer 118 define a TOV. In some embodiments, the conductive vias 126 and the seed layer 124 can include the same material.

[0173] Please refer to Figure 11, a mask 128 can be formed on the protective layer 116. The mask 128 can cover the conductive via 126. The mask 128 can include, for example, a polymer positive or negative photoresist. The mask 128 can be patterned to have an opening, which can be configured to define the cavity 110v2 of the interposer 110. In some embodiments, a lithography technique and an etching technique can be performed to remove a portion of the interposer 110 to form the cavity 110v2. In some embodiments, the cavity 110v2 can be recessed from the surface 110s2 of the interposer 110. The cavity 110v2 can have a depth D2 between the surface 110s2 and the bottom 110b2 of the cavity 110v2. In some embodiments, the depth D1 (e.g. Figure 7 shown) can be substantially equal to depth D2.

[0174] Please refer to Figure 12 , mask 128 can be removed, and protective layer 130 can be formed on protective layer 116. Protective layer 130 can be formed on surface 110s2 of interposer 110. Protective layer 130 can be formed on surface 110s4 of interposer 110. Protective layer 130 can be formed on bottom 110b2 of cavity 110v2. A conductive material 132a can be formed to fill cavity 110v2. Conductive material 132a can include a solder material, such as an alloy of gold and tin solder or an alloy of silver and tin solder. The fabrication technique of protective layer 130 can include CVD, ALD, PVD, or other suitable techniques. For example, the fabrication technique of conductive material 132a can include coating or other suitable techniques. A mask 134 can be formed on conductive material 132a. Mask 134 can cover conductive via 126. Mask 134 can include, for example, a polymer positive or negative photoresist. The mask 134 may be patterned to have a plurality of openings 136. In some embodiments, the openings 136 may be located on or within the cavity 110v2.

[0175] Please refer to Figure 13 A plurality of conductive pillars 138 may be formed within the openings 136. In some embodiments, the conductive pillars 138 may be formed within the cavity 110v2. The conductive pillars 138 may be fabricated using techniques such as CVD, ALD, PVD, electroplating, or other suitable techniques.

[0176] Please refer to Figure 14 , the mask 134 may be removed. The conductive material 132a may be exposed.

[0177] Please refer to Figure 15 , the conductive material 132 a exposed from the conductive pillars 138 may be removed, and a plurality of electrical connectors 132 b may be formed on the protection layer 130 .

[0178] Please refer to Figure 16 A packaging structure 150 can be attached to the conductive pillars 138. In some embodiments, the packaging structure 150 can be disposed within the cavity 110v2 of the interposer 110. The packaging structure 150 can include a plurality of electronic components 152, a redistribution structure 154, a plurality of conductive pads 156, and an encapsulant 158 ​​encapsulating the electronic components 152, the redistribution structure 154, and the conductive pads 156. In some embodiments, the conductive pads 156 can be bonded to the conductive pillars 138.

[0179] Please refer to Figure 17 , an encapsulation compound 160 may be formed in the cavity 110v2 to encapsulate the encapsulation structure 150 .

[0180] Please refer to Figure 18 A dielectric layer 162 may be formed on the package structure 150. The dielectric layer 162 may cover the protection layer 130. The dielectric layer 162 may be formed using CVD, ALD, PVD, or other suitable techniques.

[0181] Please refer to Figure 19 , a mask 164 can be formed on the dielectric layer 162. The mask 164 can include, for example, a positive or negative photoresist of a polymer. The mask 164 can be patterned to have an opening 166 and an opening 168. In some embodiments, the opening 166 can penetrate the mask 164 and the dielectric layer 162. In some embodiments, the opening 166 can penetrate a portion of the electronic component 152. In some embodiments, the opening 166 can be located above the cavity 110v2. In some embodiments, the opening 168 can penetrate the mask 164 and the dielectric layer 162. In some embodiments, the opening 168 can penetrate the protective layer 130. In some embodiments, the opening 168 can be located above the cavity 110v1. The conductive via 126 can be exposed from the opening 168.

[0182] Please refer to Figure 20 , mask 164 may be removed, and conductive element 170 and conductive element 172 may be formed. Conductive element 170 may be formed within opening 166, as shown. Figure 19 Conductive element 172 may be formed within opening 168, as shown. Figure 19 In some embodiments, a conductive layer (not shown) may be formed on dielectric layer 162, for example, by CVD, ALD, PVD, electroplating, or other suitable techniques. The conductive layer may fill openings 166 and 168, and a CMP technique may be performed to remove excess portions of the conductive layer. As a result, conductive elements 170 and 172 may be formed.

[0183] Please refer to Figure 21, the interposer 110 may be attached to a carrier 174. The carrier 174 may be in contact with the dielectric layer 162. The carrier 174 may include a glass substrate, a ceramic substrate, a plastic substrate, or other suitable carriers.

[0184] Please refer to Figure 22 A polishing technique, such as a CMP technique, may be performed on the surface 110s1 of the interposer 110. In some embodiments, the protective layer 116 may function as a polishing stop layer (e.g., a CMP stop layer). In some embodiments, the protective layer 130 may function as a polishing stop layer (e.g., a CMP stop layer). The protective layers 116 and 130 may be exposed from the interposer 110.

[0185] Please refer to Figure 23 A sacrificial layer 176 may be formed on the surface 110s1 of the interposer 110. The sacrificial layer 176 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The sacrificial layer 176 may be fabricated using CVD, ALD, PVD, electroplating, or other suitable techniques.

[0186] Please refer to Figure 24 A polishing technique, such as a CMP technique, may be performed to remove sacrificial layer 176. In some embodiments, the bottom of protective layer 116 may be removed. In some embodiments, the bottom of protective layer 130 may be removed. In some embodiments, a portion of seed layer 124 may be removed, and the bottom of conductive via 126 may be exposed. Surface 110s1 of interposer 110 may be exposed.

[0187] Please refer to Figure 25 A plurality of conductive elements 180 may be formed on the surface 110s1 of the interposer 110. The conductive elements 180 may be electrically connected to the electrical connector 132b and the conductive via 126, respectively. In some embodiments, the conductive elements 180 may taper away from the interposer 110. That is, the sidewalls 180s3 of the conductive elements 180 may be inclined. In some embodiments, the sidewalls 180s3 of the conductive elements 180 may be substantially vertical.

[0188] Please refer to Figure 26 A layer of spacer material 251 can be conformally formed on the surface 110s1 of the interposer 110 and can cover the conductive element 180. In some embodiments, for example, the spacer material 251 can include a low-k oxide-based dielectric, such as carbon-doped silicon oxide or fluorinated oxide. In some embodiments, the spacer material 251 can be formed using CVD, ALD, or other suitable techniques.

[0189] Please refer to Figure 27A passivation layer 178 may be formed on the surface 110s1 of the interposer 110. Specifically, the passivation layer 178 may be formed on the layer of spacer material 251. In other words, the conductive element 180 and the layer of spacer material 251 may be formed within the passivation layer 178. The fabrication techniques of the passivation layer 178 may include coating or other suitable techniques.

[0190] Please refer to Figure 28 A polishing technique, such as a CMP technique, may be performed to remove a portion of the layer of spacer material 251. This may expose a surface 180s2 of the conductive element 180. The remaining layer of spacer material 251 may be referred to as a spacer 250. In some embodiments, the surface 180s2 of the conductive element 180, the surface 110s1 of the interposer 110, and the surface 250s2 of the spacer 250 may be substantially coplanar.

[0191] Please refer to Figure 29 In some embodiments, a plurality of electrical connectors 182 may be formed respectively and correspondingly on the conductive elements 180 .

[0192] Please refer to Figure 30 , the surface 110s1 of the interposer 110 may be attached to a holder 184. The holder 184 may include a tape or other suitable material.

[0193] Please refer to Figure 31 , electronic components 186a, 186b, 188a, and 188b may be attached to surface 110s2 of interposer 110. Electronic component 186a and electronic component 186b may be connected to dielectric layer 162 via adhesive layer 187. Passivation layer 189 and conductive element 190 may be formed on the active surfaces of electronic component 188a and electronic component 188b. In some embodiments, a hybrid bonding technique may be performed to bond electronic component 188a (or electronic component 188b) to dielectric layer 162 and conductive element 170 (or conductive element 172). Specifically, the hybrid bonding technique may include oxide-to-oxide bonding and metal-to-metal bonding. The oxide-to-oxide bonding may be derived from the bonding between passivation layer 189 and dielectric layer 162 of electronic component 188a (or electronic component 188b). The metal-to-metal bond may result from bonding between conductive element 190 of electronic component 188a (or electronic component 188b) and conductive element 170 (or conductive element 172). In some embodiments, the temperature of the hybrid bonding technique may be between about 300°C and about 450°C.

[0194] In some embodiments, electronic component 188 a may be disposed over package structure 150 . Electronic component 188 b may be disposed over conductive via 126 .

[0195] Please refer to Figure 32 , the holder 184 can be removed. The interposer 110 can be sawed so that the interposers 110 can be spaced apart. Figure 31 A motherboard 194 can be attached to the surface 110s1 of the interposer 110. In some embodiments, the electrical connectors 182 can be bonded to pads (not labeled) on the motherboard 194. In some embodiments, the electrical connectors 196 can be bonded to pads (not labeled) on the motherboard 194.

[0196] Please refer to Figure 33 , a plurality of wires 198 may be formed to electrically connect the motherboard 194 and the electronic device 186a (or 186b). As a result, the semiconductor device 10 may be manufactured.

[0197] One embodiment of the present disclosure provides a semiconductor device, comprising an interposer having a first surface and a second surface parallel to the first surface; a conductive via extending between the first and second surfaces of the interposer; an insulating layer separating the conductive via from the interposer; a first electronic component disposed on the second surface and electrically connected to the conductive via; a first conductive element disposed on the first surface of the interposer and electrically connected to the conductive via; a spacer conformally disposed on the first surface of the interposer and on each sidewall of the first conductive element; and a passivation layer disposed on the spacer. The passivation layer has a first dielectric constant, and the spacer has a second dielectric constant less than the first dielectric constant.

[0198] Another embodiment of the present disclosure provides a semiconductor device including an interposer having a first surface and a second surface parallel to the first surface, wherein the interposer defines a first cavity and a second cavity extending between the first and second surfaces; an insulating via located within the first cavity; a first electronic component located on the second surface of the interposer and electrically connected to the insulating via; a second electronic component located within the second cavity; a first conductive component located on the first surface of the interposer and electrically connected to the insulating via; a spacer conformally positioned on the first surface of the interposer and on each sidewall of the first conductive component; and a passivation layer located on the spacer. The passivation layer has a first dielectric constant, and the spacer has a second dielectric constant less than the first dielectric constant.

[0199] Another embodiment of the present disclosure provides a method for fabricating a semiconductor device, comprising providing an interposer including a first surface and a second surface parallel to the first surface; recessing a first cavity from the second surface; forming an insulating layer to fill the first cavity; forming a conductive via to penetrate the insulating layer; thinning the interposer from the first surface to expose the conductive via; forming a first conductive element on the first surface of the interposer and electrically connected to the conductive via; conformally forming a spacer on the first surface of the interposer and on each sidewall of the first conductive element; forming a passivation layer on the spacer; and performing a hybrid bonding technique to bond the first electronic device to the second surface of the interposer and electrically connect to the conductive via. The passivation layer has a first dielectric constant, and the spacer has a second dielectric constant less than the first dielectric constant.

[0200] Due to the design of the semiconductor device disclosed herein, the through-insulation via (TIV, e.g., conductive via 126) has a relatively small parasitic capacitance compared to a through-substrate via (TSV). Furthermore, the depth of the through-insulation via (TIV) can be controlled by determining the depth of the cavity (e.g., 110v1), and the protective layer can prevent the interposer from being over-polished. As a result, the depth of the through-insulation via (TIV) can be relatively well controlled compared to a through-substrate via (TSV). In addition, RC delay can be reduced by using a passivation layer 178 and spacers 250 having different dielectric constants. As a result, the performance of the semiconductor device 10 can be improved.

[0201] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above may be implemented in different ways, and other processes or combinations thereof may be substituted for many of the processes described above.

[0202] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with this disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of this application.

Claims

1. A semiconductor element comprising: an interposer having a first surface and a second surface parallel to the first surface; a conductive via extending between the first surface and the second surface of the interposer; an insulating layer separating the conductive via from the interposer; a first electronic component disposed on the second surface and electrically connected to the conductive through hole; a first conductive element located on the first surface of the interposer and electrically connected to the conductive via; a spacer conformally positioned on the first surface of the interposer and on each sidewall of the first conductive element; as well as A passivation layer is located on the spacer. The passivation layer has a first dielectric constant, and the spacer has a second dielectric constant smaller than the first dielectric constant. 2 . The semiconductor device as claimed in claim 1 , further comprising a second electronic component embedded in the interposer. The semiconductor device as claimed in claim 2 , wherein the second electronic component is embedded in a packaging structure. 4 . The semiconductor device as claimed in claim 2 , further comprising a conductive pillar extending between the first surface of the interposer and the second electronic component. 5 . The semiconductor device as claimed in claim 2 , further comprising a packaging resin encapsulating the second electronic device, wherein the packaging resin completely penetrates the interposer. 6 . The semiconductor device as claimed in claim 2 , further comprising a third electronic device disposed on the second electronic device and electrically connected to the second electronic device. 7 . The semiconductor device as claimed in claim 6 , further comprising a second conductive element electrically connecting the second electronic element and the third electronic element, wherein the second conductive element passes through the second electronic element. The semiconductor device as claimed in claim 6 , wherein the insulating layer comprises silicon oxide.

9. The semiconductor device according to claim 6, further comprising: a fourth electronic component located on the second surface of the interposer; a motherboard supporting the interposer; as well as A conductive wire electrically connects the fourth electronic component and the motherboard.

10. The semiconductor device of claim 1, further comprising a protection layer disposed on the second surface of the interposer, wherein the protection layer is further disposed between the conductive via and the interposer, wherein the protection layer has a third surface that is substantially coplanar with the first surface of the interposer.

11. The semiconductor device of claim 1, wherein the spacer comprises a low-k oxide-based dielectric. 12 . The semiconductor device as claimed in claim 1 , wherein the passivation layer comprises silicon oxide.

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