Memory packaging structure and packaging method thereof

Abstract

The invention provides a memory packaging structure and a packaging method thereof, the memory packaging structure comprises a substrate, the substrate is provided with a first surface and a second surface which are oppositely arranged, and at least two grooves are formed in the substrate from the first surface to the second surface; the at least two chip stacking structures are located in the grooves respectively, and the chip stacking structures are arranged in the first direction of the substrate; and the heat dissipation structure is located between the two adjacent chip stacking structures. Through the micro-channel heat dissipation structure embedded in the substrate, the heat generated by the chip in the packaging body is taken away through fluid flow, the heat can be quickly conducted out, and the heat transfer efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a memory packaging structure and a packaging method thereof. Background Art

[0002] In recent years, with the rapid progress in the field of artificial intelligence technology, chip design has tended to develop in the direction of miniaturization, high integration, and high computing power. Three-dimensional stacking packaging technology has emerged as the times require. It is regarded as a key technical path to break through the limitations of Moore's Law and achieve high-density integration, compact size and diversified functional devices. High Bandwidth Memory (HBM) is a memory based on a 3D stacking process that stacks multiple DRAM chips together through advanced packaging technology (such as TSV silicon through vias and microbumps) and packages them together with GPUs to form a large-capacity, high-bandwidth DDR combination array. In traditional HBM packaging, HBM and logic chips are usually separately soldered on a substrate for packaging as a whole, and the packaging efficiency is low.

[0003] At the same time, at such high power density, due to the differences in thermal expansion coefficients of the various stacked materials within the three-dimensional packaging structure, the large wall temperature rise will generate thermo-mechanical stress at the interface between different materials, seriously affecting the reliability of the system; at the same time, the heat generated by the through-silicon via during operation will directly affect the carrier migration characteristics of the active components in the chip, and in extreme cases may cause chip performance degradation or even failure. The commonly used three-dimensional packaging heat dissipation method is to transfer heat to the air through surface mounting, but this heat dissipation structure is not in direct contact with the chip, and the heat cannot be transferred out in a timely and efficient manner. In view of this, exploring a three-dimensional stacking method and structural optimization that can effectively reduce thermal stress, improve heat dissipation efficiency, and ensure the long-term stable operation of the chip has become a technical problem that urgently needs to be solved. Summary of the Invention

[0004] In view of the above-mentioned problems existing in memory packaging in the prior art, the present application provides a memory packaging structure and a packaging method thereof, which are used to solve the problems of low heat dissipation efficiency of traditional packaging methods in the prior art.

[0005] To achieve the above-mentioned and other related purposes, the present invention provides a memory packaging structure, which includes:

[0006] A substrate having a first surface and a second surface opposite to each other, wherein a plurality of grooves are formed in the substrate from the first surface to the second surface.

[0007] A plurality of chip stacking structures are disposed in the groove in a one-to-one correspondence.

[0008] Optionally, a first interconnect structure is located on the first surface, the first interconnect structure includes a first dielectric layer and a first redistribution layer, and the first redistribution layer is embedded in the first dielectric layer;

[0009] a second interconnect structure located on the second surface, the second interconnect structure comprising a second dielectric layer and a second redistribution layer, wherein the second redistribution layer is embedded in the second dielectric layer;

[0010] The first conductive pillar penetrates the substrate along a thickness direction of the substrate and connects the first interconnection structure and the second interconnection structure.

[0011] Optionally, the chip stacking structure includes:

[0012] Logic chips;

[0013] a plurality of memory chips, wherein the plurality of memory chips are stacked sequentially above and / or below the logic chip;

[0014] A plurality of second conductive pillars are disposed between the logic chip and the memory chip, and between the memory chips, so as to connect the logic chip and the memory chip.

[0015] Optionally, a plurality of heat-conducting columns are further included, and the second conductive columns and the heat-conducting columns are distributed at intervals.

[0016] Optionally, the second conductive pillars adjacent to the heat-conducting pillar are distributed in a diamond shape; and the heat-conducting pillars adjacent to the second conductive pillar are distributed in a diamond shape.

[0017] Optionally, a projected area of ​​the second conductive pillar on the substrate surface is smaller than or equal to a projected area of ​​the thermal conductive pillar on the substrate surface.

[0018] Optionally, a filling layer is filled between the chip stacking structure and the groove.

[0019] Optionally, an upper surface of the chip stacking structure is flush with the first surface of the substrate.

[0020] Optionally, a heat dissipation structure is further included, located between two adjacent chip stacking structures.

[0021] Optionally, the heat dissipation structure includes:

[0022] a heat dissipation slot, comprising a flow channel, an inlet, and an outlet, wherein the flow channel is located in the substrate, and the inlet and the outlet are exposed from the second surface of the substrate;

[0023] A heat dissipation cover plate covers the heat dissipation slot.

[0024] Optionally, the heat dissipation structure includes a microchannel heat dissipation structure.

[0025] Another aspect of the present invention provides a memory packaging method, which specifically includes:

[0026] Fabricating a plurality of chip stack structures, wherein the chip stack structure includes a logic chip and a plurality of vertically stacked memory chips;

[0027] Providing a substrate, the substrate comprising a first surface and a second surface opposite to each other, with the first surface pointing to the second surface, and a plurality of grooves and a plurality of first through holes formed inside the substrate;

[0028] embedding the chip stacking structure into the groove, and filling the first through hole with a conductive medium;

[0029] forming a heat dissipation groove inside the substrate from the first surface to the second surface, and forming a heat dissipation cover plate above the heat dissipation groove;

[0030] A first interconnect structure is formed on the first surface, and a second interconnect structure is formed on the second surface. The first interconnect structure and the second interconnect structure are connected through the first conductive pillar.

[0031] Optionally, embedding the chip stacking structure into the groove includes:

[0032] filling the groove with a filler;

[0033] placing the chip stacking structure in the groove;

[0034] Then, the filler is filled into the groove until the entire groove is filled.

[0035] As described above, the memory packaging structure, packaging method thereof, and display device provided by the present invention have at least the following beneficial technical effects:

[0036] In the memory packaging structure of the present invention, a microfluidic structure heat dissipation structure embedded in the substrate utilizes fluid flow to carry away the heat generated by the chip inside the package, which can quickly dissipate heat and improve heat transfer efficiency. The logic chip and the memory chip are vertically stacked and pre-buried in the groove of the silicon substrate, and interconnected by combining TSV through-holes and micro-bumps, thereby improving the integration of the package and greatly reducing the package size. The electrical / thermal TSVs arranged in a diamond or equilateral triangle shape not only achieve signal connectivity between the logic chip and the memory chip, but also offset the horizontal and vertical thermal stress of adjacent through-hole structures, avoiding interface delamination caused by stress concentration. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1Shown is a schematic diagram of the memory packaging structure provided in embodiment 1.

[0038] Figure 2 Shown is a schematic diagram of the chip stacking structure provided in Example 1.

[0039] Figure 3 Displayed as Figure 2 The cross-sectional view in the AA' direction is shown.

[0040] Figure 4 Shown is a flowchart of the memory packaging method provided in the second embodiment.

[0041] Figure 5a The figure shows a schematic structural diagram of a second conductive pillar formed on a logic chip according to the second embodiment;

[0042] Figure 5b The figure shows a schematic structural diagram of a second conductive pillar formed on a memory chip according to the second embodiment;

[0043] Figure 6 Shown is a schematic structural diagram of a substrate in the memory packaging method provided in the second embodiment;

[0044] Figure 7 Display as Figure 6 A top view of the memory package structure shown;

[0045] Figure 8 It shows a schematic diagram of the structure after the chip stacking structure is placed on the substrate.

[0046] Figure 9 Shown is a schematic diagram of the structure in which a heat dissipation groove is formed inside the substrate.

[0047] Figure 10 It is a schematic diagram showing forming a first interconnect structure on the first surface.

[0048] Figure 11 Shown is a schematic diagram of the structure in which a temporary carrier is bonded to the first surface.

[0049] Figure 12 Shown is a schematic structural diagram of the substrate thinning process.

[0050] Figure 13 It shows a schematic structural diagram of forming a second dielectric layer and an insulating layer on the second surface.

[0051] Figure 14 A schematic diagram showing forming a second interconnect structure on the second surface is shown.

[0052] Reference numerals

[0053] 100. Substrate; 101. First surface; 102. Second surface; 103. Groove; 104. Filling layer; 150. First through hole; 110. Chip stacking structure; 111. Logic chip; 112. Memory chip; 113. Insulating layer; 114. Second conductive pillar; 115. Thermally conductive pillar; 116. Conductive through hole; 117. Thermally conductive through hole; 120. Heat dissipation structure; 121. Heat dissipation slot; 1211. Inlet; 1212. Outlet; 122. Heat dissipation cover; 130. First interconnect structure; 131. First dielectric layer; 132. First redistribution layer; 133. Bonding bump; 140. Second interconnect structure; 141. Second dielectric layer; 142. Second redistribution layer; 150. First conductive pillar; 160. Temporary carrier; 170. Insulating layer. DETAILED DESCRIPTION

[0054] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0055] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity, positional relationship and proportion of each component in actual implementation can be changed at will under the premise of realizing the technical solution of this party, and the component layout form may also be more complicated.

[0056] Example 1

[0057] This embodiment provides a memory packaging structure, such as Figure 1 As shown, a schematic diagram of the memory packaging structure provided in this embodiment is shown; the memory packaging structure provided in this application includes: a substrate 100, having a first surface 101 and a second surface 102 arranged opposite to each other, and a plurality of grooves 103 arranged at intervals from the first surface 101 to the second surface 102 are formed inside the substrate 100; a plurality of chip stacking structures 110 are arranged in the grooves 103 in a one-to-one correspondence.

[0058] For details, please refer to Figure 7 Generally, the size and shape of the groove 103 can be designed based on the size and shape of the chip stacking structure 110. Optionally, the layout of the groove 103 takes into account the layout of the heat dissipation structure and the conductive column, and the chip integration can be achieved through a reasonable layout. Specifically, Figure 1As shown, in this embodiment, the horizontal X direction along the substrate 100 is defined as the first direction. In this embodiment, two grooves 103 are provided in the first direction, and two chip stacking structures 110 are provided in the grooves 103 in a one-to-one correspondence.

[0059] Optionally, the chip stacking structure 110 is pre-buried in the groove 103 of the substrate 100, and a filling layer 104 is filled between the chip stacking structure 110 and the substrate 100. Optionally, the filling layer 104 is located between the chip stacking structure 110 and the groove 103, including the bottom surface and side walls of the chip stacking structure 110. Optionally, the filling layer 104 wraps the chip stacking structure 110, specifically including the filling layer 104 being located on the top surface, bottom surface and side walls of the chip stacking structure 110. Those skilled in the art will appreciate that a filling layer 104 is provided on the top surface of the chip stacking structure 110, but conductive structures such as conductive or bumps can be drawn out of the filling layer 104 for electrical connection. Generally, the filling layer 104 includes resin (including epoxy resin, silicone resin, etc.), silicon-based composite materials (including silica gel, etc.), polyimide and molding compounds, etc. Specifically, in this embodiment, the filling layer 104 is a resin. The filling layer 104 is located in the gap between the chip stacking structure 110 and the substrate groove 103. After curing, the filling layer 104 forms a rigid or semi-rigid support body, preventing the chip stacking structure 110 from shifting or deviating within the substrate 100. Furthermore, the filling layer 104 isolates the chip stacking structure 110 from the metal lines of the substrate 100, preventing short circuits or leakage.

[0060] Specifically, the upper surface of the chip stacking structure 110 is flush with the first surface 101 of the substrate 100. Optionally, if there is no filling layer 104 above the chip stacking structure 110, the upper surface of the chip stacking structure 110 is flush with the first surface 101 of the substrate 100; if a filling layer is filled above the chip stacking structure 110, the filling layer 104 on the upper surface of the chip stacking structure 110 is flush with the first surface 101 of the substrate 100.

[0061] Optionally, the memory package structure provided in this embodiment further includes a first interconnect structure 130, the first interconnect structure 130 including a first dielectric layer 131, a first redistribution layer 132, and bonding bumps 133; the first interconnect structure 130 is located on the first surface 101. Optionally, the memory package structure further includes a second interconnect structure 140, located on the second surface 102. Optionally, the memory package structure further includes a first conductive pillar 150, extending along the thickness direction of the substrate (i.e., Figure 1 The first conductive pillar 150 extends through the substrate 100 in the Z direction. One end of the first conductive pillar 150 is connected to the first interconnect structure 130, and the other end is connected to the second interconnect structure 140, so as to connect the first interconnect structure 130 and the second interconnect structure 140. Figure 7The position of the first conductive pillars 150 can be set according to actual needs. Specifically, in this embodiment, two first conductive pillars 150 are provided, which are respectively arranged on both sides of the chip stacking structure 110.

[0062] Specifically, the first interconnect structure 130 includes a first dielectric layer 131 and a first rewiring layer 132. The first rewiring layer 132 is embedded in the first dielectric layer 131. One side of the first rewiring layer 132 is electrically connected to the first conductive pillar 150 and the chip stacking structure 110, and the other end exposes the first dielectric layer 131 for external electrical connection. The second interconnect structure 140 includes a second dielectric layer 141 and a second rewiring layer 142. The second rewiring layer 142 is embedded in the second dielectric layer 141, and the second rewiring layer 142 is electrically connected to the first rewiring layer 132 through the first conductive pillar 150. Generally, the materials of the first dielectric layer 131 and the second dielectric layer 141 include oxide (SiO2), silicon nitride and other materials. The materials of the first rewiring layer 132 and the second rewiring layer 142 include copper, aluminum and other materials.

[0063] Specifically, if Figure 2 As shown in FIG, a schematic diagram of the chip stacking structure provided in this embodiment is shown; it can be seen from the figure that the chip stacking structure 110 includes at least one logic chip 111 and multiple memory chips 112, and the multiple memory chips 112 are stacked in sequence above and / or below the logic chip 111. Specifically, the logic chip 111 and the memory chip 112 are Figure 2 The stacking is performed in the Z direction (i.e., vertical direction) as shown. Generally, the logic chip 111 includes: a central processing unit (CPU), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), or a memory controller (such as a DDR controller), which is responsible for performing calculations, signal processing, or storage management tasks; the memory chip 112 includes: a high-bandwidth memory (HBM), a dynamic random access memory (DRAM), a three-dimensional stacked NAND flash memory, or other non-volatile storage unit for data storage and high-speed transmission. Specifically, in this embodiment, the memory chip 112 is a high-bandwidth memory chip.

[0064] Generally, the number of logic chips 111 and vertically stacked memory chips 112 can be adjusted according to actual needs. Optionally, the number of chips in the chip stacking structure 110 includes logic chips 111 + memory chips 112, specifically including: 1+3, 1+4, 1+5, ... 1+8 and other combinations. Specifically, the number of memory chips 112 is greater than or equal to 2, and three memory chips 112 are set in this embodiment. Generally, the positions of the logic chips 111 and the memory chips 112 in the vertical direction can be adjusted according to actual needs. Optionally, the logic chip 111 is located at the bottom or top of all the memory chips 112; optionally, the logic chip 111 is located in the middle of the memory chips 112. Specifically, as Figure 2 As shown, the chip stacking structure 110 in this embodiment includes a logic chip 111 and three memory chips 112, wherein the logic chip 111 is located in the second layer from the top line. Generally, the chip stacking structure 110 has a thickness of 200-300 μm and a width of 200-400 μm.

[0065] Optionally, the chip stacking structure 110 further includes an insulating layer 113, which is disposed between the logic chip 111 and the memory chip 112, and between the memory chips 112. The chip stacking structure 110 further includes a second conductive pillar 114, which is formed within the insulating layer 113 and disposed between the logic chip 111 and the memory chip 112, and between the memory chips 112, to achieve connectivity between the logic chip 111 and the memory chip 112. Generally, the second conductive pillar 114 primarily implements vertical electrical interconnection within the chip stack for signal and power transmission, and is filled with a highly conductive material such as copper.

[0066] Optionally, the chip stacking structure 110 further includes heat conducting pillars 115, which are primarily used for heat transfer within the chip stacking structure. Optionally, the heat conducting pillars 115 may be filled with a medium or not, and the filling material includes a highly thermally conductive material such as copper, tungsten, or a composite metal.

[0067] Generally, the distribution of the second conductive pillars 114 is designed according to the specific transmission path of the chip stacking structure 110, and is concentrated in the high-density area; the distribution of the heat-conducting pillars 115 is arranged according to the heat-generating area of ​​the chip stacking structure 110, and is mainly distributed near the high-power consumption unit. Figure 3 As shown, it is shown along Figure 2The cross-sectional view along the AA' direction is shown; it can be seen from the figure that the second conductive pillars 114 and the thermal conductive pillars 115 are spaced apart. Specifically, the second conductive pillars 114 adjacent to the thermal conductive pillar 115 are distributed in a rhombus shape, and the thermal conductive pillars 115 adjacent to the second conductive pillar 114 are distributed in a rhombus shape. From another angle: the second conductive pillars 114 (thermal conductive pillars 115) are arranged in an equilateral triangle. Generally, the number of the second conductive pillars 114 can be designed according to the size of the actual logic chip 111 and the memory chip 112. Specifically, as Figure 3 As described above, in this embodiment, the second conductive pillars 114 are arranged in 4 rows, each row has 5 through holes, and the second conductive pillars 114 and the thermal conductive pillars 115 are arranged at intervals.

[0068] Generally, the projected area of ​​the second conductive pillar 114 on the surface of the substrate 100 is smaller than or equal to the projected area of ​​the thermally conductive pillar 115 on the substrate surface. Assuming the conductive pillars are circular, specifically, the aspect ratio of the second conductive pillar 114 is between 5:1 and 10:1, and the aspect ratio of the thermally conductive pillar 115 is between 3:1 and 5:1. Therefore, at the same depth, the width of the second conductive pillar 114 is smaller than or equal to the width of the thermally conductive pillar 115. Specifically, the diameter of the second conductive pillar 114 is between 5 and 20 μm, and the diameter of the thermally conductive pillar 115 is between 10 and 50 μm.

[0069] Optionally, microbumps (not shown) are further included between the second conductive pillars 114 and the connections to the logic chip 111 and the memory chip 112. The microbumps are located at the connection locations between the logic chip 111 and the memory chip 112 and the second conductive pillars 114. The microbumps and the second conductive pillars 114 together form a vertical interconnection network. The microbumps act as extended contacts to enhance the reliability of the interconnection.

[0070] Optionally, the memory packaging structure further includes a heat dissipation structure 120. The arrangement of the heat dissipation structure 120 is set according to actual needs, and one or more heat dissipation structures 120 are set near the chip stacking structure 110 or other high-power heat dissipation devices. Specifically, in this embodiment, the heat dissipation structure 120 is located between two adjacent chip stacking structures 110. Generally, the heat dissipation structure 120 includes a heat sink, a heat pipe, and a microchannel heat dissipation structure. Specifically, in this embodiment, the heat dissipation structure 120 is a microchannel heat dissipation structure. Please continue to refer to Figure 1The heat dissipation structure 120 includes a heat dissipation slot 121 and a heat dissipation cover 122. Specifically, the heat dissipation cover 122 is close to the first surface 101 of the substrate 100; the heat dissipation slot 121 includes a flow channel, an inlet 1211 and an outlet 1212. The flow channel is located inside the substrate 100, and the inlet 1211 and the outlet 1212 are exposed to the second surface 102 of the substrate 100. Generally, the flow channel distribution of the heat dissipation slot 121 in the heat dissipation structure 120 includes other distributions such as serpentine, mesh, and branched. The specific distribution of the heat dissipation slot 121 is not limited and can be set according to actual needs. By optimizing the channel, the heat dissipation efficiency can be improved. Generally, the material of the heat dissipation cover 122 includes metal copper, stainless steel, aluminum alloy and other materials. Specifically, in this embodiment, the material of the heat dissipation cover 122 is copper.

[0071] The memory packaging structure provided in this embodiment stacks a logic chip and multiple memory chips vertically, and at the same time pre-buries the stacked chips in a silicon-based material. Compared with welding on the surface of the material and plastic sealing, it can improve the integration and reduce the package size. The memory packaging structure provided by the present invention integrates the heat dissipation structure inside the package body, and takes away the heat generated by the chip inside the package body through the flow of fluid. Its heat transfer efficiency is much greater than surface mount heat dissipation. In addition, the present invention sets a triangular distributed silicon via structure on the memory chip, which can not only realize signal connection between chips, but also make the thermal stress of adjacent silicon via structures in the horizontal direction and the thermal stress in the vertical direction offset in the horizontal plane direction, so that the thermal stress between the silicon via structures is separated from each other, and there will be no thermal stress overlap.

[0072] Example 2

[0073] This embodiment also provides a memory packaging method, such as Figure 4 FIG. 1 is a flowchart of a memory packaging method provided in this embodiment; the packaging method provided in this embodiment specifically includes the following steps:

[0074] S1: Fabricate at least two chip stacking structures, wherein the chip stacking structures include a logic chip and a plurality of vertically stacked memory chips;

[0075] Providing a substrate, the substrate comprising a first surface and a second surface disposed opposite to each other, at least two grooves and a plurality of through holes being formed inside the substrate from the first surface toward the second surface;

[0076] embedding the chip stack structure into the groove and filling the through hole;

[0077] forming a heat dissipation groove inside the substrate from the first surface to the second surface, and forming a heat dissipation cover plate above the heat dissipation groove;

[0078] A first interconnection structure is formed on the first surface, and a second interconnection structure is formed on the second surface. The first interconnection structure and the second interconnection structure are connected through the through hole.

[0079] Optionally, the method for manufacturing a chip stacking structure includes the following steps:

[0080] S11: providing a plurality of logic chips 111 and a plurality of memory chips 112 .

[0081] Specifically, logic chip 111 includes chips such as HBM or 3D DRAM; memory chip 112 includes chips such as CPU and GPU. Optionally, microbumps are formed on the upper and lower surfaces of logic chip 111 and memory chip 112. Optionally, the diameter of the microbumps ranges from 10 to 50 μm.

[0082] S12: stacking the logic chip 111 and the memory chip 112.

[0083] Generally, the number of layers of the chip stacking structure 110 can be selected according to actual needs. For details, please refer to Example 1 and will not be repeated here. The chip stacking structure 110 provided in this embodiment includes a layer of logic chip 111 and three layers of memory chips 112. Optionally, the logic chip 111 is located on the bottom or top surface of the chip stacking structure 110; the logic chip 111 is located in the middle chip of the chip stacking structure 110. Specifically, in this embodiment, the logic chip 111 is located in the middle position of the chip stacking structure 110.

[0084] Optionally, the stacking methods of the logic chip 111 and the memory chip 112 include: vertically stacking the logic chips 111 and the memory chips 112 layer by layer; modular stacking, first stacking the logic chips 111 and the memory chips 112 in pairs to form a sub-stack structure, and then integrating the sub-stack structure. Specifically, this embodiment adopts modular stacking, first stacking the logic chips 111 and the memory chips 112 in pairs to form a sub-stack structure, and then integrating the sub-stack structure.

[0085] Specifically, if Figure 5a-5bAs shown, it is a schematic structural diagram of forming a second conductive column on the logic chip and the memory chip provided in this embodiment; specifically, an insulating layer 113 is formed on the upper surface of the logic chip 111 and the memory chip 112, and a mask is formed above the insulating layer 113, and a conductive through-hole 116 is formed in the insulating layer 113 by etching. Generally, the diameter of the conductive through-hole 116 is between 5 and 20 μm, and the depth of the conductive through-hole 116 is equal to the thickness of the insulating layer 113. Optionally, a thermal through-hole 117 is also formed in the insulating layer 113, and the diameter of the conductive through-hole 116 is smaller than the diameter of the thermal through-hole 117, and the diameter of the thermal through-hole 117 is between 10 and 50 μm. For details, please refer to Example 1 of the present application. The insulating layer 113 is used to provide support for solidification, reduce stress, and improve heat dissipation.

[0086] Optionally, stacking the logic chip 111 and the memory chip 112 further includes forming conductive pillars on the upper surfaces of the logic chip 111 and the memory chip 112, respectively, and then stacking the logic chip 111 and the memory chip 112. After stacking, in conjunction with the subsequent step S3, an insulating layer is simultaneously filled between the logic chip 111 and the memory chip 112. The process steps for stacking the logic chip 111 and the memory chip 112 are not limited to the method disclosed in this application.

[0087] Specifically, the logic chip 111 is aligned with the memory chip 112 or the memory chip 112 is aligned with the memory chip 112, and a sub-stack structure is formed by micro-bump bonding. Finally, the sub-stack structure is integrated and bonded to form a Figure 2 The chip stacking structure shown.

[0088] Step S2: providing a substrate, wherein the substrate comprises a first surface and a second surface opposite to each other, wherein the first surface points to the second surface, and at least two grooves and a plurality of first through holes are formed inside the substrate.

[0089] like Figure 6 As shown, it is a schematic structural diagram of the substrate in the memory packaging method provided by this embodiment; Figure 6 It can be seen that the substrate 100 provided in this embodiment includes a first surface 101 and a second surface 102 arranged opposite to each other, and a plurality of grooves 103 and a plurality of first through holes 105 are formed inside the substrate 100 in the direction from the first surface 101 to the second surface 102 .

[0090] Typically, the thickness of substrate 100 is between 200 and 500 μm. The depth of groove 103 is greater than or equal to the thickness of chip stacking structure 110, and the width of groove 103 is greater than or equal to the width of chip stacking structure 110. The depth of groove 103 is between 200 and 400 μm, and the width is between 200 and 500 μm. Specifically, the depth of first through-hole 105 is greater than the depth of groove 103, and typically, the depth of first through-hole 105 is between 300 and 500 μm.

[0091] like Figure 7 As shown, it is shown as Figure 6 Top view of the structure shown. Figure 6 The structure shown is Figure 7 Generally, the position and number of the groove 103 and the first through hole 105 can be set according to actual needs, the number of the groove 103 is the same as the number of the chip stacking structure 110, and the first through hole 105 is arranged according to actual needs.

[0092] Specifically, in this embodiment, taking a two-chip stack structure 110 as an example, first through-holes 105 are distributed on both sides of the chip stack structure 110. Specifically, grooves 103 are arranged in the first direction, with a certain gap left between adjacent grooves 103 to allow for the subsequent formation of heat dissipation structure 120. The width of the reserved gap is adjusted based on the actual width of heat dissipation structure 120. Generally, the width of the reserved gap is 0.5 to 3 mm.

[0093] Step S3: embedding the chip stacking structure into the groove, and filling the first through hole with a conductive medium to form a first conductive column.

[0094] like Figure 8 As shown, it is a schematic diagram of the structure after the chip stacking structure is placed on the substrate; specifically, the specific steps of placing the chip stacking structure 110 in the groove 103 include: a first step of filling the groove 103 with filler to a certain height, specifically filling it to 20% to 30% of the total height of the entire groove; a second step of placing the chip stacking structure 110 in the groove 103, and there is a certain gap between the edge of the chip stacking structure 110 and the side wall of the groove 103; a third step of filling the groove 103 with filler until the filler fills the entire groove, and then curing it to form a filling layer 104, so that the top of the chip stacking structure 110 is flush with the first surface 101 of the substrate 100.

[0095] Optionally, the filling layer 104 may cover the upper surface of the chip stacking structure 110 . After curing, the filling layer 104 is flush with the first surface 101 of the substrate 100 . Specifically, in this embodiment, the filling layer 104 covers the upper surface of the chip stacking structure 110 .

[0096] Specifically, when the chip stacking structure 110 is placed in the groove 103, the alignment marks on the chip stacking structure 110 and the edges of the groove 103 are aligned to ensure that the spacing between the chip stacking structure 110 and the side walls of the groove 103 is between 5 and 10 μm. Generally, the alignment marks on the chip stacking structure 110 include micro-bumps, chips and other structures. And a certain thickness of filler is reserved on the bottom surface of the chip stacking structure 110 and the groove 103 to alleviate the stress concentration caused by subsequent curing and cause the chip to deflect. Generally, the filling layer 104 includes a low-viscosity, high-fluidity material, including resin (including epoxy resin, silicone resin, etc.), silicon-based composite materials (including silicone, etc.), polyimide and molding compounds, etc. Specifically, in this embodiment, the filling layer 104 is a resin.

[0097] Specifically, a conductive medium layer is filled in the first through hole 105 to form a first conductive pillar 150 to achieve a conductive function. Generally, the filling material includes conductive materials such as copper, tungsten or composite metals. In this embodiment, copper is filled in the first through hole 105.

[0098] Optionally, a planarization process is also included, using chemical mechanical polishing (CMP) or dry etching (such as plasma etching) to make the height difference between the filling layer 104 and the first conductive column 150 and the first surface of the substrate ≤1μm, to ensure the subsequent bonding quality of the heat dissipation cover or interconnection structure.

[0099] Step S4: forming a heat dissipation groove inside the substrate from the first surface to the second surface, and forming a heat dissipation cover plate above the heat dissipation groove.

[0100] Specifically, if Figure 9 As shown, it is a schematic diagram of the structure for forming a heat dissipation groove inside a substrate; specifically, a photoresist is applied above the first surface 101 of the substrate 100, and a heat dissipation groove 121 is formed on the side of the substrate 100 close to the first surface 101 through etching and other process steps. Specifically, the heat dissipation groove 121 includes a main groove, an inlet groove and an outlet groove. In particular, the depth of the inlet groove and the outlet groove is much deeper than the depth of the main groove. Specifically, the etching step can be divided into two steps. In the first etching, the first mask is used to define the position and shape of the inlet groove and the outlet groove, and a deep groove area is formed after exposure and development; in the second etching, the second mask is used to define the position and shape of the main groove. Generally, the shape of the main groove inside the substrate 100 includes other shapes such as serpentine, mesh, and branched. After development and exposure, a shallow groove area is formed.

[0101] Optionally, a layer of metal copper is sputtered on the surface of the heat dissipation slot 121. The thickness of the deposited copper layer is between 200 nm and 500 nm.

[0102] Specifically, a heat dissipation cover plate 122 is provided. A copper cover plate with a thickness of 50-200 μm and a surface flatness of ≤ 2 μm is prepared by mechanical stamping or photolithography-electroplating process. The heat dissipation cover plate 122 is aligned with the heat dissipation slot 121 and copper-copper thermal compression bonding is performed to form a sealed flow channel.

[0103] Step S5: forming a first interconnection structure on the first surface and a second interconnection structure on the second surface, wherein the first interconnection structure and the second interconnection structure are connected through the through hole.

[0104] like Figure 10 FIG. 1 is a schematic diagram showing forming a first interconnect structure on a first surface; the specific steps include:

[0105] A first dielectric layer 131 is deposited above the first surface 101. Optionally, the material of the first dielectric layer 131 includes silicon nitride, etc., by plasma enhanced chemical vapor deposition. Generally, the thickness of the first dielectric layer 131 is between 3 and 5 μm. The first dielectric layer 131 is etched to form a circuit. The circuit is filled with metal to form a first rewiring layer 132. Specifically, the first rewiring layer 132 exposes the first dielectric layer 131 and is connected to the first conductive pillars 150 in the substrate 100 and the chip stacking structure 110. Bonding bumps 133 are formed above the first rewiring layer 132.

[0106] like Figure 11 , which is a schematic structural diagram of bonding a temporary carrier on the first surface; the specific steps include: providing a temporary carrier 160 , and bonding the temporary carrier 160 to the bonding bumps 133 .

[0107] like Figure 12 As shown, it is a schematic diagram of the structure of thinning the substrate; specifically, Figure 11 The package structure shown is flipped over until the second surface 102 of the substrate 100 faces upward, and the substrate 100 is thinned from the second surface 102 until the second surface 102 of the substrate 100 exposes the inlet 1211 and the outlet 1212 of the heat dissipation slot 121 .

[0108] like Figure 13 As shown, it is a structural schematic diagram of forming a second dielectric layer and an insulating layer on the second surface; specifically, the steps include: forming a second dielectric layer 141 on the second surface 102 of the substrate 100, specifically, the thickness of the second dielectric layer 141 is between 3 and 5 μm; etching the second dielectric layer 141 to form a circuit; using metal to fill the circuit to form a second rewiring layer 142, specifically, the second rewiring layer 142 is electrically connected to the first conductive column 150.

[0109] An insulating layer 170 is formed on a side of the second dielectric layer 141 away from the substrate 100 to protect the second rewiring layer 142 .

[0110] like Figure 14 As shown, it is a schematic diagram showing a second interconnect structure formed on the second surface; Figure 14 As shown, Figure 13 The formed structure is thinned to expose the inlet 1211 and outlet 1212 of the microchannel.

[0111] Remove the temporary slide 160 and obtain Figure 1 The memory package structure shown.

[0112] The memory packaging method provided in this embodiment vertically stacks a logic chip and multiple vertical high-bandwidth memory chips, and pre-buries the stacked chips in a silicon-based material. Compared with soldering on the surface of a TSV adapter board and then plastic-sealing, this method can improve integration and reduce package size. In addition, the chip stacking structure is embedded in the groove through a three-step method, which can effectively reduce the mechanical stress between the chip stacking structure and the substrate. In addition, a microchannel heat dissipation mechanism is provided to use fluid flow to remove heat generated by the chips inside the package, thereby improving the heat dissipation effect.

[0113] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A memory packaging structure, characterized in that: include: A substrate having a first surface and a second surface opposite to each other, wherein a plurality of grooves are formed in the substrate from the first surface to the second surface. A plurality of chip stacking structures are disposed in the groove in a one-to-one correspondence.

2. The memory package structure according to claim 1, wherein: Also includes: a first interconnect structure located on the first surface, the first interconnect structure comprising a first dielectric layer and a first redistribution layer, wherein the first redistribution layer is embedded in the first dielectric layer; a second interconnect structure located on the second surface, the second interconnect structure comprising a second dielectric layer and a second redistribution layer, wherein the second redistribution layer is embedded in the second dielectric layer; The first conductive pillar penetrates the substrate along a thickness direction of the substrate and connects the first interconnection structure and the second interconnection structure.

3. The memory package structure according to claim 1, wherein: The chip stacking structure includes: Logic chips; a plurality of memory chips, wherein the plurality of memory chips are stacked sequentially above and / or below the logic chip; A plurality of second conductive pillars are disposed between the logic chip and the memory chip, and between the memory chips, so as to connect the logic chip and the memory chip.

4. The memory package structure according to claim 3, wherein: It also includes a plurality of heat-conducting columns, and the second conductive columns and the heat-conducting columns are distributed at intervals.

5. The memory package structure according to claim 4, wherein: The second conductive pillars adjacent to the heat-conducting pillar are distributed in a diamond shape; and the heat-conducting pillars adjacent to the second conductive pillar are distributed in a diamond shape.

6. The memory package structure according to claim 4, wherein: The projected area of ​​the second conductive pillar on the substrate surface is smaller than or equal to the projected area of ​​the thermal conductive pillar on the substrate surface.

7. The memory package structure according to claim 1, wherein: A filling layer is filled between the chip stacking structure and the groove.

8. The memory package structure according to claim 1, wherein: An upper surface of the chip stacking structure is flush with the first surface of the substrate.

9. The memory package structure according to claim 1, wherein: It also includes a heat dissipation structure located between two adjacent chip stacking structures.

10. The memory package structure according to claim 9, wherein: The heat dissipation structure includes: a heat dissipation slot, comprising a flow channel, an inlet, and an outlet, wherein the flow channel is located in the substrate, and the inlet and the outlet are exposed from the second surface of the substrate; A heat dissipation cover plate covers the heat dissipation slot.

11. The memory package structure according to claim 9, wherein: The heat dissipation structure includes a microchannel heat dissipation structure.

12. A memory packaging method, characterized in that: The following steps are involved: Fabricating a plurality of chip stack structures, wherein the chip stack structure includes a logic chip and a plurality of vertically stacked memory chips; Providing a substrate, the substrate comprising a first surface and a second surface opposite to each other, with the first surface pointing to the second surface, and a plurality of grooves and a plurality of first through holes formed inside the substrate; Embedding the chip stacking structure into the groove, and filling the first through hole with a conductive medium to form a first conductive column; forming a heat dissipation groove inside the substrate from the first surface to the second surface, and forming a heat dissipation cover plate above the heat dissipation groove; A first interconnect structure is formed on the first surface, and a second interconnect structure is formed on the second surface. The first interconnect structure and the second interconnect structure are connected through the first conductive pillar.

13. The memory packaging method according to claim 12, wherein: Embedding the chip stacking structure into the groove comprises: filling the groove with a filler; placing the chip stacking structure in the groove; Then, the filler is filled into the groove until the entire groove is filled.

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