Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, which can be applied to the technical field of semiconductors. The semiconductor device includes: a channel portion on a substrate; a front gate electrode on a first side of the channel portion; the source / drain electrode is positioned at two opposite ends of the channel part; the back gate electrode is arranged on the second side of the channel part, the back gate electrode and the front gate electrode are opposite to each other, the back gate electrode comprises a gate dielectric layer and a gate conductor layer, and the gate dielectric layer comprises ferroelectric materials.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device in which a ferroelectric material is introduced into a back gate and a manufacturing method thereof. Background Art

[0002] Semiconductor devices based on ferroelectric materials have advantages such as non-volatility, high switching speed, and low power consumption, showing broad application prospects in the semiconductor field. However, current ferroelectric device architectures are still limited in terms of durability and other aspects. Summary of the Invention

[0003] In view of this, the present disclosure provides a semiconductor device in which a ferroelectric material is introduced into a back gate and a method for manufacturing the same.

[0004] One aspect of the present disclosure provides a semiconductor device, comprising: a channel portion on a substrate; a front gate electrode on a first side of the channel portion; a source / drain located at opposite ends of the channel portion; and a back gate electrode on a second side of the channel portion, wherein the back gate electrode and the front gate electrode are opposite to each other, the back gate electrode comprises a gate dielectric layer and a gate conductor layer, and the gate dielectric layer comprises a ferroelectric material.

[0005] According to an embodiment of the present disclosure, the operating voltage of the back gate electrode is a first voltage, the operating voltage of the front gate electrode is a second voltage, and the first voltage is greater than the second voltage.

[0006] According to an embodiment of the present disclosure, the ferroelectric material includes hafnium dioxide doped with a target element, and the target element includes at least one of silicon, aluminum, zirconium, yttrium, gadolinium, lanthanum, and strontium.

[0007] According to an embodiment of the present disclosure, the ferroelectric material forms a layer with a thickness of 5 to 15 nm.

[0008] According to an embodiment of the present disclosure, the front gate electrode is configured for a read operation of a semiconductor device, and the back gate electrode is configured for a program and erase operation of the semiconductor device.

[0009] According to an embodiment of the present disclosure, the substrate is a semiconductor-on-insulator (SOI) substrate including a buried oxide layer and an SOI layer on the buried oxide layer. The front gate electrode is formed on the SOI layer, and the back gate electrode is formed on the side of the buried oxide layer opposite to the SOI layer.

[0010] According to an embodiment of the present disclosure, the gate dielectric layer of the front gate electrode does not include ferroelectric material.

[0011] According to an embodiment of the present disclosure, the front gate electrode further includes a gate oxide layer, and the thickness of the gate oxide layer is 0.8-0.95 nm.

[0012] Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, including: defining an active area on a substrate; forming a front gate electrode on a first side of the active area; forming a source / drain at opposite ends of a channel portion on the active area; and forming a back gate electrode on a second side of the active area, wherein the back gate electrode and the front gate electrode are opposite to each other, and the back gate electrode includes a gate dielectric layer and a gate conductor layer, and the gate dielectric layer includes a ferroelectric material.

[0013] According to an embodiment of the present disclosure, the substrate is a semiconductor-on-insulator (SOI) substrate, comprising a base substrate, a buried oxide layer on the base substrate, and an SOI layer on the buried oxide layer, wherein a front gate electrode is formed on the SOI layer, and a back gate electrode is formed on a side of the buried oxide layer opposite to the SOI layer.

[0014] According to an embodiment of the present disclosure, forming a back gate electrode includes: thinning the base substrate; using the thinned base substrate to form a sacrificial gate, the sacrificial gate and the front gate electrode facing each other; forming a sidewall on the sidewall of the sacrificial gate; and replacing the sacrificial gate with the back gate electrode.

[0015] According to the embodiments of the present disclosure, the separation of the front gate electrode and the back gate electrode enables separate operation of different bias ranges, especially the separation between high-voltage programming / erase operations and low-voltage reading, thereby reducing the damage to the front gate electrode caused by cyclic high bias. In addition, the back gate electrode no longer needs to follow the miniaturization of the top device size, thereby ensuring the logic performance of the semiconductor device and the storage performance of the ferroelectric semiconductor device. In the implementation of the SOI substrate, the thicker buried oxide layer is conducive to reducing the trap-assisted tunneling of the charge during the cyclic high bias process of the semiconductor device, thereby reducing polarization pinning and further improving the storage performance of the ferroelectric semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0017] Figure 1 Schematically shows a structural diagram of a semiconductor device according to an embodiment of the present disclosure;

[0018] Figures 2 to 15 Some stages in a process of manufacturing a semiconductor device according to an embodiment of the present disclosure are schematically shown. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0020] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0021] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or an intervening layer / element may be present therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed.

[0022] The endurance of ferroelectric devices is primarily limited by severe polarization pinning caused by interfacial charge injection. During programming and erasing, high voltages are typically required to change the polarization state of the ferroelectric material. This high voltage injection can lead to charge injection into the interface between the ferroelectric material and the gate oxide layer, causing the accumulation of interfacial defects and ultimately degrading device functionality.

[0023] Furthermore, high-voltage operation is particularly damaging to the gate oxide layer of ferroelectric devices. In ferroelectric devices, the integrity of the gate oxide layer directly determines device performance and reliability. However, sustained high-voltage stress can trigger localized breakdown or degradation of the gate oxide layer, further exacerbating the interfacial charge injection effect. This cyclical effect ultimately causes the device to lose normal operation after repeated programming and erasing. Therefore, mitigating interfacial charge injection and reducing gate oxide damage during high-voltage operation has become a key research topic in ferroelectric devices.

[0024] Figure 1 The schematic diagram shows the structure of a semiconductor device according to an embodiment of the present disclosure.

[0025] like Figure 1As shown, the semiconductor device 100 includes a channel portion 120 on a substrate 110, a first side of the channel portion (eg, Figure 1 the front gate electrode G1 on the lower side of the channel portion), the source 130 and the drain 140 at opposite ends of the channel portion, and the second side of the channel portion (eg, Figure 1 A back gate electrode G2 is formed on the upper side of the substrate (in the upper portion). The back gate electrode G2 is opposite to the front gate electrode G1. The back gate electrode G2 includes a gate dielectric layer and a gate conductor layer. The gate dielectric layer includes a ferroelectric material. The ferroelectric material may include hafnium dioxide (HfO2) doped with a target element. The target element includes at least one of silicon (Si), aluminum (Al), zirconium (Zr), yttrium (Y), gadolinium (Gd), lanthanum (La), and strontium (Sr). The target element may also be other materials, and the present disclosure is not limited thereto. The ferroelectric material may form a layer with a thickness of 5 to 15 nm.

[0026] The buried oxide layer serves as a high-quality interface layer between the ferroelectric material and the channel portion. Its thickness can be determined according to the buried oxide layer (BOX) thickness of the SOI substrate, generally ranging from 20 to 145 nm. It can improve the reliability and durability of the device.

[0027] The semiconductor device 100 has a back-gate configuration, which can be relatively easily formed based on a semiconductor-on-insulator (SOI) substrate. According to an embodiment of the present disclosure, the substrate 110 can be an SOI substrate, including a buried oxide layer (BOX), an SOI layer on the BOX layer, and a base substrate under the BOX layer. The active region can be defined in the SOI substrate or on the SOI layer by, for example, local oxidation of silicon (LOCOS). Figure 1 One of the active regions is schematically shown. The front gate electrode G1 is formed on the SOI layer. The base substrate is removed during the formation process. Therefore, the back gate electrode G2 is formed on the side of the buried oxide layer opposite the SOI layer. The buried oxide layer can serve as the gate oxide layer for the back gate electrode G2.

[0028] According to an embodiment of the present disclosure, the front gate electrode G1 is configured for a read operation of the semiconductor device, and the back gate electrode G2 is configured for a program and erase operation of the semiconductor device.

[0029] According to an embodiment of the present disclosure, the operating voltage of the back gate electrode G2 is a first voltage, and the operating voltage of the front gate electrode G1 is a second voltage, where the first voltage is greater than the second voltage. During programming and erasing operations of a semiconductor device, a higher voltage is required to change the polarization state of the ferroelectric material, while a lower voltage is required during a read operation of the semiconductor device. Therefore, the first voltage can be greater than the second voltage.

[0030] Unlike ferroelectric devices in related art, the semiconductor device according to the present disclosure incorporates a ferroelectric material into the back-gate electrode G2. The front-gate electrode G1, serving as the control gate electrode, may not incorporate a ferroelectric material. That is, the gate dielectric layer of the front-gate electrode G1 may not include a ferroelectric material. The front-gate electrode G1 also includes a gate oxide layer. Because high-voltage operation is not required, the gate oxide layer can be relatively thin, for example, 0.8 to 0.95 nm.

[0031] According to the embodiments of the present disclosure, the separation of the front gate electrode and the back gate electrode enables different bias ranges to be operated separately, especially the separation between high-voltage programming / erase operations and low-voltage reading, which reduces the damage to the gate oxide layer of the front gate electrode caused by cyclic high bias. In addition, the back gate electrode no longer needs to follow the miniaturization of the top device size, thereby ensuring the logic performance of the semiconductor device and the storage performance of the ferroelectric semiconductor device. In the implementation of the SOI substrate, the thicker buried oxide layer (BOX) is conducive to reducing the trap-assisted tunneling of the charge during the cyclic high bias process of the semiconductor device, thereby reducing polarization pinning and further improving the storage performance of the ferroelectric semiconductor device.

[0032] According to an embodiment of the present disclosure, the present disclosure also provides a method for manufacturing a semiconductor device, including: defining an active area on a substrate; forming a front gate electrode on a first side of the active area; forming a source / drain at opposite ends of a channel portion on the active area; and forming a back gate electrode on a second side of the active area, wherein the back gate electrode and the front gate electrode are opposite to each other, and the back gate electrode includes a gate dielectric layer and a gate conductor layer, and the gate dielectric layer includes a ferroelectric material.

[0033] The substrate is a semiconductor-on-insulator (SOI) substrate, comprising a base substrate, a buried oxide layer on the base substrate, and an SOI layer on the buried oxide layer, wherein a front gate electrode is formed on the SOI layer, and a back gate electrode is formed on the side of the buried oxide layer opposite to the SOI layer.

[0034] The back gate electrode is formed by thinning the base substrate; forming a sacrificial gate using the thinned base substrate, the sacrificial gate and the front gate electrode facing each other; forming a sidewall on the sidewall of the sacrificial gate; and replacing the sacrificial gate with the back gate electrode.

[0035] The present disclosure may be presented in various forms, some of which are described below. In the following description, reference is made to the selection of various materials. In addition to considering their function (for example, semiconductor materials are used to form active areas and dielectric materials are used to form electrical isolation), the selection of materials also takes into account etching selectivity. In the following description, the required etching selectivity may or may not be indicated. It should be clear to those skilled in the art that when the following mentions etching a certain material layer, if it is not mentioned that other layers are also etched or it is not shown in the figure that other layers are also etched, then such etching can be selective, and the material layer can have etching selectivity relative to other layers exposed to the same etching recipe.

[0036] Figures 2 to 15 Some stages in a process of manufacturing a semiconductor device according to an embodiment of the present disclosure are schematically shown.

[0037] like Figure 2 As shown, an SOI substrate 110 is provided. The SOI substrate 110 may include a base substrate 111, a buried oxide layer 112 on the base substrate, and an SOI layer 113 on the buried oxide layer 112. For example, the thickness of the SOI layer 113 may be approximately 10-55 nm, and the thickness of the buried oxide layer 112 may be approximately 20-145 nm. The SOI layer 113 may be thinned to a thickness of approximately 5-15 nm, for example, approximately 1 / 3 of the minimum channel length of the semiconductor device, to achieve full depletion.

[0038] like Figure 3 As shown, the active area A1 can be defined in the SOI layer 113 by, for example, LOCOS technology. For example, a SiO2 / SiN stack can be used as a hard mask to protect the active area A1, and furnace oxidation can be used to fully oxidize the non-active area portion of the SOI layer 113 not covered by the hard mask to serve as isolation between devices.

[0039] like Figure 4As shown, a first sacrificial gate 410 can be formed on the SOI substrate 110, particularly the active area defined therein. For example, a gate oxide layer 420, a first sacrificial layer 430, and a first hard mask layer 440 can be sequentially formed on the SOI substrate 110 by deposition, for example. For example, the gate oxide layer 420 can include SiO2 with a thickness of approximately 2.5 nm and formed by an in-situ steam generation (ISSG) process. The first sacrificial layer 430 can include amorphous silicon and have a thickness of approximately 100 nm. The first hard mask layer 440 can sequentially include a first hard mask oxide layer 441, a first hard mask nitride layer 442, and a first hard mask oxide layer 443. The first hard mask oxide layer 441 can include SiO2 with a thickness of approximately 10-30 nm, the first hard mask nitride layer 442 can include SiN with a thickness of approximately 20-40 nm, and the first hard mask oxide layer 443 can include SiO2 with a thickness of approximately 80-100 nm. The gate oxide layer 420, the first sacrificial layer 430, and the first hard mask layer 440 may be etched to expose the SOI layer and form a first sacrificial gate 410. The first sacrificial gate 410 may have a first direction ( Figure 4 A second direction ( Figure 4 A strip extending perpendicular to the paper.

[0040] The source / drain regions can be self-aligned and defined in the active area based on the sacrificial gate.

[0041] For example, Figure 5 As shown, a first sidewall spacer 510, for example, a nitride (for example, SiN), can be formed on the sidewall of the first sacrificial gate 410 by a sidewall spacer formation process. In the sidewall spacer formation process, a nitride with a thickness of about 20 to 40 nm can be deposited in a substantially conformal manner, and the deposited nitride is anisotropically etched. Using the first sidewall spacer 510 and the first sacrificial gate 410 as a mask, a first implantation is performed into the active area. The first implantation can be an LDD implantation to form an impurity region with a shallow depth and a low doping concentration, for example, used as a source / drain extension region. The dopant can be n-type. The n-type dopant can include phosphorus (P), with an implantation energy of 10 to 20 KeV and a dose of 1 to 5E15 cm -2 ; or it can also include arsenic (As), with an implantation energy of 5~10KeV and a dose of 1~5E15cm -2 Alternatively, the dopant may be p-type. The p-type dopant may include boron (B) with an implantation energy of 1 to 5 KeV and a dose of 5 to 8E15 cm -2 .

[0042] like Figure 6As shown, a second sidewall spacer 620, such as a nitride, can be further formed on the outside of the first sidewall spacer 510 through a sidewall spacer formation process. In addition, an intermediate layer 610, such as an oxide, can be interposed between the first sidewall spacer 510 and the second sidewall spacer 620. The intermediate layer 610 can be used as an etch stop layer during the etching process of forming the second sidewall spacer 620. In the sidewall spacer formation process, SiO2 with a thickness of about 10 to 20 nm and SiN with a thickness of about 20 to 40 nm can be deposited in sequence in a substantially conformal manner and anisotropically etched. Using the first sidewall spacer 620 together with the previously formed first sidewall spacer 510 and the first sacrificial gate 410 as a mask, a second implantation is performed into the active area. The second implantation can be an HDD implantation to form an impurity region with a greater depth and a higher doping concentration, for example, used as a source / drain region. The dopant can be n-type, for example, with an implantation energy of 10 to 20 KeV and a dose of 5 to 8E15 cm -2 The P or implant energy is 5~10KeV and the dose is 5~8E15cm -2 Alternatively, the dopant can be p-type, for example, with an implantation energy of 1-5 KeV and a dose of 5-8E15 cm -2 B.

[0043] Next, a replacement gate process may be performed to replace the sacrificial gates with gate electrodes, respectively.

[0044] For example, Figure 7 and Figure 8 As shown, a filling layer 710 is formed on the SOI substrate 110 and planarized, such as by chemical mechanical polishing (CMP), to expose the first sacrificial layer 430 in the first sacrificial gate 410. The filling layer 710 may comprise SiN and may have a thickness of 400-600 nm. The gate oxide layer 420 and the first sacrificial layer 430 may be removed by selective wet etching.

[0045] like Figure 9 As shown, a front gate electrode G1 is formed in the space freed by the removal of the first sacrificial gate 410. For example, an interface oxide layer 910 with a thickness of approximately 0.8 to 0.95 nm can be formed by ozone oxidation. A gate dielectric layer 920, a work function layer 930, and a gate conductor layer 940 can be sequentially formed on the interface oxide layer 910 by deposition. For example, the gate dielectric layer 920 can include hafnium dioxide (HfO2) with a thickness of approximately 2 to 4 nm. The work function layer 930 can include TiN with a thickness of approximately 2 to 5 nm. The gate conductor layer 940 can include tungsten (W) with a thickness of approximately 75 to 100 nm.

[0046] In this example, a gate-last process is used. However, the present disclosure is not limited thereto. For example, the gate-first process may also be used to form the gate-front electrode G1.

[0047] Additionally, interconnect components may be formed. For example, Figure 10 As shown, an interlayer dielectric layer 1010 may be formed on the front gate electrode G1, and contacts 1020 and 1030 may be formed therein. The figure schematically shows only the contacts 1020 and 1030 on the source and drain electrodes. Other contacts and interconnects may also be formed.

[0048] In the above, an active region is defined on the first side of the substrate, and a front gate electrode G1 is formed on the active region. Next, a back gate electrode may be formed on a second side of the substrate opposite to the first side.

[0049] For example, Figure 11 As shown, the substrate is turned upside down and the base substrate 111 is thinned to, for example, about 10-50 nm. The remaining portion of the base substrate 111 can be used as a sacrificial gate material for the back gate.

[0050] The sacrificial gate can be defined similarly to the front gate electrode. Figure 12 As shown, a second sacrificial gate 1210 is formed on the thinned base substrate 111. For example, a second hard mask layer 1220 can be formed on the thinned base substrate 111 by deposition. The second hard mask layer 1220 can sequentially include a second hard mask oxide layer 1221, a second hard mask nitride layer 1222, and a second hard mask oxide layer 1223. The second hard mask oxide layer 1221 can include SiO2 with a thickness of approximately 10 to 30 nm, the second hard mask nitride layer 1222 can include SiN with a thickness of approximately 20 to 40 nm, and the second hard mask oxide layer 1223 can include SiO2 with a thickness of approximately 80 to 100 nm. The second hard mask layer 1220 can be etched to expose the buried oxide layer (BOX) 112, forming the second sacrificial gate 1210.

[0051] The second sacrificial gate 1210 may be formed to be opposite to the front gate electrode G1. Figure 12 In the horizontal direction within the paper), the width of the second sacrificial gate 1210 may be greater than the width of the front gate electrode G1 so as to completely cover the channel region defined in the active region due to the front gate electrode G1.

[0052] like Figure 13 and Figure 14 As shown, a spacer 1310 made of, for example, nitride (eg, SiN) can be formed on the sidewalls of the second sacrificial gate 1210 through a spacer formation process. The spacer 1310 can help better define the back gate space.

[0053] Next, a replacement gate process may be similarly performed. For example, a back gate isolation layer 1410 may be formed on the buried oxide layer 112. A planarization process such as CMP may be performed to expose the sacrificial layer (the remaining portion of the base substrate) in the sacrificial gate 1210, and the sacrificial gate 1210 may be removed by selective wet etching.

[0054] like Figure 15 As shown, a back-gate electrode G2 is formed in the space freed by the removal of the sacrificial gate 1210. For example, a gate dielectric layer 1510, a work function layer 1520, and a gate conductor layer 1530 can be sequentially formed by deposition. For example, the gate dielectric layer 1510 can include a high-k gate dielectric, such as hafnium dioxide (HfO2), with a thickness of approximately 2-4 nm. The work function layer 1520 can include TiN with a thickness of approximately 3-5 nm. The gate conductor layer 1530 can include tungsten (W) with a thickness of approximately 75-100 nm.

[0055] Return Reference Figure 1 Another back gate isolation layer, such as an oxide, may be further formed on the back gate isolation layer 1410. In addition, a contact portion to the back gate electrode G2 may be formed in the other back gate isolation layer.

[0056] It should be noted that the size parameters provided in this disclosure are for reference only, and those skilled in the art can set other size parameters according to actual needs.

[0057] Semiconductor devices according to embodiments of the present disclosure can be applied to various electronic devices. For example, integrated circuits (ICs) can be formed based on such semiconductor devices, and electronic devices can be constructed from them. Such electronic devices may also include components such as display screens and wireless transceivers that work with the ICs. Examples of such electronic devices include smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, and mobile power supplies.

[0058] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0059] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A semiconductor device comprising: a channel portion on a substrate; a front gate electrode on a first side of the channel portion; source / drain electrodes located at opposite ends of the channel portion; as well as A back gate electrode is provided on the second side of the channel portion, wherein the back gate electrode and the front gate electrode are opposite to each other, the back gate electrode comprises a gate dielectric layer and a gate conductor layer, and the gate dielectric layer comprises a ferroelectric material.

2. The semiconductor device according to claim 1, wherein The operating voltage of the back gate electrode is a first voltage, the operating voltage of the front gate electrode is a second voltage, and the first voltage is greater than the second voltage.

3. The semiconductor device according to claim 1, wherein The ferroelectric material includes hafnium dioxide doped with a target element, wherein the target element includes at least one of silicon, aluminum, zirconium, yttrium, gadolinium, lanthanum, and strontium.

4. The semiconductor device according to claim 3, wherein The ferroelectric material is formed to have a thickness of 5 to 15 nm. The semiconductor device according to claim 1 , wherein The front gate electrode is configured for a read operation of the semiconductor device, and the back gate electrode is configured for a program and erase operation of the semiconductor device. The semiconductor device according to claim 1 , wherein: The substrate is a semiconductor-on-insulator (SOI) substrate, comprising a buried oxide layer and an SOI layer on the buried oxide layer. The front gate electrode is formed on the SOI layer, The back gate electrode is formed on a side of the buried oxide layer opposite to the SOI layer.

7. The semiconductor device according to any one of claims 1 to 6, wherein The gate dielectric layer of the front gate electrode does not include ferroelectric material.

8. The semiconductor device according to claim 7, wherein The front gate electrode further includes a gate oxide layer, and the thickness of the gate oxide layer is 0.8-0.95 nm.

9. A method for manufacturing a semiconductor device, comprising: defining an active region on the substrate; forming a front gate electrode on a first side of the active region; forming source / drain electrodes at opposite ends of the channel portion on the active region; as well as A back gate electrode is formed on the second side of the active region, wherein the back gate electrode and the front gate electrode are opposite to each other, the back gate electrode comprises a gate dielectric layer and a gate conductor layer, and the gate dielectric layer comprises a ferroelectric material.

10. The method according to claim 9, wherein: The substrate is a semiconductor-on-insulator (SOI) substrate, comprising a base substrate, a buried oxide layer on the base substrate, and an SOI layer on the buried oxide layer. The front gate electrode is formed on the SOI layer, and the back gate electrode is formed on a side of the buried oxide layer opposite to the SOI layer.

11. The method according to claim 10, wherein: Forming the back gate electrode includes: thinning the base substrate; forming a sacrificial gate by using the thinned base substrate, wherein the sacrificial gate and the front gate electrode are opposite to each other; forming sidewall spacers on sidewalls of the sacrificial gate; and The sacrificial gate is replaced by the back gate electrode.

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