Semiconductor electronic device with edge termination region and process for manufacturing same

Abstract

The invention relates to a semiconductor electronic device device with an edge termination region and a process for manufacturing the same. A semiconductor electronic device has a semiconductor body having a first conductivity type, a front surface, and a rear surface at a distance from the front surface in a first direction. The semiconductor body also has a lateral edge. The device has an active region that in use accommodates a conductive channel of the device; and an edge termination region surrounding the active region between the active region and a lateral edge of the semiconductor body in a second direction transverse to the first direction. The edge termination region has a plurality of doped portions of a second conductivity type different from the first conductivity type, and the doped portions are arranged in the semiconductor body at a distance from each other in the first direction or in the first direction and in the second direction.

Description

[0001] Priority application

[0002] This application claims the benefit of Italian Patent Application No. 102024000004948, filed on March 6, 2024, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present invention relates to a semiconductor electronic device, and in particular to a vertical conductive device with an edge termination region, and a manufacturing process of the vertical conductive device. Background Art

[0004] It is well known that semiconductor electronic devices (eg, MOSFET transistors) used in power applications need to withstand high voltages, eg, even higher than 400V.

[0005] In power applications, high breakdown voltage and low on-resistance are parameters required to improve the electrical performance of electronic devices.

[0006] Figure 1 A silicon-based MOSFET device 1 for power applications is shown in a Cartesian reference frame XYZ.

[0007] The MOSFET device 1 is a vertical conduction device and has a superjunction structure (based on the charge compensation principle), which allows the MOSFET device 1 to overcome the classic limitations of silicon, namely, to achieve a good compromise between high breakdown voltage and low on-resistance.

[0008] A MOSFET device 1 is formed in a die comprising an active area 2 and an edge region 3 .

[0009] The MOSFET device 1 comprises a semiconductor body 4 made of silicon, having a front surface 4A and a back surface 4B, and having an N-type doping. The semiconductor body 4 comprises a substrate 6 and an epitaxial region 8 grown on the substrate 6 .

[0010] Figure 1 Only a portion of the active region 2 is shown, which is configured to accommodate the conducting channel of the MOSFET device 1 in use.

[0011] The edge region 3 extends around the active region 2 in a peripheral portion of the die between the active region 2 and an outer edge 10 of the semiconductor body 4 .

[0012] The MOSFET device 1 comprises, in the active area 2 , a plurality of surface body regions 11 having a P-type doping, which extend from the front surface 4A along the Z-axis inside the epitaxial region 8 .

[0013] The surface body regions 11 extend at a distance from one another along the X axis.

[0014] Source regions 12 with N-type doping each extend inside a respective surface body region 11 .

[0015] Deep body regions 13 with P-type doping extend deep into the epitaxial region 8 along the Z axis, each starting from a corresponding surface body region 11. The presence of the deep body regions 13 defines a superjunction structure of the MOSFET device 1.

[0016] The insulating region 15 extends onto the front surface 4A of the semiconductor body 4 , and the gate insulating region 16 is arranged inside the insulating region 15 , above the front surface 4A.

[0017] Each gate insulating region 16 is arranged between two adjacent surface body regions 11 and partially covers the surface body regions 11 .

[0018] The conductive region 18 extends into the opening of the insulating region 15 and contacts the source region 12 .

[0019] Edge region 3 includes an edge termination region 20 with P-type doping, which extends at the surface in epitaxial region 8, starts from front surface 4A, and has an annular shape surrounding active region 2. Edge termination region 20 extends continuously along the X-axis from active region 2 to outer edge 10. The width of edge termination region 20 along the X-axis is between 50 μm and 200 μm.

[0020] The MOSFET device 1 further comprises an N-type doped equipotential ring 21 extending at the surface of the epitaxial region 8 at the outer edge 10 of the semiconductor body 4 and a conductive region 22 extending onto the front surface 4A in contact with the equipotential ring 21 .

[0021] The superjunction structure allows obtaining a high breakdown voltage of the MOSFET device 1 , for example, up to 1000 V and above. The presence of the ring region 20 helps to increase the breakdown voltage of the MOSFET device 1 .

[0022] However, the presence of the annular region 20 requires additional manufacturing steps (lithography, implantation and diffusion) relative to the manufacturing steps that result in the formation of the surface 11 and deep 13 body regions. Consequently, the MOSFET device 1 has high manufacturing costs.

[0023] Figure 2 Another example of a MOSFET device 50 is shown, which is also a vertical conduction and superjunction device. Figure 1 The MOSFET device 1 has the same structure as the MOSFET device 1; therefore, common elements are indicated by the same reference numerals.

[0024] In the MOSFET device 50 , the edge region 3 further comprises a further edge termination region forming a plurality of pillars 51 having a P-type doping, which extend in depth from the front surface 4A into the semiconductor body 4 .

[0025] The pillar 51 extends continuously along the Z axis, from the front surface 4A through the annular region 20 and the extension region 8 .

[0026] However, MOSFET device 50 also has high manufacturing costs.

[0027] There is a need in the art to provide a power MOSFET that overcomes the above-mentioned disadvantages. Summary of the Invention

[0028] In one embodiment, a semiconductor electronic device includes: a semiconductor body having a first conductivity type, a front surface, and a rear surface extending a distance from the front surface along a first direction, the semiconductor body further having a lateral edge; an active region configured to accommodate a conductive channel of the semiconductor electronic device in use; and an edge termination region extending around the active region between the active region and the lateral edge of the semiconductor body along a second direction transverse to the first direction. The edge termination region includes a plurality of doped portions having a second conductivity type different from the first conductivity type and arranged in the semiconductor body at a distance from one another along the first direction or along the first direction and along the second direction.

[0029] In one embodiment, a process for manufacturing a semiconductor electronic device includes providing a wafer of semiconductor material having a first conductivity type, a front surface, and a back surface spaced a distance from the front surface along a first direction, the wafer further having a lateral edge; forming an active area configured to accommodate a conductive channel of the semiconductor electronic device in use; and an edge termination region extending around the active area between the active area and the lateral edge of the wafer along a second direction transverse to the first direction. Forming the edge termination region includes forming a plurality of doped portions in the semiconductor body, the plurality of doped portions having a second conductivity type different from the first conductivity type and spaced a distance from one another along the first direction or along both the first direction and the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] For a better understanding of the present invention, embodiments of the invention will now be described, purely by way of non-limiting example, with reference to the accompanying drawings, in which:

[0031] Figure 1 shows a cross section of a MOSFET device;

[0032] Figure 2shows a cross section of an additional MOSFET device;

[0033] Figure 3 shows a top view of a semiconductor electronic device according to one embodiment;

[0034] Figure 4 Shown Figure 3 The device along Figure 3 The cross section along section line IV-IV;

[0035] Figures 5A-5G Shows the subsequent manufacturing steps Figure 4 devices;

[0036] Figure 6 and Figure 7 shows a cross section of a semiconductor electronic device according to other embodiments; and

[0037] Figure 8 and Figure 9 A top view of a semiconductor electronic device according to a further embodiment is shown. DETAILED DESCRIPTION

[0038] Figure 3 and Figure 4 A semiconductor electronic component, hereinafter referred to simply as component 100 , is shown in a Cartesian reference system XYZ having mutually orthogonal axes X, Y, Z.

[0039] The device 100 is a silicon-based semiconductor device; however, the device 100 may be a semiconductor device based on a different material, such as silicon carbide or other simple or compound semiconductor materials.

[0040] The device 100 is formed as a die 101 , which may be obtained after a dicing step of a semiconductor wafer.

[0041] The die 101 includes an edge 102 that physically defines the die 101. In practice, the edge 102 is a lateral edge that laterally defines the die 101.

[0042] The device 100 includes an active region 103 and an edge region 104 extending around the active region 103 .

[0043] In particular, the edge region 104 extends structurally continuously with the active region 103 .

[0044] Typically, the active region 103 may extend to a central portion of the die 101 , as well as to edge regions of a peripheral portion of the die 101 .

[0045] In practice, edge region 104 extends between active area 103 and edge 102 of die 101 and is externally bounded by edge 102 .

[0046] Active region 103 is configured to accommodate a conductive channel of device 100 in use.

[0047] The edge region 104 may include functional elements for reducing or preventing electric field line crowding outside the active region 103, which will be referred to below. Figure 4 For better description and explanation, in practice, the edge region 104 is configured not to accommodate the conductive channel of the device 100 in use.

[0048] like Figure 4 As shown in the cross-section of FIG. 1 , the device 100 may be a MOSFET device, particularly a vertical conduction MOSFET device, and even more particularly a super junction MOSFET device.

[0049] The device 100 may be an electronic device for power applications, in particular for high voltages, eg, above 400V.

[0050] Figure 4 Only a portion of the active region 103 is shown, in particular a portion of the active region 103 close to the edge region 104. The dash-dotted line separating the active region 103 from the edge region 104 is to be understood as qualitative.

[0051] The device 100 comprises a semiconductor body 110 , in particular a semiconductor body 110 of silicon or silicon carbide or other semiconductor material, with N-type doping, and having a front surface 110A and a back surface 110B at a distance from each other along the Z-axis.

[0052] The front surface 110A forms a front side of the semiconductor body 110 and delimits it upwards. The back surface 110B forms a back side of the semiconductor body 110 and delimits it downwards.

[0053] In practice, the front surface 110A and the rear surface 110B are opposite to each other along the Z-axis.

[0054] The semiconductor body 110 also has lateral edges that extend at a distance from the active region 103 along the X and Y axes. In practice, the lateral edges may physically delimit the semiconductor body 110, for example, in a plane transverse to the front surface 110A and the back surface 110B. The lateral edges of the semiconductor body 110 may coincide with the edges 102 of the die 101 and are therefore indicated below with the same reference numerals.

[0055] In the embodiment shown, the semiconductor body 110 includes a substrate 111 and a structure region 112 extending onto the substrate 111. For example, the structure region 112 may be epitaxially grown on the substrate 111;

[0056] The epitaxial region 112 forms a drift region of the device 100 in the active area 103 .

[0057] The substrate 111 and the epitaxial region 112 may be made of the same semiconductor material and have the same conductivity type (here, N-type).

[0058] The substrate 111 may have a higher doping level than the epitaxial region 112 .

[0059] The device 100 includes, in the active area 103 , a surface body region 115 having a P-type doping; a deep body region 116 having a P-type doping; a source region 117 having an N-type doping; and a gate region 118 .

[0060] For simplicity, in Figure 4 , only two surface body regions 115 , two deep body regions 116 , two source regions 117 and two gate regions 118 are shown. However, it is clear that the device 100 may include additional surface body regions 115 , deep body regions 116 , source regions 117 and gate regions 118 in the active area 103 .

[0061] The surface body regions 115 extend from the front surface 110A into the semiconductor body 110 , in particular into the epitaxial region 112 , at a distance from one another along the X-axis.

[0062] The source regions 117 extend at least partially within the corresponding surface body region 115 .

[0063] The deep body regions 116 extend along the Z-axis deep into the semiconductor body 110 , in particular into the epitaxial region 112 , each starting from a respective surface body region 115 .

[0064] The deep body region 116 extends a distance from the front surface 110A and is in direct contact with the surface body region 115 .

[0065] In practice, the deep body region 116 extends into the semiconductor body 110 to a depth (measured from the front surface 110A along the Z-axis) greater than the depth (measured from the front surface 110A along the Z-axis) of the surface body region 115 .

[0066] The width of the deep body region 116 (along Figure 4 The X-axis in the cross section of the surface body region 115 may be smaller than the width (along the X-axis in the cross section of the surface body region 115) Figure 4 X-axis in the cross section).

[0067] The gate region 118 includes a gate insulating portion 119 and a gate conductive portion 120 , and extends onto the front surface 110A partially covering the surface body region 115 along the Z-axis.

[0068] A drain region of conductive material, not shown here, extends at the back surface 110B, forming a drain terminal D of the device 100 .

[0069] In practice, in use, the surface body region 115 is configured to accommodate a conductive channel of the device 100, thereby forming a conductive path extending through the semiconductor body 110 along the Z-axis between the front surface 110A and the back surface 110B. Figure 4 The dashed arrows are shown in an exemplary and schematic manner.

[0070] The insulating region 123 extends onto the front surface 110A of the semiconductor body 110 , for example both in the active area 103 and in the edge region 104 .

[0071] The conductive region 124 extends onto the semiconductor body 110, making electrical contact with the source region 117. In practice, the conductive region 124 is a source contact region and forms the source terminal S of the device 100. For example, the conductive region 124 may extend through an opening in the insulating region 123, through the thickness of the insulating region 123, and to the front surface 110A.

[0072] The electrically conductive region 124 may be used, for example, in different sections of the device 100 not shown here, also to contact the surface body region 115 in order to obtain a body-source short circuit.

[0073] The device 100 includes an edge termination region 130 in the edge region 104 , which extends within the semiconductor body 110 around the active area 103 .

[0074] The edge termination region 130 comprises a plurality of recesses 132 with a P-type doping, which extend into the semiconductor body 110 , in particular into the epitaxial region 112 .

[0075] The edge termination region 130 may have a width W t , which is the width along the direction extending between the active area and the lateral edge 102 ( Figure 4 The width W is measured along the X-axis in the cross section of the embodiment of the present invention, for example, between 50 μm and 200 μm. t Larger values ​​of may be useful for device 100 capable of operating at high voltages.

[0076] In fact, the width W t It may be defined as the width, eg the maximum width, entirely occupied by the cavity 132 inside the semiconductor body 110 between the active area 103 and the lateral edge 102 .

[0077] To maximize the breakdown voltage, the cavity 132 may have a value of, for example, 5×10 15at / cm 3 With 5×10 17 at / cm 3 doping levels between .

[0078] The recesses 132 extend at a distance from each other along the Z axis. For example, the distance W between two adjacent recesses 132 along the Z axis is v It can be between 3 μm and 8 μm.

[0079] The recesses 132 also extend at a distance from each other along the X-axis. For example, the distance W between two adjacent recesses 132 along the X-axis is h It can be between 2 μm and 6 μm.

[0080] The pockets 132 may each have a width W along the X-axis. p , for example, between 1 μm and 10 μm.

[0081] In this embodiment, the cavities 132 are distributed in the semiconductor body 110 such that the edge termination region 130 has a width W of t The interior has, at least to a first approximation (i.e., except for process variability), a uniform P-type cavity density (number of cavities per unit area or unit volume). In fact, at least to a first approximation (i.e., except for process variability), the cavities 132 are all spaced at the same mutual distance W along the X-axis. h and along the Z axis at the same mutual distance W v are arranged and, at least as a first approximation, have the same width W p .

[0082] In detail, the plurality of cavities 132 include surface cavities 132A extending into the semiconductor body 110 at the front surface 110A, and deep (or buried) cavities 132B extending into the semiconductor body 110 at a distance from the front surface 110A.

[0083] The surface recess 132A extends from the front surface 110A toward the interior of the semiconductor body 110 , in particular toward the interior of the epitaxial region 112 .

[0084] The surface dimples 132A extend at a distance from one another along the X-axis. In particular, at least as a first approximation (ie, aside from process variability), the surface dimples 132A all extend at the same distance from one another along the X-axis.

[0085] The deep cavity 132B extends into the semiconductor body 110 , in particular into the epitaxial region 112 , at a distance from the front surface 110A of the semiconductor body 110 .

[0086] The deep recesses 132B extend at a distance from each other along the X-axis and along the Z-axis.

[0087] In this embodiment, the deep pockets 132B are arranged in groups extending along the Z-axis, with each group underlying a corresponding surface pocket 132A.

[0088] In particular, Figure 4 In the example shown, four deep recesses 132B are arranged below each surface recess 132A.

[0089] In detail, Figure 4 In the embodiment of FIG. 1 , the deep recesses 132B are aligned with each other along the Z axis and are also aligned with the corresponding surface recesses 132A along the Z axis. However, the recesses 132 may face each other along the Z axis in whole or in part.

[0090] The deep recesses 132B are evenly distributed, especially with the same mutual distance W along the X axis. h and have the same mutual distance W along the Z axis v The fact that the device 100 is designed and manufactured can ensure that the design and manufacture of the device 100 are simpler.

[0091] like Figure 3 As shown, the surface dimples 132A extend continuously around the active region 103. In other words, the surface dimples 132A have a substantially circular shape and form a plurality of concentric rings that completely surround the active region 103.

[0092] In a plan view (eg, on a plane parallel to the XY plane), the deep recesses 132B may have the same or different shapes relative to the surface recesses 132A.

[0093] According to an embodiment, the deep cavities 132B (all or only some of them) may also extend continuously around the active area 103; this may allow the device 100 to obtain a high breakdown voltage in use.

[0094] The presence of the surface cavities 132A may be considered optional, wherein the device includes only deep cavities 132B spaced apart from the surface 110A and located around the active region 103 .

[0095] The device 100 may optionally include an end region 140 arranged in the edge region 104 at the outer edge 102 .

[0096] The termination region 140 includes a doped region 141 having an N-type doping extending into the semiconductor body 110 at the front surface 110A, and a conductive region 142 extending onto the front surface 110A and electrically contacting the doped region 141. The termination region 140 may have the function of forming an equipotential ring with the drain terminal of the device 100 at the outer edge 102 of the die 101.

[0097] The inventors have demonstrated that the plurality of recesses 132 forming the edge termination region 130 are spaced a distance from one another along the Z-axis, which allows for a high breakdown voltage of the device 100 in use, and thus excellent electrical performance.

[0098] In particular, the fact that the cavity 132 extends from the front surface 110A to a high depth in the semiconductor body 110 , for example between 20 μm and 80 μm, may ensure that the breakdown voltage of the device 100 is further increased.

[0099] Furthermore, the inventors have determined that the recesses 132 extend along the X-axis and are spaced a certain distance apart from each other along the X-axis, which helps increase the electrical robustness of the device 100 during use. For example, the device 100 may have a high breakdown voltage greater than or equal to 1000V during use.

[0100] Furthermore, the fact that the cavities 132 extend at a distance from each other along the X-axis also allows for a reduction in the manufacturing costs of the device 100, in particular if the device 100 is a superjunction MOSFET device. Figures 5A-5G As discussed in detail, the distance along the X axis allows avoiding the use of additional masks to form an annular region extending continuously along the X axis, rather than as for Figure 1 and Figure 2 As discussed with respect to the known devices 1 and 50.

[0101] In the following, reference is made to Figures 5A to 5G , refer to Figure 4 The cross-section shown illustrates steps in the fabrication of the device 100 .

[0102] exist Figure 5A In the present invention, a silicon wafer 200 is provided, which has a front surface 200A and a back surface 200B opposite to the front surface 200A parallel to the Z axis; alternatively, the wafer 200 can be a different semiconductor material, such as silicon carbide or other simple or compound semiconductor materials.

[0103] Wafer 200 comprises a substrate, again indicated by 111 , on which an epitaxial layer 201 has been grown.

[0104] Epitaxial layer 201 and substrate 111 are the same material (silicon); however, they may be made of different materials.

[0105] The epitaxial layer 201 and the substrate 111 have the same conductivity type, and here have N-type doping.

[0106] Epitaxial layer 201 forms front surface 200A of wafer 200 .

[0107] Furthermore, doped portions 203 with a P-type doping have been formed in the wafer 200 , which will form the deep body region 116 , as well as P-type doped portions which will form the deepest row of deep cavities 132B and are therefore again indicated by 132B.

[0108] For example, the doped portion 203 , 132B may be formed by implanting a P-type dopant into the epitaxial layer 201 , such as by selectively implanting the P-type dopant into desired regions using a photolithographic mask.

[0109] Then, if Figure 5B As shown, epitaxial layer 205 is grown on epitaxial layer 201. Epitaxial layer 205 has the same material as epitaxial layer 201 (here, silicon); however, it can be a different material.

[0110] Epitaxial layer 205 forms the new front surface of wafer 200, again indicated as 200A for simplicity. Figure 5B In FIG, the dotted line separates epitaxial layer 205 from epitaxial layer 201 .

[0111] exist Figure 5C In the embodiment of the present invention, doped portion 207 is formed in epitaxial layer 205 above and in contact with doped portion 203. For example, doped portion 207 can be formed by implanting a P-type dopant into epitaxial layer 205, such as by selectively implanting the P-type dopant into the desired region using a photolithographic mask.

[0112] exist Figure 5D In FIG. 2 , epitaxial layer 209 is grown on front surface 200A, on epitaxial layer 205 .

[0113] Epitaxial layer 209 has the same material as epitaxial layer 205 (here, silicon); however, it may be a different material.

[0114] Epitaxial layer 209 forms the new front surface of wafer 200, again indicated as 200A for simplicity. Figure 5D In FIG, the dotted line separates epitaxial layer 205 from epitaxial layer 209 .

[0115] exist Figure 5E In the embodiment shown in FIG4 , a doped portion 211 having a P-type doping is formed in the epitaxial layer 209 above and in contact with the doped portion 207. In addition, a P-type doped portion is formed in the epitaxial layer 209, which will form another row of deep recesses 132B and is therefore again indicated by 132B.

[0116] For example, the doped portions 211 , 132B may be formed by implanting a P-type dopant into the epitaxial layer 209 , such as by selectively implanting the P-type dopant into desired regions using a photolithographic mask.

[0117] exist Figure 5F In FIG, epitaxial layer 213 is grown on front surface 200A, on epitaxial layer 209. Epitaxial layer 213 has the same material as epitaxial layer 209 (here silicon); however, it may be a different material.

[0118] Epitaxial layer 213 forms the new front surface of wafer 200, again indicated as 200A for simplicity. Figure 5F In FIG, the dotted line separates epitaxial layer 213 from epitaxial layer 209 .

[0119] exist Figure 5F After the growth, it has been referred to Figures 5C to 5E The description is repeated sequentially until the surface recesses 132A ( Figure 5G ).

[0120] In addition, Figure 5G , successive epitaxial layers grown on top of each other form the epitaxial region 112 of the device 100 .

[0121] In practice, the cavities 132 and the deep body regions 116 may be formed simultaneously by alternating epitaxial growth steps and dopant implantation steps.

[0122] Figures 5C to 5E The steps of are repeated a number of times, depending on the desired thickness of the epitaxial region 112 , the desired thickness of the deep body region 116 , and the desired number of recesses 132 in the edge termination region 130 .

[0123] One or more annealing steps may be performed to activate the cavities 132A, 132B and the deep body region 116 .

[0124] Subsequently, in a manner not shown here, a reference Figure 4 The remaining regions of the device 100 are depicted, including the surface body region 115 , the source region 117 , and the gate regions 117 118 .

[0125] Finally, manufacturing steps known per se follow, such as dicing the wafer 200 and forming electrical contacts, thereby forming the device 100 .

[0126] The described manufacturing process allows reducing the manufacturing cost of the device 100, in particular when the device 100 is a MOSFET device having a superjunction structure. In fact, the cavity 132 of the edge termination region 130 can be formed with the same mask and the same implantation steps used to form the deep body region 116, without the need for additional dedicated lithography and implantation steps.

[0127] In addition, with Figure 1 and Figure 2 The described process may also have reduced complexity and execution time compared to known device manufacturing processes.

[0128] Figure 6 A different embodiment of the present electronic device is shown, here indicated by 300. The electronic device 300 has a general structure similar to the device 100; therefore, common elements are indicated by the same reference numerals and are not described again in detail.

[0129] The device 300 is also a superjunction vertical conduction MOSFET device.

[0130] In detail, the device 300 includes a semiconductor body 110 and has a surface body region 115 , a deep body region 116 , a source region 117 and a gate region 118 in the active area 103 .

[0131] The device 300 includes an edge termination region 330 in the edge region 104 , which extends within the semiconductor body 110 around the active area 103 .

[0132] Here, the edge termination region 330 further comprises a plurality of recesses 332 of a conductivity type (P) opposite to the conductivity type of the semiconductor body 110 (N), including surface recesses 332A and deep recesses 332B, which extend into the semiconductor body 110 , in particular within the epitaxial region 112 .

[0133] The edge termination region 330 may have a width W as described with reference to the device 100. t .

[0134] In a plan view parallel to the XY plane, the cavity 332 may have a shape similar to that of the reference numeral 102 around the active region 103. Figure 3 The same trend as discussed for the recesses 132 of FIG. For example, the recesses 332 may each have a circular shape surrounding the active region 103, in particular forming concentric circles with each other.

[0135] Compared to what has been shown and described with respect to device 100 , recesses 332 may have variable pitch and width at the surface.

[0136] The cavities 332 are distributed in the semiconductor body 110 in such a way that the edge termination region 330 has a width W t The P-type cavity density (the number of cavities per unit area or unit volume) is non-uniform.

[0137] In detail, the cavities 332 may have an increasing density moving from the active area 103 toward the outer edge 102 of the die 101 parallel to the X-axis. For example, the width of the cavities 332 and / or the distance between two adjacent cavities 332 along the X-axis may have a decreasing trend moving from the active area 103 parallel to the X-axis and toward the outer edge 102.

[0138] For example, Figure 6 As shown, two adjacent recesses 332 along the x-axis may be spaced apart near the active region 103 by a distance W′. h , at a distance W″ at a center portion of the edge termination region 330 h , near the edge 102 at a distance W"' h Arrangement, where W'' h <W” h <W’ h .

[0139] For example, the distance W' h For example, the distance W"h may be comprised between 2 μm and 7 μm. For example, the distance W"' h May be comprised between 1 μm and 6 μm.

[0140] The edge termination region 330 allows the device 300 to have a high breakdown voltage in use.

[0141] In particular, the fact that the density of the cavities 332 is not uniform in the edge termination region 330 , and even more particularly is higher farther from the active area 103 , may ensure high electrical performance.

[0142] Figure 7 A further embodiment of the present electronic device is shown, here indicated by 400. The electronic device 400 has a similar general structure to the device 100; therefore, common elements are indicated by the same reference numerals and are not described again in detail.

[0143] The device 400 is also a superjunction vertical conduction MOSFET device.

[0144] In detail, the device 400 includes a surface body region 115 , a deep body region 116 , a source region 117 , and a gate region 118 in the active area 103 .

[0145] The device 400 includes an edge termination region 430 in the edge region 104 , which extends within the semiconductor body 110 around the active area 103 .

[0146] The edge termination region 430 comprises a plurality of recesses 432 extending into the semiconductor body 110 , here also being of a conductivity type (having a P-type doping) opposite to the conductivity type of the semiconductor body 110 (having an N-type doping).

[0147] In a plan view parallel to the XY plane, the cavity 432 surrounding the active region 103 may have a Figure 3 The same trend as discussed for the rows of recesses 132B is followed, for example, so that each recess forms a circle around the active area 103. The circles formed by the recesses 332B of each row may also be concentric with each other here.

[0148] In detail, the plurality of recesses 432 include surface recesses 432A extending at the front surface 110A, and deep recesses 432B extending at a distance from the front surface 110A.

[0149] The edge termination region 430 has a direction ( Figure 7 The width is measured along the Z-axis (the X-axis in FIG), which is variable as a function of the depth in the semiconductor body 110. Specifically, the width decreases from the front surface 110A toward the back surface 110B along the Z-axis.

[0150] Specifically, at the front surface 110A, the surface recess 432A defines the upper width W of the edge termination region 430. t,f , for example comprised between 50 μm and 200 μm.

[0151] The deep recess 432B defines the rear width W of the edge termination region 430 at the depth of the epitaxial region 112. t,b , for example, between 30 μm and 120 μm.

[0152] Upper width W t,f Greater than rear width W t,b ; In particular, the upper width W t,f The maximum width of the edge termination area 430 is defined, and the rear width W t,b A minimum width of the edge termination region 430 is defined.

[0153] Furthermore, the dimples 432 may be arranged such that the edge termination region 430 has a non-uniform density of dimples 432, eg, larger at greater depths from the front surface 110A within the epitaxial region 112. This may ensure a high breakdown voltage of the device 400 in use.

[0154] For example, moving from the front surface 110A parallel to the Z-axis toward the back surface 110B, the pockets 432 may have decreasing widths as measured along the X-axis.

[0155] Electrical simulations performed by the applicant have verified that the decreasing trend of the width of the edge termination region 430 can help ensure excellent electrical performance of the device 400 in use.

[0156] In fact, referring to devices 100, 300, 400, the respective edge termination regions 130, 330, 430 are formed by a plurality of cavities 132, 332, 432 having a conductivity type different from that of the semiconductor body 110 and arranged at a distance from one another along the Z-axis or along both the Z-axis and the X-axis. This fact provides the edge termination regions with high design versatility. Therefore, the present electronic device can be adapted for a variety of applications.

[0157] It is also clear to those skilled in the art that reference Figures 5A to 5G The described manufacturing steps may be applicable to the manufacturing of the devices 300 , 400 .

[0158] Figure 8 and Figure 9 Other embodiments of the present semiconductor electronic device are shown, indicated by 500 and 600 respectively.

[0159] Devices 500 and 600 include edge termination regions (indicated by 502 and 602 , respectively) having P-type cavities in the edge region 104 around the active area.

[0160] The distribution of the cavities 502, 602 in the semiconductor body 110 may be equal to or different from that for the cavities 132 ( Figure 4 )、332( Figure 6 ) and 432( Figure 7 ) discussed in the distribution.

[0161] In particular, devices 500 and 600 are Figure 3 and Figure 4 The device 100 of FIG. 1 differs in the distribution of the cavities 502 , 602 around the active area 103 .

[0162] In detail, in devices 500 and 600 , the cavities 502 , 602 extend discontinuously around the active region 103 , thereby forming a plurality of portions separated from each other.

[0163] The discontinuous distribution of the recesses 502 or 602 around the active region 103 can simplify the design steps of the devices 500 and 600 , especially the design steps of the photolithography mask.

[0164] Finally, it is obvious that modifications and variations may be made to the semiconductor electronic device and to the process for its manufacture described and illustrated herein without departing from the scope of the present invention as defined in the appended claims.

[0165] For example, the surface recesses and / or deep recesses in the edge termination area can be (all or only some) floating or have dedicated areas for biasing to a specific potential. In particular, the surface recesses and deep recesses can be (e.g., all) floating; in this case, the actual potential of the recesses can be determined during the design step by appropriate dimensions as a function of the specific application. In addition, the use of floating recesses simplifies the manufacture of the device.

[0166] For example, the edge termination region may have a different number and distribution of recesses than described.

[0167] For example, the deep body regions and / or doped recesses of the edge termination area may be produced by forming trenches in the wafer 200 and filling the trenches with doped semiconductor material, instead of or in addition to subsequent steps of epitaxial growth and dopant species implantation.

[0168] For example, the gate region 118 may be trench-type (ie, extending into the semiconductor body 110 along the Z-axis).

[0169] For example, depending on the specific application of the semiconductor electronic device, the active region 103 may also accommodate basic units of devices other than MOSFETs.

[0170] For example, the present invention is also applicable to semiconductor electronic devices other than superjunction vertical conduction MOSFETs, such as lateral conduction MOSFETs, vertical conduction MOSFETs and non-superjunction types, or devices other than MOSFETs, such as trench FETs, diodes, tri-transistors, MESFETs, MISFETs, IGBTs, etc.

[0171] The conductivity types P and N may be reversed from those discussed above. For example, the semiconductor body may be of P type, while the cavity of the edge termination region may be of N type.

[0172] Finally, the different embodiments described and illustrated above may be combined to provide further solutions.

Claims

1. A semiconductor electronic device comprising: a semiconductor body having a first conductivity type, a front surface, and a rear surface extending at a distance from the front surface along a first direction, the semiconductor body further having a lateral edge; an active region configured to include a conductive channel of the semiconductor electronic device; as well as an edge termination region extending around the active area between the active area and the lateral edge of the semiconductor body along a second direction transverse to the first direction; The edge termination region includes a plurality of doped portions having a second conductivity type different from the first conductivity type and being arranged in the semiconductor body at a distance from one another along the first direction or along the first direction and the second direction. 2 . The semiconductor electronic device according to claim 1 , wherein the plurality of doped portions include surface doped portions extending from the front surface into the semiconductor body, wherein the surface doped portions are spaced apart from each other by a distance along the second direction.

3. The semiconductor electronic device according to claim 1 , wherein the plurality of doped portions include deeply doped portions extending into the semiconductor body at a distance from the front surface, and wherein the deeply doped portions are spaced apart from each other by a distance along the second direction and the first direction. 4 . The semiconductor electronic device of claim 1 , wherein the plurality of doped portions include deeply doped portions extending into the semiconductor body at a distance from the front surface, and wherein the deeply doped portions are spaced apart from each other by a distance along the first direction. The semiconductor electronic device according to claim 1 , wherein the doped portions face each other and are aligned with each other along the first direction. The semiconductor electronic device according to claim 1 , wherein the doped portions at least partially face each other along the first direction. The semiconductor electronic device according to claim 1 , wherein the edge termination region has a uniform density of doped portions. The semiconductor electronic device of claim 1 , wherein the edge termination region has a non-uniform density of doped portions. 9 . The semiconductor electronic device of claim 8 , wherein the edge termination region has a first density of doped portions near the active area and a second density of doped portions greater than the first density near the lateral edge of the semiconductor body. 10 . The semiconductor electronic device of claim 1 , wherein the edge termination region has a density of doped portions that increases along the second direction from the active area toward the lateral edge. 11 . The semiconductor electronic device of claim 1 , wherein the edge termination region has a density of doped portions that increases along the first direction from the front surface toward the back surface. 12 . The semiconductor electronic device of claim 1 , wherein the edge termination region has a width along the second direction that decreases from the front surface toward the back surface along the first direction. 13 . The semiconductor electronic device according to claim 1 , wherein the doped portions each have a width along the second direction, the width being between 1 μm and 10 μm.

14. The semiconductor electronic device of claim 1, wherein the device is a vertical conduction MOSFET device.

15. The semiconductor electronic device of claim 1 , wherein the device is a super junction MOSFET device having at least one deep body region extending into the active area at a distance from the front surface along the first direction.

16. A process for manufacturing a semiconductor electronic device, comprising: providing a wafer of semiconductor material having a first conductivity type, a front surface, and a back surface spaced a distance from the front surface along a first direction, the wafer further having a lateral edge; forming an active region, the active region being configured to include a conductive channel of the semiconductor electronic device; as well as forming an edge termination region extending around the active area between the active area and the lateral edge of the wafer in a second direction transverse to the first direction; The forming of the edge termination region includes forming a plurality of doped portions in the semiconductor body, wherein the plurality of doped portions have a second conductivity type different from the first conductivity type and are spaced a certain distance from each other along the first direction or along the first direction and the second direction.

17. The process of claim 16, wherein forming the edge termination region comprises performing at least one of: growing at least one epitaxial layer on the front surface of the wafer; and The doped portion is formed in the at least one epitaxial layer.

18. The process of claim 16, further comprising forming at least one deep body region of the second conductivity type in the wafer, the deep body region being formed at least partially simultaneously with the doped portion of the edge termination region.

Images