Normally-closed gate-controlled junction field effect transistor

Abstract

The invention provides a normally-closed gate-controlled junction field effect transistor, which comprises a substrate and an epitaxial layer, the channel region of the second doping type is formed at a position below the top surface of the epitaxial layer; the gate region of the first doping type is formed on the channel region; the channel adjusting region of the second doping type is formed at a position below the top surface of the epitaxial layer and is connected with the edge of the channel region; the source region of the second doping type is formed at a position below the top surface of the epitaxial layer, and the source region is connected with the channel adjusting region on the same side, so that the source region and the gate region are separated by the channel adjusting region in the transverse direction; the passivation protection layer at least covers the top surface of the channel adjustment region and the side surface of the gate region; and the well region of the first doping type is formed below the channel region, the channel adjusting region and the source region. The technical problem that the use scene is limited due to the fact that most of traditional grid-control junction field effect transistors are normally open is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a normally-off gate-controlled junction field-effect transistor. Background Art

[0002] Compared to silicon-based devices, silicon carbide devices offer advantages such as higher voltage resistance, faster switching speeds, higher operating temperatures, improved heat dissipation, and better radiation resistance, and therefore have broad application prospects in power electronics circuits. Silicon carbide devices can adopt device structures such as MOSFET and JFET. JFET devices are three-port devices that operate by controlling the reverse and forward bias of the PN transistor by applying gate voltage, thereby controlling the opening and closing of the channel. They have advantages such as low noise, small size, and high-frequency response. JFET devices made of silicon carbide can be used in a wide range of power electronics applications, such as server power supplies and electric vehicle main drive inverters.

[0003] Silicon carbide gate-controlled junction field-effect transistor, referred to as SiC JFET, is called Silicon Carbide Junction Field-Effect Transistor in English. The existing silicon carbide gate-controlled junction field-effect transistor has various regions such as Figure 1a As shown, a first well region 1-1, a first doping type source contact region 1-2, a second doping type source contact region 1-3, a gate 1-4, a first channel region 1-5, and a dielectric layer 1-9.

[0004] The gate-controlled junction field-effect transistor can be used as a power device. Figure 1a The gate-controlled junction field-effect transistor shown in the figure generally has a negative threshold voltage, which means that it is normally open when no voltage is applied. Normally-on semiconductor devices require a control voltage to be applied before they can be turned off, which can pose a safety hazard in many practical scenarios. For example, when the system is in the off state, there is no control voltage input, or during the system power-on initialization phase, the control voltage is unstable. In these cases, using normally-on devices may cause system instability or even damage. Therefore, due to the normally-on characteristic of general gate-controlled junction field-effect transistors, they are often impossible or difficult to use in most application scenarios; or in order to use these devices, the control circuit must be specially designed.

[0005] In addition, a power device is actually a switch, so switching loss cannot be ignored during application. Figure 1a The conventional gate-controlled junction field-effect transistor shown in the figure has a large input capacitance and gate leakage when the device is turned on, resulting in increased switching loss and drive current of the device, and thus poor performance.

[0006] Figure 1b for Figure 1a Energy band diagram of the first channel region 1-5 at the cross-sectional position shown by the dotted line of the silicon carbide gate-controlled junction field-effect transistor when the gate voltage Vg=0V is turned off.

[0007] For wide bandgap semiconductors such as SiC, GaN, GaO, and diamond, the built-in voltage Vb of the pn junction composed of p-type and n-type wide bandgap semiconductors with relatively high doping concentrations will be slightly less than Eg / q (Eg is the bandgap width, q is the electron charge). For example, if the p-type and n-type doping concentrations exceed 1×10 17 cm -3 , the built-in voltage of the pn junction of 4H-SiC can reach over 3.0 volts. A JFET, formed by a wide-bandgap semiconductor pn junction, can undergo self-depletion when the gate voltage is zero, realizing a normally-off junction field-effect transistor (JFET).

[0008] In other words, theoretically, the threshold voltage (Vth) of a silicon carbide-gated junction field-effect transistor can be greater than or less than zero. A JFET with a threshold voltage (Vth) greater than zero is called a normally-off device, also known as an enhancement-mode device. A JFET with a threshold voltage (Vth) less than zero is called a normally-on device, also known as a depletion-mode device.

[0009] However, the doping dose in the channel region significantly affects the threshold voltage (Vth), meaning that the threshold voltage (Vth) is particularly sensitive to the doping dose in the channel region. Furthermore, from a practical perspective, the threshold voltage (Vth) for a normally-off gate-controlled junction field-effect transistor to operate normally cannot be lower than 1.0 volt. Consequently, a normally-off gate-controlled junction field-effect transistor has not been practically fabricated.

[0010] Therefore, traditional gate-controlled junction field-effect transistors are limited in their usage scenarios because they are mostly normally-on, which is a technical problem that technical personnel in this field urgently need to solve.

[0011] The above information disclosed in the Background section is only for enhancement of understanding of the background of the application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art. Summary of the Invention

[0012] The present application provides a normally-off gate-controlled junction field-effect transistor to solve the technical problem that traditional gate-controlled junction field-effect transistors are mostly normally-on, resulting in limited usage scenarios.

[0013] The present application provides a normally-off gate-controlled junction field-effect transistor, comprising: a substrate, an epitaxial layer formed on the substrate; a drain electrode formed on the back side of the substrate; A channel region of a second doping type is formed below a top surface of the epitaxial layer; a gate region of a first doping type formed on the channel region; A channel regulating region of the second doping type is formed below the top surface of the epitaxial layer and connected to the edge of the channel region; A source region of the second doping type is formed below the top surface of the epitaxial layer and is connected to the channel adjustment region on the same side, so that the source region and the gate region are separated in a lateral direction by the channel adjustment region; a passivation protection layer, covering at least a top surface of the channel adjustment region and a side surface of the gate region; A well region of a first doping type is formed under the channel region, the channel regulating region, and the source region.

[0014] By adopting the above technical solution, this application has the following technical effects: The normally-off gate-controlled junction field-effect transistor of the present application introduces a channel adjustment region, which facilitates the adjustment of the value of the threshold voltage Vth, thereby enabling the threshold voltage Vth to be a large positive value. The preparation difficulty is low and it can meet the needs of mass production.

[0015] For the normally-off gate-controlled junction field-effect transistor of the present application, since the gate and source regions are separated by a channel regulation region and lack a PN junction, the device input capacitance is accordingly very small. This small input capacitance enables the normally-off gate-controlled junction field-effect transistor of the present application to have a faster switching speed and lower switching losses. Maintaining a predetermined spacing between the gate and source regions in the lateral direction also prevents gate leakage.

[0016] The passivation protection layer is an oxide layer grown by a thermal oxidation process. It has good quality and can provide good passivation protection for the top surface of the channel adjustment region and the side of the gate region, thereby avoiding affecting the PN junction formed by the gate region and the channel region, and the PN junction formed by the channel adjustment region and the gate region. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1a Schematic diagram of an existing silicon carbide gate-controlled junction field-effect transistor; Figure 1b for Figure 1a Energy band diagram of the first channel region 1-5 of the cross-section shown by the dotted line of the silicon carbide gate-controlled junction field effect transistor when the gate voltage Vg=0V is turned off; Figure 2-1 A schematic diagram of an implementation of a normally-off gate-controlled junction field-effect transistor of the present application; Figure 2-2 Schematic diagram of yet another implementation of the normally-off gate-controlled junction field-effect transistor of the present application; Figure 3-1 for Figure 2-2 Schematic diagram of a normally-off gate-controlled junction field effect transistor in which the channel regulation region and the channel region are completely depleted; Figure 3-2 for Figure 2-2 Schematic diagram of a normally-off gate-controlled junction field effect transistor in which the channel regulating region and the channel region are partially depleted; Figure 4 A schematic diagram of another implementation of the normally-off gate-controlled junction field-effect transistor of the present application; Figure 5 A graph showing a change in gate-source current Igs versus gate-source voltage Vgs for the normally-off gate-controlled junction field-effect transistor of the present application and the prior art; Figure 6 A simulation diagram of the current distribution and path of the source-drain current Ids of the normally-off gate-controlled junction field-effect transistor of this application when it is forward-conducting; Figure 7 A simulation diagram of the current distribution and path of the gate leakage current Igss when the gate of the normally-off gate-controlled junction field-effect transistor of this application is voltaged; Figure 8 A curve comparison of the on-resistance Rdson of the normally-off gate-controlled junction field-effect transistor of the present application and the prior art device as the device temperature changes; Figure 9 A comparison graph of the input capacitance Ciss of the normally-off gate-controlled junction field-effect transistor of the present application and the prior art device versus the gate-source voltage Vgs; Figure 10 A graph showing the change in gate current Ig versus gate-source voltage Vgs of the normally-off gate-controlled junction field-effect transistor of the present application; Figure 11 A simulation diagram of the current distribution and path of the normally-off gate-controlled junction field-effect transistor of the present application when the gate-source voltage Vgs fails to open the channel; Figure 12 This is a simulation diagram of the current distribution and path of the normally-off gate-controlled junction field-effect transistor of the present application when the gate-source voltage Vgs is zero and the source-drain voltage Vds is positive; Figure 13 A simulation diagram of the current distribution of the normally-off gate-controlled junction field-effect transistor of the present application during forward conduction; Figure 14This is a graph showing the LSF of the normally-off gate-controlled junction field-effect transistor of the present application, which shows the capability of conducting current and the gate-source voltage Vgs.

[0018] Reference numerals: In the background technology: First well region 1-1, first doping type source contact region 1-2, second doping type source contact region 1-3, Gate 1-4, first channel region 1-5, dielectric layer 1-9; This application: Channel region 1, source region 2, channel adjustment region 3, passivation protection layer 4, gate region 5, gate electrode 6, Isolation layer 7, source electrode 8, well region 9, drift region 10, substrate 11, drain electrode 12, channel 13, The source contact region 14 and the channel region depletion portion 16 are provided. DETAILED DESCRIPTION

[0019] In order to make the technical solutions and advantages of this application more clearly understood, the following further describes the exemplary embodiments of this application in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of this application, and are not an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of this application can be combined with each other unless there is a conflict. Example 1

[0020] like Figure 2-1 、 Figure 2-2 、 Figure 4 As shown, the normally-off gate-controlled junction field-effect transistor of the present application includes: A wide bandgap semiconductor substrate 11 and an epitaxial layer of the wide bandgap semiconductor formed on the substrate 11; a drain electrode 12 formed on the back side of the substrate 11; A channel region 1 of a second doping type is formed below the top surface of the epitaxial layer; specifically, the channel region 1 may be formed downward from the top surface of the epitaxial layer; A gate region 5 of a first doping type is formed on the channel region 1; A channel regulating region 3 of the second doping type is formed below the top surface of the epitaxial layer and connected to the edge of the channel region 1; specifically, the channel regulating region 3 can be formed downward from the top surface of the epitaxial layer; a source region 2 of the second doping type, formed below the top surface of the epitaxial layer and connected to the channel adjustment region 3 on the same side, such that the source region 2 and the gate region 5 are separated in the lateral direction by the channel adjustment region 3; specifically, the source region 2 may be formed downward from the top surface of the epitaxial layer; a passivation protection layer 4 covering at least the top surface of the channel regulation region 3 and the side surfaces of the gate region 5; A well region 9 of the first doping type is formed under the channel region 1 , the channel regulating region 3 , and the source region 2 . The well region 9 and the source region 2 are connected via a connection structure.

[0021] The portion of the epitaxial layer where no functional region is formed serves as a drift region 10 .

[0022] For the convenience of description, the first doping type is P-type and the second doping type is N-type.

[0023] The gate region 5 of the first doping type (i.e., P-type), the channel adjustment region 3 of the second doping type (i.e., N-type wide bandgap semiconductor), and the well region 9 of the first doping type (i.e., P-type) form two back-to-back PN junctions; The first doping type (ie, P-type) gate region 5 , the second doping type (ie, N-type wide bandgap semiconductor) channel region 1 , and the first doping type (ie, P-type) well region 9 form two back-to-back PN junctions.

[0024] When the normally-off gate-controlled junction field-effect transistor is not connected to the gate voltage Vg, the potential of the corresponding gate region 5 is zero; and when the source is not connected to the source voltage, the potential of the corresponding source region 2 and the well region 9 is zero. At this time, the built-in voltage Vb of the PN junction composed of the P-type semiconductor with a relatively high doping concentration and the N-type wide bandgap semiconductor is relatively large, which corresponds to the following in this application: The gate region 5 and the channel region 1 form a PN junction, and the channel region 1 and the well region 9 form a PN junction; The channel regulating region 3 and the gate region 5 form a PN junction, and the channel regulating region 3 and the well region 9 form a PN junction.

[0025] The built-in voltage of these four PN junctions completely depletes the channel region 1 and the channel regulating region 3, thereby increasing the threshold voltage of the normally-off gate-controlled junction field-effect transistor. Therefore, the normally-off gate-controlled junction field-effect transistor requires a larger positive gate voltage to eliminate the depletion regions in the channel region 1 and the channel regulating region 3, thereby opening the channel and turning on the device.

[0026] The channel adjustment region 3 plays a key role in achieving a high threshold voltage (Vth). Therefore, the upper surface of the channel adjustment region 3 must be passivated and protected. The best passivation layer is formed by thermally oxidizing the entire surface after the doping process for forming the channel adjustment region 3 is completed. This layer forms a passivation layer on the top surface of the channel adjustment region 3 and the sides of the gate region 5. This ensures that the electrical characteristics of the channel adjustment region 3 are not affected by etching and other processes, maintaining stable electrical characteristics of the channel adjustment region 3.

[0027] The passivation protection layer 4 is an oxide layer grown by a thermal oxidation process, and has good quality. It can provide good passivation protection for the top surface of the channel adjustment region 3 and the side of the gate region 5, thereby avoiding affecting the PN junction formed by the gate region 5 and the channel region 1, and the PN junction formed by the channel adjustment region 3 and the gate region 5.

[0028] At the same time, because the gate region 5 is directly above the channel region 1, that is, the vertical outer edge of the gate region 5 is located within the vertical outer edge of the channel region 1 in the lateral direction, the gate region 5 and the source region 2 maintain a preset spacing in the lateral direction equal to the lateral length of the channel adjustment region 3; in the vertical direction, the gate region 5 and the source region 2 are not in the same layer, but are located in a layer above the source region 2. This ensures that the gate region 5 and the source region 2 are completely non-contacting, and no PN junction is formed between them.

[0029] For the normally-off gate-controlled junction field-effect transistor of the present application, since there is no PN junction between the gate region 5 and the source region 2, the input capacitance of the device is accordingly very small; the input capacitance is very small, so that the normally-off gate-controlled junction field-effect transistor of the present application has a faster switching speed, which makes the switching loss smaller.

[0030] The gate region 5 and the source region 2 maintain a preset distance in the lateral direction, and gate leakage will not be caused.

[0031] The normally-off gate-controlled junction field-effect transistor of the present application is provided with a separate channel regulation region 3 independent of the channel region 1, which has the following functions: On the one hand, a PN junction is formed between the channel adjustment region 3 and the gate region 5 ; the channel adjustment region 3 and the channel region 1 work together to reach a preset value of the threshold voltage Vth, and the preset value of the threshold voltage Vth can reach a relatively large value; On the other hand, the channel adjustment region 3 and the channel region 1 are two independent regions, so that the doping dose and doping concentration of the channel adjustment region 3 and the channel region 1 are independent of each other; The channel region 1 determines a portion of the preset value of the threshold voltage Vth as the first portion; The channel regulating region 3 determines the portion of the threshold voltage Vth preset value other than the first portion, thereby meeting the requirement that the threshold voltage Vth preset value of the normally-off gate-controlled junction field effect transistor is greater than or equal to 1.0 volt.

[0032] The threshold voltage Vth is particularly sensitive to the doping dose of the channel region 1 , and is less sensitive to the doping dose of the channel adjustment region 3 . Therefore, the value of the threshold voltage Vth can be adjusted by adjusting the doping dose of the channel adjustment region 3 .

[0033] In this way, the normally-off gate-controlled junction field-effect transistor of the present application conveniently realizes the adjustment of the value of the threshold voltage Vth due to the introduction of the channel adjustment region 3, thereby achieving a larger positive value of the threshold voltage Vth, with low preparation difficulty and adaptability to the needs of mass production.

[0034] The normally-off silicon carbide gate-controlled junction field-effect transistor of the present application has excellent performance.

[0035] Normally-on devices are devices that operate in on-mode when no gate voltage is applied, and require a voltage to be applied to the gate of the device to turn it off.

[0036] In contrast, a normally-off device operates in an off-high-impedance mode when no gate control voltage is applied, and a voltage must be applied to the gate of the device to turn it on.

[0037] In practice, the vertical outer edge of the channel region 1 and the vertical outer edge of the gate region 5 are aligned in the vertical direction, that is, the channel region 1 is located directly below the gate region 5 .

[0038] In this way, the upper end point of the channel regulating region 3 and the lower end point of the gate region 5 form a point contact, so that a tip electric field effect exists at the point contact position.

[0039] The gate region 5 and the channel region 1 form a PN junction, and the channel region 1 and the well region 9 form a PN junction; An upper end point of the channel adjustment region 3 and a lower end point of the gate region 5 form a PN junction, and the channel adjustment region 3 and the well region 9 form a PN junction.

[0040] In the four PN junctions, there are three parallel plates with built-in electric fields and one tip with built-in electric field: The PN junction formed by the gate region 5 and the channel region 1, the PN junction formed by the channel region 1 and the well region 9, and the PN junction formed by the channel adjustment region 3 and the well region 9 are all built-in electric fields of the parallel plates formed by the flat plate structure. The built-in electric fields of the parallel plates of these three PN junctions form their respective built-in voltages.

[0041] Since the upper end point of the channel adjustment region 3 and the lower end point of the gate region 5 are respectively tip structures and have a tip electric field effect, the PN junction formed by the upper end point of the channel adjustment region 3 and the lower end point of the gate region 5 forms a tip built-in electric field, and the tip built-in electric field is much larger than the built-in electric field of the parallel plate, so that the built-in voltage of the PN junction formed by the upper end point of the channel adjustment region 3 and the lower end point of the gate region 5 is much larger than the built-in voltage formed by the built-in electric field of the parallel plate.

[0042] Therefore, the PN junction formed by the gate region 5 and the channel region 1, the PN junction formed by the channel region 1 and the well region 9, the PN junction formed by the upper end point of the channel adjustment region 3 and the lower end point of the gate region 5, and the PN junction formed by the channel adjustment region 3 and the well region 9. The built-in voltage of these four PN junctions causes the channel region 1 and the channel adjustment region 3 to be completely depleted, thereby increasing the threshold voltage of the normally-off gate-controlled junction field-effect transistor. As a result, the normally-off gate-controlled junction field-effect transistor requires a larger positive gate voltage to eliminate the depletion regions in the channel region 1 and the channel adjustment region 3, open the channel, and achieve device conduction.

[0043] The passivation protection layer 4 prevents the PN junction formed by the gate region 5 and the channel region 1 and the PN junction formed by the upper end of the channel regulating region 3 and the lower end of the gate region 5 from being affected.

[0044] Specifically, such as Figure 2-1 、 Figure 2-2 、 Figure 4 As shown, the source region 2, the channel regulating region 3, and the channel region 1 are located in the same layer.

[0045] In implementation, as an optional method, such as Figure 2-1 As shown, the cross section of the source region 2 is rectangular, and the cross section of the channel adjustment region 3 is rectangular; the position where the source region 2 and the channel adjustment region 3 are connected is a linear plane.

[0046] The source region 2 and the channel adjustment region 3 of such a shape have a simple preparation process and are easy to prepare. They also better reflect the usefulness of the channel adjustment region, enhance the depletion of the channel adjustment region, and have a stronger turn-off capability.

[0047] As another alternative, Figure 2-2 As shown, the cross section of the source region 2 is L-shaped, and the cross section of the channel adjustment region 3 is rectangular; the position where the source region 2 and the channel adjustment region 3 are connected is an L-shaped plane.

[0048] The source region 2 and the channel adjustment region 3 of this shape require a slightly more complicated preparation process; the current flow path is shorter, resulting in a smaller on-resistance Rdson.

[0049] In implementation, such as Figure 2-1 、 Figure 2-2 、 Figure 3-1 、 Figure 4 As shown, as an optional embodiment, the channel adjustment region 3 is completely depleted, and the channel region 1 is completely depleted. That is, the width X of the self-depletion region of the channel adjustment region 3 is the same as the width W3 of the channel adjustment region 3, and the width Y of the self-depletion region of the channel region 1 is the same as the width W1 of the channel region 1.

[0050] In implementation, the ratio of the width X of the self-depletion region of the channel adjustment region 3 to the width W3 of the channel adjustment region 3 is greater than or equal to 3 / 5 and less than or equal to 1, and the ratio of the width Y of the self-depletion region of the channel region 1 to the width W1 of the channel region 1 is greater than or equal to 3 / 5 and less than or equal to 1.

[0051] like Figure 3-2 As shown, the width X of the self-depletion region of the channel adjustment region 3 is smaller than the width W3 of the channel adjustment region 3 , and the width Y of the self-depletion region of the channel region 1 is smaller than the width W1 of the channel region 1 .

[0052] When the gate voltage Vg is zero volts and the voltages of the source region 2 and the well region 9 are zero volts, the built-in voltages of the gate region 5 and the well region 9 can deplete the depletion region of the channel regulating region 3 and the depletion region of the channel region 1 (corresponding to Figure 3-2 The channel region depletion portion 16).

[0053] Although the channel adjustment region 3 and the gate region 5 are connected at only a very small intersection area, that is, the upper end of the channel adjustment region 3 and the lower end of the gate region 5 form a point contact, the electric field at the tip of the gate region 5 and the channel adjustment region 3 is much stronger than the parallel plate electric field of the channel region depletion part 16; since the concentration of the channel adjustment region 3 is much lower than that of the gate region 5, most of the channel adjustment region 3 (corresponding to Figure 3-2 ) or even all areas (corresponding Figure 3-1 Thus, when the gate voltage Vg is zero volts, the length of the depletion portion 16 from the source region 2 to the channel region is X+Y.

[0054] Even if the strong electric field from the epitaxial layer enters the channel region 1 through the channel 13 between the two well regions and reduces the length of the depletion region of the channel region, the depletion region of the channel adjustment region 3 will provide a sufficiently high potential barrier to prevent electrons from the source region 2 from entering the channel region 1, forming a normally-off device.

[0055] The threshold voltage Vth depends not only on the self-depletion effect of the channel region 1, but also on the self-depletion effect of the channel adjustment region 3. Since the channel barrier is mainly provided by the self-depletion region of the channel adjustment region 3 and the self-depletion region of the channel region, Figure 3-2 The effective gate length Lg of the normally-off gate-controlled junction field-effect transistor shown can be as small as less than 0.2 microns. A smaller Lg can further reduce the channel resistance. Therefore, a smaller Lg is one of the reasons why the channel resistance of the channel region 1 is smaller.

[0056] The channel adjustment region 3 of the normally-off gate-controlled junction field-effect transistor of the present invention is the key to controlling the value of the threshold voltage Vth to be no less than 1.0 volt. Because when the gate voltage is zero, the channel region 1 and the channel adjustment region 3 are completely depleted, the current cannot flow smoothly, and the device behaves as normally-off. When the gate voltage is 3V, the depletion of the channel region 1 and the channel adjustment region 3 has completely disappeared, and the current can pass through the channel region 1 and the channel adjustment region 3 smoothly, and the doping concentration of the channel region 1 and the channel adjustment region 3 is higher than that of the drift region 10, so the resistance of the channel region 1 and the channel adjustment region 3 is small, meeting practical requirements. That is, the present application needs to achieve a balance between normally-off and small on-resistance.

[0057] In implementation, such as Figure 2-1 , such as 2-2, Figure 4 As shown, the normally-off gate-controlled junction field-effect transistor also includes: a gate electrode 6 formed on the gate region 5 , wherein the gate electrode 6 is smaller than the gate region 5 , and a vertical outer edge of the gate electrode 6 is located within a vertical outer edge of the gate region 5 ; a source electrode 8 connected to the source region 2, with a gap between the source electrode 8 and the channel regulating region 3 to ensure isolation between the two; The passivation protection layer 4 also covers the portion of the source region 2 not covered by the source electrode 8 ; the passivation protection layer 4 also covers the region of the gate region 5 not covered by the gate electrode 6 until it is connected to the gate electrode 6 .

[0058] That is, the passivation protection layer 4 connects the gate electrode 6 and the source electrode 8, thereby covering the side surfaces of the channel adjustment region 3 and the gate region 5 therebetween, the portion of the top surface of the source region 2 not covered by the source electrode 8, and the portion of the top surface of the gate region 5 not covered by the gate electrode 6. This structure in which the passivation protection layer 4 connects the gate electrode 6 and the source electrode 8 is a structural requirement formed from the perspective of simplifying the manufacturing process.

[0059] In implementation, such as Figure 2-1 、 Figure 2-2 、 Figure 4 As shown, the normally-off gate-controlled junction field-effect transistor also includes: an isolation layer 7 formed between the source electrode 8 and the gate electrode 6 and covering the passivation protection layer 4; A source contact region 14 of the first doping type is formed on a side of the source region 2 opposite to the channel regulating region 3 and connected to the well region 9; The source electrode 8 is located above the source region 2 and the source contact region 14 , so that the well region 9 and the source region 2 are stably connected to the source voltage.

[0060] The isolation layer 7 is usually formed by deposition, and its quality is average, but it is sufficient to isolate the source electrode 8 and the gate electrode 6 .

[0061] The isolation layer 7 is formed between the source electrode 8 and the gate electrode 6 and covers the passivation protection layer 4 and the source region 2. The isolation layer 7 isolates the source electrode 8 from the gate electrode 6.

[0062] The passivation protection layer 4 is an oxide layer grown by a thermal oxidation process, which has good quality and mainly protects the top surface of the channel adjustment region 3 and the gate region 5; at the same time, it also prevents the sodium ions and potassium ions in the isolation layer 7 from affecting the channel region 1 and the channel adjustment region 3.

[0063] In practice, the doping concentration of the channel region 1 is at least one order of magnitude greater than the doping concentration of the drift region 10, so that within the operating temperature range, as the temperature of the normally-off gate-controlled junction field-effect transistor increases: The electron mobility of the channel region 1 with a higher doping concentration becomes higher, and the channel resistance decreases instead; The electron mobility of the drift region 10 with a lower doping concentration becomes lower, and the resistance of the drift region 10 increases; This makes the on-resistance of the normally-off gate-controlled junction field-effect transistor change very little with temperature.

[0064] Specifically, the doping concentration of the channel region 1 is on the order of 10 17 cm -3 to 10 18 cm -3 , the doping concentration of the drift region 10 is on the order of 10 16 cm -3 .

[0065] Temperature characteristics of the normally-off gate-controlled junction field-effect transistor of the present invention: Because both channel region 1 and channel adjustment region 3 are highly doped with N-type dopants and participate in electrical conduction, the electron mobility in channel region 1 is primarily determined by ionized impurity scattering and does not decrease with increasing temperature. Conversely, as the temperature of the normally-off gate-controlled junction field-effect transistor increases, the electron mobility in channel region 1 also increases, and more electrons in channel region 1 are excited from impurities to participate in electrical conduction, which in turn reduces the channel region resistance.

[0066] However, the doping concentration in the drift region 10 is relatively low. As the temperature of the normally-off gated junction field-effect transistor increases, electron mobility decreases, and the resistance of the drift region 10 increases. The resistance of the channel region and the resistance of the drift region 10 add up and compensate for each other, resulting in a small temperature-dependent change in the on-resistance of the normally-off gated junction field-effect transistor. The aforementioned range of channel region 1 doping concentration values ​​ensures that the on-resistance of the normally-off gated junction field-effect transistor varies minimally with temperature.

[0067] In practice, the doping concentration of the channel regulating region 3 is in the range of greater than or equal to 1×10 17 cm -3 and less than or equal to 1×10 18 cm -3 ; The width of the channel adjustment region 3 in the lateral direction is in the range of greater than or equal to 0.05 micrometers and less than or equal to 0.35 micrometers; and the doping concentration of the channel regulating region 3 is lower than the doping concentration of the channel region 1; The height of the channel adjustment region 3 in the vertical direction ranges from greater than or equal to 0.05 micrometers to less than or equal to 0.2 micrometers.

[0068] The doping concentration N1 of the channel region 1 is greater than or equal to 1×10 17 cm -3 and less than or equal to 1×10 18 cm -3 ; The width of the channel region 1 in the lateral direction is in the range of greater than or equal to 0.15 micrometers and less than or equal to 0.5 micrometers; The height of the channel region 1 in the vertical direction ranges from greater than or equal to 0.05 micrometers to less than or equal to 0.2 micrometers.

[0069] It should be noted that the doping concentration, lateral width, and vertical height of the channel adjustment region 3, and the doping concentration, lateral width, and vertical height of the channel region 1 of the present application are not simply arbitrary values.

[0070] Instead, it is based on the structure of the present application and under the guidance of the technical concept of the present application, and targeted selection and technical simulation are carried out, and verified by the simulation results. Among them, the structure of the present application includes: setting up a channel adjustment region 3 separately, and setting clear requirements for the location of the channel adjustment region; the gate region 5 is located directly above the channel region 1; the source region 2 and the gate region 5 are separated in the vertical direction and the lateral direction, etc. The technical concept of the present application at least includes: by setting up independent channel regions 1 and channel adjustment regions 3, the threshold voltage of the gate-controlled junction field effect transistor is greater than or equal to 1.0 volt to achieve normally off, while fully considering that the on-resistance cannot be too large, so as to achieve a practical device.

[0071] In practice, the doping concentration of the gate region 5 is in the range of greater than or equal to 1×10 19 cm -3 .

[0072] The gate drive capability characteristics of normally-off gate-controlled junction field-effect transistors are described below: Longchi factor LSF = Ich / Ig; where, when the gate voltage Vg is close to 3 volts, the gate leakage current Ig, the electron current flowing through the channel region 1 Ich; The value range of the Longchi factor LSF is greater than or equal to 100 and less than or equal to 10000.

[0073] When the gate voltage Vg approaches 3V, the depletion regions of the channel regulation region 3 and the channel region 1 approach zero, and the PN junction between the gate region 5 and the channel region 1 approaches forward conduction. Hole current diffuses from the gate region 5 through the channel region 1 into the well region 9, resulting in a gate leakage current Ig. Correspondingly, a large electron current Ich flows through the channel region 1.

[0074] The "LoongSpeed ​​Factor" (LSF) is defined here, and its quantitative expression is "LSF=Ich / Ig".

[0075] Conversely, when the gate voltage Vg is less than zero, approaching -3 volts, the back gate (well region 9 acting as the back gate) will also turn on. However, the doping concentration of well region 9 is much lower than that of channel region 1, and the channel regulation region 3 and channel region depletion portion 16 remain unchanged. Only the hole concentration on the surface of well region 9 changes, and no channel current is generated. However, the gate leakage current Ig that diffuses from well region 9 through channel region depletion portion 16 into gate region 5 still exists. The magnitude of the reverse gate leakage current Ig is roughly equivalent to the magnitude of the forward gate leakage current. If the gate leakage current Ig is too large, the gate drive circuit design of the normally-off gate-controlled junction field-effect transistor will be very difficult and consume a lot of power.

[0076] The "Run Factor" is critical in normally-off gate-controlled junction field-effect transistors (JFETs). A higher value is desirable, typically between 100 and 10,000. Increasing the doping concentration of gate region 5 and gate electrode 6 can increase the Run Factor. Reducing the effective gate length Lg is also an effective way to improve the Run Factor. For normally-off gate-controlled junction field-effect transistors, the Run Factor can be calculated within a gate bias range of 2.5-3V, with a typical bias voltage of 2.9V, which can be used as the "typical Run Factor."

[0077] like Figure 2-1 、 Figure 2-2 、 Figure 4 As shown, the specific requirements and operating modes of the normally-off gate-controlled junction field-effect transistor are explained below: The gate region 5 and the well region 9 are both highly doped with P-type.

[0078] The channel region 1 is N-type doped.

[0079] The channel 13 between the two well regions is an N-type doped region, and the doping concentration of the channel 13 is higher than that of the channel region 1. The gate region 5, the channel region 1, and the well region 9 form two back-to-back PN junctions. The vertical height and doping concentration N1 of the channel region 1 need to be controlled within a specific range (taking 4H-SiC as an example, the vertical height of the channel region 1 is less than or equal to 0.2 microns, and the doping concentration N1 of the channel region 1 is greater than or equal to 1×10 17 cm -3 and less than or equal to 1×10 18 cm -3 ).

[0080] The P-type doping concentration of gate region 5 should be as high as possible, which should be greater than or equal to 1×10 19 cm -3 As mentioned above, there is no particular requirement for the height of the gate region 5 .

[0081] The channel regulation region 3 is an extension of the channel region 1 and plays a key role in realizing the normally-off JFET. Its key parameter is that the length in the lateral direction is greater than or equal to 0.05 microns.

[0082] Source region 2 is very densely doped with N-type, and the doping concentration needs to be greater than or equal to 1×10 20 cm -3 , in order to form a good ohmic contact.

[0083] Specifically, the source contact region 14 is very densely doped with P-type, and the doping concentration needs to reach 1×10 18 cm -3 The source contact region 14 and the well region 9 are actually both P-type doped, so that the well region 9 is in a zero potential state.

[0084] The source electrode 8 is connected to the source region 2 and the source contact region 14 through an ohmic contact, so that the well region 9 and the source region 2 are stably connected to the source voltage.

[0085] The passivation protection layer area 4 is a thermal oxidation area. After all doping area processes are completed, high-temperature thermal oxidation is performed to form it. This thermal oxidation process and oxide layer play a key role in the process consistency and manufacturability of the entire device.

[0086] The gate electrode 6 is a metal electrode region of the gate region 5 .

[0087] The isolation layer 7 is an oxide layer that serves to isolate the gate electrode 6 from the source electrode 8. The isolation layer 7 is used to significantly reduce leakage and coupling capacitance between the gate and the source.

[0088] The working mode is as follows: The normally-off gate-controlled junction field-effect transistor is actually a four-terminal device consisting of a grounded back gate, a control gate, a source terminal, and a drain terminal.

[0089] The well region 9 serves as a junction back gate terminal and is connected to the source electrode 8 through the source contact region 14 and is always in a zero potential state.

[0090] The gate region 5 is connected to the gate electrode 6 for controlling the gate terminal (upper gate), and the voltage of the gate region 5 is usually in a regulation state between -5 volts and +3 volts.

[0091] The source region 2 is called the source end, which is connected to the source electrode 8 to provide conductive electrons. The conductive electrons can flow out of the source region 2 through the channel adjustment region 3, the channel region 1, the channel 13 between the two well regions, the drift region 10, and the substrate 11 to reach the drain electrode 12 called the drain end.

[0092] When the voltage of the control gate region 5 is greater than a certain value, which is called the threshold voltage Vth, the channel region 1 can allow electrons to pass from the source region 2 through the channel adjustment region 3, the channel 13 between the two well regions, the drift region 10, and the substrate 11 to the drain electrode 12. This state is called the normally-off gate-controlled junction field-effect transistor is turned on.

[0093] When the voltage of the control gate region 5 is lower than the threshold voltage Vth, the channel region 1 can prevent electrons from passing through, blocking the flow of electrons through the path. This state is called the normally-off gate-controlled junction field-effect transistor is turned off.

[0094] The following table shows a comparison of the parameters of the normally-off gate-controlled junction field effect transistor of the present application and the gate-controlled junction field effect transistor without a channel adjustment region in the prior art:

[0095] In the above table, μm means micrometer; Threshold voltage Vth, in volts (V); drain voltage Vd, in volts (V); drain current Id, in milliamperes (mA); On-resistance Rdson, in milliohms (mΩ); gate voltage Vg, in volts (V); drain current Id, in amperes (A); Breakdown voltage BV, in volts (V); gate voltage Vg, in volts (V); drain current Id, in milliamperes (mA).

[0096] Chip number 4 in the table is a conventional gate-controlled junction field effect transistor without a channel adjustment region. The threshold voltage Vth of the conventional gate-controlled junction field effect transistor without a channel adjustment region is less than 1.0, and its normally-off characteristics do not meet practical requirements.

[0097] In the table, chip number 1, chip number 2, and chip number 3 are normally-off gate-controlled junction field effect transistors with channel adjustment regions according to the present application, and the doping concentration of the channel adjustment regions 3 of chip number 1, chip number 2, and chip number 3 is the same. The threshold voltage Vth of the normally-off gate-controlled junction field effect transistors of chip number 1, chip number 2, and chip number 3 is greater than 1.0, and the normally-off characteristics can meet practical requirements. As the width of the channel adjustment region 3 increases, the threshold voltage Vth of the device increases. The presence of the channel adjustment region 3 has a trad-off effect on the on-resistance Rdson and breakdown voltage BV of the device. The presence of the channel adjustment region 3 can better achieve the normally-off characteristics of the device, but it will also cause an increase in the on-resistance Rdson.

[0098] Figure 5 Graphs showing the change of gate-source current Igs versus gate-source voltage Vgs for the normally-off gate-controlled junction field effect transistor of the present application and the prior art are shown. The prior art is a gate-controlled junction field effect transistor without a separate channel adjustment region 3 .

[0099] Figure 5 This shows that the normally-off gate-controlled junction field effect transistor can reduce the gate-source current Igs of the device due to the provision of a separate channel adjustment region 3, the height difference between the gate region 5 and the source region 2, and the spacing in the lateral direction.

[0100] Figure 6 This is a simulation diagram of the current distribution and path of the source-drain current Ids when the normally-off gate-controlled junction field-effect transistor of this application is forward-conducted.

[0101] Figure 7 This is a simulation diagram of the current distribution and path of the gate leakage current Igss when the gate of the normally-off gate-controlled junction field-effect transistor of this application is voltaged.

[0102] Figure 8 This is a curve comparison of the on-resistance Rdson of the normally-off gate-controlled junction field effect transistor of the present application and the prior art device as the device temperature changes. Figure 8 As shown, it is shown that the normally-off gate-controlled junction field-effect transistor of the present application has a better temperature coefficient of on-resistance Rdson than the prior art, and high temperature has little effect on the deterioration of on-resistance Rdson.

[0103] Figure 9 This is a curve comparison of the input capacitance Ciss of the normally-off gate-controlled junction field effect transistor of the present application and the prior art device as the gate-source voltage Vgs changes. Figure 9 As shown, the normally-off gate-controlled junction field-effect transistor of the present application has a better input capacitance Ciss than that of the prior art, which is due to the height difference between the gate region 5 and the source region 2 and the existence of the channel adjustment region 3.

[0104] Figure 10 Graph showing the change in gate current Ig versus gate-source voltage Vgs of the normally-off gate-controlled junction field-effect transistor of the present application.

[0105] Figure 11 This is a simulation diagram of the current distribution and path of the normally-off gate-controlled junction field effect transistor of this application when the gate-source voltage Vgs fails to open the channel. Figure 11 As shown in Figure 1, when the gate-source voltage Vgs fails to open the channel, the device current is almost composed of the gate current Ig, and the current distribution and path are given.

[0106] Figure 12 This is a simulation diagram of the current distribution and path of the normally-off gate-controlled junction field effect transistor of this application when the gate-source voltage Vgs is zero and the source-drain voltage Vds is positive. Figure 12 As shown in the figure, when the gate-source voltage Vgs is zero and the source-drain voltage Vds is positive, the current of the device is almost composed of the gate-drain current Ids, and the current distribution and path are given, reflecting the normally-off characteristics of the device.

[0107] Figure 13 This figure shows a simulation of the current distribution of the normally-off gate-controlled junction field-effect transistor of this application during forward conduction. During forward conduction, the current is primarily composed of the source-drain current Ids, while the gate-source current Igs is relatively small. Depletion in channel region 1 and channel regulation region 3 is almost completely eliminated, resulting in a low channel resistance.

[0108] Figure 14 This is a graph showing the LSF of the normally-off gate-controlled junction field effect transistor of the present invention, which shows the ability of the on-state current and the gate-source voltage Vgs. Figure 14 As shown in the figure, the LSF, the ability to conduct current, is related to the gate-source voltage Vgs. The larger the gate-source voltage Vgs, the stronger the ability to conduct current, but the gate leakage current Igss will increase, so there is a trad-off relationship. However, the LSF is relatively large, and the ability to conduct current is very good at a small gate-source voltage Vgs.

[0109] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0110] This application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate a device for implementing the functions specified in one or more processes in the flowchart and / or one or more blocks in the block diagram.

[0111] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0112] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0113] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0114] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A normally-off gate-controlled junction field-effect transistor, characterized in that: include: A substrate (11), and an epitaxial layer formed on the substrate (11); A channel region (1) of a second doping type is formed below the top surface of the epitaxial layer; A gate region (5) of a first doping type, formed on the channel region (1); A channel regulating region (3) of a second doping type is formed below the top surface of the epitaxial layer and is connected to the edge of the channel region (1); A source region (2) of a second doping type is formed below the top surface of the epitaxial layer and is connected to the channel adjustment region (3) on the same side, so that the source region (2) and the gate region (5) are separated in a lateral direction by the channel adjustment region (3); A passivation protection layer (4) covering at least the top surface of the channel regulation region (3) and the side surfaces of the gate region (5); A well region (9) of a first doping type is formed below the channel region (1), the channel adjustment region (3), and the source region (2).

2. The normally-off gate-controlled junction field-effect transistor according to claim 1, wherein: The vertical outer edge of the channel region (1) and the vertical outer edge of the gate region (5) are aligned in the vertical direction.

3. The normally-off gate-controlled junction field-effect transistor according to claim 1, wherein: The channel adjustment region (3) and the channel region (1) are two independent regions, so that the doping concentrations of the channel adjustment region (3) and the channel region (1) are independent of each other; The channel region (1) determines a portion of a preset threshold voltage Vth as a first portion, and the channel adjustment region (3) determines a portion of the preset threshold voltage Vth other than the first portion, so as to meet the requirement that the preset threshold voltage Vth of the normally-off gate-controlled junction field effect transistor is greater than or equal to 1.0 volt.

4. The normally-off gate-controlled junction field effect transistor according to claim 1, wherein: The passivation protection layer (4) is an oxide layer formed by a thermal oxidation process.

5. The normally-off gate-controlled junction field effect transistor according to claim 1, wherein: The cross section of the source region (2) is rectangular, and the cross section of the channel adjustment region (3) is rectangular; the position where the source region (2) and the channel adjustment region (3) are connected is a linear plane; Alternatively, the cross section of the source region (2) is L-shaped, and the cross section of the channel adjustment region (3) is rectangular; and the position where the source region (2) and the channel adjustment region (3) are connected is an L-shaped plane.

6. The normally-off gate-controlled junction field effect transistor according to claim 1, wherein: The ratio of the width X of the self-depletion region of the channel adjustment region (3) to the width W3 of the channel adjustment region (3) is greater than or equal to 3 / 5 and less than or equal to 1, and the ratio of the width Y of the self-depletion region of the channel region (1) to the width W1 of the channel region (1) is greater than or equal to 3 / 5 and less than or equal to 1.

7. The normally-off gate-controlled junction field effect transistor according to any one of claims 1 to 6, characterized in that: Also includes: A gate electrode (6) is formed on the gate region (5), the gate electrode (6) is smaller than the gate region (5), and the vertical outer edge of the gate electrode (6) is located within the vertical outer edge of the gate region (5); A source electrode (8) is connected to the source region (2), and a gap is maintained between the source electrode (8) and the channel regulating region (3) to ensure isolation between the two; The passivation protection layer (4) further covers an area of ​​the source region (2) not covered by the source electrode (8); and the passivation protection layer (4) further covers an area of ​​the gate region (5) not covered by the gate electrode (6).

8. The normally-off gate-controlled junction field-effect transistor according to claim 7, wherein: Also includes: an isolation layer (7), formed between the source electrode (8) and the gate electrode (6), and covering the passivation protection layer (4); A source contact region (14) of a first doping type is formed on a side of the source region (2) opposite to the channel regulating region (3) and is connected to the well region (9); The source electrode (8) is located above the source region (2) and the source contact region (14), so that the well region (9) and the source region (2) are stably connected to the source voltage.

9. The normally-off gate-controlled junction field effect transistor according to any one of claims 1 to 6, characterized in that: The epitaxial layer serves as a drift region (10); The doping concentration of the channel region (1) is at least one order of magnitude greater than the doping concentration of the drift region (10), so that within the operating temperature range, as the temperature of the normally-off gate-controlled junction field-effect transistor increases: The electron mobility of the channel region (1) with a higher doping concentration becomes higher, and the channel resistance will decrease instead; The electron mobility of the drift region (10) with a lower doping concentration becomes lower, and the resistance of the drift region (10) increases; This makes the on-resistance of the normally-off gate-controlled junction field-effect transistor change very little with temperature.

10. The normally-off gate-controlled junction field effect transistor according to claim 9, wherein: The doping concentration of the channel region (1) is on the order of 10 17 cm -3 to 10 18 cm -3 , the doping concentration of the drift region (10) is on the order of 10 16 cm -3 .

11. The normally-off gate-controlled junction field effect transistor according to any one of claims 1 to 6, characterized in that: The doping concentration of the channel adjustment region (3) is in the range of greater than or equal to 1×10 17 cm -3 and less than or equal to 1×10 18 cm -3 ; The width of the channel adjustment region (3) in the lateral direction is in the range of greater than or equal to 0.05 micrometers and less than or equal to 0.35 micrometers; The doping concentration of the channel regulating region (3) is lower than the doping concentration of the channel region (1); The height of the channel adjustment region (3) in the vertical direction has a value range of greater than or equal to 0.05 micrometers and less than or equal to 0.2 micrometers.

12. The normally-off gate-controlled junction field effect transistor according to claim 11, wherein: The doping concentration N1 of the channel region (1) is in the range of greater than or equal to 1×10 17 cm -3 and less than or equal to 1×10 18 cm -3 ; The width of the channel region (1) in the lateral direction is in the range of greater than or equal to 0.15 micrometers and less than or equal to 0.5 micrometers; The height of the channel region (1) in the vertical direction ranges from greater than or equal to 0.05 micrometers to less than or equal to 0.2 micrometers.

13. The normally-off gate-controlled junction field effect transistor according to any one of claims 1 to 6, characterized in that: The gate region (5) has a doping concentration range of greater than or equal to 1×10 19 cm -3 .

14. The normally-off gate-controlled junction field effect transistor according to any one of claims 1 to 6, characterized in that: Longchi factor LSF = Ich / Ig; where, when the gate voltage Vg is close to 3 volts, the gate leakage current Ig, the electron current flowing through the channel region (1) Ich; The value range of the Longchi factor LSF is greater than or equal to 100 and less than or equal to 10000.

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